PGA205BU

PGA205 TI | Alldatasheet

Document overview

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Technical content

1025kΩ25kΩ 25kΩ25kΩ 4VIN VIN PGA204 PGA205 Ref VO Over-Voltage Protection Over-Voltage Protection Feedback Digitally Selected Feedback Network VO1 Digital Ground 6 9 8 VO2 V–VOS Adj PGA204 PGA205 International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 Programmable Gain INSTRUMENTATION AMPLIFIER

FEATURES

l DIGITALLY PROGRAMMABLE GAIN: PGA204: G=1, 10, 100, 1000V/V PGA205: G=1, 2, 4, 8V/V l LOW OFFSET VOLTAGE: 50 µV max l LOW OFFSET VOLTAGE DRIFT: 0.25 µV/°C l LOW INPUT BIAS CURRENT: 2nA max l LOW QUIESCENT CURRENT: 5.2mA typ l NO LOGIC SUPPLY REQUIRED l 16-PIN PLASTIC DIP, SOL-16 PACKAGES

APPLICATIONS

l GENERAL PURPOSE ANALOG BOARDS l MEDICAL INSTRUMENTATION

DESCRIPTION

The PGA204 and PGA205 are low cost, general pur- pose programmable-gain instrumentation amplifiers offering excellent accuracy. Gains are digitally se- lected: PGA204—1, 10, 100, 1000, and PGA205—1, 2, 4, 8V/V. The precision and versatility, and low cost of the PGA204 and PGA205 make them ideal for a wide range of applications. Gain is selected by two TTL or CMOS-compatible address lines, A 0 and A1. Internal input protection can withstand up to ±40V on the analog inputs without damage. The PGA204 and PGA205 are laser trimmed for very low offset voltage (50µV), drift (0.25µV/°C) and high common-mode rejection (115dB at G=1000). They op- erate with power supplies as low as ±4.5V, allowing use in battery operated systems. Quiescent current is 5mA. The PGA204 and PGA205 are available in 16-pin plastic DIP, and SOL-16 surface-mount packages, speci- fied for the –40°C to +85°C temperature range. © 1991 Burr-Brown Corporation PDS-1176A Printed in U.S.A. October, 1993 SBOS022

• Specification same as PGA204BP. NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes time to switch to a new gain. PGA204BP, BU PGA204AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS SPECIFICATIONS ELECTRICAL At TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted. PGA204 G=1, 10, 100, 1000V/V INPUT Offset Voltage, RTI T A=+25°C ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV vs Temperature T A=TMIN to TMAX ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°C vs Power Supply V S=±4.5V to ±18V 0.5+2/G 3+10/G * * µV/V Long-Term Stability ±0.2+0.5/G * µV/mo Impedance, Differential 10 10||6 * Ω || pF Common-Mode 10 10||6 * Ω || pF Input Common-Mode Range V O =0V (see text) ±10.5 ±12.7 * * V Safe Input Voltage ±40 * V Common-Mode Rejection V CM =±10V, ΔR S=1kΩ G=1 80 99 75 90 dB G=10 96 114 90 106 dB G=100 110 123 106 110 dB G=1000 115 123 106 110 dB BIAS CURRENT ±0.5 ±2* ±5n A vs Temperature ±8 * pA/ °C Offset Current ±0.5 ±2* * n A vs Temperature ±8 * pA/ °C NOISE , Voltage, RTI(1): f=10Hz G ≥100, RS=0Ω 16 * nV/ √Hz f=100Hz G ≥100, RS=0Ω 13 * nV/ √ Hz f=1kHz G ≥100, RS=0Ω 13 * nV/ √Hz fB=0.1Hz to 10Hz G ≥100, RS=0Ω 0.4 * µVp-p Noise Current f=10Hz 0.4 * pA/ √Hz f=1kHz 0.2 * pA/ √Hz fB=0.1Hz to 10Hz 18 * pAp-p GAIN , Error G=1 ±0.005 ±0.024 * ±0.05 % Gain vs Temperature G=1 to 1000 ±2.5 ±10 * * ppm/ °C Nonlinearity G=1 ±0.0004 ±0.001 * ±0.002 % of FSR G=10 ±0.0004 ±0.002 * ±0.004 % of FSR G=100 ±0.0004 ±0.002 * ±0.004 % of FSR G=1000 ±0.0008 ±0.01 * ±0.02 % of FSR OUTPUT Voltage, Positive(2) IO =5mA, TMIN to TMAX (V+)–1.5 (V+)–1.3 * * V Negative(2) IO =–5mA, TMIN to TMAX (V–)+1.5 (V–)+1.3 * * V Load Capacitance Stability 1000 * pF Short Circuit Current +23/–17 * mA FREQUENCY RESPONSE Bandwidth, –3dB G=1 1 * MHz G=10 80 * kHz G=100 10 * kHz G=1000 1 * kHz Slew Rate V O =±10V, G=10 0.3 0.7 * * V/ µs Settling Time(3), 0.1% G=1 22 * µs G=10 23 * µs G=100 100 * µs G=1000 1000 * µs 0.01% G=1 23 * µs G=10 28 * µs G=100 140 * µs G=1000 1300 * µs Overload Recovery 50% Overdrive 70 * µs DIGITAL LOGIC Digital Ground Voltage, VDG V– (V+)–4 * * V Digital Low Voltage V– V DG +0.8V * * V Digital Input Current 1 * µA Digital High Voltage V DG +2 V+ * * V POWER SUPPLY , Voltage ±4.5 ±15 ±1 8 * **V Current V IN=0V +5.2/–4.2 ±6.5 * ±7.5 mA TEMPERATURE RANGE Specification –40 +85 * * °C Operating –40 +125 * * °C θJA 80 * °C/W

At TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted. INPUT Offset Voltage, RTI T A=+25°C ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV vs Temperature T A=TMIN to TMAX ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°C vs Power Supply V S=±4.5V to ±18V 0.5+2/G 3+10/G * * µV/V Long-Term Stability ±0.2+0.5/G * µV/mo Impedance, Differential 10 10||6 * Ω ||pF Common-Mode 10 10||6 * Ω ||pF Input Common-Mode Range V O =0V (see text) ±10.5 ±12.7 * * V Safe Input Voltage ±40 * V Common-Mode Rejection V CM =±10V, ΔR S=1kΩ G=1 80 94 75 88 dB G=2 85 100 80 94 dB G=4 90 106 85 100 dB G=8 95 112 89 106 dB BIAS CURRENT ±0.5 ±2* ±5n A vs Temperature ±8 * pA/ °C Offset Current ±0.5 ±2* * n A vs Temperature ±8 * pA/ °C Noise Voltage, RTI(1): f=10Hz G=8, R S=0Ω 19 * nV/ √Hz f=100Hz G=8, R S=0Ω 15 * nV/ √Hz f=1kHz G=8, R S=0Ω 15 * nV/ √Hz fB=0.1Hz to 10Hz G=8, R S=0Ω 0.5 * µVp-p Noise Current f=10Hz 0.4 * pA/ √Hz f=1kHz 0.2 * pA/ √Hz fB=0.1Hz to 10Hz 18 * pAp-p GAIN , Error G=1 ±0.005 ±0.024 * ±0.05 % Gain vs Temperature G=1 to 8 ±2.5 ±10 * * ppm/ °C Nonlinearity G=1 ±0.00024 ±0.001 * ±0.002 % of FSR G=2 ±0.00024 ±0.002 * ±0.004 % of FSR G=4 ±0.00024 ±0.002 * ±0.004 % of FSR G=8 ±0.00024 ±0.002 * ±0.004 % of FSR OUTPUT Voltage, Positive(2) IO =5mA, TMIN to TMAX (V+)–1.5 (V+)–1.3 * * V Negative(2) IO =–5mA, TMIN to TMAX (V–)+1.5 (V–)+1.3 * * V Load Capacitance Stability 1000 * pF Short Circuit Current +23/–17 * mA FREQUENCY RESPONSE Bandwidth, –3dB G=1 1 * MHz G=2 400 * kHz G=4 200 * kHz G=8 100 * kHz Slew Rate V O =±10V, G=8 0.3 0.7 * * V/ µs Settling Time(3), 0.1% G=1 22 * µs G=2 22 * µs G=4 23 * µs G=8 23 * µs 0.01% G=1 23 * µs G=2 23 * µs G=4 25 * µs G=8 28 * µs Overload Recovery 50% overdrive 70 * µs DIGITAL LOGIC INPUTS Digital Ground Voltage, VDG V– (V+)–4 * * V Digital Low Voltage V– V DG +0.8V * * V Digital Low Current 1 * µA Digital High Voltage V DG +2 V+ * * V POWER SUPPLY , Voltage ±4.5 ±15 ±1 8 * **V Current V IN=0V +5.2/–4.2 ±6.5 * ±7.5 mA TEMPERATURE RANGE Specification –40 +85 * * °C Operating –40 +125 * * °C θJA 80 * °C/W PGA205BP, BU PGA205AP, AU PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS PGA205 G=1, 2, 4, 8V/V * Specification same as PGA204BP. NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includes time to switch to a new gain.

PACKAGE INFORMATION

MODEL PACKAGE NUMBER (1) PGA204AP 16-Pin Plastic DIP 180 PGA204BP 16-Pin Plastic DIP 180 PGA204AU SOL-16 Surface Mount 211 PGA204BU SOL-16 Surface Mount 211 PGA205AP 16-Pin Plaseic DIP 180 PGA205BP 16-Pin Plastic DIP 180 PGA205AU SOL-16 Surface Mount 211 PGA205BU SOL-16 Surface Mount 211 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ABSOLUTE MAXIMUM RATINGS MODEL GAINS PACKAGE TEMPERATURE RANGE PGA204AP 1, 10, 100, 1000V/V 16-Pin Plastic DIP –40 to +85 °C PGA204BP 1, 10, 100, 1000V/V 16-Pin Plastic DIP –40 to +85 °C PGA204AU 1, 10, 100, 1000V/V SOL-16 Surface-Mount –40 to +85 °C PGA204BU 1, 10, 100, 1000V/V SOL-16 Surface-Mount –40 to +85 °C PGA205AP 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 to +85 °C PGA205BP 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 to +85 °C PGA205AU 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 to +85 °C PGA205BU 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 to +85 °C

ORDERING INFORMATION

4V –IN 5V +IN 6V OS Adj 7V OS Adj 8V – FPO MECHANICAL INFORMATION MILS (0.001") MILLIMETERS Die Size 186 x 130 ±5 4.72 x 3.30 ±0.13 Die Thickness 20 ±3 0.51 ±0.08 Min. Pad Size 4 x 4 0.1 x 0.1 Backing Gold Substrate Bias: Internally connected to V– power supply. PGA204/205 DIE TOPOGRAPHY PIN CONFIGURATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with ap- propriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NC: No Internal Connection. VO1 NC NC V IN IN VOS Adjust VOS Adjust Dig. Ground Feedback V O Ref V Top View PAD FUNCTION 9V O2

10 Ref

11 V O

12 Feedback

14 Dig. Ground 15 A

16 A 1

COMMON-MODE REJECTION vs FREQUENCY Frequency (Hz) Common-Mode Rejection (dB) 140 120 100 10 100 1k 10k 100k 1M G = 1k G = 100 G = 10 G = 1 G = 10 G = 1k,100 “B” Grade G = 1 TYPICAL PERFORMANCE CURVES At TA = +25°C, and VS = ±15V, unless otherwise noted. GAIN vs FREQUENCY Frequency (Hz) Gain (V/V) 10 100 10k 100k 1M 1k 100 G=1k G=100 G=10 G=1 INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE Output Voltage (V) Common-Mode Voltage (V) –15 –10 0 5 15 –5 –10 –15 Limited by A + Output Swing A3 – Output Swing Limit A3 + Output Swing Limit Limited by A – Output Swing Limited by A – Output Swing Limited by A + Output Swing VD/2 VCM VO (Any Gain) VD/2 POSITIVE POWER SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power Supply Rejection (dB) 10 100 10k 1M 1k 140 120 100 100k G = 1 G = 10 G = 100 G = 1k NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power Supply Rejection (dB) 10 100 10k 1M 1k 140 120 100 100k G = 1 G = 10 G = 100 G = 1k INPUT- REFERRED NOISE VOLTAGE vs FREQUENCY Frequency (Hz) Input-Referred Noise Voltage (nV/√ Hz) 11 0 1 k 100 100 10k G = 1 G = 10 G = 100, 1k G = 1k BW Limit

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. INPUT-REFERRED OFFSET VOLTAGE WARM-UP vs TIME Time from Power Supply Turn-on (s) Offset Voltage Change (µV) 15 30 45 60 75 90 105 120 G 100> INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE Temperature (°C) Input Bias and Input Offset Current (nA) –75 –25 25 75 100 125 ±IB IOS –50 0 50 INPUT BIAS CURRENT vs DIFFERENTIAL INPUT VOLTAGE Differential Overload Voltage (V) Input Current (mA) –45 –30 –15 0 15 30 45 G = 1 G = 10 G = 100, 1k INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE Input Bias Current (mA) –45 –30 –15 0 15 30 45 |Ib1| + |Ib2| Common-Mode Voltage (V) Over-Voltage Protection One Input Both Inputs Both Inputs One Input Over-Voltage Protection Normal Operation MAXIMUM OUTPUT VOLTAGE vs FREQUENCY Output Voltage (Vp-p) 100 10k 1M Frequency (Hz) 100k1k G ≤ 10 SLEW RATE vs TEMPERATURE Slew Rate (V/µs) –75 1.0 0.8 0.6 0.4 0.2 125 Temperature (°C) –50 –25 0 25 50 75 100 G=8 or 10

OUTPUT CURRENT LIMIT vs TEMPERATURE Short Circuit Current (mA) –40 Temperature (°C) –15 10 35 60 +|ICL | –|ICL | TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. QUIESCENT CURRENT vs TEMPERATURE Temperature (°C) Quiescent Current (mA) –75 6.0 5.5 5.0 4.5 4.0 –50 –25 0 25 50 75 100 125 QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE Quiescent Current (mA) 5.2 5.0 4.5 4.0 3.5 Power Supply Voltage (V) ±5 ±10 ±15 ±20 POSITIVE OUTPUT SWING vs TEMPERATURE Output Voltage (V) –75 125 Temperature (°C) –50 –25 0 25 50 75 100 VS = ±15V VS = 11.4 VS = ±4.5 NEGATIVE OUTPUT SWING vs TEMPERATURE Output Voltage (V) –75 –16 –14 –12 –10 125 Temperature (°C) –50 –25 0 25 50 75 100 VS = ±15V VS = 11.4 VS = ±4.5

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. SMALL-SIGNAL RESPONSE, G = 1 +200mV –200mV +10V –10V +200mV –200mV +10V –10V +10V –10V +200mV –200mV LARGE-SIGNAL RESPONSE, G = 1 SMALL-SIGNAL RESPONSE, G = 1000 LARGE-SIGNAL RESPONSE, G = 1000 SMALL-SIGNAL RESPONSE, G = 10 LARGE-SIGNAL RESPONSE, G = 10

TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, and VS = ±15V, unless otherwise noted. NOISE, 0.1 TO 10Hz, G = 1 1s/Div 0.5µV/Div 0.2µV/Div 1s/Div INPUT-REFERRED NOISE,

0.1 TO 10Hz, G = 1000

FIGURE 1. Basic Connections.

APPLICATION INFORMATION

Figure 1 shows the basic connections required for operation of the PGA204/205. Applications with noisy or high imped- ance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-impedance connection to assure good common-mode rejection. A resis- tance of 5Ω in series with the Ref pin will cause a typical device to degrade to approximately 80dB CMR (G=1). The PGA204/205 has an output feedback connection (pin 12). Pin 12 must be connected to the output terminal (pin 11) for proper operation. The output Feedback connection can be used to sense the output voltage directly at the load for best accuracy. DIGITAL INPUTS The digital inputs A 0 and A1 select the gain according to the logic table in Figure 1. Logic “1” is defined as a voltage greater than 2V above digital ground potential (pin 14). Digital ground can be connected to any potential from the V– power supply to 4V less than V+. Digital ground is normally connected to ground. The digital inputs interface directly CMOS and TTL logic components. Approximately 1µA flows out of the digital input pins when a logic “0” is applied. Logic input current is nearly zero with a logic “1” input. A constant current of approximatelyA 1 A 2 A 3 1025kΩ25kΩ 25kΩ25kΩ 4VIN VIN PGA204 PGA205 VO = G (VIN – VIN) VO Over-Voltage Protection Over-Voltage Protection Feedback Digitally Selected Feedback Network VO1 6 9 8 VO2VOS Adj +15V 1µF +15V 1µF PGA204 VIN VIN + VO A1 A0 Sometimes shown in simplified form: A1 A0PGA205PGA204 GAIN 100 1000 Ref

may require iterative adjustment. trim voltage with an op amp as shown. noise of “low noise” chopper-stabilized amplifiers. bias current (e.g. the bridge sensor shown in Figure 4). FIGURE 4. Providing an Input Common-Mode Current terms of a common-mode and differential input voltages. after the PGA204/205 to increase the voltage swing. inherrently provided by source.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PGA204AP Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type - PGA204AP PGA204AP.A Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type -40 to 85 PGA204AP PGA204AU Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 PGA204AU PGA204AU.A Active Production SOIC (DW) | 16 40 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 PGA204AU PGA204AU/1K Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 85 PGA204AU PGA204AU/1K.A Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 85 PGA204AU PGA204BP Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type - PGA204BP PGA204BP.A Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type -40 to 85 PGA204BP PGA204BU Active Production SOIC (DW) | 16 40 | TUBE Yes Call TI Level-3-260C-168 HR - PGA204BU PGA204BU.A Active Production SOIC (DW) | 16 40 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 85 PGA204BU PGA204BU/1K Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes Call TI Level-3-260C-168 HR - PGA204BU PGA204BU/1K.A Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 85 PGA204BU PGA205AP Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type -40 to 85 PGA205AP PGA205AP.A Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type -40 to 85 PGA205AP PGA205AU Active Production SOIC (DW) | 16 40 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 85 PGA205AU PGA205AU.A Active Production SOIC (DW) | 16 40 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 85 PGA205AU PGA205AU/1K Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 85 PGA205AU PGA205AU/1K.A Active Production SOIC (DW) | 16 1000 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 85 PGA205AU PGA205BP Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type -40 to 85 PGA205BP PGA205BP.A Active Production PDIP (N) | 16 25 | TUBE Yes Call TI N/A for Pkg Type -40 to 85 PGA205BP PGA205BU Active Production SOIC (DW) | 16 40 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 85 PGA205BU PGA205BU.A Active Production SOIC (DW) | 16 40 | TUBE Yes Call TI Level-3-260C-168 HR -40 to 85 PGA205BU (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 23-May-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA204AU/1K SOIC DW 16 1000 356.0 356.0 35.0 PGA204BU/1K SOIC DW 16 1000 356.0 356.0 35.0 PGA205AU/1K SOIC DW 16 1000 356.0 356.0 35.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) PGA204AP N PDIP 16 25 506 13.97 11230 4.32 PGA204AP.A N PDIP 16 25 506 13.97 11230 4.32 PGA204AU DW SOIC 16 40 507 12.83 5080 6.6 PGA204AU.A DW SOIC 16 40 507 12.83 5080 6.6 PGA204BP N PDIP 16 25 506 13.97 11230 4.32 PGA204BP.A N PDIP 16 25 506 13.97 11230 4.32 PGA204BU DW SOIC 16 40 507 12.83 5080 6.6 PGA204BU.A DW SOIC 16 40 507 12.83 5080 6.6 PGA205AP N PDIP 16 25 506 13.97 11230 4.32 PGA205AP.A N PDIP 16 25 506 13.97 11230 4.32 PGA205AU DW SOIC 16 40 507 12.83 5080 6.6 PGA205AU.A DW SOIC 16 40 507 12.83 5080 6.6 PGA205BP N PDIP 16 25 506 13.97 11230 4.32 PGA205BP.A N PDIP 16 25 506 13.97 11230 4.32 PGA205BU DW SOIC 16 40 507 12.83 5080 6.6 PGA205BU.A DW SOIC 16 40 507 12.83 5080 6.6 Pack Materials-Page 3

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