PGA112AIDGSR

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G□=□1 RF RI Output Stage SPI Interface SCLK DIO CS VOUT5 DVDD AVDD GND VREF MSP430 Microcontroller +3V +5V VREF PGA112 PGA113 V /CH0CAL CH1 CAL3 CAL4 CAL1 CAL20.1VCAL 0.9VCAL 10k/c87 80k/c87 MUX CAL2/3 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 Single-Supply, Single-Ended, Precision Programmable Gain Amplifier with MUX Remote e-Meter Reading Rail-to-Rail Input/Output Automatic Gain Control Offset: µ V (typ), 100 µ V (max) Portable Data Acquisition Zer ø Drift: 0.35 µ C (typ), 1.2 µ C (max) PC-Based Signal Acquisition Systems Low Noise: 12nV/ Hz Test and Measurement Input Offset Current: 5nA max (+25 Programmable Logic Controllers Gain Error: 0.1% max 32), Battery-Powered Instruments 0.3% max 32) Handheld Test Equipment Binary Gains: 16, 32, 64, 128 (PGA112, PGA116) Scope Gains: 10, 20, 50, 100, 200 The PGA112 and PGA113 (binary/scope gains) offer (PGA113, PGA117) two analog inputs, a three-pin SPI interface, and Gain Switching Time: 200ns software shutdown in an MSOP-10 package. The Two Channel MUX: PGA112, PGA113 PGA116 and PGA117 (binary/scope gains) offer Channel MUX: PGA116, PGA117 analog inputs, a four-pin SPI interface with daisy-chain capability, and hardware and software Four Internal Calibration Channels shutdown in a TSSOP-20 package. Amplifier Optimized for Driving CDAC ADCs All versions provide internal calibration channels for Output Swing: 50mV to Supply Rails system-level calibration. The channels are tied to AV DD and DV DD for Mixed Voltage Systems GND, 0.9V CAL 0.1V CAL and V REF respectively. V CAL I Q 1.1mA (typ) an external voltage connected to Channel is used as the system calibration reference. Binary gains are: Software/Hardware Shutdown: I Q µ A (typ) 16, 32, 64, and 128; scope gains are: Temperature Range: C to +125 C 10, 20, 50, 100, and 200. SPI Interface (10MHz) with Daisy-Chain Capability Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. UNLESS OTHERWISE NOTED this document contains Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE AND MODEL COMPARISON SHUTDOWN OF MUX GAINS SPI DEVICE INPUTS (Eight Each) DAISY-CHAIN HARDWARE SOFTWARE PACKAGE PGA112 Two Binary No No ü MSOP-10 PGA113 Two Scope No No ü MSOP-10 PGA116 Binary ü ü ü TSSOP-20 PGA117 Scope ü ü ü TSSOP-20 ORDERING INFORMATION (1) (Gains/Channels) PACKAGE-LEAD DESIGNATOR MARKING PGA112 Binary (2) Channels MSOP-10 DGS P112 PGA113 Scope (3) Channels MSOP-10 DGS P113 PGA116 (4) Binary (2) /10 Channels TSSOP-20 PW PGA116 PGA117 (4) Scope (3) /10 Channels TSSOP-20 PW PGA117 (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com (2) Binary gains: 16, 32, 64, and 128. (3) Scope gains: 10, 20, 50, 100, and 200. (4) Available 2008. Over operating free-air temperature range, unless otherwise noted. PGA112, PGA113, PGA116, PGA117 UNIT Supply Voltage V Signal Input Terminals, Voltage (2) GND 0.5 to (AV DD 0.5 V Signal Input Terminals, Current (2) mA Output Short-Circuit Continuous Operating Temperature to +125 C Storage Temperature to +150 C Junction Temperature +150 C Human Body Model (HBM) 3000 V ESD Ratings: Charged Device Model (CDM) 1000 V Machine Model (MM) 300 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

CHARACTERISTICS: V S AV DD DV DD +5V PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 Boldface limits apply over the specified temperature range, T A C to +125 At T A +25 R L 10k Ω //C L 100pF connected to DV DD /2, and V REF GND, unless otherwise noted. PGA112, PGA113 PARAMETER CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE Input Offset Voltage V OS AV DD DV DD +5V, V REF V IN AV DD /2, V CM 2.5V 100 µ V AV DD DV DD +5V, V REF V IN AV DD /2, V CM 4.5V 325 µ V vs Temperature, C to +125 C dV OS /dT AV DD DV DD +5V, V CM 2.5V 0.35 1.2 µ C vs Temperature, C to +85 C AV DD DV DD +5V, V CM 2.5V 0.15 0.9 µ C vs Temperature, C to +125 C AV DD DV DD +5V, V CM 4.5V 0.6 1.8 µ C vs Temperature, C to +85 C AV DD DV DD +5V, V CM 4.5V 0.3 1.3 µ C AV DD DV DD +2.2V to +5.5V, V CM 0.5V, vs Power Supply PSRR µ V/V V REF V IN AV DD AV DD DV DD +2.2V to +5.5V, V CM 0.5V, Over Temperature, C to +125 C µ V/V V REF V IN AV DD INPUT ON-CHANNEL CURRENT Input On-Channel Current (Ch0, Ch1) I IN V REF V IN AV DD 1.5 nA Over Temperature, C to +125 C V REF V IN AV DD See Typical Characteristics nA INPUT VOLTAGE RANGE Input Voltage Range (1) I VR GND 0.1 AV DD 0.1 V Overvoltage Input Range No Output Phase Reversal (2) GND 0.3 AV DD 0.3 V INPUT IMPEDANCE (Channel On) (3) Channel Input Capacitance C CH pF Channel Switch Resistance R SW 150 Ω Amplifier Input Capacitance C AMP pF Amplifier Input Resistance R AMP Input Resistance to GND G Ω V CAL /CH0 R IN CAL1 or CAL2 Selected 100 k Ω GAIN SELECTIONS Nominal Gains Binary gains: 16, 32, 64, 128 128 Scope gains: 10, 20, 50, 100, 200 200 DC Gain Error G V OUT GND 85mV to DV DD 85mV 0.006 0.1 G V OUT GND 85mV to DV DD 85mV 0.1 G V OUT GND 85mV to DV DD 85mV 0.3 DC Gain Drift G V OUT GND 85mV to DV DD 85mV 0.5 ppm/ C G V OUT GND 85mV to DV DD 85mV ppm/ C G V OUT GND 85mV to DV DD 85mV ppm/ C Op Amp Input 0.9V CAL CAL2 DC Gain Error (4) 0.02 V REF V CAL AV DD /2, G Op Amp Input 0.9V CAL CAL2 DC Gain Drift (4) ppm/ C V REF V CAL AV DD /2, G Op Amp Input 0.1V CAL CAL3 DC Gain Error (4) 0.02 V REF V CAL AV DD /2, G Op Amp Input 0.1V CAL CAL3 DC Gain Drift (4) ppm/ C V REF V CAL AV DD /2, G INPUT IMPEDANCE (Channel Off) (3) Input Impedance C CH See Figure pF INPUT OFF-CHANNEL CURRENT V REF GND, V OFF-CHANNEL AV DD /2, Input Off-Channel Current (Ch0, Ch1) (5) I LKG 0.05 nA V ON-CHANNEL AV DD 0.1V V REF GND, V OFF-CHANNEL AV DD /2, Over Temperature, C to +125 C See Typical Characteristics V ON-CHANNEL AV DD 0.1V Channel-to-Channel Crosstalk 130 dB (1) Gain error is a function of the input voltage. Gain error outside of the range (GND 85mV V OUT DV DD 85mV) increases to 0.5% (typical). (2) Input voltages beyond this range must be current limited to |10mA| through the input protection diodes on each channel to prevent permanent destruction of the device. (3) See Figure (4) Total V OUT error must be computed using input offset voltage error multiplied by gain. Includes op amp G error. (5) Maximum specification limitation limited by final test time and capability. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

www.ti.com ELECTRICAL CHARACTERISTICS: V S AV DD DV DD +5V (continued) Boldface limits apply over the specified temperature range, T A C to +125 At T A +25 R L 10k Ω //C L 100pF connected to DV DD /2, and V REF GND, unless otherwise noted. PGA112, PGA113 PARAMETER CONDITIONS MIN TYP MAX UNIT OUTPUT Voltage Output Swing from Rail I OUT 0.25mA, AV DD DV DD (6) GND 0.05 DV DD 0.05 V I OUT 5mA, AV DD DV DD (6) GND 0.25 DV DD 0.25 V DC Output Nonlinearity V OUT GND 85mV to DV DD 85mV (7) 0.0015 %FSR Short-Circuit Current I SC 30/+60 mA Capacitive Load Drive C LOAD See Typical Characteristics NOISE Input Voltage Noise Density e n f 10kHz, C L 100pF, V S nV/ Hz f 10kHz, C L 100pF, V S 2.2V nV/ Hz Input Voltage Noise e n f 0.1Hz to 10Hz, C L 100pF, V S 0.362 µ V PP f 0.1Hz to 10Hz, C L 100pF, V S 2.2V 0.736 µ V PP Input Current Density I n f 10kHz, C L 100pF 400 fA/ Hz SLEW RATE Slew Rate SR See Table µ s SETTLING TIME Settling Time t S See Table µ s FREQUENCY RESPONSE Frequency Response See Table MHz THD NOISE G f 1kHz, V OUT PP at 2.5V DC C L 100pF 0.003 G 10, f 1kHz, V OUT PP at 2.5V DC C L 100pF 0.005 G 50, f 1kHz, V OUT PP at 2.5V DC C L 100pF 0.03 G 128, f 1kHz, V OUT PP at 2.5V DC C L 100pF 0.08 G 200, f 1kHz, V OUT PP at 2.5V DC C L 100pF 0.1 G f 20kHz, V OUT PP at 2.5V DC C L 100pF 0.02 G 10, f 20kHz, V OUT PP at 2.5V DC C L 100pF 0.01 G 50, f 20kHz, V OUT PP at 2.5V DC C L 100pF 0.03 G 128, f 20kHz, V OUT PP at 2.5V DC C L 100pF 0.08 G 200, f 20kHz, V OUT PP at 2.5V DC C L 100pF 0.11 POWER SUPPLY Operating Voltage Range (6) AV DD 2.2 5.5 V DV DD 2.2 5.5 V Quiescent Current Analog I QA I O G V OUT V REF 0.33 0.45 mA Over Temperature, C to +125 C 0.45 mA I O G V OUT V REF SCLK at 10MHz, Quiescent Current Digital (8) (9) (10) I QD 0.75 1.2 mA CS Logic DIO Logic I O G V OUT V REF SCLK at 10MHz, Over Temperature, C to +125 C (8) (9) (10) 1.2 mA CS Logic DIO Logic Shutdown Current Analog Digital (8) (9) I SDA I SDD I O V OUT V REF G SCLK Idle µ A I O V OUT G SCLK at 10MHz, 245 µ A CS Logic DIO Logic POWER-ON RESET (POR) Digital interface disabled and Command Register set to POR POR Trip Voltage 1.6 V values for DV DD POR Trip Voltage (6) When AV DD is less than DV DD the output is clamped to AV DD 300mV. (7) Measurement limited by noise in test equipment and test time. (8) Does not include current into or out of the V REF pin. Internal R F and R I are always connected between V OUT and V REF (9) Digital logic levels: DIO logic µ A internal current source. (10) Includes current from op amp output structure. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

(Input) VREF Break-Before-Make PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 ELECTRICAL CHARACTERISTICS: V S AV DD DV DD +5V (continued) Boldface limits apply over the specified temperature range, T A C to +125 At T A +25 R L 10k Ω //C L 100pF connected to DV DD /2, and V REF GND, unless otherwise noted. PGA112, PGA113 PARAMETER CONDITIONS MIN TYP MAX UNIT TEMPERATURE RANGE Specified Range +125 C Operating Range +125 C Thermal Resistance θ JA MSOP-10 164 C/W DIGITAL INPUTS (SCLK, CS DIO) Logic Low 0.3DV DD V Input Leakage Current (SCLK and CS only) µ A Weak Pull-Down Current (DIO only) µ A Logic High 0.7DV DD DV DD V Hysteresis 700 mV DIGITAL OUTPUT (DIO) Logic High I OH 3mA (sourcing) DV DD 0.4 DV DD V Logic Low I OL +3mA (sinking) GND GND 0.4 V CHANNEL AND GAIN TIMING Channel Select Time 0.2 µ s Gain Select Time 0.2 µ s SHUTDOWN MODE TIMING Enable Time 4.0 µ s V OUT goes high-impedance, R F and R I remain connected Disable Time 2.0 µ s between V OUT and V REF POWER-ON-RESET (POR) TIMING POR Power-Up Time DV DD µ s POR Power-Down Time DV DD 1.5V µ s Table Frequency Response versus Gain L 100pF, R L 10k Ω 0.1% 0.01% 0.1% 0.01% TYPICAL SLEW SLEW SETTLING SETTLING TYPICAL SLEW SLEW SETTLING SETTLING 3dB RATE- RATE- TIME: TIME: SCOPE 3dB RATE- RATE- TIME: TIME: BINARY FREQUENCY FALL RISE PP PP GAIN FREQUENCY FALL RISE PP PP GAIN (V/V) (MHz) (V/ µ (V/ µ µ µ (V/V) (MHz) (V/ µ (V/ µ µ µ 2.55 2.55 3.8 6.4 2.6 3.8 6.4 2.6 12.8 10.6 2.6 1.8 12.8 10.6 2.6 1.8 12.8 10.6 2.6 1.8 12.8 10.6 2.2 2.6 1.6 12.8 12.8 2.3 2.6 1.3 12.8 9.1 2.3 2.8 1.8 12.8 13.3 2.3 0.9 9.1 7.1 2.4 3.8 0.6 3.5 100 0.38 3.5 4.4 128 0.35 2.5 2.5 4.8 200 0.23 2.3 6.9 Figure Equivalent Input Circuit Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

TIMING: V S AV DD DV DD +2.2V to +5V PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com Boldface limits apply over the specified temperature range, T A C to +125 At T A +25 R L 10k Ω //C L 100pF connected to DV DD /2, and V REF GND, unless otherwise noted. PGA112, PGA113, PGA116, PGA117 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input Capacitance (SCLK, CS and DIO pins) pF Input Rise/Fall Time (1) t RFI µ s CS SCLK, and DIO pins) Output Rise/Fall Time (DIO pin) (1) t RFO C LOAD 60pF ns CS High Time CS pin) (1) t CSH ns SCLK Edge to CS Fall Setup Time (1) t CSO ns CS Fall to First SCLK Edge Setup Time t CSSC ns SCLK Frequency (2) f SCLK MHz SCLK High Time (3) t HI ns SCLK Low Time (3) t LO ns SCLK Last Edge to CS Rise Setup Time (1) t SCCS ns CS Rise to SCLK Edge Setup Time (1) t CS1 ns DIN Setup Time t SU ns DIN Hold Time t HD ns SCLK to DOUT Valid Propagation Delay (1) t DO ns CS Rise to DOUT Forced to Hi-Z (1) t SOZ ns (1) Ensured by design; not production tested. (2) When using devices in daisy-chain mode, the maximum clock frequency for SCLK is determined by a combination of propagation delay time DO 25ns), data input setup time SU 10ns), SCLK high time HI 40ns), and DOUT rise and fall times RFO 10ns). In addition, maximum clock frequency depends directly on the number of devices in the daisy-chain. (3) t HI and t LO must not be less than 1/SCLK (max). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 Figure SPI Mode Figure SPI Mode Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

www.ti.com MSOP-10 DGS PACKAGE (TOP VIEW) PGA112, PGA113 TERMINAL FUNCTIONS MSOP PACKAGE PIN NAME (+2.2V to +5.5V) CH1 Input MUX channel Input MUX channel and V CAL input. For system calibration purposes, connect this pin to a low-impedance external reference voltage to use internal calibration channels. The four internal V CAL /CH0 calibration channels are connected to GND, 0.9V CAL 0.1V CAL and V REF respectively. V CAL is loaded with 100k Ω (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise, V CAL /CH0 appears as high impedance. Reference input pin. Connect external reference for V OUT offset shift or to midsupply for midsupply V REF referenced systems. V REF must be connected to a low-impedance reference capable of sourcing and sinking at least 2mA or V REF must be connected to GND. V OUT Analog voltage output. When AV DD DV DD V OUT is clamped to AV DD 300mV. GND Ground pin SCLK Clock input for SPI serial interface DIO Data input/output for SPI serial interface. DIO contains a weak, µ A internal pull-down current source. CS Chip select line for SPI serial interface Digital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems to prevent overvoltage/lockup condition on an analog-to-digital (ADC) input (for example, a microcontroller DV DD with an ADC running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DV DD DV DD should be bypassed with a 0.1 µ F ceramic capacitor, and DV DD must supply the current for the digital portion of the PGA as well as the load current for the op amp output stage. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 TSSOP-20 PW PACKAGE (TOP VIEW) PGA116, PGA117 TERMINAL FUNCTIONS TSSOP PACKAGE PIN NAME (+2.2V to +5.5V) CH5 Input MUX channel CH4 Input MUX channel CH3 Input MUX channel CH2 Input MUX channel CH1 Input MUX channel Input MUX channel and V CAL input. For system calibration purposes, connect this pin to a low-impedance external reference voltage to use internal calibration channels. The four internal V CAL /CH0 calibration channels are connected to GND, 0.9V CAL 0.1V CAL and V REF respectively. V CAL is loaded with 100k Ω (typical) when internal calibration channels CAL2 or CAL3 are selected. Otherwise, V CAL /CH0 appears as high impedance. Reference input pin. Connect external reference for V OUT offset shift or to midsupply for midsupply V REF referenced systems. V REF must be connected to a low-impedance reference capable of sourcing and sinking at least 2mA or to GND. V OUT Analog voltage output. When AV DD DV DD V OUT is clamped to AV DD 300mV. CH7 Input MUX channel CH8 Input MUX channel CH9 Input MUX channel ENABLE Hardware enable pin. Logic low puts the part into Shutdown mode Q µ A). GND Ground pin SCLK Clock input for SPI serial interface Data input for SPI serial interface. DIN contains a weak, µ A internal pull-down current source to DIN allow for ease of daisy-chain configurations. Data output for SPI serial interface. DOUT goes to high-Z state when CS goes high for standard SPI DOUT interface. CS Chip select line for SPI serial interface Digital and op amp output stage supply voltage (+2.2V to +5.5V). Useful in multi-supply systems to prevent overvoltage/lockup condition on an ADC input (for example, a microcontroller with an ADC DV DD running on +3V and the PGA powered from +5V). Digital I/O levels to be relative to DV DD DV DD should be bypassed with a 0.1 µ F ceramic capacitor, and DV DD must supply the current for the digital portion of the PGA as well as the load current for the op amp output stage. CH6 Input MUX channel Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

G□=□1 RF RI Output Stage SPI Interface SCLK DIO CS VOUT5 DVDD AVDD GND VREF MSP430 Microcontroller +3V +5V VREF PGA112 PGA113 V /CH0CAL CH1 CAL3 CAL4 CAL1 CAL20.1VCAL 0.9VCAL 10k/c87 80k/c87 MUX CAL2/3 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 10k/c87 G□=□1 RF RI Output Stage SPI Interface SCLK ENABLE DIN CS VOUT9 DVDD19 AVDD GND VREF 8 13 DOUT17 +5V VREF PGA116 PGA117 CH8 12 CH9 CH7 11 CH6 10 CH5 20 CH4 2 CH3 3 CH2 4 CH1 5 7V /CH0CAL CAL3 CAL4 CAL1 CAL20.1VCAL 0.9VCAL 10k/c87 80k/c87 MUX CAL2/3 C 0.1 F BYPASS /c109 ADC MSP430 Microcontroller +3V C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com Figure PGA112, PGA113 (MSOP-10) Figure PGA116, PGA117 (TSSOP-20) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

/c4580 Offset□Voltage□( V)/c109 Population /c4590 /c45100 /c4570 /c4560 /c4510/c4520/c4530/c4540/c4550 0 10 90 1008020 30 40 706050 V =□2.5VCM /c45260.0 Offset□Voltage□( V)/c109 Population /c45130.0/c45162.5 V =□4.5VCM 325.0/c45292.5 /c450.72 Offset□Voltage□Drift□( V/ C)/c109 /c176 Population V =□2.5VCM /c451.04 Offset□Voltage□Drift□( V/ C)/c109 /c176 Population V =□4.5VCM /c451.17 /c451.44 Offset□Voltage□Drift□( V/ C)/c109 /c176 Population V =□4.5VCM /c451.62 /c450.96 Offset□Voltage□Drift□( V/ C)/c109 /c176 Population V =□2.5VCM PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. OFFSET VOLTAGE OFFSET VOLTAGE Figure Figure OFFSET VOLTAGE DRIFT OFFSET VOLTAGE DRIFT C to +85 C TO +85 Figure Figure OFFSET VOLTAGE DRIFT OFFSET VOLTAGE DRIFT C to +125 C TO +125 Figure 10. Figure 11. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

Input□Voltage□(V) 100 100 /c45 /c45 /c45 /c45 /c45 Input□Offset□Voltage□( V) /c109 32 4 V (V)OUT DC□Output□Nonlinearity□Error□(%FSR) 0.0010 0.0008 0.0006 0.0004 0.0002 0.0002 0.0004 0.0006 0.0008 0.0010 /c45 /c45 /c45 /c45 /c45 0.50 5.01.0 1.5 G□=□128 G□=□16 G□=□2G□=□1 AV =□DV =□+5VDD DD /c450.08 Gain□Error□(%) Population /c450.08 Gain□Error□(%) Population Gain□Error□Drift□( )ppm/ C/c176 Population G□=□1 0.100.05 /c450.240 Gain□Error□(%) Population 300 PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. INPUT OFFSET VOLTAGE vs INPUT VOLTAGE PGA112/PGA116 NONLINEARITY Figure 12. Figure 13. GAIN ERROR GAIN ERROR G 32) Figure 14. Figure 15. GAIN ERROR DRIFT GAIN ERROR 50) C to +125 Figure 16. Figure 17. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

1.0 Gain□Error□Drift□(ppm/ C)/c176 Population 0.5 G 50/c179 0.50 Gain□Error□Drift□(ppm/ C)/c176 Population 0.25

1 G 32/c60 /c163

/c450.08 Gain□Error□(%) Population /c450.08 Gain□Error□(%) Population /c451.6 Gain□Error□Drift□(ppm/ C)/c176 Population /c451.6 Gain□Error□Drift□(ppm/ C)/c176 Population >□2.0/c451.8 2.0 PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. GAIN ERROR DRIFT GAIN ERROR DRIFT C to +125 C to +125 Figure 18. Figure 19. CAL2 GAIN ERROR CAL3 GAIN ERROR Figure 20. Figure 21. CAL2 GAIN ERROR DRIFT CAL3 GAIN ERROR DRIFT C to +125 C to +125 Figure 22. Figure 23. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

2.5s/div 250nV/div V =□2.2VS 2.5s/div 100nV/div V =□5VS 1 10 100 1k 100k Frequency□(Hz) 100 Voltage□Noise□(nV/ ) /c214Hz 10k 100 Current□Noise□(fA/ /c214Hz Voltage□Noise,□V =□5VS Voltage□Noise,□V =□2.2VS Current□Noise,□V =□5VS 500 200 Frequency□(Hz) THD+N□(%) 0.1 0.01 0.001 0.0001 10010 100k1k 10k G□=□128 Frequency□(Hz) THD+N□(%) 0.1 0.01 0.001 0.0001 10010 100k1k 10k G□=□128 G□=□8 G□=□4G□=□2 G□=□1 Frequency□(Hz) THD+N□(%) 0.1 0.01 0.001 0.0001 10010 100k1k 10k G□=□1 PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. 0.1Hz TO 10Hz NOISE 0.1Hz TO 10Hz NOISE Figure 24. Figure 25. PGA112 THD NOISE vs FREQUENCY SPECTRAL NOISE DENSITY OUT PP Figure 26. Figure 27. PGA112 THD NOISE vs FREQUENCY PGA113 THD NOISE vs FREQUENCY OUT PP OUT PP Figure 28. Figure 29. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

Frequency□(Hz) THD+N□(%) 0.1 0.01 0.001 0.0001 10010 100k1k 10k G□=□20 G□=□10G□=□2 G□=□1 G□=□5 T emperature□( C)/c176 I (mA)Q 0.8 0.4 0.3 0.2 0.1 75/c45 25/c45 50 100 1250 25 50 0.5 0.6 0.7 V =□5.5VS V =□2.2VS Digital Analog f =□10MHzSCLK Supply□Voltage□(V) I +□I (mA)QA QD 1.2 1.0 0.8 0.6 0.4 0.2 SCLK□=□10MHz SCLK□=□5MHz SCLK□=□2MHzSCLK□=□500kHz /c45 50 /c45 25 0 125 T emperature□( C)/c176 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Shutdown□I ( A)/c109 Q 25 50 75 100 Digital Analog 0 10 20 30 40 50 60 70 80 90 100 Output□Current□(mA) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Output□Voltage□(V) V =□5.5V G□=□1 S +125 C/c176 +25 C/c176 /c45 /c176 40 C 0 2 4 6 8 10 12 14 16 18 24 Output□Current□(mA) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Output□Voltage□(V) 2220 V =□2.2V G□=□1 S +125 C/c176 +25 C/c176 /c45 /c176 40 C PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. PGA113 THD NOISE vs FREQUENCY QUIESCENT CURRENT OUT PP vs TEMPERATURE Figure 30. Figure 31. TOTAL QUIESCENT CURRENT SHUTDOWN QUIESCENT CURRENT vs SUPPLY VOLTAGE vs TEMPERATURE Figure 32. Figure 33. OUTPUT VOLTAGE OUTPUT VOLTAGE vs OUTPUT CURRENT vs OUTPUT CURRENT Figure 34. Figure 35. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

Frequency□(Hz) 2.5 2.0 1.5 1.0 0.5 Output□Voltage□(V) 100k 1M G□=□1 G□=□8 G□=□4 G□=□2 AV =□DV =□2.2VDD DD 1k 10k 10M Frequency□(Hz) 2.5 2.0 1.5 1.0 0.5 Output□Voltage□(V) 100k 1M G□=□128 G□=□16 G□=□64 G□=□32 AV = 2.2VDD DV =DD 100 1k 10k 10M Frequency□(Hz) Output□Voltage□(V) 100k 1M G□=□1 G□=□8 G□=□4 G□=□2 AV =□DV =□5.5VDD DD 100 1k 10k 10M Frequency□(Hz) Output□Voltage□(V) 100k 1M G□=□128 G□=□16 G□=□64 G□=□32 AV =□DV =□5.5VDD DD 1k 10k 100k 1M 10M Frequency□(Hz) 2.5 2.0 1.5 1.0 0.5 Output□Voltage□(V) G□=□10 G□=□2 G□=□1 G□=□5 AV =□DVDD DD =□2.2V 1k 10k 100k 1M 10M Frequency□(Hz) 2.5 2.0 1.5 1.0 0.5 Output□Voltage□(V) G□=□100 G□=□20 G□=□200 G□=□50 AV =□DVDD DD =□2.2V PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. PGA112 OUTPUT VOLTAGE SWING vs FREQUENCY PGA112 OUTPUT VOLTAGE SWING vs FREQUENCY Figure 36. Figure 37. PGA112 OUTPUT VOLTAGE SWING vs FREQUENCY PGA112 OUTPUT VOLTAGE SWING vs FREQUENCY Figure 38. Figure 39. PGA113 OUTPUT VOLTAGE SWING vs FREQUENCY PGA113 OUTPUT VOLTAGE SWING vs FREQUENCY Figure 40. Figure 41. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

Frequency□(Hz) Output□Voltage□(V) G□=□10 G□=□2 G□=□1 G□=□5 AV =□DVDD DD =□5.5V 100 1k 10k 100k 1M 10M Frequency□(Hz) Output□Voltage□(V) G□=□20 G□=□200 G□=□100 G□=□50 AV =□DVDD DD =□5.5V 0 50 100 200 Gain Settling□Time□( s)/c109 150 0.01% 0.1% C =□100pF//R =□10k /c87L L OUT PPV =□4V 0 100 200 300 400 500 600 700 800 Load□Capacitance□(pF) Overshoot□(%) G□=□1 G 2> /c45 50 /c45 25 0 25 50 75 100 125 T emperature□(/c176 C) CH1 CH0 /c45 50 /c45 25 0 25 50 75 100 125 T emperature□(/c176 C) |□Input□Off-Channel□Leakage□Current□(nA)□| CH1 CH0 PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. PGA113 OUTPUT VOLTAGE SWING vs FREQUENCY PGA113 OUTPUT VOLTAGE SWING vs FREQUENCY Figure 42. Figure 43. SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE GAIN vs SETTLING TIME Figure 44. Figure 45. INPUT ON-CHANNEL CURRENT INPUT OFF-CHANNEL LEAKAGE CURRENT vs TEMPERATURE vs TEMPERATURE Figure 46. Figure 47. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

Frequency□(Hz) 140 130 120 110 100 Crosstalk□(dB) 1M100k 0.1 1 10 100 10M Frequency□(Hz) 110 100 PSRR□(dB) 1M100k10k1k G□=□200 G□=□50 G□=□10 G□=□2 G□=□1 G 2/c179 2.5 s/div/c109 G□=□20 G□=□10 G□=□1100mV Output Input V /GIN 2.5 s/div/c109 Output Input G□=□50 G□=□100,□200 100mV V /GIN 2.5 s/div/c109 2V/div G□=□10 G□=□2 G□=□1 Output Input 2.5 s/div/c109 2V/div Input G□=□50 G□=□100,□200Output PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. POWER-SUPPLY REJECTION RATIO vs FREQUENCY CROSSTALK vs FREQUENCY Figure 48. Figure 49. SMALL-SIGNAL PULSE RESPONSE SMALL-SIGNAL PULSE RESPONSE Figure 50. Figure 51. LARGE-SIGNAL PULSE RESPONSE LARGE-SIGNAL PULSE RESPONSE Figure 52. Figure 53. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

Output□(1V/div) Supply□(5V/div) 1ms/div 1V/div V =□5V R =□10k C =□100pF S L /c87 L VIN VOUT 10 s/div/c109 2V/div Output Active In Shutdown CS Output CS In Shutdown Active SERIAL INTERFACE INFORMATION SERIAL DIGITAL INTERFACE: SPI MODES PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) At T A +25 AV DD DV DD 5V, R L 10k Ω connected to DV DD /2, V REF GND, and C L 100pF, unless otherwise noted. POWER-UP/POWER-DOWN TIMING OUTPUT OVERDRIVE PERFORMANCE Figure 54. Figure 55. OUTPUT VOLTAGE vs SHUTDOWN MODE Figure 56. edge), the device takes no action. This condition provides reliable serial communication. Furthermore, this condition also provides a way to quickly reset the The PGA uses a standard serial peripheral interface SPI interface to a known starting condition for data (SPI). Both SPI Mode 0,0 and Mode 1,1 are synchronization. Transmitted data are latched supported, as shown in Figure and described in internally on the rising edge of CS. Table If there are not even-numbered increments of clocks (that is, 16, 32, 64, and so forth) between CS going low (falling edge) and CS going high (rising Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS SCLK DIN DOUT CS SCLK DIN DOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

10 A/c109

www.ti.com Figure 57. SPI Mode 0,0 and Mode 1,1 Table SPI Mode Setting (1) Clock idles low Data are read on the rising edge of clock. Data change on the falling edge of clock. (2) Clock idles high Data are read on the rising edge of clock. Data change on the falling edge of clock. (1) CPHA means sample on first clock edge (rising or falling) after a valid CS (2) CPHA means sample on second clock edge (rising or falling) after a valid CS On the PGA116/PGA117, CS DIN, and SCLK are Schmitt-triggered CMOS logic inputs. DIN has a weak internal pull-down to support daisy-chain communications on the PGA116/PGA117. DOUT is a CMOS logic output. When CS is high, the state of DOUT is high-impedance. When CS is low, DOUT is driven as illustrated in Figure On the PGA112/PGA113, there are digital output and digital input gates both internally connected to the DIO pin. DIN is an input-only gate and DOUT is a digital output that can give a 3-state output. The DIO pin has a weak µ A pull-down current source to prevent the pin from floating in systems with a high-impedance SPI DOUT line. When CS is high, Figure 58. Digital I/O Structure PGA116/PGA117 the state of the internal DOUT gate is high-impedance. When CS is low, the state of DIO depends on the previous valid SPI communication; either DIO becomes an output to clock out data or it remains an input to receive data. This structure is shown in Figure Figure 59. Digital I/O Structure PGA112/PGA113 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

INTERFACE: PGA112/PGA113 ONLY Hi-Z CS SCLK DIN DOUT Hi-Z D15 D14 D13 D12 D11 D10 G0 CH3 CH2 CH1 CH0 D15 D14 D13 D12 D11 D10 DIOPin D15 Hi-Z CS SCLK DIN DOUT D14 D13 D12 D11 D10 DIOPin Hi-Z CS SCLK DIN DOUT D15 D14 D13 D12 D11 D10 D8 D7 DIOPin Hi-Z CS SCLK DIN DOUT Hi-Z D15 D14 D13 D12 D11 D10 D4 D3 G0 CH3 CH2 CH1 CH0 D15 D14 D13 D12 D11 D10 DIOPin PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 Figure 60. SPI Serial Interface Timing Diagrams Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

COMMANDS: PGA112/PGA113 ONLY PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com Table SPI Commands (PGA112/PGA113) (1) (2) THREE-WIRE D15 D14 D13 D12 D11 D10 SPI COMMAND READ CH3 CH2 CH1 CH0 WRITE NOP WRITE SDN_DIS WRITE SDN_EN WRITE (1) SDN Shutdown mode. Enter Shutdown mode by issuing an SDN_EN command. Shutdown mode is cleared (returned to the last valid write configuration) by a SDN_DIS command or by any valid Write command. (2) POR (power-on-reset) value of internal Gain/Channel Select Register is all 0s. This value sets Gain and Channel V CAL /CH0. Table Gain Selection Bits (PGA112/PGA113) BINARY GAIN SCOPE GAIN 100 128 200 Table MUX Channel Selection Bits (PGA112/PGA113) PGA112 CH3 CH2 CH1 CH0 PGA113 V CAL /CH0 CH1 X (1) X X X X X X X Factory Reserved X CAL1 (2) CAL2 (3) CAL3 (4) CAL4 (5) (1) X channel is not used. (2) CAL1: connects to GND. (3) CAL2: connects to 0.9V CAL (4) CAL3: connects to 0.1V CAL (5) CAL4: connects to V REF Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

AMP: INPUT STAGE Input□Voltage□(V) Input□Offset□V oltage□( V) /c109 10 62 3 4 5 AV =□5VDD PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 PMOS transistors. The result of this transition appears as a small input offset voltage transition that is reflected to the output by the selected PGA gain. The PGA112/PGA113 and PGA116/PGA117 are This transition may be either increasing or single-ended input, single-supply, programmable gain decreasing, and differs from part to part as described amplifiers with an input multiplexer. Multiplexer in Figure and Figure These figures illustrate channel selection and gain selection are done possible differences in input offset voltage between through a standard SPI interface. The two different devices when used with AV DD +5V. PGA112/PGA113 have a two-channel input MUX and Because the exact transition region varies from the PGA116/PGA117 have a 10-channel input MUX. device to device, the Electrical Characteristics table The PGA112 and PGA116 provide binary gain specifies an input offset voltage above and below this selections (1, 16, 32, 64, 128) and the input transition region. PGA113 and PGA117 provide scope gain selections (1, 10, 20, 50, 100, 200). All models use a split-supply architecture with an analog supply, AV DD and a digital supply, DV DD This split-supply architecture allows for ease of interface to analog-to-digital converters (ADCs) and microcontrollers in mixed-supply voltage systems, such as where the analog supply is +5V and the digital supply is +3V. Four internal calibration channels are provided for system-level calibration. The channels are tied to GND, 0.9V CAL 0.1V CAL and V REF respectively. V CAL an external voltage connected to V CAL /CH0, acts as the system calibration reference. If V CAL is the system ADC reference, then gain and offset calibration on the ADC are easily accomplished through the PGA using only one MUX input. If calibration is not used, then V CAL /CH0 can be used as a standard MUX input. All four versions provide a V REF pin that can be tied to Figure 61. PGA Rail-to-Rail Input Stage ground or, for ease of scaling, to midsupply in single-supply systems where midsupply is used as a virtual ground. The PGA112/PGA113 offer a software-controlled shutdown feature for low standby power. The PGA116/PGA117 offer both hardware- and software-controlled shutdown for low standby power. The PGA112/PGA113 have a three-wire SPI digital interface; the PGA116/PGA117 have a four-wire SPI digital interface. The PGA116/117 also have daisy-chain capability. The PGA op amp is a rail-to-rail input and output (RRIO) single-supply op amp. The input topology uses two separate input stages in parallel to achieve rail-to-rail input. As Figure shows, there is a PMOS transistor on each input for operation down to ground; there is also an NMOS transistor on each Figure 62. V OS versus Input Voltage Case input in parallel for operation to the positive supply rail. When the common-mode input voltage (that is, the single-ended input, because this PGA is configured internally for noninverting gain) crosses a level that is typically about 1.5V below the positive supply, there is a transition between the NMOS and Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

G□=□1 PGA112 PGA113 VREF V /2S VIN0 VIN1 VOUT CH0 CH1 MUX /c45 VOUT0 =□G V AV /2 (G 1)/c180 /c45 /c180 /c45 IN0 DD (2) Input□Voltage□(V) Input□Offset□V oltage□( V) /c109 /c45 /c45 /c45 10 62 3 4 5 AV =□5VDD OP AMP: GENERAL GAIN EQUATIONS V =□G V + /2,□where: /2□<□G V <□+ /2 /c180 /c45OUT1 IN1 DD /c45 /c180 /c180 /c45 /c180 AV AV AV AV DD OUT1 IN1 DD DD IN1 DD RI RF G□=□1 PGA112 PGA113 VREF VIN VOUT CH1 V =□G V /c180OUT IN (1) PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com Figure 65. PGA112/PGA113 Configuration for Positive and Negative Excursions Around Midsupply Virtual Ground When: G Figure 63. V OS versus Input Voltage Case Then: V OUT0 G V IN0 Figure shows the basic configuration for using the PGA112/113 as a gain block. V OUT IN is the selected (3) noninverting gain, depending on the model selected, Where: for either binary or scope gains. G 16, 32, 64, and 128 (binary gains) G 10, 20, 50, 100, and 200 (scope gains) Table details the internal typical values for the op amp internal feedback resistor F and op amp internal input resistor I for both binary and scope gains. Table Typical R F and R I versus Gain Binary Scope Gain Gain Figure 64. PGA112/PGA113 Used as a Gain Block (V/V) R F Ω R I Ω (V/V) R F Ω R I Ω 3.25k 3.25k 3.25k 3.25k 3.25k 3.25k Where: 9.75k 3.25k 13k 3.25k G 16, 32, 64, and 128 (binary gains) 22.75k 3.25k 29.25k 3.25k G 10, 20, 50, 100, and 200 (scope 48.75k 3.25k 61.75k 3.25k gains) 100.75k 3.25k 159.25k 3.25k Figure shows the PGA configuration and gain 204.75k 3.25k 100 321.75k 3.25k equations for V REF AV DD /2. V OUT0 is V OUT when 128 412.75k 3.25k 200 646.75k 3.25k CH0 is selected and V OUT1 is V OUT when CH1 is selected. Notice the V REF pin has no effect for G because the internal feedback resistor, R F is shorted out. This configuration allows for positive and negative voltage excursions around a midsupply virtual ground. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

AMP: FREQUENCY RESPONSE VERSUS ANALOG MUX /c45 6 (4) Example: PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 GAIN The analog input MUX provides two input channels Table documents how small-signal bandwidth and for the PGA112/PGA113 and input channels for slew rate change correspond to changes in PGA the PGA116/PGA117. The MUX switches are gain. designed to be break-before-make and thereby eliminate any concerns about shorting the two input Full power bandwidth (that is, the highest frequency signal sources together. that a sine wave can pass through the PGA for a given gain) is related to slew rate by Equation Four internal MUX CAL channels are included in the analog MUX for ease of system calibration. These CAL channels allow ADC gain and offset errors to be calibrated out. This calibration does not remove the Where: offset and gain errors of the PGA for gains greater SR Slew rate in µ s than but most systems should see a significant f Frequency in Hz increase in the ADC accuracy. In addition, these CAL V OP Output peak voltage in volts channels can be used by the ADC to read the minimum and maximum possible voltages from the PGA. With these minimum and maximum levels known, the system architecture can be designed to For G then SR 10.6V/ µ s (slew rate rise is indicate an out-of-range condition on the measured minimum slew rate). analog input signals if these levels are ever For a system, choose 0.1V V OUT 4.9V or measured. V OUTPP 4.8V or V OUTP 2.4V. To use the CAL channels, V CAL /CH0 must be SR (V/ µ π f V OP permanently connected to the system ADC reference. 10.6 π f (2.4) f 702.9kHz There is a typical 100k Ω load from V CAL /CH0 to This example shows that a G configuration ground. Table illustrates how to use the CAL can produce a 4.8V PP sine wave with frequency channels with V REF ground. Table describes how up to 702.9kHz. This computation only shows the to use the CAL channels with V REF AV DD /2. The theoretical upper limit of frequency for this V REF pin must be connected to a source that is example, but does not indicate the distortion of low-impedance for both dc and ac in order to the sine wave. The acceptable distortion depends maintain gain and nonlinearity accuracy. Worst-case on the specific application. As a general current demand on the V REF pin occurs when G guideline, maintain two to three times the because there is a 3.25k Ω resistor between V OUT and calculated slew rate to minimize distortion on the V REF For a system with AV DD 2.5V, the V REF sine wave. For this example, the application pin buffer must source and sink 2.5V/3.25k Ω 0.7mA should only use G 4.8V PP up to a frequency minimum for a V OUT that can swing from ground to range of 234kHz to 351kHz, depending upon the +5V. acceptable distortion. For a given gain and slew rate requirement, check for adequate small-signal bandwidth (typical 3dB frequency) in order to assure that the frequency of the signal can be passed without attenuation. Table Frequency Response versus Gain L 100pF, R L 10k Ω 0.1% 0.01% 0.1% 0.01% TYPICAL SLEW SLEW SETTLING SETTLING TYPICAL SLEW SLEW SETTLING SETTLING 3dB RATE- RATE- TIME: TIME: SCOPE 3dB RATE- RATE- TIME: TIME: BINARY FREQUENCY FALL RISE PP PP GAIN FREQUENCY FALL RISE PP PP GAIN (V/V) (MHz) (V/ µ (V/ µ µ µ (V/V) (MHz) (V/ µ (V/ µ µ µ 2.55 2.55 3.8 6.4 2.6 3.8 6.4 2.6 12.8 10.6 2.6 1.8 12.8 10.6 2.6 1.8 12.8 10.6 2.6 1.8 12.8 10.6 2.2 2.6 1.6 12.8 12.8 2.3 2.6 1.3 12.8 9.1 2.3 2.8 1.8 12.8 13.3 2.3 0.9 9.1 7.1 2.4 3.8 0.6 3.5 100 0.38 3.5 4.4 128 0.35 2.5 2.5 4.8 200 0.23 2.3 6.9 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

G□=□1 RF RI Output Stage SPI Interface REF3225 SCLK DIO CS VOUT DVDDAVDD GND VREF MSP430 Microcontroller +3V +3V VREF PGA112 PGA113 V /CH0CAL CH1 CAL3 CAL4 CAL1 CAL20.1VCAL 0.9VCAL 10k/c87 80k/c87 MUX CAL2/3 2.5V ADC□Ref C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com Figure 66. Using CAL Channels with V REF Ground Table Using the MUX CAL Channels with V REF GND (AV DD 3V, DV DD 3V, ADC Ref 2.5V, and V REF GND) MUX GAIN OP AMP OP AMP FUNCTION SELECT SELECT MUX INPUT (+In) OUT MUX, op amp, and ADC can Minimum Signal CAL1 GND GND 50mV read. Op amp V OUT is limited by negative saturation. 90% ADC Ref for system 0.9 Gain Calibration CAL2 2.25V 2.25V full-scale or gain calibration CAL /CH0) of the ADC. Maximum signal level that the MUX, op amp, and ADC can read. Op amp V OUT is 0.9 Maximum Signal CAL2 2.25V 2.95V limited by positive saturation. CAL /CH0) System is limited by ADC max input of 2.5V (ADC Ref 2.5V). 0.1 10% ADC Ref for system Offset Calibration CAL3 0.25V 0.25V CAL /CH0) offset calibration of the ADC. Minimum signal level that the MUX, op amp, and ADC can Minimum Signal CAL4 V REF GND 50mV read. Op amp V OUT is limited by negative saturation. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

G□=□1 RF RI Output Stage SPI Interface SCLK DIO CS VOUT DVDDAVDD GND VREF MSP430 Microcontroller +3V +3V VREF PGA112 PGA113 V /CH0CAL CH1 CAL3 CAL4 CAL1 CAL20.1VCAL 0.9VCAL 10k/c87 80k/c87 MUX CAL2/3 ADC□Ref OPA364 R 10k/c87 F C 2.7nF F +3V CL2 0.1 F/c1090.1 F/c109RY 100k/c87 RX 100k/c87 +3V (1.5V) C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 Figure 67. Using CAL Channels with V REF AV DD Table Using the MUX CAL Channels with V REF AV DD (AV DD 3V, DV DD 3V, ADC Ref 3V, and V REF 1.5V) MUX GAIN OP AMP OP AMP FUNCTION SELECT SELECT MUX INPUT (+In) OUT MUX, Minimum Signal CAL1 GND GND 50mV op amp, and ADC can read. Op amp V OUT is limited by negative saturation. 0.9 90% ADC Ref for system full-scale or Gain Calibration CAL2 2.7V 2.7V CAL /CH0) gain calibration of the ADC. Maximum signal level that the MUX, 0.9 Maximum Signal CAL2 or 2.25V 2.95V op amp, and ADC can read. Op amp CAL /CH0) V OUT is limited by positive saturation. 0.1 10% ADC Ref for system offset Offset Calibration CAL3 0.3V 0.3V CAL /CH0) calibration of the ADC. V REF Check CAL4 V REF 1.5V 1.5V Midsupply voltage used as V REF Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

Transfer□Function with□Offset□Error□+□Gain□Error Transfer□Function with□Gain□Error□Only Ideal□Transfer□Function Gain□Error VFS_ACTUAL VFS_IDEAL Analog□Input Digital□Output V 1LSB /c45REF_ADC0V 0000h 0FFFh Offset□Error VZ_IDEAL VZ_ACTUAL PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com In practice, the zero input (0V) or full-scale input PGA112/PGA113 REF_ADC 1LSB) of ADCs cannot always be measured because of internal offset error and gain Analog-to-digital converters (ADCs) contain two major error. However, if measurements are made very close errors that can be easily removed by calibration at a to the full-scale input and the zero input, both zero system level. These errors are gain error and offset and full-scale can be calibrated very accurately with error, as shown in Figure Figure shows a the assumption of linearity from the calibration points typical transfer function for a 12-bit ADC. The analog to the desired end points of the ADC ideal transfer input is on the x-axis with a range from to function. For the zero calibration, choose REF_ADC 1LSB), where V REF_ADC is the ADC 10%V REF_ADC this value should be above the internal reference voltage. The y-axis is the hexadecimal offset error and sufficiently out of the noise floor equivalent of the digital codes that result from ADC range of the ADC. For the gain calibration, choose conversions. The dotted red line represents an ideal 90%V REF_ADC this value should be less than the transfer function with 0000h representing analog internal gain error and sufficiently below the tolerance input and 0FFFh representing an analog input of of V REF These key points can be summarized in this REF_ADC 1LSB). The solid blue line illustrates the way: offset error. Although the solid blue line includes both offset error and gain error, at an analog input of For zero calibration: the offset error voltage, V Z_ACTUAL can be measured. The ADC cannot read the ideal zero because of The dashed black line represents the transfer function offset error with gain error. The dashed black line is equivalent to Must be far enough above ground to be above the solid blue line without the offset error, and can be noise floor and ADC offset error measured and computed using V Z_ACTUAL and Therefore, choose 10%V REF_ADC for zero V Z_IDEAL The difference between the dashed black calibration line and the dotted red line is the gain error. Gain and offset error can be computed by taking zero input and For gain calibration: full-scale input readings. Using these error The ADC cannot read the ideal full-scale because calculations, compute a calibrated ADC reading to of gain error remove the ADC gain and offset error. Must be far enough below full-scale to be below the V REF tolerance and ADC gain error Therefore, choose 90%V REF_ADC for gain calibration Figure 68. ADC Offset and Gain Error Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

V 90□=□0.9(V )REF REF_ADC (5) V 10□=□0.1(V )REF REF_ADC (6) V 90□=□ADC at□V 90MEAS MEASUREMENT REF (7) V 10□=□ADC at□V 10MEAS MEASUREMENT REF (8) G =MEAS V 90 V 10/c45MEAS MEAS V 90 V 10/c45REF REF (9) O =□V 10 (V 10 G )/c45 /c180MEAS MEAS REF MEAS (10) V =□Any□V ADCAD_MEAS IN MEASUREMENT (11) V =ADC_CAL V O /c45AD_MEAS MEAS GMEAS (12) Ideal□Transfer□Function Transfer□Function with□Offset□Error□+□Gain□Error V =□+5VREF Offset□Error□=□+4LSB Gain□Error□=□+6LSB0FFFh□(4.99878V) (4.5114751443V) (0.5056191443V) 0000h□(0V) 0V VIN Digital□Output□(V ) AD_MEAS 0.5V (0.1 V )/c180 REF_ADC 4.5V (0.9 V )/c180 REF_ADC 4.99878V (V 1LSB)REF_ADC /c45 PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 The 12-bit ADC example in Figure illustrates the technique for calibrating an ADC using a 10%V REF_ADC and 90%V REF_ADC reading where V REF_ADC is the ADC reference voltage. Note that the 10%V REF reading also contains a gain error because it is not a V IN calibration point. First, use the Compute the ADC measured gain. The slope of 90%V REF and 10%V REF points to compute the the curve connecting the measured 10%V REF and measured gain error. The measured gain error is then measured 90%V REF point is computed and used to remove the gain error from the 10%V REF compared to the slope between the ideal reading, giving a measured 10%V REF number. The 10%V REF and ideal 90%V REF This result is the measured 10%V REF number is used to compute the measured gain. measured offset error. Compute the ADC measured offset. The measured offset is computed by taking the difference between the measured 10%V REF and the (ideal 10%V REF (measured gain). Compute the calibrated ADC readings. Any ADC reading can therefore be calibrated by removing the gain error and offset error. The measured offset is subtracted from the ADC reading and then divided by the measured gain to give a Figure 69. 12-Bit Example of ADC Calibration for corrected reading. If this calibration is performed on a Gain and Offset Error timed basis, relative to the specific application, gain and offset error over temperature are also removed from the ADC reading by calibration. The gain error and offset error in ADC readings can be calibrated by using 10%V REF_ADC and For example; given: 90%V REF_ADC calibration points. Because the 12-Bit ADC calibration is ratiometric to V REF_ADC the exact value ADC Gain Error +6LSB of V REF_ADC does not need to be known in the end ADC Offset Error +4LSB application. ADC Reference REF_ADC +5V Follow these steps to compute a calibrated ADC Temperature +25 C reading: Take the ADC reading at V IN 90% V REF and Table shows the resulting system accuracy. V IN 10% V REF The ADC readings for 10%V REF and 90%V REF are taken. Table 10. Bits of System Accuracy (1) (to 0.5LSB) ADC ACCURACY WITHOUT ADC ACCURACY WITH PGA112 V IN CALIBRATION CALIBRATION 10%V REF_ADC 8.80 Bits 12.80 Bits 90%V REF_ADC 7.77 Bits 11.06 Bits (1) Difference in maximum input offset voltage for V IN 10%V REF_ADC and V IN 90%V REF_ADC is the reason for different accuracies. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

APPLICATIONS: GENERAL-PURPOSE INPUT VOUT CH1 DVDD AVDD VREF V /2S (+2.5V) VS (+5V) CH0 VIN0 200mVPP MUXRA VREF_ADC RB RX PGA112 PGA113 G□=□1 +100mV /c45100mV +2.5V +2.6V +2.4V +2.5V +4.5V +0.5V VOUT0 VIN0 VCH0 CA VIN1 RA RF RI G□=□20 /c45 +4.9625V +37.5mV VOUT1 PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com Table summarizes the scaling resistor values for SCALING R A R X and R B for different ADC Ref voltages. V REF_ADC is the reference voltage used for the ADC Figure is an example application that connected to the PGA112/PGA113 output. It is demonstrates the flexibility of the PGA for assumed the ADC input range is to V REF_ADC The general-purpose input scaling. V IN0 is a 100mV input Bipolar Input to Single-Supply Scaling section gives that is ac-coupled into CH0. The PGA112/PGA113 is the algorithm to compute resistor values for powered from a +5V supply voltage, V S and references not listed in Table As a general configured with the V REF pin connected to V S guideline, R B should be chosen such that the input (+2.5V). V CH0 is the 100mV input, level-shifted and on-channel current multiplied by R B is less than or centered on V S (+2.5V). A gain of is applied to equal to the input offset voltage. This value ensures CH0, and because of the PGA113 configuration, the that the scaling network contributes no more error output voltage at V OUT is centered on V S than the input offset voltage. Individual (+2.5V). may require other design trade-offs. CH1 is set to G through a resistive divider and scalar network, we can read or 0V. This setting provides bipolar to single-ended input scaling. Figure 70. General-Purpose Input Scaling Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 Table 11. Bipolar to Single-Ended Input Scaling (1) (2) V REF_ADC (V) V IN1 (V) CH1 INPUT R A Ω R X Ω R B Ω 2.5 0.047613 9.2 4.81k 1.247613 2.447613 2.5 0.050317 3.16 2.4k 1.250317 2.450317 0.058003 13.5 5.76k 1.498003 2.938003 0.059303 4.02 2.87k 1.499303 2.939303 4.096 0.082224 7.87k 2.048304 4.014384 4.096 0.086018 6.49 3.92k 2.052098 4.018178 0.093506 965 2.493506 4.893506 0.095227 9.2 4.81k 2.495227 4.895227 (1) Scaling is based on 0.02(V REF_ADC to 0.98(V REF_ADC using standard 0.1% resistor values. (2) Assumes symmetrical V IN and symmetrical scaling for CH1 input minimum and maximum. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

R =A

2 R g/c180 /c180 B

9.23077k =/c87 2 10k 0.315789474/c180 /c87 /c180 1 0.315789474/c45 R =X R RB A/c180 R +□RB A 4.81k =/c87 10k 9.23077k/c87 /c180 /c87 10k +□9.23077k/c87 /c87 R 10k/c87 B RX 4.81k/c87 RA 9.2k/c87 CH1□Input (2.447817V, 0.0474093V) VIN1 (+5V, 5V)/c45 VREF_ADC (2.5V) APPLICATIONS: HIGH GAIN/WIDE k =□k k 0.96□=□0.98 0.02 /c45VO VO+ VO /c45 /c45 g□= k V /c180VO REF_ADC 2 |V | k /c45 /c180/c180 VREF_ADCIN1 VO 0.315789474□= 0.96 2.5/c180 2 5 0.96 2.5/c45 /c180/c180 PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com Note that this process assumes a symmetrical V IN1 and that symmetrical scaling is used for CH1 input minimum and maximum values. The following steps give the algorithm to compute resistor values for references not listed in Table R X can now be computed from the starting value of R B and the computed value for R A Step Choose the following: V REF_ADC 2.5V (ADC reference voltage) V IN1 (magnitude of V IN assuming scaling is for V IN1 Choose R B as a standard resistor value. The input on-channel current multiplied by R B should be less than the input offset voltage, such that R B is not a major source of inaccuracy. R B 10k Ω (select as a starting value for resistors) For the most negative V IN1 choose the percentage (in decimal format) of V REF_ADC desired at the ADC input. k VO 0.02 (CH1 input k VO V REF_ADC when V IN1 V IN1 For the most positive V IN1 choose the percentage Figure 71. Bipolar to Single-Ended Input Algorithm (in decimal format) of V REF_ADC desired at the ADC input. Since this scaling is based on symmetry, k VO+ must be the same percentage away from V REF_ADC at the upper limit as at the BANDWIDTH CONSIDERATIONS lower limit where k VO is computed. As a result of the combination of wide bandwidth and k VO+ k VO high gain capability of the PGA112/PGA113 and PGA116/PGA117, there are several printed circuit k VO+ 0.02 0.98 board (PCB) design and system recommendations to consider for optimum application performance. (CH1 input k VO+ V REF_ADC when V IN1 IN1 Power-supply bypass. Bypass each Step Compute the following: power-supply pin separately. Use a ceramic To simplify analysis, create one constant called capacitor connected directly from the k VO power-supply pin to the ground pin of the IC on the same PCB plane. Vias can then be used to connect to ground and voltage planes. This configuration keeps parasitic inductive paths out A constant, is created to simplify resistor value of the local bypass for the PGA. Good analog computations. design practice dictates the use of a large value tantalum bypass capacitor on the PCB for each respective voltage. R A is now selected from the starting value of R B and the g constant. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

APPLICATIONS: DRIVING/INTERFACING TO 10k/c87 CDAC□SAR ADC G□=□1 RF RI Output Stage SPI Interface SCLK DIO CS VOUT5 DVDD AVDD GND VREF +3V +5V VREF PGA112 PGA113 (MSOP-10) V /CH0CAL 2CH1 CAL3 CAL4 CAL1 CAL20.1VCAL 0.9VCAL 10k/c87 80k/c87 MUX CAL2/3 R 100/c87 FILT CFILT (1nF) CSH 40pF 12-Bit□Settling 500kHz 16-Bit□Settling 300kHz /c174 /c174 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 C 0.1 F BYPASS /c109 PGA112 PGA113 PGA116 PGA117 www.ti.com SBOS424A MARCH 2008 REVISED JUNE 2008 Signal trace routing. Keep V OUT and other low Bypass capacitors greater than 100pF are impedance traces away from MUX channel inputs recommended. Lower impedances and a bypass that are high impedance. Poor signal routing can capacitor placed directly at the input MUX cause positive feedback, unwanted oscillations, channels keep crosstalk between channels to a or excessive overshoot and ringing on minimum as a result of parasitic capacitive step-changing signals. If the input signals are coupling from adjacent PCB traces and pin-to-pin particularly noisy, separate MUX input channels capacitance. with guard traces on either side of the signal traces. Connect the guard traces to ground near the PGA and at the signal entry point into the ADCS PCB. On multilayer PCBs, ensure that there are CDAC SAR ADCs contain an input sampling no parallel traces near MUX input traces on capacitor, C SH to sample the input signal during a adjacent layers; capacitive coupling from other sample period as shown in Figure After the layers can be a problem. Use ground planes to sample period, C SH is removed from the input signal. isolate MUX input signal traces from signal traces Subsequent comparisons of the charge stored on C SH on other layers. are performed during the ADC conversion process. Additionally, group and route the digital signals To achieve optimal op amp stability, input signal into the PGA as far away as possible from the settling, and the demands for charge from the input analog MUX input signals. Most digital signals signal conditioning circuitry, most ADC a resistor FILT and drive capability that can easily couple into the capacitor FILT filter placed between the op amp high-impedance inputs of the input MUX output and ADC input. For the PGA112/PGA113, channels. This coupling can create unwanted setting C FILT 1nF and R FILT 100 Ω yields optimum noise that gains up to V OUT system performance for sampling converters operating at speeds up to 500kHz, depending upon Input MUX channels and source impedance. the application settling time and accuracy Input MUX channels are high-impedance; when requirements. combined with high gain, the channels can pick up unwanted noise. Keep the input signal sources low-impedance 10k Ω Also, consider bypassing input MUX channels with a ceramic bypass capacitor directly at the MUX input pin. Figure 72. Driving/Interfacing to ADCs Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113

(POR) 10k/c87 ADC G□=□1 RF RI Output Stage SPI Interface SCLK DIO CS VOUT5 DVDD AVDD GND VREF MSP430 Microcontroller +3V +5V VREF PGA112 PGA113 (MSOP-10) VCAL/CH0 CH1 CAL3 CAL4 CAL1 CAL20.1VCAL 0.9VCAL 10k/c87 80k/c87 MUX CAL2/3 PGA112 PGA113 PGA116 PGA117 SBOS424A MARCH 2008 REVISED JUNE 2008 www.ti.com At initial power-on, the state of the PGA is G and Channel active. CAUTION: For most applications, Figure shows a typical mixed-supply voltage set AV DD DV DD to prevent V OUT from driving system where the analog supply, AV DD is +5V and current into AV DD and raising the voltage level of the digital supply voltage, DV DD is +3V. The analog AV DD output stage of the PGA and the SPI interface digital circuitry are both powered from DV DD When considering the power required for DV DD use the Electrical Characteristics table and add any load The PGA112/PGA113 have a software shutdown current anticipated on V OUT this load current must be mode, and the PGA116/PGA117 offer both a provided by DV DD This split-supply architecture hardware and software shutdown mode. When the ensures compatible logic levels with the PGA is shut down, it goes into a low-power standby microcontroller. It also ensures that the PGA output mode. The Electrical Characteristics table details the cannot run the input for the onboard ADC into an current draw in shutdown mode with and without the overvoltage condition; this condition could cause SPI interface being clocked. In shutdown mode, R F device latch-up and system lock-up, and require and R I remain connected between V OUT and V REF power-supply sequencing. Each supply pin should be When DV DD is less than 1.6V, the digital interface is individually bypassed with a 0.1 µ F ceramic capacitor disabled and the channel and gain selections are directly at the device to ground. If there is only one held to the respective POR states of Gain and power supply in the system, AV DD and DV DD can both Channel V CAL /CH0. When DV DD is above 1.8V, the be connected to the same supply; however, it is digital interface is enabled and the POR gain and recommended to use individual bypass capacitors channel states remain unchanged until a valid SPI directly at each respective supply pin to a single point communication is received. ground. V OUT is diode-clamped to AV DD (as shown in Figure therefore, set DV DD less than or equal to AV DD 0.3V. DV DD and AV DD must be within the operating voltage range of +2.2V to +5.5V. Figure 73. Split Power-Supply Architecture: AV DD DV DD Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PGA112 PGA113

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PGA112AIDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA112AIDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA112AIDGST ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA112AIDGSTG4 ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA113AIDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA113AIDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA113AIDGST ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA113AIDGSTG4 ACTIVE MSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PGA116AIPW PREVIEW TSSOP PW 20 70 TBD Call TI Call TI PGA116AIPWR PREVIEW TSSOP PW 20 2000 TBD Call TI Call TI PGA117AIPW PREVIEW TSSOP PW 20 70 TBD Call TI Call TI PGA117AIPWR PREVIEW TSSOP PW 20 2000 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA112AIDGSR MSOP DGS 10 2500 370.0 355.0 55.0 PGA112AIDGST MSOP DGS 10 250 370.0 355.0 55.0 PGA113AIDGSR MSOP DGS 10 2500 370.0 355.0 55.0 PGA113AIDGST MSOP DGS 10 250 195.0 200.0 45.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Jul-2008 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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