PGA103P

PGA103 BURR-BROWN | Alldatasheet

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Technical content

FEATURES

l DIGITALLY PROGRAMABLE GAINS: G=1, 10, 100V/V l CMOS/TTL-COMPATIBLE INPUTS l LOW GAIN ERROR: ±0.05% max, G=10 l LOW OFFSET VOLTAGE DRIFT: 2 µV/°C l LOW QUIESCENT CURRENT: 2.6mA l LOW COST l 8-PIN PLASTIC DIP, SO-8 PACKAGES

APPLICATIONS

l DATA ACQUISITION SYSTEMS l GENERAL PURPOSE ANALOG BOARDS l MEDICAL INSTRUMENTATION

DESCRIPTION

The PGA103 is a programmable-gain amplifier for general purpose applications. Gains of 1, 10, or 100 are digitally selected by two CMOS/TTL-compatible in- puts. The PGA103 is ideal for systems that must handle wide dynamic range signals. The PGA103’s high speed circuitry provides fast set- tling time, even at G=100 (8µs to 0.01%). Bandwidth is 250kHz at G=100, yet quiescent current is only 2.6mA. It operates from ±4.5V to ±18V power supplies. The PGA103 is available in 8-pin plastic DIP and SO-8 surface-mount packages, specified for the –40°C to +85°C temperature range. PGA103VIN VO V+ V– 100 GAIN A 1 A 0 VO = G • VIN International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1993 Burr-Brown Corporation PDS-1208B Printed in U.S.A. November, 1993

TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise specified. PGA103P, U PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT Offset Voltage, RTI G = 1 T A = +25°C ±200 ±1500 µV G = 10 ±100 ±500 µV G = 100 ±100 ±500 µV vs Temperature T A = TMIN to TMAX G = 1 ±5 µV/°C G = 10 ±2 µV/°C G = 100 ±2 µV/°C vs Power Supply V S = ±4.5V to ±18V G = 1 30 70 µV/V G = 10 10 35 µV/V G = 100 10 35 µV/V Impedance 108 || 2 Ω || pF INPUT BIAS CURRENT Initial Bias Current ±50 ±150 nA vs Temperature ±100 pA/ °C NOISE VOLTAGE, RTI G = 100, RS = 0Ω f = 10Hz 16 nV/ √Hz f = 100Hz 11 nV/ √Hz f = 1kHz 11 nV/ √Hz fB = 0.1Hz to 10Hz 0.6 µVp-p NOISE CURRENT f = 10Hz 2.8 pA/ √Hz f = 1kHz 0.3 pA/ √Hz fB = 0.1Hz to 10Hz 76 pAp-p GAIN Gain Error Gain vs Temperature G = 1 ±2 ppm/ °C G = 10 ±10 ppm/ °C G = 100 ±30 ppm/ °C Nonlinearity G = 1 ±0.001 ±0.003 % of FSR G = 10 ±0.002 ±0.005 % of FSR G = 100 ±0.004 ±0.01 % of FSR OUTPUT Voltage, Positive (V+) –3.5 (V+) –2.5 V Negative (V–) +3.5 (V–) +2.5 V Load Capacitance, max 1000 pF Short-Circuit Current ±25 mA FREQUENCY RESPONSE Bandwidth, –3dB G = 1 1.5 MHz G = 10 750 kHz G = 100 250 kHz Slew Rate V O = ±10V 9 V/ µs Settling Time, 0.1% G = 1 2 µs G = 10 2.2 µs G = 100 6.5 µs Settling Time, 0.01% G = 1 2.5 µs G = 10 2.5 µs G = 100 8 µs Overload Recovery 50% Overdrive 2.5 µs DIGITAL LOGIC INPUTS Digital Low Voltage –5.6 0.8 V Digital Low or High Current 1 µA Digital High Voltage 2V + V

SPECIFICATIONS (CONT) ELECTRICAL TA = +25°C, VS = ±15V, RL = 2kΩ unless otherwise specified. PGA103P, U PARAMETER CONDITIONS MIN TYP MAX UNITS POWER SUPPLY Voltage Range ±4.5 ±15 ±18 V Current V IN = 0V ±2.6 ±3.5 mA TEMPERATURE RANGE Specification –40 +85 °C Operating –40 +125 °C θJA: P or U Package 100 °C/W The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. Top View DIP/SO-8 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

PACKAGE INFORMATION

MODEL PACKAGE NUMBER (1) PGA103P 8-Pin Plastic DIP 006 PGA103U SO-8 Surface-Mount 182 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. VO NC Ground VIN ELECTROSTATIC DISCHARGE SENSITIVITY Any integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with ap- propriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published speci- fications.

ORDERING INFORMATION

MODEL PACKAGE TEMPERATURE RANGE PGA103P 8-Pin Plastic DIP –40 °C to +85°C PGA103U SO-8 Surface-Mount –40 °C to +85°C

3A, 3B, 3C(1) Ground 4A, 4B, 4C(2) VIN 6V – O 8V + PGA103 DIE TOPOGRAPHY 6 NC NC 4B4A3C3B3A2 NC: No Connection NOTES: (1) Connect all three indicated pads. (2) Connect all three indicated pads. Substrate Bias: Internally connected to V– power supply. MECHANICAL INFORMATION MILS (0.001") MILLIMETERS Die Size 69 x 105 ±5 1.75 x 2.67 ±0.13 Die Thickness 20 ±3 0.51 ±0.08 Min. Pad Size 4 x 4 0.1 x 0.1 Backing Gold TYPICAL PERFORMANCE CURVES TA = +25°C, VS = ±15V unless otherwise noted. NC NC NC POWER SUPPLY REJECTION vs FREQUENCY Frequency (Hz) Power Supply Rejection (dB) 120 100 10 100 1k 10k 100k 1M G=1 G=100 G=10 VOLTAGE GAIN vs FREQUENCY 10k 100k 1M 10M Frequency (Hz) Voltage Gain (dB) G=100 G=10 G=1 –10

TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = ±15V unless otherwise noted. SMALL SIGNAL RESPONSE 2µs/div 50mV/div G=1 G=10 G=100 Current Noise (pA/√Hz) Voltage Noise (nV/√Hz) QUIESCENT CURRENT vs TEMPERATURE –50 –25 0 25 50 75 100 125 Temperature (°C) Quiescent Current (mA) LARGE SIGNAL RESPONSE 2µs/div 5V/div G=100 G=10 G=1 INPUT VOLTAGE NOISE vs FREQUENCY 1000 100 1 10 100 1k 10k 100k 1M Frequency (Hz) G=1 G=10 G=100 Bandwidth Limited INPUT CURRENT NOISE vs FREQUENCY 0.1 1 10 100 1k 10k 100k 1M Frequency (Hz) All Gains 100

APPLICATION INFORMATION

Figure 1 shows the basic connections required for operation of the PGA103. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. Some applications select gain of the PGA103 with switches or jumpers. Figure 2 shows pull-up resistors connected to assure a noise-free logic “1” when the switch or jumper is off or open. Fixed-gain applications can connect the logic inputs directly to V+ or ground (or other valid logic level) without a series resistor. OFFSET TRIMMING Offset voltage is laser-trimmed to typically less than 200µV (referred to input) in all three gains. The input-referred offset voltage can be different for each gain. FIGURE 2. Switch or Jumper-Selected Gains. logic threshold voltage will be affected by the trim voltage. FIGURE 3. Offset Voltage Trim Circuit.

1 Closed Closed

10 Closed Open

100 Open Closed

logic inputs are referenced to the ground terminal, pin 3. selected gain (see settling time specifications). FIGURE 1. Basic Connections. Logic voltages referred to pin 3.