PFE850-12-054NA

PFE850-12-054XA_18 BEL | Alldatasheet

Document overview

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Technical content

The PFE850-12-054xA is a 850 Watt, AC to DC power-factor-corrected (PFC) power supply that converts standard AC mains power into a main output of 12 VDC for powering intermediate bus architectures (IBA) in high performance and reliability servers, routers, and network switches. The PFE85 0-12-054xA meets international safety standards and displays the CE-Mark for the European Low Voltage Directive (LVD).

• Best-in-class, 80 PLUS certified “Platinum” efficiency
• Wide input voltage range: 90-264 VAC
• AC input with power factor correction
• Always-On 16.5 W programmable standby output (3.3/5 V)
• Hot-plug capable
• Parallel operation with active digital current sharing
• Full digital controls for improved performance
• High density design: 19.8 W/in3
• Small form factor: 54.5 x 40.0 x 321.5 mm
• I2C communication interface for control, programming and monitoring with PSMI and PMBus® protocol
• Overtemperature, output overvoltage and overcurrent protection
• 256 Bytes of EEPROM for user information
• 2 Status LEDs: AC OK and DC OK with fault signaling
• High Performance Servers
• Routers
• Switches Disclaimer: PMBus is a registered trademark of SMIF, Inc.

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end is fan cooled and ideally suited for server integration with a matching airflow path. unity power factor over a wide operating range. on the output ensures no reverse load current and renders the supply ideally suited for operation in redundant power systems. controllers. Its protection with an active OR-ing device provides for maximum reliability. I2C bus. It allows full monitoring of the supply, including input and output voltage, current, power, and inside temperatures. power demand and supply temperature and can be overridden through the I2C bus. Figure 1. PFE850-12-054xA Block Diagram cause permanent damage to the supply.

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions & Protection BCD.00040_AI General Condition: TA = 0… 45 °C unless otherwise noted. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Vi nom Nominal Input Voltage 100 230 230 VAC Vi Input Voltage Ranges Normal operating (Vi min to Vi max) 90 264 VAC Vi red Derated Input Voltage Range See Figure 20 and Figure 41 90 115 VAC Ii max Max Input Current 13 Arms Ii p Inrush Current Limitation Vi min to Vi max, TNTC = 25°C (Figure 5) 40 Ap Fi Input Frequency 47 50/60 64 Hz PF Power Factor Vi nom, 50 Hz, > 0.3 I1 nom 0.96 W/VA Vi on Turn-on Input Voltage1) Ramping up 80 87 VAC Vi off Turn-off Input Voltage1) Ramping down 75 85 VAC η Efficiency without Fan Vi nom, 0.1∙Ix nom, Vx nom, TA = 25°C 89.7 Vi nom, 0.2∙Ix nom, Vx nom, TA = 25°C 93.1 Vi nom, 0.5∙Ix nom, Vx nom, TA = 25°C 94.4 Vi nom, Ix nom, Vx nom, TA = 25°C 93.9 Thold Hold-up Time After last AC zero point, V1 > 10.8 V, VSB within regulation, Vi = 230 VAC, Px nom 12 ms 1) The Front-End is provided with a minimum hysteresis of 3 V during turn-on and turn-off within the ranges.

4.1 INPUT FUSE

Quick-acting 16 A input fuses (5 x 20 mm) in series with both the L- and N-line inside the power supply protect against severe defects. The fuses are not accessible from the outside and are therefore not serviceable parts.

4.2 INRUSH CURRENT

The AC-DC power supply exhibits an X-capacitance of only 3.2 μF, resulting in a low and short peak current, when the supply is connected to the mains. The internal bulk capacitor will be charged through an NTC which will limit the inrush current. NOTE: Do not repeat plug-in / out operations within a short time, or else the internal in -rush current limiting device (NTC) may not sufficiently cool down and excessive inrush current or component failure(s) may result.

4.3 INPUT UNDER-VOLTAGE

If the sinusoidal input voltage stays below the input undervoltage lockout threshold Vi on, the supply will be inhibited. Once the input voltage returns within the normal operating range, the supply will return to normal operation again.

4.4 POWER FACTOR CORRECTION

Power factor correction (PFC) is achieved by controlling the input current waveform synchronously with the input voltage. A fully digital controller is implemented giving outstanding PFC results over a wide input voltage and load ranges. The input current will follow the shape of the input voltage. If for instance the input voltage has a trapezoidal waveform, then the current will also show a trapezoidal waveform. In addition, the PFC circuit has a stability region to be observed when operating the power supply at high input current amplitudes. At a low source inductance (<150 μH) the power supply will work stable up to its full maximum input current (13 Arms). If the source inductance is higher, the region with stable PFC operation is slightly reduced (as shown in Figure 4). The power supply will also work in the unstable region, but it may exhibit a slight current oscillation during the sinusoidal peak.

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4.5 EFFICIENCY

operating temperature regardless of the ambient temperature and load conditions. Figure 2. Efficiency vs. Load current (ratio metric loading) Figure 3. Power factor vs. Load current Figure 4. PFC Stability region Figure 5. Inrush current, Vin = 230Vac, 90°

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions & Protection BCD.00040_AI PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Main Output V1 V1 nom Nominal Output Voltage 0.5 ∙I1 nom, Tamb = 25 °C

12.0 VDC

V1 set Output Setpoint Accuracy -0.5 +0.5 % V1 nom dV1 tot Total Regulation Vi min to Vi max, 0 to 100% I1 nom, Ta min to Ta max -1 +1 % V1 nom P1 nom Nominal Output Power V1 = 12 VDC 840 W I1 nom Nominal Output Current V1 = 12 VDC 70 ADC v1 pp Output Ripple Voltage V1 nom, I1 nom, 20 MHz BW (See Section 6.1) 150 mVpp dV1 Load Load Regulation Vi = Vi nom, 0 - 100 % I1 nom 47 mV dV1 Line Line Regulation Vi =Vi min…Vi max 0 mV I1 max Current Limitation PFE850-12-054NA Ta < 45 °C 74 78 ADC Current Limitation PFE850-12-054RA Vi > 145 VAC, Ta < 45 °C 71 75 Vi > 90 VAC, Ta < 45 °C 66 70 dIshare Current Sharing Deviation from I1 tot / N, I1 > 10% -3 +3 A dVdyn Dynamic Load Regulation ΔI1 = 50% I1 nom, I1 = 5 … 100% I1 nom, dI1/dt = 1A/μs, recovery within 1% of V1 nom -0.6 0.6 V Trec Recovery Time 1 ms tAC V1 Start-up Time from AC V1 = 10.8 VDC (see Figure 7) 2 sec tV1 rise Rise Time V1 = 10…90% V1 nom (see Figure 8) 1 10 ms CLoad Capacitive Loading Ta = 25°C 30000 μF Standby Output VSB VSB nom Nominal Output Voltage 0.5 ∙ISB nom, Tamb = 25°C VSB_SEL = 1 3.3 VDC VSB set Output Setpoint Accuracy VSB_SEL = 0 5.0 VDC VSB_SEL = 0 / 1 -0.5 +0.5 %V1nom dVSB tot Total Regulation Vi min to Vi max, 0 to 100% ISB nom, Ta min to Ta max -1 +1 %VSBnom PSB nom Nominal Output Power VSB = 3.3 VDC, normal airflow 16.5 W VSB = 3.3 VDC, reverse airflow 11.5 VSB = 5.0 VDC, normal/reverse airflow 16.5 ISB nom Nominal Output Current VSB = 3.3 VDC, normal airflow 5 ADC VSB = 3.3 VDC, reverse airflow 3.5 VSB = 5.0 VDC, normal/reverse airflow 3.3 VSB pp Output Ripple Voltage VSB nom, ISB nom, 20 MHz BW (See Section 6.1) 80 mVpp dVSB Droop 0 - 100 % ISB nom VSB_SEL = 1 67 mV VSB_SEL = 0 44 ISB max Current Limitation VSB_SEL = 1, normal airflow 5.25 6 ADC VSB_SEL = 1, reverse airflow 4 4.75 VSB_SEL = 0, normal/reverse airflow 3.45 4.3 dVSBdyn Dynamic Load Regulation ΔISB = 50% ISB nom, ISB = 5 … 100% ISB nom, dIo/dt = 0.5 A/μs, recovery within 1% of V1 nom -3 3 %VSBnom Trec Recovery Time 250 μs tAC VSB Start-up Time from AC VSB = 90% VSB nom (see Figure 26) 2 sec tVSB rise Rise Time VSB = 10…90% VSB nom (see Figure 26) 4 20 ms CLoad Capacitive Loading Tamb = 25°C 10000 μF General Condition: TA = 0…45 °C unless otherwise noted.

6 PFE850-12-054xA

5.1 OUTPUT VOLTAGE RIPPLE

Figure 6. Output ripple test setup quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects. Table 1. Suitable Capacitors for V1 Table 2. Suitable Capacitors for VSB Figure 7. Turn-On AC Line 230VAC, full load (200ms/div) Figure 8. Turn-On AC Line 230VAC, full load (5ms/div)

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Figure 17. Load transient V1, 30 to 65 A (500 μs/div) Figure 18. Load transient V1, 65 to 30A (500 μs/div)

6.1 OVERVOLTAGE PROTECTION

the supply from the AC mains or by toggling the PSON_L input.

6.2 VSB UNDERVOLTAGE DETECTION

voltage, the main output V1 is inhibited.

6.3 CURRENT LIMITATION

current limitation and its voltage drops below ~10.0 VDC for more than 200 ms, the output will latch off (standby remains on).

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tech.support@psbel.com PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Vi mon Input RMS Voltage Vi min ≤ Vi ≤ Vi max -2.5 +2.5 % Ii mon Input RMS Current Ii > 4 Arms -5 +5 % Ii ≤ 4 Arms -0.2 +0.2 Arms Pi mon True Input Power Pi > 100 W -5 +5 % Pi ≤ 100 W -5 +5 W V1 mon V1 Voltage -2 +2 % I1 mon V1 Current I1 > 10 A -2 +2 % I1 ≤ 10 A -0.2 +0.2 A Po nom Total Output Power Po > 120 W -4 +4 % Po ≤ 120 W -4.5 +4.5 W VSB mon Standby Voltage -0.1 +0.1 V ISB mon Standby Current ISB ≤ ISB nom -0.2 +0.2 A PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT PSKILL_H / PSON_L / VSB_SEL / HOTSTANDBYEN_H Inputs VIL Input Low Level Voltage -0.2 0.8 V VIH Input High Level Voltage 2.4 3.5 V IIL, H Maximum Input Sink or Source Current 0 1 mA RpuPSKILL_H Internal Pull Up Resistor on PSKILL_H 100 kΩ RpuPSON_L Internal Pull Up Resistor on PSON_L 10 kΩ RpuVSB_SEL Internal Pull Up Resistor on VSB_SEL 10 kΩ RpuHOTSTANDBYEN_H Internal Pull Up Resistor on HOTSTANDBYEN_H 10 kΩ RLOW Resistance Pin to SGND for Low Level 0 1 kΩ RHIGH Resistance Pin to SGND for High Level 50 kΩ PWOK_H Output VOL Output Low Level Voltage Isink < 4 mA 0 0.4 V VOH Output High Level Voltage Isource < 0.5 mA 2.6 3.5 V RpuPWOK_H Internal Pull Up Resistor on PWOK_H 1 kΩ ACOK_H Output VOL Output Low Level Voltage Isink < 2 mA 0 0.4 V VOH Output High Level Voltage Isource < 50 µA 2.6 3.5 V RpuACOK_H Internal Pull Up Resistor on ACOK_H 10 kΩ SMB_ALERT_L Output Vext Maximum External Pull Up Voltage 12 V VOL Output Low Level Voltage Isource < 4 mA 0 0.4 V IOH Maximum High Level Leakage Current 10 µA RpuSMB_ALERT_L Internal Pull Up Resistor on SMB_ALERT_L None kΩ See chapter 8.12 to 8.17 and PFE Programming Manual BCA.00006 for further information on communication interface.

8.1 ELECTRICAL CHARACTERISTICS

8.2 INTERFACING WITH SIGNALS

an open collector/drain to prevent back feeding inputs when the power supply is switched off. voltage is not affected by an unpowered power supply. use a 15 V zener diode as protection device against positive voltage on pins. protection device and is disconnected from internal circuits when the power supply is switched off. Figure 24. Interconnection of Signal Pins

8.3 FRONT LEDs

position of the LEDs see Table 3 lists the different LED status.

• The order of the criteria in the table corresponds to the testing precedence in the controller.

Table 3. LED Status

8.4 PRESENT_L

PRESENT_L pin should not exceed 10 mA.

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Figure 25. PRESENT_L signal pin

8.5 PSKILL_H INPUT

unit. The standby output will remain on regardless of the PSKILL_H input state.

8.6 AC TURN-ON / DROP-OUTS / ACOK_H

Table 4. AC Turn-on / Dip Timing Figure 26. AC turn-on timing Figure 27. AC short dips Figure 28. AC long dips

8.7 PSON_L INPUT

low pin is also used to clear any latched fault condition. The timing diagram is given Figure 29 and the parameters in Table 5. Table 5. AC Turn-on / Dip Timing

8.8 PWOK_L SIGNAL

regulation. This pin is active-low. The timing diagram is shown in Figure 26 / Figure 29 and referenced in the Table 6. Figure 29. PSON_L turn-on/off timing Table 6. PWOK_L timing

8.9 CURRENT SHARE

its ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases. The standby output uses a passive current share method (droop output voltage characteristic).

8.10 SENSE INPUTS

allowed voltage drop is 200 mV on the positive rail and 100 mV on the PGND rail. protected against short circuit. In this case the power supply will shut down.

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8.11 HOT-STANDBY OPERATION

that only one of the power supplies is allowed to enter the hot-standby mode. already have been in the hot-standby mode. NOTE: The system controller needs to ensure that only one of the power supplies is allowed to enter the hot-standby model. Figure 30. Hot-standby enable/disable current thresholds Figure 31. PSU power losses with/without hot-standby mode Figure 32. Recommended hot-standby configuration

1 PSU on

2 PSU on

1 Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF

Table 7. I2C / SMBus Specification Figure 34. I2C / SMBus Timing

8.12 I2C / PMBus® COMMUNICATION

• There are no internal pull-up resistors
• The SDA/SCL IOs are 3.3/5 V tolerant
• Full SMBus clock speed of 100 kbps
• Clock stretching limited to 1 ms
• SCL low time-out of >25 ms with recovery within 10 ms
• Recognizes any time Start/Stop bus conditions

Figure 33. Physical layer of communication interface the general SMB_ALERT_L call address 25(0x19) by sending its status register. only VSB is provided, communication is not possible.

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8.13 ADDRESS / PROTOCOL SELECTION (APS)

(0 V). A fixed addressing offset exists between the Controller and the EEPROM. If the APS pin is left open, the supply will operate with the PSMI protocol at controller / EEPROM addresses 0xB6/0xA6. 1) E12 resistor values, use max 5% resistors, see also Figure 35. 2) The LSB of the address byte is the R/W bit. Table 8. Address and protocol encoding Figure 35. I2C address and protocol setting

8.14 CONTROLLER AND EEPROM ACCESS

needed. Such repeaters usually encode the low state with different voltage levels depending on the transmission direction. the DSP. By default the write protection is on. The EEPROM provides 256 bytes of user memory. None of the bytes are used for the operation of the power supply. Figure 36. I2C Bus to DSP and EEPROM

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions & Protection BCD.00040_AI

8.15 EEPROM PROTOCOL

The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read commands are defined, it is recommended to use the single byte write / read commands. WRITE The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the bus should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory. READ The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with the data byte at the specified location.

8.16 PSMI PROTOCOL

New power management features in computer systems require the system to communicate with the power supply to access current, voltage, fan speed, and temperature information. Current measurements provide data to the system for determining potential system configuration limitations and provide actual system power consumption for facility planning. Temperature and fan monitoring allow the system to better manage fan speeds and temperatures for optimizing system acoustics. Voltage monitoring allows the system to calculate input wattage and warning of system voltage regulation problems. The Power Supply Management Interface (PSMI) supports diagnostic capabilities and allows managing of redundant power supplies. The communication method is SMBus. The current design guideline is version 2.12. The communication protocol is register based and defines a read and write communication protocol to read / write to a single register address. All registers are accessed via the same basic command given below. No PEC (Packet Error Code) is used. WRITE The write protocol used is the SMBus 2.0 Write Word protocol. All writes are 16-bit words; byte reads are not supported nor allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming Manual for further information. READ The read protocol used is the SMBus 2.0 Read Word protocol. All reads are 16 -bit words; byte reads are not supported nor allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming Manual for further information. S Address W A Data Address A Data A P Data nA P S Address W A Data Address A S Address R A S Address W A Register ID A Data Low Byte A Data High Byte A P S Address W A Register ID A Data Low Byte AS Address R A Data High Byte nA P

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tech.support@psbel.com

8.17 PMBus® PROTOCOL

The Power Management Bus (PMBus®) is an open standard protocol that defines means of communicating with power conversion and other devices. For more information, please see the System Management Interface Forum web site at: www.powerSIG.org. PMBus® command codes are not register addresses. They describe a specific command to be executed. The PFE850-12-054xA supply supports the following basic command structures:

• Clock stretching limited to 1 ms
• SCL low time-out of >25 ms with recovery within 10 ms
• Recognized any time Start/Stop bus conditions WRITE The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte or after the first data byte (Byte command) or then after sending 2 data bytes (Word command). In addition, Block write commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual for further information. READ The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word. In addition, Block read commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual BCA.00006 for further information. S Address W A Command A Data Low Byte1) A Data High Byte1) A P 1) Optional S Address W A Command A Byte 1 A Byte N A P Byte Count A S Address W A Command A Data (Low) Byte AS Address R A Data High Byte1) nA P 1) Optional S Address W A Command A Byte 1 A S Address R A Byte N nA PByte Count A

8.18 GRAPHICAL USER INTERFACE

programming and monitoring of the PFE850-12-054xA Front-End. The utility can be downloaded on befuse.com/power-solutions and supports both the PSMI and PMBus® protocols. tree. In the monitoring view the power supply can be controlled and monitored. obviously requires 2 power supplies being operated as a redundant system (like the evaluation kit). NOTE: The user of the GUI needs to ensure that only one of the power supplies have the hot-standby mode enabled. Figure 37. Monitoring dialog of the I2C Utility

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have been designed for horizontal operation. and is a function of output power and the inlet temperature. then end user must derate the input power to meet a maximum 70°C temperature at the front, see Figure 43. automatically to meet such a temperature limitation. Figure 38. Airflow direction Figure 39. Fan speed vs. main output load for Figure 40. Fan speed vs. main output load for Figure 41. Thermal derating for PFE850-12-054NA Figure 42. Thermal derating for PFE850-12-054RA All rights strictly reserved. Reproduction or issue to third parties in any form is not permitted without written authority from Power-One. All materials used, and finished product, must meet the requirements of the current RoHS directive 2002/95/EC. For additional information use other data files, or ask.

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions & Protection BCD.00040_AI PARAMETER DESCRIPTION / CONDITION CRITERION ESD Contact Discharge IEC / EN 61000-4-2, ±8 kV, 25+25 discharges per test point (metallic case, LEDs, connector body) B ESD Air Discharge IEC / EN 61000-4-2, ±15 kV, 25+25 discharges per test point (non-metallic user accessible surfaces) B Radiated Electromagnetic Field IEC / EN 61000-4-3, 10 V/m, 1 kHz/80% Amplitude Modulation, 1 µs Pulse Modulation, 10 kHz…2 GHz A Burst IEC / EN 61000-4-4, level 3 AC port ±2 kV, 1 minute DC port ±1 kV, 1 minute B Surge IEC / EN 61000-4-5 Line to earth: level 3, ±2 kV Line to line: level 2, ±1 kV VSB: A; V1: B1 A RF Conducted Immunity IEC/EN 61000-4-6, Level 3, 10 Vrms, CW, 0.1 … 80 MHz A Voltage Dips and Interruptions IEC/EN 61000-4-11 1: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 10 ms 2: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 20 ms 3: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration >20 ms A VSB: A; V1: B VSB, V1: B

1 V1 drops to 90 … 97% V1 nom for 3 ms

PARAMETER DESCRIPTION / CONDITION CRITERION Conducted Emission EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG, single unit Class A 6 dB margin EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG, 2 units in rack system Class A 6 dB margin Radiated Emission EN55022 / CISPR 22: 30 MHz … 1 GHz, QP, single unit Class A 6 dB margin EN55022 / CISPR 22: 30 MHz … 1 GHz, QP, 2 units in rack system Class A 6 dB margin Harmonic Emissions IEC61000-3-2, Vin = 100 VAC/ 60 Hz, 100% Load Class A IEC61000-3-2, Vin = 120 VAC/ 60 Hz, 100% Load Class A IEC61000-3-2, Vin = 200 VAC/ 60 Hz, 100% Load Class A IEC61000-3-2, Vin = 230 VAC/ 50 Hz, 100% Load Class A IEC61000-3-2, Vin = 240 VAC/ 50 Hz, 100% Load Class A Acoustical Noise Sound power statistical declaration (ISO 9296, ISO 7779, IS9295) @ 50% load 42 dBA AC Flicker IEC / EN 61000-3-3, dmax < 3.3% PASS PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Agency Approvals Approved to latest edition of the following standards: UL/CSA60950-1, IEC60950-1 and EN60950-1. Isolation Strength Input (L/N) to case (PE) Input (L/N) to output Output to case (PE) Basic Reinforced Functional dC Creepage / Clearance Primary (L/N) to protective earth (PE) Primary to secondary Electrical Strength Test Input to case Input to output (tested by manufacturer only) 2121

4242 VDC

10.1 IMMUNITY

NOTE: Most of the immunity requirements are derived from EN 55024:1998/A2:2003.

10.2 EMISSION

Maximum electric strength testing is performed in the factory according to IEC/EN 60950, and UL 60950. Input-to-output electric strength tests should not be repeated in the field. Bel Power Solutions will not honor any warranty claims resulting from electric strength field tests.

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NOTE: A 3D step file of the power supply casing is available on request. Figure 43. Side View 1 Figure 44. Top View

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Figure 40. Pin Assignment

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions & Protection BCD.00040_AI ITEM DESCRIPTION ORDERING PN SOURCE I2C Utility Windows XP/Vista/7 compatible GUI to program, control and monitor PFE Front-Ends (and other I2C units) N/A belfuse.com/power-solutions Dual Connector Board Connector board to operate 2 PFE units in parallel. Includes an on-board USB to I2C converter (use I2C Utility as desktop software). SNP-OP-BOARD-01 Bel Power Solution Latch Lock Optional latch lock to prevent accidental removal of the power supply from the system while the AC plug is engaged. XSL.00019.0 Bel Power Solution NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice.