PFE600-12-054XA

PFE600-12-054XA BEL | Alldatasheet

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San Jose, CA 95112 USA © 2015 Bel Power Solutions, inc. North America +1-866.513.2839 Asia-Pacific +86.755.29885888 Europe, Middle East +353 61 225 977 tech.support@psbel.com BCD.00036_AH  Best-in-class, 80 PLUS certified “Platinum” efficiency  Wide input voltage range: 90-264 VAC  AC input with power factor correction  Always-On 16.5 W programmable standby output (3.3/5V)  Hot-plug capable  Parallel operation with active digital current sharing  Full digital controls for improved performance  High density design: 14.0 W/in3  Small form factor: 54.5 x 40.0 x 321.5 mm  I2C communication interface for control, programming and monitoring with PSMI and PMBus™ protocol  Overtemperature, output overvoltage and overcurrent protection  256 Bytes of EEPROM for user information The PFE600-12-054xA is a 600 Watt, AC to DC power-factor-corrected (PFC) power supply that converts standard AC mains power into a main output of 12 VDC for powering intermediate bus architectures (IBA) in high performance and reliability servers, routers, and network switches. The PFE600-12-054xA meets international safety standards and displays the CE-Mark for the European Low Voltage Directive (LVD).  High performance servers  Routers  Switches

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH The PFE600-12-054xA AC-DC power supply is a mainly DSP controlled, highly efficient front-end. It incorporates resonance-soft-switching technology and interleaved power trains to reduce component stresses, providing increased system reliability and very high efficiency. With a wide input operating voltage range and no derating of output power with input voltage and temperature, the PFE600-12-054xA maximizes power availability in demanding server, switch, and router applications. The front-end is fan cooled and ideally suited for server integration with a matching airflow path. The PFC stage is controlled using a state-of-the-art integrated control-IC to guarantee best efficiency and unity power factor over a wide operating range. The DC-DC stage uses soft switching resonant techniques in conjunction with synchronous rectification. An active OR-ing device on the output ensures no reverse load current and renders the supply ideally suited for operation in redundant power systems. The always-on standby output with selectable voltage level (3.3/5 V) provides power to external power distribution and management controllers. Its protection with an active OR-ing device provides for maximum reliability. Status information is provided with front-panel LEDs. In addition, the power supply can be controlled and the fan speed set via the I2C bus. It allows full monitoring of the supply, including input and output voltage, current, power, and inside temperatures. Cooling is managed by a fan controlled by the DSP controller. The fan speed is adjusted automatically depending on the actual power demand and supply temperature and can be overridden through the I2C bus. Figure 1 – PFE600-12-054xA Block Diagram Stresses in excess of the absolute maximum ratings may cause performance degradation, adversely affect long- term reliability and cause permanent damage to the supply. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Vi maxc Maximum Input Continuous 264 VAC Logic Signals V1Sense+ L Buck Aux Converter VsbSense+ VsbSense- GND Vsb N PFC DC DC Digital Prim Controls V1Sense- I2C PWM Filter PE PWM Communication Bus APS Digital Sec Controls EEPROM FAN

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH General Condition: TA = 0… 45 °C unless otherwise noted. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Vi nom Nominal Input Voltage 100 230 230 VAC Vi Input Voltage Ranges Normal operating (Vi min to Vi max) 90 264 VAC Ii max Max Input Current 8.5 Arms Ii p Inrush Current Limitation Vi min to Vi max, 90°, TNTC = 25 °C (see Figure 4 ) 40 Ap Fi Input Frequency 47 50/60 64 Hz PF Power Factor Vi nom, 50 Hz, > 0.2 I1 nom 0.9 W/VA Vi on Turn-on Input Voltage1) Ramping up 80 87 VAC Vi off Turn-off Input Voltage1) Ramping down 75 85 VAC η Efficiency without Fan Vi nom, 0.1∙Ix nom, Vx nom, TA = 25 °C 85.4 Vi nom, 0.2∙Ix nom, Vx nom, TA = 25 °C 92.8 Vi nom, 0.5∙Ix nom, Vx nom, TA = 25 °C 94.5 Vi nom, Ix nom, Vx nom, TA = 25 °C 94.0 Thold Hold-up Time After last AC zero point, V1 > 10.8 V, VSB within regulation, Vi = 230 VAC, Px nom 20 ms 1) The Front-End is provided with a minimum hysteresis of 3 V during turn-on and turn-off within the ranges. 4.1. INPUT FUSE Quick-acting 12.5 A input fuses (5 x 20 mm) in series with both the L- and N-line inside the power supply protect against severe defects. The fuses are not accessible from the outside and are therefore not serviceable parts. 4.2. INRUSH CURRENT The AC-DC power supply exhibits an X-capacitance of only 3.2 μF, resulting in a low and short peak current, when the supply is connected to the mains. The internal bulk capacitor will be charged through an NTC which will limit the inrush current. NOTE: Do not repeat plug-in / out operations within a short time, or else the internal in-rush current limiting device (NTC) may not sufficiently cool down and excessive inrush current or component failure(s) may result. 4.3. INPUT UNDER-VOLTAGE If the input voltage exceeds Vi maxC, the power supply remains on and may get damaged if the voltage exceeds a tolerable level. If the sinusoidal input voltage stays below the input undervoltage lockout threshold Vi on, the supply will be inhibited. Once the input voltage returns within the normal operating range, the supply will return to normal operation again. 4.4. POWER FACTOR CORRECTION Power factor correction (PFC) is achieved by controlling the input current waveform synchronously with the input voltage. A linear IC is used giving good PFC results over wide input voltage and load ranges. The input current will follow the shape of the input voltage. If for instance the input voltage has a trapezoidal waveform, then the current will also show a trapezoidal waveform. 4.5. EFFICIENCY High efficiency (see Figure 2) is achieved by using state-of-the-art silicon power devices in conjunction with soft- transition topologies minimizing switching losses and a full digital control scheme. Synchronous rectifiers on the output reduce the losses in the high current output path. The speed of the fan is digitally controlled to keep all components at an optimal operating temperature regardless of the ambient temperature and load conditions.

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH Standby Output VSB VSB nom Nominal Output Voltage 0.5 ∙ISB nom, Tamb = 25°C VSB_SEL = 1 3.3 VDC VSB set Output Setpoint Accuracy VSB_SEL = 0 5.0 VDC VSB_SEL = 0 / 1 -0.5 +0.5 %V1nom dVSB tot Total Regulation Vi min to Vi max, 0 to 100% ISB nom, Ta min to Ta max -1 +1 %VSBnom PSB nom Nominal Output Power VSB_SEL = 0 / 1 16.5 W ISB nom Nominal Output Current VSB = 3.3 VDC 5 ADC VSB = 5.0 VDC 3.3 VSB pp Output Ripple Voltage VSB nom, ISB nom, 20 MHz BW (See chapter 5.1) 40 mVpp dVSB Droop 0 - 100 % ISB nom VSB_SEL = 1 67 dVSB VSB_SEL = 0 44 ISB max Current Limitation VSB_SEL = 1 5.25 6 ADC VSB_SEL = 0 3.45 4.3 dVSBdyn Dynamic Load Regulation ΔISB = 50% ISB nom, ISB = 5 … 100% ISB nom, dIo/dt = 0.5 A/μs, recovery within 1% of V1 nom -3 3 %VSBnom Trec Recovery Time 250 μs tAC VSB Start-up Time from AC VSB = 90% VSB nom (Figure 6) 2 sec tVSB rise Rise Time VSB = 10…90% VSB nom (Figure 7) 4 20 ms CLoad Capacitive Loading Tamb = 25 °C 10000 μF 5.1. OUTPUT VOLTAGE RIPPLE The internal output capacitance at the power supply output (behind OR ring element) is minimized to prevent disturbances during hot plug. In order to provide low output ripple voltage in the application, external capacitors should be added close to the power supply output. The setup of Figure 6 has been used to evaluate suitable capacitor types. The capacitor combinations of Table 1 and Table 2 should be used to reduce the output ripple voltage. The ripple voltage is measured with 20 MHz BWL, close to the external capacitors. PGND VSB PFExxxx-12-054NA Connection board Figure 5 - Output ripple test setup NOTE: Care must be taken when using ceramic capacitors with a total capacitance of 1 µF to 50 µF on output V1, due to their high quality factor the output ripple voltage may be increased in certain frequency ranges due to resonance effects. External capacitor V1 dV1max Unit 2Pcs 47 µF/16 V/X5R/1210 150 mVpp 1Pcs 1000 µF/16 V/Low ESR Aluminum/ø10x20 60 mVpp 1Pcs 270 µF/16 V/Conductive Polymer/ø8x12 60 mVpp 2Pcs 47 µF/16 V/X5R/1210 plus 1Pcs 270 µF Conductive Polymer OR 1Pcs 1000 µF Low ESR AlCap 60 mVpp Table 1 - Suitable capacitors for V1 External capacitor VSB dV1max Unit 1Pcs 10 µF/16 V/X5R/1206 40 mVpp 2Pcs 10 µF/16 V/X5R/1206 30 mVpp 1Pcs 47 µF/16 V/X5R/1210 25 mVpp 2Pcs 100 µF/6.3 V/X5R/1206 20 mVpp Table 2 - Suitable capacitors for VSB

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH See chapter 8.12 to 8.17 and PFE Programming Manual BCA.00006 for further information on communication interface. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Vi mon Input RMS Voltage Vi min ≤ Vi ≤ Vi max -2.5 +2.5 % Ii mon Input RMS Current Ii > 4 Arms -5 +5 % Ii ≤ 4 Arms -0.2 +0.2 Arms Pi mon True Input Power Pi > 100 W -5 +5 % Pi ≤ 100 W -5 +5 W V1 mon V1 Voltage -2 +2 % I1 mon V1 Current I1 > 10 A -2 +2 % I1 ≤ 10 A -0.2 +0.2 A Po nom Total Output Power Po > 120 W -4 +4 % Po ≤ 120 W -4.5 +4.5 W VSB mon Standby Voltage -0.1 +0.1 V ISB mon Standby Current ISB ≤ ISB nom -0.2 +0.2 A 8.1. ELECTRICAL CHARACTERISTICS PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT PSKILL_H / PSON_L / VSB_SEL / HOTSTANDBYEN_H Inputs VIL Input Low Level Voltage -0.2 0.8 V VIH Input High Level Voltage 2.4 3.5 V IIL, H Maximum Input Sink or Source Current 0 1 mA RpuPSKILL_H Internal Pull up Resistor on PSKILL_H 100 kΩ RpuPSON_L Internal Pull up Resistor on PSON_L 10 kΩ RpuVSB_SEL Internal Pull up Resistor on VSB_SEL 10 kΩ RpuHOTSTANDBYEN_H Internal Pull up Resistor on HOTSTANDBYEN_H 10 kΩ RLOW Resistance Pin to SGND for Low Level 0 1 kΩ RHIGH Resistance Pin to SGND for High Level 50 kΩ PWOK_H Output VOL Output Low Level Voltage Isink < 4 mA 0 0.4 V VOH Output High Level Voltage Isource < 0.5 mA 2.6 3.5 V RpuPWOK_H Internal Pull up Resistor on PWOK_H 1 kΩ ACOK_H Output VOL Output Low Level Voltage Isink < 2 mA 0 0.4 V VOH Output High Level Voltage Isource < 50 µA 2.6 3.5 V RpuACOK_H Internal Pull up Resistor on ACOK_H 10 kΩ SMB_ALERT_L Output Vext Maximum External Pull up Voltage 12 V VOL Output Low Level Voltage Isource < 4 mA 0 0.4 V IOH Maximum High Level Leakage Current 10 µA RpuSMB_ALERT_L Internal Pull up Resistor on SMB_ALERT_L None kΩ

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH 8.2. INTERFACING WITH SIGNALS All signal pins have protection diodes implemented to protect internal circuits. When the power supply is not powered, the protection devices start clamping at signal pin voltages exceeding ±0.5 V. Therefore all input signals should be driven only by an open collector/drain to prevent back feeding inputs when the power supply is switched off. If interconnecting of signal pins of several power supplies is required, then this should be done by decoupling with small signal schottky diodes as shown in examples in Figure 23 (except for SMB_ALERT_L, ISHARE and I 2C pins). This will ensure the pin voltage is not affected by an unpowered power supply. SMB_ALERT_L pins can be interconnected without decoupling diodes, since these pins have no internal pull up resistor and use a 15 V zener diode as protection device against positive voltage on pins. ISHARE pins must be interconnected without any additional components. This in-/output also has a 15 V zener diode as a protection device and is disconnected from internal circuits when the power supply is switched off. PSU 1 PDU PSU 2 VSB_SEL PSU 1 PDU PSU 2 3.3V VSB_SEL 3.3V 3.3V PWOK 3.3V PWOK Figure 23 - Interconnection of Signal Pins 8.3. FRONT LEDS The front-end has 2 front LEDs showing the status of the supply. LED number one is green and indicates AC power is on or off, while LED number two is bi-colored: green and yellow, and indicates DC power presence or fault situations. For the position of the LEDs see Table 3 lists the different LED status. OPERATING CONDITION LED SIGNALING AC LED AC Line within range Solid Green AC Line UV condition Off DC LED 1) PSON_L High Blinking Yellow (1:1) Hot-Standby Mode Blinking Yellow/Green (1:2) V1 or VSB out of regulation Solid Yellow Over temperature shutdown Output over voltage shutdown (V1 or VSB) Output over current shutdown (V1 or VSB) Fan error (>15%) Over temperature warning Blinking Yellow/Green (2:1) Minor fan regulation error (>5%, <15%) Blinking Yellow/Green (1:1) 1) The order of the criteria in the table corresponds to the testing precedence in the controller. Table 3 - LED Status

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH 8.7. PSON_L INPUT The PSON_L is an internally pulled-up (3.3 V) input signal to enable/disable the main output V1 of the front-end. This active-low pin is also used to clear any latched fault condition. The timing diagram is given in Figure 30 and the parameters in Table 5. OPERATING CONDITION MIN MAX UNIT tPSON_L V1on PSON_L to V1 delay (on) 2 20 ms tPSON_L V1off PSON_L to V1 delay (off) 2 20 ms tPSON_L H min PSON_L minimum High time 10 ms Table 5 - AC Turn-on / Dip Timing 8.8. PWOK_H SIGNAL The PWOK_H is an open drain output with an internal pull-up to 3.3 V indicating whether both VSB and V1 outputs are within regulation. This pin is active-low. The timing diagram is shown in Figure 25 / Figure 30 and referenced in the Table 6. VSB AC Input PSON_L ACOK_H PWOK_H tPSON_L V1on tV1 rise tPWOK_H del tPSON_L V1off tPWOK_H warn tPSON_L H min Figure 28 - PSON_L turn-on/off timing OPERATING CONDITION MIN MAX UNIT tPWOK_H del PWOK_H to V1 delay (on) 100 500 ms tPWOK_H warn*) PWOK_H to V1 delay (off) caused by: PSKILL_H 0 1 ms PSON_L, ACOK_H, OT, Fan Failure 1 2.5 ms UV and OV on VSB 1 30 ms OC on V1 (Software trigger) -11 0 ms OC on V1 (Hardware trigger) -1 0 ms OV on V1 -3 0 ms *) A positive value means a warning time, a negative value a delay (after fact). Table 6 - PWOK_H timing 8.9. CURRENT SHARE The PFE front-ends have an active current share scheme implemented for V1. All the ISHARE current share pins need to be interconnected in order to activate the sharing function. If a supply has an internal fault or is not turned on, it will disconnect its ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases. The current share function uses a digital bi-directional data exchange on a recessive bus configuration to transmit and receive current share information. The controller implements a Master/Slave current share function. The power supply providing the largest current among the group is automatically the Master. The other supplies will operate as Slaves and increase their output current to a value close to the Master by slightly increasing their output voltage. The voltage increase is limited to +250 mV. The standby output uses a passive current share method (droop output voltage characteristic). 8.10. SENSE INPUTS Both main and standby outputs have sense lines implemented to compensate for voltage drop on load wires. The maximum allowed voltage drop is 200 mV on the positive rail and 100 mV on the PGND rail. With open sense inputs the main output voltage will rise by 270 mV and the standby output by 50 mV. Therefore if not used, these inputs should be connected to the power output and PGND close to the power supply connector. The sense inputs are protected against short circuit. In this case the power supply will shut down.

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH 8.11. HOT-STANDBY OPERATION The hot-standby operation is an operating mode allowing to further increase efficiency at light load conditions in a redundant power supply system. Under specific conditions one of the power supplies is allowed to disable its DC/DC stage. This will save the power losses associated with this power supply and at the same time the other power supply will operate in a load range having a better efficiency. In order to enable the hot standby operation, the HOTSTANDBYEN_H and the ISHARE pins need to be interconnected. A power supply will only be allowed to enter the hot-standby mode, when the HOTSTANDBYEN_H pin is high, the load current is low (see Figure 31) and the supply was allowed to enter the hot-standby mode by the system controller via the appropriate I2C command (by default disabled). The system controller needs to ensure that only one of the power supplies is allowed to enter the hot-standby mode. If a power supply is in a fault condition, it will pull low its active-high HOTSTANDBYEN_H pin which indicates to the other power supply that it is not allowed to enter the hot-standby mode or that it needs to return to normal operation should it already have been in the hot-standby mode. NOTE: The system controller needs to ensure that only one of the power supplies is allowed to enter the hot-standby model. Figure 32 shows the achievable power loss savings when using the hot -standby mode operation. A total power loss reduction of 45% is achievable.

1 PSU on

2 PSU on

Figure 29 - Hot-standby enable/disable current thresholds Figure 30 - PSU power losses with/without hot-standby mode Figure 31 - Recommended hot-standby configuration In order to prevent voltage dips when the active power supply is unplugged while the other is in hot-standby mode, it is strongly recommended to add the external circuit as shown in Figure 31. If the PRESENT_L pin status needs also to be read by the system controller, it is recommended to exchange the bipolar transistors with small signal MOS transistors or with digital transistors. 8.12. I2C / SMBUS COMMUNICATION The interface driver in the PFE supply is referenced to the V1 Return. The PFE supply is a communication Slave device only; it never initiates messages on the I2C / SMBus by itself. The communication bus voltage and timing is defined in Table 7 further characterized through: 0 50 100 150 200 250 300 350 400 450 Po [W] Total Power Loss [W] Hot-Standby Disabled Hot-Standby Enabled PSU 1 PSU 2 VSB CS HOTSTANDBYEN PRESENT_L VSB CS HOTSTANDBYEN PRESENT_L 3 x 3k3

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH  There are no internal pull-up resistors  The SDA/SCL IOs are 3.3/5 V tolerant  Full SMBus clock speed of 100 kbps  Clock stretching limited to 1 ms  SCL low time-out of >25 ms with recovery within 10 ms  Recognizes any time Start/Stop bus conditions Figure 32 - Physical layer of communication interface The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investigate. This is a logical OR of the Shutdown and Warning events. The power supply responds to a read command on the general SMB_ALERT_L call address 25(0x19) by sending its status register. Communication to the DSP or the EEPROM will be possible as long as the input AC voltage is provided. If no AC is present, communication to the unit is possible as long as it is connected to a life V1 output (provided e.g. by the redundant unit). If only VSB is provided, communication is not possible. PARAMETER DESCRIPTION CONDITION MIN MAX UNIT ViL Input low voltage -0.5 1.0 V ViH Input high voltage 2.3 5.5 V Vhys Input hysteresis 0.15 V VoL Output low voltage 3 mA sink current 0 0.4 V tr Rise time for SDA and SCL 20+0.1Cb1 300 Ns tof Output fall time ViHmin  ViLmax 10 pF < Cb1 < 400 pF 20+0.1Cb1 250 Ns Ii Input current SCL/SDA 0.1 VDD < Vi < 0.9 VDD -10 10 μA Ci Internal Capacitance for each SCL/SDA 50 pF fSCL SCL clock frequency 0 100 kHz Rpu External pull-up resistor fSCL ≤ 100 kHz 1000ns / Cb1 Ω tHDSTA Hold time (repeated) START fSCL ≤ 100 kHz 4.0 μs tLOW Low period of the SCL clock fSCL ≤ 100 kHz 4.7 μs tHIGH High period of the SCL clock fSCL ≤ 100 kHz 4.0 μs tSUSTA Setup time for a repeated START fSCL ≤ 100 kHz 4.7 μs tHDDAT Data hold time fSCL ≤ 100 kHz 0 3.45 μs tSUDAT Data setup time fSCL ≤ 100 kHz 250 ns tSUSTO Setup time for STOP condition fSCL ≤ 100 kHz 4.0 μs tBUF Bus free time between STOP and START fSCL ≤ 100 kHz 5 ms

1 Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF

Table 7 - I2C / SMBus Specification Figure 33 - I2C / SMBus Timing 8.13. ADDRESS/PROTOCOL SELECTION (APS) The APS pin provides the possibility to select the communication protocol and address by connecting a resistor to V1 return (0 V). A fixed addressing offset exists between the Controller and the EEPROM. NOTES If the APS pin is left open, the supply will operate with the PSMI protocol at controller / EEPROM addresses 0xB6 / 0xA6. The ASP pin is only read at start-up of the power supply. Therefore it is not possible to change the communication protocol and address dynamically. 3.3/5V Rpull-upTX RX SDA/SCL trtLOWtHIGHtLOW tHDSTAtSUSTA tHDDAT tSUDAT tSUSTO tBUF tof SDA SCL

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH 8.16. PSMI PROTOCOL New power management features in computer systems require the system to communicate with the power supply to access current, voltage, fan speed, and temperature information. Current measurements provide data to the system for determining potential system configuration limitations and provide actual system power consumption for facility planning. Temperature and fan monitoring allow the system to better manage fan speeds and temperatures for optimizing system acoustics. Voltage monitoring allows the system to calculate input wattage and warning of system voltage regulation problems. The Power Supply Management Interface (PSMI) supports diagnostic capabilities and allows managing of redundant power supplies. The communication method is SMBus. The current design guideline is version 2.12. The communication protocol is register based and defines a read and write communication protocol to read / write to a single register address. All registers are accessed via the same basic command given below. No PEC (Packet Error Code) is used. WRITE The write protocol used is the SMBus 2.0 Write Word protocol. All writes are 16-bit words; byte reads are not supported nor allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming Manual for further information. READ The read protocol used is the SMBus 2.0 Read Word protocol. All reads are 16-bit words; byte reads are not supported nor allowed. The shaded areas in the figure indicate bits and bytes written by the PSMI master device. See PFE Programming Manual for further information. 8.17. PMBus™ PROTOCOL The Power Management Bus (PMBus™) is an open standard protocol that defines means of communicating with power conversion and other devices. For more information, please see the System Management Interface Forum web site at: www.powerSIG.org. PMBus™ command codes are not register addresses. They describe a specific command to be executed. The PFE1100-12-054xA supply supports the following basic command structures:  Clock stretching limited to 1 ms  SCL low time-out of >25 ms with recovery within 10 ms  Recognized any time Start/Stop bus conditions WRITE The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte or after the first data byte (Byte command) or then after sending 2 data bytes (Word command). In addition, Block write commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual for further information. S Address W A Register ID A Data Low Byte A Data High Byte A P S Address W A Register ID A Data Low Byte AS Address R A Data High Byte nA P S Address W A Command A Data Low Byte1) A Data High Byte1) A P 1) Optional S Address W A Command A Byte 1 A Byte N A P Byte Count A

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH READ The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word. In addition, Block read commands are supported with a total maximum length of 255 bytes. See PFE Programming Manual BCA.00006 for further information. 8.18. GRAPHICAL USER INTERFACE Bel Power Solutions provides with its “ I2C Utility” a Windows® XP/Vista/Win7 compatible graphical user interface allowing the programming and monitoring of the PFE600 -12-054xA Front-End. The utility can be downloaded on www.belpowersolutions.com and supports both the PSMI and PMBus™ protocols. The GUI allows automatic discovery of the units connected to the communication bus and will show them in the navigation tree. In the monitoring view the power supply can be controlled and monitored. If the GUI is used in conjunction with the PFE600 -12-054xA Evaluation Kit it is also possible to control the PSON_L pin(s) of the power supply. Further there is a button to disable the inter nal fan for approximately 10 seconds. This allows the user to take input power measurements without fan consumptions to check efficiency compliance to the Climate Saver Computing Platinum specification. The monitoring screen also allows to enable the hot-standby mode on the power supply. The mode status is monitored and by changing the load current it can be monitored when the power supply is being disabled for further energy savings. This obviously requires 2 power supplies being operated as a redundant system (like the evaluation kit). NOTE: The user of the GUI needs to ensure that only one of the power supplies have the hot-standby mode enabled. Figure 36 - Monitoring dialog of the I2C Utility S Address W A Command A Data (Low) Byte AS Address R A Data High Byte1) nA P 1) Optional S Address W A Command A Byte 1 A S Address R A Byte N nA PByte Count A

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH 10.1. IMMUNITY NOTE: Most of the immunity requirements are derived from EN 55024:1998/A2:2003. PARAMETER DESCRIPTION / CONDITION CRITERION ESD Contact Discharge IEC / EN 61000-4-2, ±8 kV, 25+25 discharges per test point (metallic case, LEDs, connector body) B ESD Air Discharge IEC / EN 61000-4-2, ±15 kV, 25+25 discharges per test point (non-metallic user accessible surfaces) B Radiated Electromagnetic Field IEC / EN 61000-4-3, 10 V/m, 1 kHz/80% Amplitude Modulation, 1 µs Pulse Modulation, 10 kHz…2 GHz A Burst IEC / EN 61000-4-4, level 3 AC port ±2 kV, 1 minute DC port ±1 kV, 1 minute B Surge IEC / EN 61000-4-5 Line to earth: level 3, ±2 kV Line to line: level 2, ±1 kV VSB: A,V1: B1 A RF Conducted Immunity IEC/EN 61000-4-6, Level 3, 10 Vrms, CW, 0.1 … 80 MHz A Voltage Dips and Interruptions IEC/EN 61000-4-11 1: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 10 ms 2: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration 20 ms 3: Vi 230 V, 100% Load, Phase 0 °, Dip 100%, Duration >20 ms A A B

1 V1 drops to 90 … 97% V1 nom for 3 ms

10.2. EMISSION PARAMETER DESCRIPTION / CONDITION CRITERION Conducted Emission EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG, single unit Class A 6 dB margin EN55022 / CISPR 22: 0.15 … 30 MHz, QP and AVG, 2 units in rack system Class A 6 dB margin Radiated Emission EN55022 / CISPR 22: 30 MHz … 1 GHz, QP, single unit Class A 6 dB margin EN55022 / CISPR 22: 30 MHz … 1 GHz, QP, 2 units in rack system Class A 6 dB margin Harmonic Emissions IEC61000-3-2, Vin = 100 VAC/ 60 Hz, 100% Load Class A IEC61000-3-2, Vin = 120 VAC/ 60 Hz, 100% Load Class A IEC61000-3-2, Vin = 200 VAC/ 60 Hz, 100% Load Class A IEC61000-3-2, Vin = 230 VAC/ 50 Hz, 100% Load Class A IEC61000-3-2, Vin = 240 VAC/ 50 Hz, 100% Load Class A Acoustical Noise Sound power statistical declaration (ISO 9296, ISO 7779, IS9295) @ 50% load 42 dBA Maximum electric strength testing is performed in the factory according to IEC/EN 60950, and UL 60950. Input-to- output electric strength tests should not be repeated in the field. Bel Power Solutions will not honor any warranty claims resulting from electric strength field tests. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Agency Approvals Approved to the latest edition of the following standards: UL/CSA 60950-1, IEC60950-1 and EN60950-1 Isolation Strength Input (L/N) to case (PE) Basic Input (L/N) to output Reinforced Output to case (PE) Functional dC Creepage / Clearance Primary (L/N) to protective earth (PE) Primary to secondary Electrical Strength Test Input to case Input to output (tested by manufacturer only) 2121

4242 VDC

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH Figure 44 - Front and Rear View Power Supply Connector: Tyco Electronics P/N 2-1926736-3 (NOTE: Column 5 is recessed (short pins)) Mating Connector: Tyco Electronics P/N 2-1926739-5 or FCI 10108888-R10253SLF PIN NAME DESCRIPTION Output 6, 7, 8, 9, 10 V1 +12 VDC main output 1, 2, 3, 4, 5 PGND Power ground (return) Control Pins A1 VSB Standby positive output (+3.3/5 V) B1 VSB Standby positive output (+3.3/5 V) C1 VSB Standby positive output (+3.3/5 V) D1 VSB Standby positive output (+3.3/5 V) E1 VSB Standby positive output (+3.3/5 V) A2 SGND Signal ground (return) B2 SGND Signal ground (return) C2 HOTSTANDBYEN_H Hot standby enable signal: active-high D2 VSB_SENSE_R Standby output negative sense E2 VSB_SENSE Standby output positive sense A3 APS I2C address and protocol selection (select by a pull down resistor) B3 N/C Reserved C3 SDA I2C data signal line D3 V1_SENSE_R Main output negative sense E3 V1_SENSE Main output positive sense A4 SCL I2C clock signal line B4 PSON_L Power supply on input (connect to A2/B2 to turn unit on): active-low C4 SMB_ALERT_L SMB Alert signal output: active-low D4 N/C Reserved AC LED DC LED

© 2015 Bel Power Solutions, inc. 866.513.2839 tech.support@psbel.com BCD.00036_AH E4 ACOK_H AC input OK signal: active-high A5 PSKILL_H Power supply kill (lagging pin): active-high B5 ISHARE Current share bus (lagging pin) C5 PWOK_H Power OK signal output (lagging pin): active-high D5 VSB_SEL Standby voltage selection (lagging pin) E5 PRESENT_L Power supply present (lagging pin): active-low ITEM DESCRIPTION ORDERING PART NUMBER SOURCE I2C Utility Windows XP/Vista/7 compatible GUI to program, control and monitor PFE Front- Ends (and other I2C units) N/A www.belpowersolutions.com Dual Connector Board Connector board to operate 2 PFE units in parallel. Includes an on-board USB to I2C converter (use I2C Utility as desktop software). SNP-OP-BOARD-01 Bel Power Solution Latch Lock Optional latch lock to prevent accidental removal of the power supply from the system while the AC plug is engaged. XSL.00019.0 Bel Power Solution NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice.