PCF8574A_15 TI1 | Alldatasheet
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Technical content
(e.g. Processor) Peripheral Devices RESET, ENABLE, or control inputs INT or status outputs LEDs SDA SCL INT GND VCC Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community PCF8574A SCPS069F –JULY 2001–REVISED NOVEMBER 2015 PCF8574ARemote8-BitI/OExpanderforI2CBus
1 Features
- Low Standby-Current Consumption of 10 μA Max 3 Description This 8-bit input/output (I/O) expander for the two-line• I2C to Parallel-Port Expander bidirectional bus (I2C) is designed for 2.5-V to 6-V• Open-Drain Interrupt Output VCC operation.• Compatible With Most Microcontrollers The PCF8574A device provides general-purpose• Latched Outputs With High-Current Drive remote I/O expansion for most microcontrollerCapability for Directly Driving LEDs families via the I2C interface [serial clock (SCL), serial
- Latch-Up Performance Exceeds 100 mA Per data (SDA)]. JESD 78, Class II The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high-2 Applications current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or• Telecom Shelters: Filter Units output without the use of a data-direction control• Servers signal. At power on, the I/Os are high. In this mode,• Routers (Telecom Switching Equipment) only a current source to VCC is active.
- Personal Computers Device Information(1)
- Personal Electronics PART NUMBER PACKAGE (PIN) BODY SIZE (NOM)• Industrial Automation VQFN (20) 4.50 mm × 3.50 mm
- Products with GPIO-Limited Processors PDIP (16) 19.30 mm × 6.35 mm PCF8574A SOIC (16) 10.30 mm × 7.50 mm TSSOP (20) 6.50 mm × 4.40 mm TVSOP (20) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SCPS069F –JULY 2001–REVISED NOVEMBER 2015 www.ti.com Table of Contents
4 Revision History
Changes from Revision E (January 2015) to Revision F Page Changes from Revision D (October 2005) to Revision E Page
- Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
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Product Folder Links: PCF8574A
(TOP VIEW) 1 1 INT SCL NC SDA VCC NC NC GND NC DGV OR PW PACKAGE (TOP VIEW) RGY PACKAGE (TOP VIEW) 1 20 10 1 1 NC GND NC SCL NC SDA VCC NC INT PCF8574A www.ti.com SCPS069F –JULY 2001–REVISED NOVEMBER 2015
5 Pin Configuration and Functions
NAME RGY DGV or PW DW or N GND 15 15 8 — Ground INT 1 1 13 O Interrupt output. Connect to VCC through a pullup resistor. NC 3, 8, 13, 18 3, 8, 13, 18 - — Do not connect 4, 5, 6, 7,10, 11, 12, 14, 10, 11, 12, 14,P[0..7] 9, 10, 11, I/O P-port input/output. Push-pull design structure.16, 17, 19, 20 16, 17, 19, 20 12 SCL 2 2 14 I Serial clock line. Connect to VCC through a pullup resistor SDA 4 4 15 I/O Serial data line. Connect to VCC through a pullup resistor. VCC 5 5 16 — Voltage supply Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: PCF8574A
SCPS069F –JULY 2001–REVISED NOVEMBER 2015 www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI Input voltage range(2) –0.5 VCC + 0.5 V VO Output voltage range(2) –0.5 VCC + 0.5 V IIK Input clamp current VI < 0 –20 mA IOK Output clamp current VO < 0 –20 mA IOK Input/output clamp current VO < 0 or VO > VCC ±400 μA IOL Continuous output low current VO = 0 to VCC 50 mA IOH Continuous output high current VO = 0 to VCC –4 mA Continuous current through VCC or GND ±100 mA TJ Junction temperature 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 1000pins(1) V(ESD) Electrostatic discharge V Charged device model (CDM), per JEDEC specification JESD22- 1500C101, all pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
VCC Supply voltage 2.5 6 V VIH High-level input voltage 0.7 × VCC VCC + 0.5 V VIL Low-level input voltage –0.5 0.3 × VCC V IOH High-level output current –1 mA IOL Low-level output current 25 mA TA Operating free-air temperature –40 85 °C
6.4 Thermal Information
THERMAL METRIC(1) DGV DW N PW RGY UNIT
20 PINS 16 PINS 16 PINS 20 PINS 20 PINS
θJA Junction-to-ambient thermal resistance 92 57 67 83 37 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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www.ti.com SCPS069F –JULY 2001–REVISED NOVEMBER 2015
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP(1) MAX UNIT VIK Input diode clamp voltage II = –18 mA 2.5 V to 6 V –1.2 V VPOR Power-on reset voltage(2) VI = VCC or GND, IO = 0 6 V 1.3 2.4 V IOH P port VO = GND 2.5 V to 6 V 30 300 μA IOHT P-port transient pullup current High during acknowledge, VOH = GND 2.5 V –1 mA SDA VO = 0.4 V 2.5 V to 6 V 3 IOL P port VO = 1 V 5 V 10 25 mA INT VO = 0.4 V 2.5 V to 6 V 1.6 SCL, SDA ±5 II INT VI = VCC or GND 2.5 V to 6 V ±5 μA A0, A1, A2 ±5 IIHL P port VI ≥ VCC or VI ≤ GND 2.5 V to 6 V ±400 μA Operating mode VI = VCC or GND, IO = 0, fSCL = 100 kHz 40 100 ICC 6 V μA Standby mode VI = VCC or GND, IO = 0 2.5 10 Ci SCL VI = VCC or GND 2.5 V to 6 V 1.5 7 pF SDA 3 7 Cio VIO = VCC or GND 2.5 V to 6 V pF P port 4 10 (1) All typical values are at VCC = 5 V, TA = 25°C. (2) The power-on reset circuit resets the I2C-bus logic with VCC < VPOR and sets all I/Os to logic high (with current source to VCC).
6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12) MIN MAX UNIT fscl I2C clock frequency 100 kHz tsch I2C clock high time 4 μs tscl I2C clock low time 4.7 μs tsp I2C spike time 100 ns tsds I2C serial-data setup time 250 ns tsdh I2C serial-data hold time 0 ns ticr I2C input rise time 1 μs ticf I2C input fall time 0.3 μs tocf I2C output fall time (10-pF to 400-pF bus) 300 ns tbuf I2C bus free time between stop and start 4.7 μs tsts I2C start or repeated start condition setup 4.7 μs tsth I2C start or repeated start condition hold 4 μs tsps I2C stop-condition setup 4 μs tvd Valid-data time SCL low to SDA output valid 3.4 μs Cb I2C bus capacitive load 400 pF
6.7 Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 13) FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT) tpv Output data valid SCL P port 4 μs tsu Input data setup time P port SCL 0 μs th Input data hold time P port SCL 4 μs tiv Interrupt valid time P port INT 4 μs tir Interrupt reset delay time SCL INT 4 μs Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: PCF8574A
6.8 Typical Characteristics
Figure 1. Supply Current vs Temperature Figure 2. Standby Supply Current vs Temperature Figure 4. I/O Sink Current vs Output Low VoltageFigure 3. Supply Current vs Supply Voltage Figure 5. I/O Sink Current vs Output Low Voltage Figure 6. I/O Sink Current vs Output Low Voltage
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2 Bytes for Complete Device
7 Parameter Measurement Information
Figure 12. I2C Interface Load Circuit and Voltage Waveforms
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Figure 15. Load Circuits
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Pin numbers shown are for the DW and N packages. I2C Bus Control PCF8574A www.ti.com SCPS069F –JULY 2001–REVISED NOVEMBER 2015
8 Detailed Description
8.1 Overview
The PCF8574A device provides general-purpose remote I/O expansion for most microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high-current drive capability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to VCC is active. An additional strong pullup to VCC allows fast rising edges into heavily loaded outputs. This device turns on when an output is written high and is switched off by the negative edge of SCL. The I/Os should be high before being used as inputs. The PCF8574A device provides an open-drain output (INT) that can be connected to the interrupt input of a microcontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, tiv, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at the acknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledge clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, or writing to, another device does not affect the interrupt circuit. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Therefore, the PCF8574A device can remain a simple slave device.
8.2 Functional Block Diagram
8.2.1 Simplified Block Diagram of Device
Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: PCF8574A
P0−P7 VCC GND C S I D Q FF C S I D Q FF Write Pulse Data From Shift Register Power-On Reset Read Pulse Data to Shift Register 100 µA PCF8574A SCPS069F –JULY 2001–REVISED NOVEMBER 2015 www.ti.com Functional Block Diagram (continued)
8.2.2 Simplified Schematic Diagram of Each P-Port Input/Output
8.3 Feature Description
8.3.1 I2C Interface
I2C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA I/O while the SCL input is high. After the start condition, the device address byte is sent, most- significant bit (MSB) first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDA I/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the start and the stop conditions. The data byte follows the address acknowledge. If the R/W bit is high, the data from this device are the values read from the P port. If the R/W bit is low, the data are from the master, to be output to the P port. The data byte is followed by an acknowledge sent from this device. If other data bytes are sent from the master, following the acknowledge, they are ignored by this device. Data are output only if complete bytes are received and acknowledged. The output data will be valid at time, tpv, after the low-to-high transition of SCL and during the clock cycle for the acknowledge. A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master.
8.3.2 Interface Definition
7 (MSB) 6 5 4 3 2 1 0 (LSB) I2C slave address L H H H A2 A1 A0 R/W I/O data bus P7 P6 P5 P4 P3 P2 P1 P0
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8.3.3 Address Reference
8.4 Device Functional Modes
Figure 16 and Figure 17 show the address and timing diagrams for the write and read modes, respectively. Figure 16. Write Mode (Output)
Figure 17. Read Mode (Input)
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9 Application and Implementation
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 18 shows an application in which the PCF8574A device can be used.
9.2 Typical Application
that could be powered on while VCC is powered off, then the supply current, ICC, will increase as a result. A. Device address is configured as 0100000 for this example. B. P0, P2, and P3 are configured as outputs. C. P1, P4, and P5 are configured as inputs. D. P6 and P7 are not used and must be configured as outputs. Figure 18. Application Schematic
3.3 V 5 V
9.2.1 Design Requirements
9.2.1.1 Minimizing ICC When I/Os Control LEDs
Figure 27. For a P-port configured as an input, ICC increases as VI becomes lower than VCC. The LED is a diode, value resistor in parallel with the LED. Figure 20 shows VCC less than the LED supply voltage by at least VT. when the P-port is configured as an input and the LED is off. Figure 19. High-Value Resistor in Parallel With LED Figure 20. Device Supplied by a Lower Voltage
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9.2.2 Detailed Design Procedure
9.2.3 Application Curves
Figure 21. Maximum Pull-Up Resistance (Rp(max)) Figure 22. Minimum Pull-Up Resistance (Rp(min))
10 Power Supply Recommendations
10.1 Power-On Reset Requirements
reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 23 and Figure 24. Figure 23. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC Figure 24. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 1 specifies the performance of the power-on reset feature for PCF8574A for both types of power-on reset. Table 1. Recommended Supply Sequencing and Ramp Rates(1)
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8 GND 9P4
11 Layout
11.1 Layout Guidelines
not a concern for I2C signal speeds. needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 27.
11.2 Layout Example
Figure 27. Layout Example for PCF8574A
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www.ti.com SCPS069F –JULY 2001–REVISED NOVEMBER 2015
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser based versions of this data sheet, refer to the left hand navigation. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: PCF8574A
www.ti.com 16-Nov-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PCF8574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574ADW ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8574A PCF8574ADWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8574A PCF8574ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PCF8574A PCF8574ADWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 PCF8574A PCF8574ADWRE4 ACTIVE SOIC DW 16 TBD Call TI Call TI -40 to 85 PCF8574ADWRG4 OBSOLETE SOIC DW 16 TBD Call TI Call TI -40 to 85 PCF8574AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 PCF8574AN PCF8574ANE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 PCF8574AN PCF8574APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 PF574A PCF8574ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PF574A
www.ti.com 16-Nov-2015 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PCF8574ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PF574A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Nov-2015 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCF8574ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0 PCF8574ADWR SOIC DW 16 2000 367.0 367.0 38.0 PCF8574APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCF8574ARGYR VQFN RGY 20 3000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 16-Nov-2015 Pack Materials-Page 2
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194
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