MMPF0200Z NXP | Alldatasheet
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Technical content
Document Number: MMPF0200Z Rev. 2.0, 11/2014 Freescale Semiconductor Advance Information * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2014. All rights reserved.
12 Channel Configurable Power
Management Integrated Circuit The PF0200Z Power Management Integrated Circuit (PMIC) provides a highly programmable/ configurable architecture, with fully integrated power devices and minimal external components. With up to four buck converters, one boost regulator, six linear regulators, RTC supply, and coin-cell charger, the PF0200Z can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip One Time Programmable (OTP) memory, the PF0200Z is available in pre- programmed standard versions, or non-programmed to support custom programming. The PF0200Z is especially suited to the i.MX 6SoloLite, i.MX 6Solo and i.MX 6DualLite versions of the i.MX 6 family of devices and is supported by full system level reference designs, and pre-programmed versions of the device. This device is powered by SMARTMOS technology. Features:
- Three to four buck converters, depending on configuration
- Boost regulator to 5.0 V output
- Six general purpose linear regulators
- Programmable output voltage, sequence, and timing
- OTP (One Time Programmable) memory for device configuration
- Coin cell charger and RTC supply
- DDR termination reference voltage
- Power control logic with processor interface and event detection
- I 2C control
- Individually programmable ON, OFF, and Standby modes
Figure 1. Simplified Application Diagram
Applications
- G P S
- Auto infotainment
- Heads up display (HUD)
- Rear displays
- Digital instrumentation cluster (DIC) ES SUFFIX (WF-TYPE)
56 QFN 8X8
i.MX6X I2C Communication I2C Communication PF0200Z Control Signals Parallel control/GPIOS LICELL Charger COINCELL Main Supply VGEN1 VGEN2 VGEN4 VGEN6 SWBST SW3A/B SW1A/B SW2 GPS MIPI uPCIe SATA - FLASH NAND - NOR Interfaces Processor Core Voltages Camera VREFDDR DDR Memory DDR MEMORY INTERFACE SD-MMC/ NAND Mem. SATA HDD WAM GPS MIPI HDMI LDVS Display USB Ethernet CAN
Analog Integrated Circuit Device Data
2 Freescale Semiconductor
Analog Integrated Circuit Device Data Freescale Semiconductor 3 PF0200Z
4 Freescale Semiconductor
1 Orderable Parts
device uses “NP” as the programming code. Contact your Freescale representative for more details. Table 1. Orderable Part Variations
- For Tape and Reel add an R2 suffix to the part number.
- For programming details see Table 8.
2 Internal Block Diagram
Figure 2. Simplified Internal Block Diagram
6 Freescale Semiconductor
3 Pin Connections
3.1 Pinout Diagram
Figure 3. Pinout Diagram
3.2 Pin Definitions
Table 2. PF0200Z Pin Definitions Analog Reserved pin. Connect to GND in application. 12 RSVD2 - - Reserved Reserved for pin to pin compatibility. Connect this pin to VIN. to GNDREF through a board ground plane. GNDREF, via board ground plane. capacitor as close to the pin as possible.
8 Freescale Semiconductor
close to the pin as possible. capacitor as close to the pin as possible. externally via the board ground plane.
34 SW3BIN
close to the pin as possible.
47 VDDOTP I 10 V (3) Digital &
Table 2. PF0200Z Pin Definitions (continued)
48 GNDREF GND - GND Ground reference for the main band gap regulator. close to the pin as possible. allow effective thermal dissipation.
- 10 V Maximum voltage rating during OTP fuse prog ramming. 7.5 V Maximum DC voltage rated otherwise.
- Unused switching regulators should be connected as follow: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should
be connected to VIN with a 0.1 F bypass capacitor.
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4 General Product Characteristics
4.1 Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings damage to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
- ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device
Model (CDM), Robotic (CZAP = 4.0 pF).
4.2 Thermal Characteristics
Table 4. Thermal Ratings
- Do not operate beyond 125 °C for extended periods of time. O peration above 150 °C may cause permanent damage to the IC. See
Table 5 for thermal protection features.
- Pin soldering temperature limit is for 10 seconds maximum durat ion. Not designed for immersion soldering. Exceeding these limits may
cause a malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.
- Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
- The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
- Per JEDEC JESD51-6 with the board horizontal.
- Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top
surface of the board near the package.
- Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1 ).
- Thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature per
JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Analog Integrated Circuit Device Data
12 Freescale Semiconductor
General Product Characteristics
Electrical Characteristics
4.2.1 Power Dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the thermal management and to avoid overheating, the PF0200Z provides thermal protection. An internal comparator monitors the die temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I will be generated when the respective thresholds specified in Table 5 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register INTSENSE0. In the event of excessive power dissipation, thermal protection circuitry will shut down the PF0200Z. This thermal protection will act above the thermal protection threshold listed in Table 5. To avoid any unwanted power downs resulting from internal noise, the protection is debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured such that this protection is not tripped under normal conditions.
4.3 Electrical Characteristics
4.3.1 General Specifications
Table 5. Thermal Protection Thresholds Table 6. General PMIC Static Characteristics
Analog Integrated Circuit Device Data Freescale Semiconductor 13 PF0200Z General Product Characteristics Pin Name Parameter Load Condition Min Max Unit STANDBY VIL –0 . 0 0 . 2 * V S N V S V VIH – 0.8 * VSNVS 3.6 V VDDOTP VIL –0 . 0 0 . 3 V VIH –1 . 1 1 . 7 V Table 6. General PMIC Static Characteristics (continued)
Analog Integrated Circuit Device Data
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General Product Characteristics
4.3.2 Current Consumption
Table 7. Current Consumption Summary 25 °C, unless otherwise noted.
- Refer to Figure 4 for Coin Cell mode characteristics over temperature.
- When VIN is below the UVDET threshold, in the range of 1.8 V VIN < 2.65 V, the quiescent current increases by 50 A, typically.
- For PFM operation, headroom should be 300 mV or greater.
- Additional current may be drawn in the coin cell mode w hen RESETBMCU is pulled up to VSNVS due an internal path from
mode, for non-i.MX 6 applications.
Analog Integrated Circuit Device Data Freescale Semiconductor 15 PF0200Z General Product Characteristics Figure 4. Coin Cell Mode Current Versus Temperature
Analog Integrated Circuit Device Data
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Features
5 General Description
The PF0200Z is the Power Management Integrated Circuit (PMIC) designed primarily for use with Freescale’s i.MX 6 series of application processors.
5.1 Features
This section summarizes the PF0200Z features.
- Input voltage range to PMIC: 2.8 - 4.5 V
- Buck regulators
- Three to four channel configurable
- SW1A/B, 2.5 A; 0.3 to 1.875 V
- S W 2 , 1 . 5 A; 0.4 to 3.3 V
- SW3A/B, 2.5 A (single phase); 0.4 to 3.3 V
- SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 to 3.3 V
- Dynamic voltage scaling
- Modes: PWM, PFM, APS
- Programmable output voltage
- Programmable current limit
- Programmable soft start
- Programmable PWM switching frequency
- Programmable OCP with fault interrupt
- Boost regulator
- SWBST, 5.0 to 5.15 V, 0.6 A, OTG support
- Modes: PFM and Auto
- OCP fault interrupt
- L D O s
- Six user programable LDO
- VGEN1, 0.80 to 1.55 V, 100 mA
- VGEN2, 0.80 to 1.55 V, 250 mA
- VGEN3, 1.8 to 3.3 V, 100 mA
- VGEN4, 1.8 to 3.3 V, 350 mA
- VGEN5, 1.8 to 3.3 V, 100 mA
- VGEN6, 1.8 to 3.3 V, 200 mA
- Soft start
- LDO/Switch supply
- DDR memory reference voltage
- VREFDDR, 0.6 to 0.9 V, 10 mA
- 1 6 MHz internal master clock
- OTP(One time programmable) me mory for device configuration
- User programmable start-up sequence and timing
- Battery backed memory including coin cell charger
- I 2C interface
- User programmable Standby, Sleep, and Off modes
5.2 Functional Block Diagram
Figure 5. Functional Block Diagram
5.3 Functional Description
5.3.1 Power Generation
allow controlled supply rail adjustments for the processor cores and/or other circuitry. the i.MX processors; VSNVS may be powered from VIN, or from a coin cell.
Analog Integrated Circuit Device Data
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5.3.2 Control Logic
The PF0200Z PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start- up section, or by configuring the “Try Before Buy” feature to test different power up sequences before choosing the final OTP configuration. The PF0200Z PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. A charger for the coin cell is included as well.
5.3.2.1 Interface Signals
PWRON is an input signal to the IC that generates a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG bit. Refer to section Turn On Events for more details. STANDBY STANDBY is an input signal to the IC. When it is asserted the part enters standby mode and when de-asserted, the part exits standby mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section Standby Mode for more details. Note: When operating the PMIC at VIN 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide VSNVS, or the PMIC will not reliably enter and exit the STANDBY mode. RESETBMCU RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used to bring the processor out of reset, or as an indicator that all supplies have been enabled; it is only asserted for a turn-off event. When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0200Z is turned off if the fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described above will be repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on Extended Page 1 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode may be permanently chosen by programming OTP fuses. SDWNB SDWNB is an open-drain, active low output that notifies the processor of an imminent PMIC shutdown. It is asserted low for one 32 kHz clock cycle before powering down and is then de-asserted in the OFF state. INTB INTB is an open-drain, active low output. It is asserted when any fault occurs, provided that the fault interrupt is unmasked. INTB is de-asserted after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
6 Functional Block Requirements and Behaviors
6.1 Start-up
100 kohm resistor. The OTP configuration is enabled by connecting VDDOTP to GND.
6.1.1 Device Start-up Configuration
Table 8 shows the Default Configuration which can be accessed on all devices as described previously. Table 8. Start-up Configuration
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Figure 6. Default Start-up Sequence Table 8. Start-up Configuration (continued) *VSNVS will start from 1.0 V if LICELL is valid before VIN.
6.1.2 One Time Prog rammability (OTP)
code(ECC) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. The parameters that can be configured by OTP are listed below.
- General: I 2C slave address, PWRON pin configuration, start-up sequence and timing
- Buck regulators: Output voltage, single phase or indepen dent mode configuration, switching frequency, and soft start ramp rate
- Boost regulator and LDOs: Output voltage NOTE: When prototyping or programming fuses, the user must ensure that register settings are consistent with the hardware configuration. This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it will be gated by the buck regulator in the start-up sequence.
Table 9. Default Start-up Sequence Timing
- Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may
extend to a maximum of 24 ms.
- Depends on the external signal driving PWRON.
- Rise time is a function of slew rate of regulators and nominal voltage selected.
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6.1.2.1 Start-up Sequence and Timing
sequence and will remain off. See Table 10. The delay between each position is equal; however, four delay options are available. See Table 11. The start-up sequence will terminate at the last programmed regulator.
6.1.2.2 PWRON Pin Configuration
on the part and if the switch is held low for greater than or equal to 4.0 seconds, the part will turn off or enter Sleep mode.
6.1.2.3 I 2C Address Configuration
address (I2C_SLV_ADDR[2:0]) are programmable as shown in Table 13. Table 10. Start-up Sequence
00000 Off
00001 SEQ_CLK_SPEED[1:0] * 1
00010 SEQ_CLK_SPEED[1:0] * 2
11111 SEQ_CLK_SPEED[1:0] * 31
Table 11. Start-up Sequence Clock Speed Table 12. PWRON Configuration
0 PWRON pin HIGH = ON
1 PWRON pin pulled LOW momentarily = ON
6.1.2.4 Soft Start Ramp Rate
The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in Dynamic Voltage Scaling.
6.1.3 OTP Prototyping
shown in Table 121 and Table 122.
- If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
- If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 1, the values are loaded from the fuses. It is required to set all the FUSE_PORx bits to load the fuses.
- If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR_XOR = 0, the TBBOTP registers remain initialized at zero. The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP registers maintained and not loaded from a different source. The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and SCL are pulled up, must be powered by a 1.7 to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V, TBB_POR = 1 and there is a valid turn-on event.
6.1.4 Reading OTP Fuses
turn-on event occurs, the PMIC will power on with the configuration programmed in the fuses. Table 13. I2C Address Configuration
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16 MHz and 32 kHz Clocks
6.1.5 Programming OTP Fuses
banks of twenty-six fuses, each that can be programmed.
- VIN < UVDET
- All regulators are in SLEEP mode
- All regulators are in PFM switching mode A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
- During start-up, VIN > UVDET
- PWRON_CFG = 1, for power button debounce timing In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 25 are referenced to the 32 kHz derived from the 16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.
6.2.1 Clock adjustment
Table 14. Source of Start-up Sequence Table 15. 16 MHz Clock Specifications characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
- 2.0 MHz clock is derived from the 16 MHz clock.
6.3 Bias and References Block Description
6.3.1 Internal Core Voltage References
kept powered as long as there is a valid supply and/or valid coin cell. Table 16 shows the main characteristics of the core circuitry.
6.3.1.1 External Components
Table 16. Core Voltages Electrical Specifications(26) characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
- 3.0 V < V IN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system
Table 17. External Components for Core Voltages
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6.3.2 VREFDDR Voltage Reference
low-frequency pole. This divider then utilizes a voltage follower to drive the load. Figure 7. VREFDDR Block Diagram
6.3.2.1 VREFDDR Control Register
The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 18. Table 18. Register VREFDDCRTL - ADDR 0x6A Table 19. VREFDDR External Components(27)
- Use X5R or X7R capacitors.
- VINREFDDR to GND, 1.0 F minimum capacitance is provided by buck regulator output.
Table 20. VREFDDR Electrical Characteristics
- When VREFDDR is off there is a quiescent current of 1.5 A typical.
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6.4 Power Generation
6.4.1 Modes of Operation
the state diagram of the PF0200Z, along with the conditions to enter and exit from each state. Figure 8. State Diagram not possible in the Coin Cell mode and the interrupt signal, INTB, is only active in Sleep, Standby, and ON states.
6.4.1.1 ON Mode
The PF0200Z enters the On mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.
6.4.1.2 OFF Mode
The PF0200Z enters the Off mode after a turn-off event. A thermal shutdown event also forces the PF0200Z into the Off mode. Only VCOREDIG and VSNVS are powered in the mode of operation. To exit the Off mode, a valid turn-on event is required. RESETBMCU is asserted, LOW, in this mode.
6.4.1.3 Standby Mode
- Depending on STANDBY pin configuration, St andby is entered when the STANDBY pin is asserted. This is typically used for low-power mode of operation.
- When STANDBY is de-asserted, Standby mode is exited. A product may be designed to go into a Low-power mode after periods of inactivity. The STANDBY pin is provided for board level control of going in and out of such deep sleep modes (DSM). When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the operating mode of the regulators or disabling some regulators. The configuration of the regulators in Standby is pre- programmed through the I2C interface. Note that the STANDBY pin is programmable for Active High or Active Low polarity, and that decoding of a Standby event will take into account the programmed input polarity as shown in Table 21. When the PF0200Z is powered up first, regulator settings for the Standby mode are mirrored from the regulator settings for the ON mode. To change the STANDBY pin polarity to Active Low, set the STANDBYINV bit via software first, and then change the regulator settings for Standby mode as required. For simplicity, STANDBY will generally be referred to as active high throughout this document. Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor and peripherals some time after a standby instruction has been received to terminate processes to facilitate seamless entering into Standby mode. When enabled (STBYDLY = 01, 10, or 11) per Table 22, STBYDLY will delay the Standby initiated response for the entire IC, until the STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the Standby event.
Table 21. Standby Pin and Polarity Control
- STANDBY = 0: System is not in Sta ndby, STANDBY = 1: System is in Standby
- The state of the STANDBY pin only has influence in On mode.
- Bit 6 in Power Control Register (ADDR - 0x1B)
Table 22. STANDBY Delay - Initiated Response
00 No Delay
01 One 32 k period (default)
10 Two 32 k periods
11 Three 32 k periods
- Bits [5:4] in Power Control Register (ADDR - 0x1B)
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6.4.1.4 Sleep Mode
- Depending on PWRON pin configuration, Sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
- To exit Sleep mode, assert the PWRON pin. In the Sleep mode, the regulator will use the set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B. The activated regulators will maintain settings for this mode and voltage until the next turn-on event. Table 23 shows the control bits in Sleep mode. During Sleep mode, interrupts are active and the INTB pin will report any unmasked fault event.
6.4.1.5 Coin Cell Mode
Coin Cell state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode. Table 23. Regulator Mode Control
- For sleep mode, an activated switching regulator, should use the off
SWxOFF[6:0] for SW2 and SW3A/B.
6.4.2 State Machine Flow Summary
6.4.2.1 Turn On Events
- If PWRON_CFG = 0, the PWRON signal is high and V IN > UVDET, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set.
- If PWRON_CFG = 1, V IN > UVDET and PWRON transitions from high to low, the PMIC will turn on; the interrupt and sense bits, PWRONI and PWRONS respectively, will be set.
Table 24. State Machine Flow Summary
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PWRONDBNC[1:0] as defined in the table below. The interrupt is cleared by software, or when cycling through the OFF mode.
6.4.2.2 Turn Off Events
- PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
- PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRS TEN = 1 and PWRON is held low for longer than 4.0
seconds. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit. Dissipation section for more detailed information.
6.4.3 Power Tree
cell. Refer to Table 26 for a summary of all power supplies provided by the PF0200Z. Table 25. PWRON Hardware Debounce Bit Settings
- The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.
Table 26. Power Tree Summary
- Current rating per independent phase, when SW3A/B is set in single phase, current capability is up to
Table 27. UVDET Threshold
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Figure 9. PF0200Z Typical Power Map
6.4.4 Buck Regulators
Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.
6.4.4.1 Current Limit
current limit condition persists for more than 8.0 ms, a fault interrupt is generated.
6.4.4.2 General Control
load current variation. Available switching modes for buck regulators are presented in Table 28. Table 28. Switching Mode Description OFF The regulator is switched off and the output voltage is discharged. PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. mode depending on load conditions.
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Table 29 summarizes the Buck regulator programmability for Normal and Standby modes. output voltage options are the same for Normal and Standby modes for each regulator. output voltage programmed in its voltage register. set point as programmed by SW1ABOFF[5:0] for SW1A/B and by SWxOFF[6:0] for SW2 and SW3A/B.
- Normal operation: The output voltage is selected by I2C bits SW1AB[5:0] for SW1A/B and SWx[6:0] for SW2 and SW3A/B.
A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 32 and Table 33.
- Standby Mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the
SW1ABDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively. Table 29. Regulator Mode Control
0000 Off Off
0001 PWM Off
0010 Reserved Reserved
0011 PFM Off
0100 APS Off
0101 PWM PWM
0110 PWM APS
0111 Reserved Reserved
1000 APS APS
1001 Reserved Reserved
1010 Reserved Reserved
1011 Reserved Reserved
1100 APS PFM
1101 PWM PFM
1110 Reserved Reserved
1111 Reserved Reserved
- Sleep Mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest
SW1ABDVSSPEED[1:0] and SWxDVSSPEED[1:0] I2C bits shown in Table 32 and Table 33, respectively. Table 30, Table 31, Table 32, and Table 33 summarize the set point control and DVS time stepping applied to all regulators. The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the DVS period the overcurrent condition on the regulator should be masked. Table 30. DVS Control Logic for SW1A/B
0 SW1AB[5:0]
1 SW1ABSTBY[5:0]
Table 31. DVS Control Logic for SW2 and SW3A/B
0 SWx[6:0]
1 SWxSTBY[6:0]
Table 32. DVS Speed Selection for SW1A/B Table 33. DVS Speed Selection for SW2 and SW3A/B
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Figure 10. Voltage Stepping with DVS Table 34. Regulator Phase Clock Selection Table 35. Optimum Phasing
1.0 MHz
2.0 MHz
4.0 MHz
currents are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. the percentage of power stages that are enabled. Table 36. Regulator Frequency Configuration
11 Reserved
Table 37. Programmable Current Configuration
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6.4.4.3 SW1A/B
SW1A/B is a 2.5 A single phase regulator. The SW1ALX and SW1BLX pins should be connected together on the board. SW1_CONFIG[1:0] = 01 is the only configuration supported. count by using only one inductor for SW1A/B. Figure 11 shows the physical connection for SW1A/B in single phase. Figure 11. SW1A/B Single Phase Block Diagram Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register. Table 38. SW1 Configuration
00 Reserved
01 A/B Single Phase
10 Reserved
respectively. Table 39 shows the output voltage coding for SW1A/B. Note: Output voltages of 0.6 V and below are not supported. Table 39. SW1A/B Output Voltage Configuration
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register is provided in Table 41 through Table 45. Table 40. SW1A/B Register Summary Table 41. Register SW1ABVOLT - ADDR 0x20 Table 42. Register SW1ABSTBY - ADDR 0x21 Table 43. Register SW1ABOFF - ADDR 0x22 Table 44. Register SW1ABMODE - ADDR 0x23 SW1ABMODE 3:0 R/W 0x80 Sets the SW1AB switching operation mode. See Table 29 for all possible configurations.
Table 45. Register SW1ABCONF - ADDR 0x24 Table 46. SW1A/B External Component Recommendations
- Use X5R or X7R capacitors.
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Table 47. SW1A/B Electrical Characteristics
- PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 2.5 A 0.625 V VSW1AB 1.450 V 1.475 V VSW1AB 1.875 V
- PFM, steady state, 2.8 V < V IN < 4.5 V, 0 < ISW1AB < 150 mA 0.625 V < VSW1AB < 0.675 V 0.7 V < VSW1AB < 0.85 V 0.875 V < VSW1AB < 1.875 V VSW1ABACC -25 -3.0% -65 -45 -3.0% 3.0% 3.0% mV Rated Output Load Current, (38) 2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V ISW1AB – – 2500 mA Current Limiter Peak Current Detection (38)
- SW1A/B Single Phase (current through inductor) SW1ABILIM = 0 SW1ABILIM = 1 I SW1ABLIM 4.5 3.3 6.5 4.9 8.5 6.4 A Start-up Overshoot ISW1AB = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V VSW1ABOSH –– 6 6 m V Turn-on Time Enable to 90% of end value I SW1AB = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V tONSW1AB – – 500 µs Switching Frequency SW1ABFREQ[1:0] = 00 SW1ABFREQ[1:0] = 01 SW1ABFREQ[1:0] = 10 f SW1AB 1.0 2.0 4.0 MHz Efficiency (Single Phase)
- V IN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 H PFM, 0.9 V, 1.0 mA PFM, 1.2 V, 50 mA APS, PWM, 1.2 V, 500 mA APS, PWM, 1.2 V, 750 mA APS, PWM, 1.2 V, 1250 mA APS, PWM, 1.2 V, 2500 mA SW1AB Output Ripple V SW1AB –1 0– m V Line Regulation (APS, PWM) V SW1ABLIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW1ABLOR –– 2 0 m V
- Transient load = 0 to 1.25 A, di/dt = 100 mA/ s Overshoot Undershoot V SW1ABLOTR – mV Quiescent Current PFM Mode APS Mode I SW1ABQ – 235 µA SW1A P-MOSFET RDSON VINSW1A = 3.3 V RONSW1AP – 215 245 m SW1A N-MOSFET RDSON VINSW1A = 3.3 V RONSW1AN – 258 326 m SW1A P-MOSFET Leakage Current VINSW1A = 4.5 V ISW1APQ –– 7 . 5 µ A SW1A N-MOSFET Leakage Current VINSW1A = 4.5 V ISW1ANQ –– 2 . 5 µ A SW1B P-MOSFET RDSON VINSW1B = 3.3 V RONSW1BP – 215 245 m SW1B N-MOSFET RDSON VINSW1B = 3.3 V RONSW1BN – 258 326 m SW1B P-MOSFET Leakage Current VINSW1B = 4.5 V ISW1BPQ –– 7 . 5 µ A SW1B N-MOSFET Leakage Current VINSW1B = 4.5 V ISW1BNQ –– 2 . 5 µ A Discharge Resistance R SW1ABDIS – 600 – Notes 38. Current rating of SW1AB supports the Power Virus mode of operation of the i.MX6X processor.
Table 47. SW1A/B Electrical Characteristics (continued)
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Figure 12. SW1AB Efficiency Waveforms
6.4.4.4 SW2
Figure 13 shows the block diagram and the external component connections for SW2 regulator. Figure 13. SW2 Block Diagram range from 0.800 to 3.300 V with 50 mV increments, as determined by bits SW2[5:0]. high range, and the lower range be used for voltages from 0.400 to 1.975 V. output voltage coding valid for SW2. Note: Output voltages of 0.6 V and below are not supported.
Table 48. SW2 Output Voltage Configuration
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is provided in Tables 50 to Table 54.
- For voltages less than 2.0 V, only use set points 0 to 63
Table 48. SW2 Output Voltage Configuration (continued)
Table 49. SW2 Register Summary Table 50. Register SW2VOLT - ADDR 0x35 mode. See Table 48 for all possible configurations. for all possible configurations. Table 51. Register SW2STBY - ADDR 0x36 SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during Standby mode. See Table 48 for all possible configurations. Table 48 for all possible configurations. Table 52. Register SW2OFF - ADDR 0x37 Table 48 for all possible configurations. for all possible configurations. Table 53. Register SW2MODE - ADDR 0x38 SW2MODE 3:0 R/W 0x80 Sets the SW2 switching operation mode. See Table 28 for all possible configurations.
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Table 54. Register SW2CONF - ADDR 0x39 SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector. SW2PHASE 5:4 R/W 0x00 SW2 Phase clock selection. SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection. Table 55. SW2 External Component Recommendations
- Use X5R or X7R capacitors.
Table 56. SW2 Electrical Characteristics
- PWM, APS, 2.8 V < V IN < 4.5 V, 0 < ISW2 < 1.5 A 0.625 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V
- PFM, 2.8 V < V IN < 4.5 V, 0 < ISW2 50 mA 0.625 V < VSW2 < 0.675 V 0.7 V < VSW2 < 0.85 V 0.875 V < VSW2 < 1.975 V 2.0 V < VSW2 < 3.3 V VSW2ACC -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV Rated Output Load Current (42) 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V ISW2 – – 1500 mA Current Limiter Peak Current Detection
- Current through Inductor SW2ILIM = 0 SW2ILIM = 1 ISW2LIM 2.1 1.57 3.0 2.25 3.9 2.93 A Start-up Overshoot ISW2 = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW2 = 4.5 V VSW2OSH –– 6 6 m V Turn-on Time Enable to 90% of end value ISW2 = 0.0 mA DVS clk = 50 mV/8 s, VIN = VINSW2 = 4.5 V tONSW2 – – 550 µs Switching Frequency SW2FREQ[1:0] = 00 SW2FREQ[1:0] = 01 SW2FREQ[1:0] = 10 fSW2 1.0 2.0 4.0 MHz Efficiency
- V IN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 H PFM, 3.15 V, 1.0 mA PFM, 3.15 V, 50 mA APS, PWM, 3.15 V, 400 mA APS, PWM, 3.15 V, 600 mA APS, PWM, 3.15 V, 1000 mA APS, PWM, 3.15 V, 1500 mA SW2 Output Ripple V SW2 –1 0– m V Line Regulation (APS, PWM) V SW2LIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW2LOR –– 2 0 m V
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Figure 14. SW2 Efficiency Waveforms
- Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/ s Overshoot Undershoot V SW2LOTR – mV Quiescent Current PFM Mode APS Mode (Low output voltage settings) APS Mode (High output voltage settings) I SW2Q 145 305 µA SW2 P-MOSFET RDSON at VIN = VINSW2 = 3.3 V RONSW2P – 190 209 m SW2 N-MOSFET RDSON at VIN = VINSW2 = 3.3 V RONSW2N – 212 255 m SW2 P-MOSFET Leakage Current VIN = VINSW2 = 4.5 V ISW2PQ –– 1 2 µ A SW2 N-MOSFET Leakage Current VIN = VINSW2 = 4.5 V ISW2NQ –– 4 . 0 µ A Discharge Resistance R SW2DIS – 600 – Notes 41. When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V. 42. The higher output voltages available depend on the voltage dr op in the conduction path as given by the following equation: (VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).
Table 56. SW2 Electrical Characteristics (continued)
6.4.4.5 SW3A/B
modes and Table 29 show the actual configuration options for the SW3xMODE[3:0] bits.
- A single phase
- Independent regulators The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 57 shows the options for the SW3CFG[1:0] bits. SW3A/B Single Phase In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 15. This configuration reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.
Figure 15. SW3A/B Single Phase Block Diagram Table 57. SW3 Configuration
00 A/B Single Phase
11 A/B Independent
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registers as shown in Table 59. Figure 16. SW3A/B Independent Output Block Diagram voltage range from 0.800 to 3.300 V with 50 mV increments, as determined by bits SW3x[5:0]. high range and that that the lower range be used for voltages from 0.400 to 1.975 V. SW3xSTBY[6] and SW3xOFF[6] bits. Therefore, the output voltage range will remain the same on all three operating modes. Table 58 shows the output voltage coding valid for SW3x. Note: Output voltages of 0.6 V and below are not supported.
Table 58. SW3A/B Output Voltage Configuration
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- For voltages less than 2.0 V, only use set points 0 to 63.
Table 58. SW3A/B Output Voltage Configuration (continued)
provided on Tables 60 through Table 69. Table 59. SW3AB Register Summary Table 60. Register SW3AVOLT - ADDR 0x3C for all possible configurations. Table 61. Register SW3ASTBY - ADDR 0x3D
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Table 62. Register SW3AOFF - ADDR 0x3E on bit SW3A[6] during OTP or TBB configuration. for all possible configurations. Table 63. Register SW3AMODE - ADDR 0x3F phase) switching operation mode. for all possible configurations. (Single phase) when in Sleep mode. Table 64. Register SW3ACONF - ADDR 0x40 SW3APHASE 5:4 R/W 0x00 SW3A Phase clock selection. See Table 34. SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 33. Table 65. Register SW3BVOLT - ADDR 0x43 all possible configurations.
Table 66. Register SW3BSTBY - ADDR 0x44 Table 67. Register SW3BOFF - ADDR 0x45 Table 68. Register SW3BMODE - ADDR 0x46 Table 69. Register SW3BCONF - ADDR 0x47 SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 36. SW3BPHASE 5:4 R/W 0x00 SW3B Phase clock selection. See Table 34. SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 33.
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Table 70. SW3A/B External Component Requirements
- Use X5R or X7R capacitors.
Table 71. SW3A/B Electrical Characteristics SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
- PWM, APS 2.8 V < V IN < 4.5 V, 0 < ISW3x < ISW3xMAX 0.625 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V
- PFM , steady state (2.8 V < V IN < 4.5 V, 0 < ISW3x < 50 mA) 0.625 V < VSW3x < 0.675 V 0.7 V < VSW3x < 0.85 V 0.875 V < VSW3x < 1.975 V 2.0 V < VSW3x < 3.3 V VSW3xACC -25 -3.0% -6.0% -65 -45 -3.0% -3.0% 3.0% 6.0% 3.0% 3.0% mV Rated Output Load Current (46)
- 2.8 V < V IN < 4.5 V, 0.625 V < VSW3x < 3.3 V PWM, APS mode single phase PWM, APS mode independent (per phase) ISW3x – 2500 1250 mA
- Single phase (Current through inductor) SW3xILIM = 0 SW3xILIM = 1
- Independent mode (Current through inductor per phase) SW3xILIM = 0 SW3xILIM = 1 I SW3xLIM 3.5 2.7 1.8 1.3 5.0 3.8 2.5 1.9 6.5 4.9 3.3 2.5 A Start-up Overshoot ISW3x = 0.0 mA DVS clk = 25 mV/4 s, VIN = VINSW3x = 4.5 V VSW3xOSH –– 6 6 m V Turn-on Time Enable to 90% of end value ISW3x = 0 mA DVS clk = 25 mV/4 s, VIN = VINSW3x = 4.5 V tONSW3x – – 500 µs Switching Frequency SW3xFREQ[1:0] = 00 SW3xFREQ[1:0] = 01 SW3xFREQ[1:0] = 10 f SW3x 1.0 2.0 4.0 MHz Efficiency (Single Phase)
- f SW3 = 2.0 MHz, LSW3x 1.0 H PFM, 1.5 V, 1.0 mA PFM, 1.5 V, 50 mA APS, PWM 1.5 V, 500 mA APS, PWM 1.5 V, 750 mA APS, PWM 1.5 V, 1250 mA APS, PWM 1.5 V, 2500 mA SW3AB Output Ripple V SW3x –1 0– m V Line Regulation (APS, PWM) V SW3xLIR –– 2 0 m V DC Load Regulation (APS, PWM) V SW3xLOR –– 2 0 m V Transient Load Regulation
- Transient Load = 0.0 mA to I SW3x/2, di/dt = 100 mA/s Overshoot Undershoot VSW3xLOTR – mV Quiescent Current PFM Mode (Single Phase) APS Mode (Single Phase) PFM Mode (Independent mode) APS Mode (SW3A Independent mode) APS Mode (SW3B Independent mode) I SW3xQ 300 250 150 µA SW3A P-MOSFET R DSON at VIN = VINSW3A = 3.3 V RONSW3AP – 215 245 m SW3A N-MOSFET RDSON at VIN = VINSW3A = 3.3 V RONSW3AN – 258 326 m SW3A P-MOSFET Leakage Current VIN = VINSW3A = 4.5 V ISW3APQ –– 7 . 5 µ A
Table 71. SW3A/B Electrical Characteristics (continued) SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
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Figure 17. SW3AB Single Phase Efficiency Waveforms
- When output is set to > 2.6 V the output will follow the input down when V IN gets near 2.8 V.
- The higher output voltages available depend on the voltage dr op in the conduction path as given by the following equation:
(VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance). SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
6.4.5 Boost Regulator
NMOS transistor is integrated on-chip. Figure 18 shows the block diagram and component connection for the boost regulator. Figure 18. Boost Regulator Architecture
6.4.5.1 SWBST Setup and Control
sequence if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros. Table 72. Register SWBSTCTL - ADDR 0x66
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6.4.5.2 SWBST External Components
6.4.5.3 SWBST Specifications
- In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current.
The SWBST regulator starts up by default in the Auto mode, if SWBST is part of the startup sequence. Table 73. SWBST External Component Requirements
- Use X5R or X7R capacitors.
Table 74. SWBST Electrical Specifications VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted. Table 72. Register SWBSTCTL - ADDR 0x66 (continued)
Table 74. SWBST Electrical Specifications (continued) VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
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6.4.6 LDO Regulators Description
to Bias and References Block Description section for further information on the internal reference voltages. of this bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. Figure 19. General LDO Block Diagram
6.4.6.1 Transient Response Waveforms
transient line and load response refers to the overshoot, or undershoot only, excluding the DC shift. Figure 20. Transient Waveforms
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6.4.6.2 Short-circuit Protection
maskable through the VGENxFAULTM mask bit. for SCP behavior configuration.
6.4.6.3 LDO Regulator Control
voltage according to Table 76 for VGEN1 and VGEN2; and uses the voltage set point on Table 77 for VGEN3 through VGEN6. Table 75. Short-circuit Behavior
0 Current limit
1 Shutdown
Table 76. VGEN1, VGEN2 Output Voltage Configuration
Table 77. VGEN3/ 4/ 5/ 6 Output Voltage Configuration Table 78. LDO Control
- STANDBY refers to a Standby event as described earlier.
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Table 79. Register VGEN1CTL - ADDR 0x6C VGEN1 3:0 R/W 0x80 Sets VGEN1 output voltage. See Table 76 for all possible configurations. Table 80. Register VGEN2CTL - ADDR 0x6D VGEN2 3:0 R/W 0x80 Sets VGEN2 output voltage. See Table 76 for all possible configurations. Table 81. Register VGEN3CTL - ADDR 0x6E VGEN3 3:0 R/W 0x80 Sets VGEN3 output voltage. See Table 77 for all possible configurations.
Table 82. Register VGEN4CTL - ADDR 0x6F VGEN4 3:0 R/W 0x80 Sets VGEN4 output voltage. See Table 77 for all possible configurations. Table 83. Register VGEN5CTL - ADDR 0x70 VGEN5 3:0 R/W 0x80 Sets VGEN5 output voltage. See Table 77 for all possible configurations. Table 84. Register VGEN6CTL - ADDR 0x71 VGEN6 3:0 R/W 0x80 Sets VGEN6 output voltage. See Table 77 for all possible configurations.
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6.4.6.4 External Components
Table 85 lists the typical component values for the general purpose LDO regulators.
6.4.6.5 LDO Specifications
Table 85. LDO External Components
- Use X5R/X7R ceramic capacitors.
Table 86. VGEN1 Electrical Characteristics IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN1 = 75 mA, 20 Hz to 20 kHz VGEN1[3:0] = 0000 - 1101 VGEN1[3:0] = 1110, 1111 PSRRVGEN1 50 dB Output Noise Density VIN1 = 1.75 V, IGEN1 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISE VGEN1 – -108 -118 -124 -100 -108 -112 dBV/ Hz Turn-on Slew Rate
- 10% to 90% of end value
- 1 . 7 5 V VIN1 3.4 V, IGEN1 = 0.0 mA VGEN1[3:0] = 0000 to 0111 VGEN1[3:0] = 1000 to 1111 SLWRVGEN1 12.5 16.5 mVs Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN1 = 0.0 mA GEN1tON 60 – 500 s Turn-Off Time Disable to 10% of initial value, VIN1 = 1.75 V IGEN1 = 0.0 mA GEN1tOFF –– 1 0 m s Start-Up Overshoot Transient Load Response
- V IN1 = 1.75 V, 3.4 V IGEN1 = 10 to 100 mA in 1.0 s. Peak of overshoot or undershoot of VGEN1 with respect to final value
- Refer to Figure 20 VGEN1LOTR –– 3 . 0 % Transient Line Response
- I GEN1 = 75 mA VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for VGEN1[3:0] = 0000 to 1101 VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for VGEN1[3:0] = 1110, 1111
- Refer to Figure 20 VGEN1LITR –5 . 0 8 . 0 m V Notes 52. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout region of the regulator under test.
Table 86. VGEN1 Electrical Characteristics (continued) IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
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Table 87. VGEN2 Electrical Characteristics IGEN2 = 10mA and 25°C, unless otherwise noted.
- I GEN2 = 187.5 mA, 20 Hz to 20 kHz VGEN2[3:0] = 0000 - 1101 VGEN2[3:0] = 1110, 1111 PSRRVGEN2 50 dB Output Noise Density
- V IN1 = 1.75 V, IGEN2 = 187.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN2 – -108 -118 -124 -100 -108 -112 dBV/ Hz Turn-On Slew Rate
- 10% to 90% of end value
- 1 . 7 5 V VIN1 3.4 V, IGEN2 = 0.0 mA VGEN2[3:0] = 0000 to 0111 VGEN2[3:0] = 1000 to 1111 SLWRVGEN2 12.5 16.5 mVs Turn-On Time Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V IGEN2 = 0.0 mA GEN2tON 60 – 500 s
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
operate in the dropout region of the regulator under test. Table 87. VGEN2 Electrical Characteristics (continued) IGEN2 = 10mA and 25°C, unless otherwise noted.
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Table 88. VGEN3 Electrical Characteristics IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN3 = 75 mA, 20 Hz to 20 kHz VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V PSRRVGEN3 35 dB Output Noise Density
- V IN2 = VIN2MIN, IGEN3 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISE VGEN3 – -114 -129 -135 -102 -123 -130 dBV/ Hz Turn-on Slew Rate
- 10% to 90% of end value
- V I N 2 MINVIN2 3.6 V, IGEN3 = 0.0 mA VGEN3[3:0] = 0000 to 0011 VGEN3[3:0] = 0100 to 0111 VGEN3[3:0] = 1000 to 1011 VGEN3[3:0] = 1100 to 1111 SLWR VGEN3 – 22.0 26.5 30.5 34.5 mVs
- When the LDO Output voltage is set above 2.6 V, the minimum al lowed input voltage needs to be at least the output voltage plus 0.25 V,
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
Table 88. VGEN3 Electrical Characteristics (continued) IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
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Table 89. VGEN4 Electrical Characteristics IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN4 = 262.5 mA, 20 Hz to 20 kHz VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V PSRRVGEN4 35 dB Output Noise Density
- V IN2 = VIN2MIN, IGEN4 = 262.5 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN4 – -114 -129 -135 -102 -123 -130 dBV/ Hz Turn-on Slew Rate
- 10% to 90% of end value
- V I N 2MIN VIN2 3.6 V, IGEN4 = 0.0 mA VGEN4[3:0] = 0000 to 0011 VGEN4[3:0] = 0100 to 0111 VGEN4[3:0] = 1000 to 1011 VGEN4[3:0] = 1100 to 1111 SLWR VGEN4 – 22.0 26.5 30.5 34.5 mVs
- When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
Table 89. VGEN4 Electrical Characteristics (continued) IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
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Table 90. VGEN5 Electrical Characteristics IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN5 = 75 mA, 20 Hz to 20 kHz VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V PSRRVGEN5 35 dB Output Noise Density
- V IN3 = VIN3MIN, IGEN5 = 75 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN5 – -114 -129 -135 -102 -123 -130 dBV/ Hz Turn-on Slew Rate
- 10% to 90% of end value
- V I N 3MIN VIN3 4.5 mV, IGEN5 = 0.0 mA VGEN5[3:0] = 0000 to 0011 VGEN5[3:0] = 0100 to 0111 VGEN5[3:0] = 1000 to 1011 VGEN5[3:0] = 1100 to 1111 SLWR VGEN5 – 22.0 26.5 30.5 34.5 mVs
- When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
Table 90. VGEN5 Electrical Characteristics (continued) IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
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Table 91. VGEN6 Electrical Characteristics IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
- I GEN6 = 150 mA, 20 Hz to 20 kHz VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V PSRRVGEN6 35 dB Output Noise Density
- V IN3 = VIN3MIN, IGEN6 = 150 mA 100 Hz – <1.0 kHz 1.0 kHz – <10 kHz 10 kHz – 1.0 MHz NOISEVGEN6 – -114 -129 -135 -102 -123 -130 dBV/ Hz Turn-On Slew Rate
- 10% to 90% of end value
- V I N 3 MIN VIN3 4.5 V. IGEN6 = 0.0 mA VGEN6[3:0] = 0000 to 0011 VGEN6[3:0] = 0100 to 0111 VGEN6[3:0] = 1000 to 1011 VGEN6[3:0] = 1100 to 1111 SLWR VGEN6 – 22.0 26.5 30.5 34.5 mVs Turn-on Time Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V IGEN6 = 0.0 mA GEN6tON 60 – 500 s
6.4.7 VSNVS LDO/Switch
voltage minus the voltage drop across the switch, which is 40 mV at a rated maximum load current of 400 A. voltages as when VIN is applied, providing certain conditions are met as described in Table 92.
- When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V
for proper regulation due to the dropout voltage generated through the internal LDO transistor.
- The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied
Table 91. VGEN6 Electrical Characteristics (continued) IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
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Figure 21. VSNVS Supply Switch Architecture The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 93. Table 92. VSNVS Modes of Operation Table 93. Register VSNVSCTL - ADDR 0x6B
- Only valid when a valid input voltage is present.
Table 94. VSNVS External Components
2.25 V (VTL0) -
Table 95. VSNVS Electrical Characteristics
- 5 . 0 A < ISNVS < 400 A (OFF) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
- 5 . 0 A < ISNVS < 400A (ON) 3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110 UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
- 5 0A < ISNVS < 400 A (Coin Cell mode) 2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110 1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101] VSNVS -5.0% -8.0% -5.0% -4.0% VCOIN-0.04 -8.0% 3.0 1.0 - 1.8 3.0 1.0 - 1.8 1.0 - 1.8 7.0% 7.0% 5.0% 4.0% VCOIN 7.0% V Dropout Voltage VIN = VCOIN = 2.85 V, VSNVSVOLT[2:0] = 110, ISNVS = 400 A VSNVSDROP –– 5 0 m V Current Limit VIN > VTH1, VSNVSVOLT[2:0] = 110 VIN > VTH0, VSNVSVOLT[2:0] = 000 to 101 VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101 ISNVSLIM 1100 500 480 6750 6750 4500 V IN Threshold (Coin Cell Powered to VIN Powered) VIN going high with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 V TH0 2.25 2.40 2.55 V VIN Threshold (VIN Powered to Coin Cell Powered) VIN going low with valid coin cell VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 V TL0 2.20 2.35 2.50 V VIN Threshold Hysteresis for VTH1-VTL1 VHYST1 5.0 – – mV VIN Threshold Hysteresis for VTH0-VTL0 VHYST0 5.0 – – mV Output Voltage During Crossover VSNVSVOLT[2:0] = 110 VCOIN > 2.9 V Switch to LDO: VIN > 2.825 V, ISNVS = 100 A LDO to Switch: VIN < 3.05 V, ISNVS = 100 A VSNVSCROSS 2.70 – – V
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3.1 V (UVDETL)< V
- For 1.8 V I SNVS limited to 100 A for VCOIN < 2.1 V
- The start-up of VSNVS is not monotonic. It first rises to 1. 0 V and then settles to its programmed value within the specified tR1 time.
- From coin cell insertion to VSNVS =1.0 V, the delay time is typically 400 ms.
- During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though t his is
outside the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause any malfunction. clock cycles before switching back to the external crystal oscillator. Table 95. VSNVS Electrical Characteristics (continued)
6.4.7.1 Coin Cell Battery Backup
between 1.8 and 3.0 V. A small capacitor should be placed from LICELL to ground under all circumstances. programmable through the VCOIN[2:0] bits on register COINCTL on Table 97. The coin cell charger voltage is programmable. charging will be stopped when VIN is below UVDET. Table 96. Coin Cell Charger Voltage
- Coin cell voltages selected based on the
type of LICELL used on the system. Table 97. Register COINCTL - ADDR 0x1A Coin cell charger output voltage selection. Table 98. Coin Cell Charger External Components
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6.5 Control Interface I 2C Block Description
registers the resources of the IC can be controlled. The registers also provide status information about how the IC is operating. and SDA to ground for bus pull-up resistors of 4.8 kohm.
6.5.1 I2C Device ID
new slave address; these bits take affect right away.
6.5.2 I 2C Operation
each byte will be sent out unless a STOP command or NACK is received prior to completion. The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. Figure 22. I2C Write Example Table 99. Coin Cell Charger Specifications
Figure 23. I2C Read Example
6.5.3 Interrupt Handling
occurs while the processor clears an existing interrupt bit, the INTB pin will remain low. bit was already high, the INTB pin will go low after unmasking. The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.5.4 Interrupt Bit Summary
descriptions, refer to the related chapters. Table 100. Interrupt, Mask and Sense Bits
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A full description of all interrupt, mask, and sense registers is provided in Tables 101 to 112.
- Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
Table 101. Register INTSTAT0 - ADDR 0x05 Table 102. Register INTMASK0 - ADDR 0x06 Table 100. Interrupt, Mask and Sense Bits (continued)
Table 103. Register INTSENSE0 - ADDR 0x07 Table 104. Register INTSTAT1 - ADDR 0x08
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Table 105. Register INTMASK1 - ADDR 0x09 Table 106. Register INTSENSE1 - ADDR 0x0A Table 107. Register INTSTAT3 - ADDR 0x0E Table 108. Register INTMASK3 - ADDR 0x0F
Table 109. Register INTSENSE3 - ADDR 0x10 Table 110. Register INTSTAT4 - ADDR 0x11 Table 111. Register INTMASK4 - ADDR 0x12 Table 112. Register INTSENSE4 - ADDR 0x13
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6.5.5 Specific Registers
6.5.5.1 IC and Version Identification
Table 113. Register DEVICEID - ADDR 0x00 DEVICEID 3:0 R 0x01 Die version. Table 114. Register SILICON REV- ADDR 0x03
- Default value depends on the silicon revision.
Table 115. Register FABID - ADDR 0x04 Table 112. Register INTSENSE4 - ADDR 0x13 (continued)
6.5.5.2 Embedded Memory
for bit retention with coin cell backup.
6.5.6 Register Bitmap
write to the page register is necessary.
- R is read-only access
- R/W is read and write access
- RW1C is read and write access with write 1 to clear
Table 116. Register MEMA ADDR 0x1C Table 117. Register MEMB ADDR 0x1D Table 118. Register MEMC ADDR 0x1E Table 119. Register MEMD ADDR 0x1F
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Reset: Reset signals are color coded based on the following legend. Default: The value after reset, as noted in the Default column of the memory map.
- Fixed defaults are explicitly declared as 0 or 1.
- “X” corresponds to Read / Write bits that are initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits that may have other dependencies. For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts.
6.5.6.1 Register map
Table 120. Functional Page
00 DeviceID R 8'b0001_0001
03 SILICONREVID R 8'b0001_0000
04 FABID R 8'b0000_0000
05 INTSTAT0 RW1C 8'b0000_0000
06 INTMASK0 R/W 8'b0011_1111
07 INTSENSE0 R 8'b00xx_xxxx
08 INTSTAT1 RW1C 8'b0000_0000
09 INTMASK1 R/W 8'b0111_1111
10 INTSENSE3 R 8'b0000_000x
11 INTSTAT4 RW1C 8'b0000_0000
12 INTMASK4 R/W 8'b0011_1111
13 INTSENSE4 R 8'b00xx_xxxx
20 SW1ABVOLT R/W/M 8'b00xx_xxxx
21 SW1ABSTBY R/W 8'b00xx_xxxx
22 SW1ABOFF R/W 8'b00xx_xxxx
23 SW1ABMODE R/W 8'b0000_1000
24 SW1ABCONF R/W 8'bxx00_xx00
35 SW2VOLT R/W 8'b0xxx_xxxx
Table 120. Functional Page (continued)
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36 SW2STBY R/W 8'b0xxx_xxxx
37 SW2OFF R/W 8'b0xxx_xxxx
38 SW2MODE R/W 8'b0000_1000
39 SW2CONF R/W 8'bxx01_xx00
40 SW3ACONF R/W 8'bxx10_xx00
43 SW3BVOLT R/W 8'b0xxx_xxxx
44 SW3BSTBY R/W 8'b0xxx_xxxx
45 SW3BOFF R/W 8'b0xxx_xxxx
46 SW3BMODE R/W 8'b0000_1000
47 SW3BCONF R/W 8'bxx10_xx00
66 SWBSTCTL R/W 8'b0xx0_10xx
70 VGEN5CTL R/W 8'b000x_xxxx
71 VGEN6CTL R/W 8'b000x_xxxx
Table 121. Extended Page 1
80 OTP FUSE READ
84 OTP LOAD MASK R/W 8'b0000_0000
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Table 121. Extended Page 1 (continued)
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- In PF0200Z It is required to set all of the FUSE_PORx bits to be able to load the fuses.
Table 122. Extended Page 2
81 SW1AB PWRSTG R/W 8'b1111_1111
84 SW2 PWRSTG R 8'b1111_1111
85 SW3A PWRSTG R 8'b1111_1111
86 SW3B PWRSTG R 8'b1111_1111
87 PWRCTRL R 8'b0111_1111
88 PWRCTRL OTP
90 IO DRV R/W 8'b00xx_xxxx
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Table 122. Extended Page 2 (continued)
- Do not write in reserved registers.
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7 Typical Applications
7.1 Introduction
component references and additional components such as filters, refer to the individual sections.
7.1.1 Application Diagram
Figure 24. Typical Application Schematic
7.1.2 Bill of Material
equivalent components may be used. Table 123. Bill of Material (72)
1 Power management IC MMPF0200NPAZES Freescale
108 Freescale Semiconductor
1.0 A 1 20 V SOD-123FL MBR120VLSFT1G ON Semiconductor Schottky Diode
Table 123. Bill of Material (72) (continued)
7.2 PF0200Z Layout Guidelines
7.2.1 General Board Recommendations
- It is recommended to use an eight layer board stack-up arranged as follows:
- High current signal
- G N D
- S i g n a l
- Power
- Power
- S i g n a l
- G N D
- High current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER RO UTING (high-current signals), copper-pour the unused area. 3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.
7.2.2 Component Placement
- Freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circuit drawings
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7.2.3 General Routing Requirements
- Some recommended things to keep in mind for manufacturability:
- Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
- Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
- Minimum allowed spacing between line and hole pad is 3.5 mils
- Minimum allowed spacing between line and line is 3.0 mils 2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be also shielded. 3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. Avoid coupling traces between important signal/low no ise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node (i.e. SW1ALX, SW1BLX, SW2LX, SW3ALX, SW3BLX, and SWBSTLX). 5. Make sure that all components related to a specif ic block are referenced to the corresponding ground.
7.2.4 Parallel Routing Requirements
- CLK is the fastest signal of the system, so it must be given special care.
- To avoid contamination of these delicate signals by near by high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.
Figure 25. Recommended Shielding for Critical Signals
- These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
- Care must be taken with these signals not to contamin ate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
7.2.5 Switching Regulator Layout Recommendations
- Per design, the switching regulators in PF0200Z are designed to operate with only one input bulk capacitor. However, it is
capacitor should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
- Make high-current ripple traces low-inductance (short, high W/L ratio).
- Make high-current traces wide or copper islands.
Figure 26. Generic Buck Regulator Architecture Figure 27. Recommended Layout for Buck Regulators
Analog Integrated Circuit Device Data
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7.3 Thermal Information
7.3.1 Rating Data
The thermal rating data of the packages has been simulated with the results listed in Table 4. Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta- JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.
7.3.2 Estimation of Junction Temperature
An estimation of the chip junction temperature TJ can be obtained from the equation: TJ = TA + (RθJA x PD) with: TA = Ambient temperature for the package in °C RJA = Junction to ambient thermal resistance in °C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RθJB x PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See Functional Block Requirements and Behaviors for more details on thermal management.
8 Packaging
8.1 Packaging Dimensions
for specific thermal characteristics for each package. Table 124. Package Drawing Information
Analog Integrated Circuit Device Data
114 Freescale Semiconductor
REV. A
Analog Integrated Circuit Device Data Freescale Semiconductor 115 PF0200Z Packaging Packaging Dimensions ES SUFFIX 56-PIN QFN 98ASA00589D REV. A
Analog Integrated Circuit Device Data
116 Freescale Semiconductor
REV. A
Analog Integrated Circuit Device Data Freescale Semiconductor 117 PF0200Z
Revision History
9 Revision History
REVISION DATE DESCRIPTION OF CHANGES 1.0 5/2014 • Initial release 2.0 11/2014 • Updated as per PB 16483
- Updated VTL1, VTH1 and VSNVScross specifications
Document Number: MMPF0200Z Rev. 2.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2014 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support