PES32T8

PES32T8 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 38

Technical content

Features

‹ High Performance PCI Express Switch – Thirty-two 2.5 Gbps PCI Express lanes – Eight switch ports – Upstream port configurable up to x8 – Downstream ports configurable up to x8 – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – One virtual channel – Eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ‹ Flexible Architecture with Numerous Configuration Options – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Ability to load device conf iguration from serial EEPROM ‹ Legacy Support – PCI compatible INTx emulation – Bus locking ‹ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates thirty-two 2.5 G bps embedded SerDes with 8B/10B encoder/decoder (no separate transceivers needed) ‹ Reliability, Availability, and Serviceability (RAS) Features – Supports ECRC and Advanced Error Reporting – Internal end-to-end parity protecti on on all TLPs ensures data integrity even in systems t hat do not implement end-to-end CRC (ECRC) – Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O – Compatible with Hot-Plug I/O expanders used on PC and server motherboards Block Diagram Figure 1 Internal Block Diagram 8-Port Switch Core / 32 PCI Express Lanes Frame Buffer Route Table Port Arbitration Scheduler SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer SerDes Phy Logical Layer Multiplexer / Demultiplexer Transaction Layer Data Link Layer SerDes Phy Logical Layer (Port 0) (Port 1) (Port 7) 89PES32T8 Data Sheet 32-Lane 8-Port PCI Express® Switch

2 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet ‹ Power Management – Utilizes advanced low-power desi gn techniques to achieve low typical power consumption – Supports PCI Power Management Interface specification (PCI-PM 1.1)

• Supports device power management states: D0, D3 hot and D3cold – Unused SerDes are disabled ‹ Testability and Debug Features – Ability to read and write any in ternal register via the SMBus ‹ Sixteen General Purpose Input/Output Pins – Each pin may be individually co nfigured as an input or output – Each pin may be individually co nfigured as an interrupt input – Some pins have selectable alternate functions ‹ Packaged in a 31mm x 31mm 500-ball BGA with 1mm ball spacing Product Description Utilizing standard PCI Express in terconnect, the PES32T8 provides the most efficient I/O connectivity solution for applications requiring high throughput, low latency, and simple board layout with a minimum number of board layers. It provides c onnectivity for up to 8 ports across 32 integrated serial lanes. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully compliant with PCI Express Base specifica- tion revision 1.1. The PES32T8 is based on a flexible and efficient layered architec- ture. The PCI Express layers consist of SerDes, Physical, Data Link and Transaction layers. The PES32T8 can operate either as a store and forward switch or a cut-through switch and is designed to switch memory and I/O transactions. It suppor ts eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated resource management to enable efficient switching and I/O connectivity. Figure 2 I/O Expansion Application MemoryMemoryMemory Processor MemoryNorth Bridge PES32T8 I/O 10GbE I/O 10GbE I/O SATA I/O SATAPCI Express Slots Processor x4 x4 x8 x8

3 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Figure 3 Configuration Options Note: The configurations in the above diagram show the maximum port widths. The PES32T8 can negotiate to narrower port widths — x4, x2, or x1. SMBus Interface The PES32T8 contains two SMBus interfaces. T he slave interface provides full access to the configuration registers in the PES32 T8, allowing every configuration r egister in the device to be read or written by an exte rnal agent. The master interface allows the default configuration register values of the PES32T8 to be overridden following a reset with val ues programmed in an external se rial EEPROM. The master interf ace is also used by an external Hot-Plug I/O expander. Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an SMBus data pin, and 4 SMBus address pins. In the slave interface, these address pins allow the SMBus address to which the device responds to be configured. In the master in terface, these address pins allow the SMBus address of the serial configuration EEPROM from which data is loaded to be configured. The SMBus address is set up on negation of PERSTN by sampling the corr esponding address pins. When the pins are sa mpled, the resulting address is assigned as shown in Table 1. Bit Slave SMBus Address Master SMBus Address

1 SSMBADDR[1] MSMBADDR[1]

2 SSMBADDR[2] MSMBADDR[2]

3 SSMBADDR[3] MSMBADDR[3]

4 0 MSMBADDR[4]

5 SSMBADDR[5] 1

Table 1 Master and Slave SMBus Address Assignment PES32T8 PES32T8 PES32T8 PCIe x8 7-port 6-port 5-port 4-port x4x4 x4 x4x8 x8 upstreamX4 upstream 8-port PES32T8 PES32T8 PCIe x8PCIe x8PCIe x8 x8 x8 x8x4x8 x8 x4 PCIe x4 x4x4 x4 x4x4x4 x4x4 x4x4x4 x4 x4 PES32T8 PES32T8 PES32T8 PCIe x8 7-port 6-port 5-port 4-port x4x4 x4 x4x8 x4x4 x4 x4x8 x4x4 x4 x4 x4x4x4x4 x4x4 x4x4x8 x8 upstreamX4 upstream 8-port PES32T8 PES32T8 PCIe x8PCIe x8PCIe x8 x8 x8 x8x4x8 x8 x4 x4x4x8x8 x8x8 x4x4 PCIe x4 x4x4 x4x4 x4x4x4 x4x4 x4x4x4 x4 x4

4 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet As shown in Figure 4, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure 4(a), the master and slave SMBuses are tied together and the PES32T8 acts both as a SMBus master as well as a SMBus slave on th is bus. This requires that the SMBus master or processor that has access to PES32T8 registers supports SMBus arbitration. In some systems, this SMBus master interface may be implemented using general pur pose I/O pins on a processor or micro c ontroller, and may not support SMBus arbitration. To support these systems, the PES32T8 may be configured to operate in a split configuration as shown in Figure 4(b). In the split configuration, the master and slave SMBuses oper ate as two independent buses and thus multi-master arbitration is never required. The PES32T8 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. Figure 4 SMBus Interface Configuration Examples Hot-Plug Interface The PES32T8 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES 32T8 utilizes an external I/O expander, such as that used on PC mother boards, connected to the SMBus mast er interface. Following res et and configura- tion, whenever the state of a Hot-Plug out put needs to be modified, the PES32T8 generat es an SMBus transaction to the I/O expan der with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate function of GPIO) of the PES32T8. In response to an I/O expander interrupt, the PES32T8 generates an SMBus transacti on to read the state of all of the Hot-Plug inputs from the I/O expander. General Purpose Input/Output The PES32T8 provides 16 General Purpose Inpu t/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip fu nctions. These alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM. Processor PES32T8 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM Processor PES32T8 SSMBCLK SSMBDAT MSMBCLK MSMBDAT SMBus Master Other SMBus Devices Serial EEPROM (a) Unified Configuration and Management Bus (b) Split Configuration and Management Buses

5 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Pin Description The following tables lists the functions of the pins provided on the PES32T8. Some of the functions listed may be multiplexed o nto the same pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Signal Type Name/Description PE0RP[3:0] PE0RN[3:0] I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for port 0. Port 0 is the upstream port. PE0TP[3:0] PE0TN[3:0] O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 0. Port 0 is the upstream port. PE1RP[3:0] PE1RN[3:0] I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pairs for port 1. When port 0 is merged with port 1, these signals become port 0 receive pairs for lanes 4 through 7. PE1TP[3:0] PE1TN[3:0] O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 1. When port 0 is merged with port 1, these signals become port 0 transmit pairs for lanes 4 through 7. PE2RP[3:0] PE2RN[3:0] I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for port 2. PE2TP[3:0] PE2TN[3:0] O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 2. PE3RP[3:0] PE3RN[3:0] I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive pairs for port 3. When port 2 is merged with port 3, these signals become port 2 receive pairs for lanes 4 through 7. PE3TP[3:0] PE3TN[3:0] O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 3. When port 2 is merged with port 3, these signals become port 2 transmit pairs for lanes 4 through 7. PE4RP[3:0] PE4RN[3:0] I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive pairs for port 4. PE4TP[3:0] PE4TN[3:0] O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 4. PE5RP[3:0] PE5RN[3:0] I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive pairs for port 5. When port 4 is merged with port 5, these signals become port 4 receive pairs for lanes 4 through 7. PE5TP[3:0] PE5TN[3:0] O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 5. When port 4 is merged with port 5, these signals become port 4 transmit pairs for lanes 4 through 7. PE6RP[3:0] PE6RN[3:0] I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive pairs for port 6. PE6TP[3:0] PE6TN[3:0] O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 6. PE7RP[3:0] PE7RN[3:0] I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive pairs for port 7. When port 6 is merged with port 7, these signals become port 6 receive pairs for lanes 4 through 7. Table 2 PCI Express Interface Pins (Part 1 of 2)

6 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet PE7TP[3:0] PE7TN[3:0] O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans- mit pairs for port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs for lanes 4 through 7. PEREFCLKP[2:1] PEREFCLKN[2:1] I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the dif- ferential reference clock is determined by the REFCLKM signal. REFCLKM I PCI Express Reference Clock Mode Select. This signal selects the fre- quency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz Signal Type Name/Description MSMBADDR[4:1] I Master SMBus Address. These pins determine the SMBus address of the serial EEPROM from which configuration information is loaded. MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the master SMBus. It is active and generating the clock only when the EEPROM or I/O Expanders are being accessed. MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas- ter SMBus. SSMBADDR[5,3:1] I Slave SMBus Address. These pins determine the SMBus address to which the slave SMBus interface responds. SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans- fers on the slave SMBus. SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus. Table 3 SMBus Interface Pins Signal Type Name/Description Table 2 PCI Express Interface Pins (Part 2 of 2)

7 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Signal Type Name/Description GPIO[0] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P2RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 2 GPIO[1] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P4RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 4 GPIO[2] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN0 Alternate function pin type: Input Alternate function: I/O Expander interrupt 0 input GPIO[3] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN1 Alternate function pin type: Input Alternate function: I/O Expander interrupt 1 input GPIO[4] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN2 Alternate function pin type: Input Alternate function: I/O Expander interrupt 2 input GPIO[5] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: IOEXPINTN3 Alternate function pin type: Input Alternate function: I/O Expander interrupt 3 input GPIO[6] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: Reserved Alternate function pin type: Input Alternate function: Reserved GPIO[7] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: GPEN Alternate function pin type: Output Alternate function: General Purpose Event (GPE) output GPIO[8] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P1RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 1 GPIO[9] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P3RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 3 Table 4 General Purpose I/O Pins (Part 1 of 2)

8 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet GPIO[10] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P5RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 5 GPIO[11] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P6RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 6 GPIO[12] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Alternate function pin name: P7RSTN Alternate function pin type: Output Alternate function: Reset output for downstream port 7 GPIO[13] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[14] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. GPIO[15] I/O General Purpose I/O. This pin can be configured as a general purpose I/O pin. Signal Type Name/Description CCLKDS I Common Clock Downstream. When the CCLKDS pin is asserted, it indi- cates that a common clock is being used between the downstream device and the downstream port. CCLKUS I Common Clock Upstream. When the CCLKUS pin is asserted, it indi- cates that a common clock is being used between the upstream device and the upstream port. MSMBSMODE I Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus should operate at 100 KHz instead of 400 KHz. This value may not be overridden. P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 0 is merged with port 1 to form a single x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0. When this pin is high, port 0 and port 1 are not merged, and each oper- ates as a single x4 port P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 2 is merged with port 3 to form a single x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7 of port 2. When this pin is high, port 2 and port 3 are not merged, and each oper- ates as a single x4 port. Table 5 System Pins (Part 1 of 2) Signal Type Name/Description Table 4 General Purpose I/O Pins (Part 2 of 2)

9 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 4 is merged with port 5 to form a single x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7 of port 4. When this pin is high, port 4 and port 5 are not merged, and each oper- ates as a single x4 port. P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low internally via a 251K ohm resistor. When this pin is low, port 6 is merged with port 7 to form a single x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7 of port 6. When this pin is high, port 6 and port 7 are not merged, and each oper- ates as a single x4 port. PERSTN I Fundamental Reset. Assertion of this signal resets all logic inside the PES32T8 and initiates a PCI Express fundamental reset. RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES32T8 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active. This allows software to read and write registers internal to the device before normal device opera- tion begins. The device exits the reset state when the RSTHALT bit is cleared in the SWCTL register by an SMBus master. SWMODE[3:0] I Switch Mode. These configuration pins determine the PES32T8 switch operating mode. These pins should be static and not change after the negation of PERSTN. 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM initialization 0x2 - through 0xF Reserved Signal Type Name/Description JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system clock with a nominal 50% duty cycle. JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG Controller. JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary scan logic or JTAG Controller. When no data is being shifted out, this signal is tri-stated. JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the boundary scan logic or JTAG Controller. JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary scan logic and JTAG TAP Controller. An external pull-up on the board is recommended to meet the JTAG specification in cases where the tester can access this signal. However, for systems running in functional mode, one of the following should occur: 1) actively drive this signal low with control logic 2) statically drive this signal low with an external pull-down on the board Table 6 Test Pins Signal Type Name/Description Table 5 System Pins (Part 2 of 2)

10 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Signal Type Name/Description VDDCORE I Core VDD. Power supply for core logic. VDDIO I I/O VDD. LVTTL I/O buffer power supply. VDDPE I PCI Express Digital Power. PCI Express digital power used by the digital power of the SerDes. VDDAPE I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. VTTPE I PCI Express Serial Data Transmit Termination Voltage. VSS I Ground. Table 7 Power and Ground Pins

11 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Pin Characteristics Note: Some input pads of the PES32T8 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can cause a slight increase in power consumption. Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes PCI Express Inter- face PE0RN[3:0] I CML Serial Link PE0RP[3:0] I PE0TN[3:0] O PE0TP[3:0] O PE1RN[3:0] I PE1RP[3:0] I PE1TN[3:0] O PE1TP[3:0] O PE2RN[3:0] I PE2RP[3:0] I PE2TN[3:0] O PE2TP[3:0] O PE3RN[3:0] I PE3RP[3:0] I PE3TN[3:0] O PE3TP[3:0] O PE4RN[3:0] I PE4RP[3:0] I PE4TN[3:0] O PE4TP[3:0] O PE5RN[3:0] I PE5RP[3:0] I PE5TN[3:0] O PE5TP[3:0] O PE6RN[3:0] I PE6RP[3:0] I PE6TN[3:0] O PE6TP[3:0] O PE7RN[3:0] I PE7RP[3:0] I PE7TN[3:0] O PE7TP[3:0] O Table 8 Pin Characteristics (Part 1 of 2)

12 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet PCI Express Inter- face (cont.) PEREFCLKN[2:1] I LVPECL/ CML Diff. Clock Input Refer to Table 9 PEREFCLKP[2:1] I REFCLKM I LVTTL Input pull-down SMBus MSMBADDR[4:1] I LVTTL Input pull-up MSMBCLK I/O STI 2 pull-up on board MSMBDAT I/O STI pull-up on board SSMBADDR[5,3:1] I Input pull-up SSMBCLK I/O STI pull-up on board SSMBDAT I/O STI pull-up on board General Purpose I/O GPIO[15:0] I/O LVTTL High Drive pull-up System Pins CCLKDS I LVTTL Input pull-up CCLKUS I pull-up MSMBSMODE I pull-down P01MERGEN I pull-down P23MERGEN I pull-down P45MERGEN I pull-down P67MERGEN I pull-down PERSTN I RSTHALT I pull-down SWMODE[3:0] I pull-down EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up JTAG_TDI I STI pull-up JTAG_TDO O JTAG_TMS I STI pull-up JTAG_TRST_N I STI pull-up External pull-down 1. Internal resistor values under typical operating conditions are 54K Ω for pull-up and 251K Ω for pull-down. 2. Schmitt Trigger Input (STI). Function Pin Name Type Buffer I/O Type Internal Resistor1 Notes Table 8 Pin Characteristics (Part 2 of 2)

13 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Logic Diagram — PES32T8 Figure 5 PES32T8 Logic Diagram Reference Clocks PEREFCLKP PEREFCLKN JTAG_TCK GPIO[15:0]

16 General Purpose

MSMBADDR[4:1] MSMBCLK MSMBDAT SSMBADDR[5,3:1] SSMBCLK SSMBDAT Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Functions JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG VSS SWMODE[3:0] CCLKDS PERSTN REFCLKM MSMBSMODE VTTPE PE0RP[0] PE0RN[0] PE0RP[3] PE0RN[3] PCI Express Switch SerDes Input PE0TP[0] PE0TN[0] PE0TP[3] PE0TN[3] PCI Express Switch SerDes Output ... Port 0 Port 0 ... PE1RP[0] PE1RN[0] PE1RP[3] PE1RN[3] PCI Express Switch SerDes Input PE1TP[0] PE1TN[0] PE1TP[3] PE1TN[3] PCI Express Switch SerDes Output ... Port 1 Port 1 ... PE2RP[0] PE2RN[0] PE2RP[3] PE2RN[3] PCI Express Switch SerDes Input PE2TP[0] PE2TN[0] PE2TP[3] PE2TN[3] PCI Express Switch SerDes Output ... Port 2 Port 2 ... PE3RP[0] PE3RN[0] PE3RP[3] PE3RN[3] PCI Express Switch SerDes Input PE3TP[0] PE3TN[0] PE3TP[3] PE3TN[3] PCI Express Switch SerDes Output ... Port 3 Port 3 ... PE4RP[0] PE4RN[0] PE4RP[3] PE4RN[3] PCI Express Switch SerDes Input PE4TP[0] PE4TN[0] PE4TP[3] PE4TN[3] PCI Express Switch SerDes Output ... Port 4 Port 4 ... PE7RP[0] PE7RN[0] PE7RP[3] PE7RN[3] PCI Express Switch SerDes Input PE5TP[0] PE5TN[0] PE5TP[3] PE5TN[3] PCI Express Switch SerDes Output ... Port 7 Port 5 ... PE6TP[0] PE6TN[0] PE6TP[3] PE6TN[3] PCI Express Switch SerDes Output Port 6 ... PE7TP[0] PE7TN[0] PE7TP[3] PE7TN[3] PCI Express Switch SerDes Output Port 7 ... PE6RP[0] PE6RN[0] PE6RP[3] PE6RN[3] PCI Express Switch SerDes Input ... Port 6 PE5RP[0] PE5RN[0] PE5RP[3] PE5RN[3] PCI Express Switch SerDes Input ... Port 5 PES32T8 P23MERGEN P67MERGEN P01MERGEN P45MERGEN

14 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet System Clock Parameters Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 13 and 14. AC Timing Characteristics Parameter Description Min Typical Max Unit PEREFCLK RefclkFREQ Input reference clock frequency range 100 125 1 1. The input clock frequency will be either 100 or 125 MHz depending on signal REFCLKM. MHz RefclkDC Duty cycle of input clock 40 50 60 % TR, TF Rise/Fall time of input clocks 0.2*RCUI RCUI 3 3. RCUI (Reference Clock Unit Interval) refers to the reference clock period. VSW Differential input voltage swing4 4. AC coupling required. 0.6 1.6 V Tjitter Input clock jitter (cycle-to-cycle) 125 ps RT Termination Resistor 110 Ohms Table 9 Input Clock Requirements Parameter Description Min 1 Typical1 Max1 Units PCIe Transmit UI Unit Interval 399.88 400 400.12 ps TTX-EYE Minimum Tx Eye Width 0.7 .9 UI TTX-EYE-MEDIAN-to- MAX-JITTER Maximum time between the jitter median and maximum deviation from the median 0.15 UI TTX-RISE, TTX-FALL D+ / D- Tx output rise/fall time 50 90 ps TTX- IDLE-MIN Minimum time in idle 50 UI TTX-IDLE-SET-TO- IDLE Maximum time to transition to a valid Idle after sending an Idle ordered set 20 UI TTX-IDLE-TO-DIFF- DATA Maximum time to transition from valid idle to diff data 20 UI TTX-SKEW Transmitter data skew between any 2 lanes 500 1300 ps PCIe Receive UI Unit Interval 399.88 400 400.12 ps T RX-EYE (with jitter) Minimum Receiver Eye Width (jitter tolerance) 0.4 UI TRX-EYE-MEDIUM TO MAX JITTER Max time between jitter median & max deviation 0.3 UI TRX-IDLE-DET-DIFF- ENTER TIME Unexpected Idle Enter Detect Threshold Integration Time 10 ms TRX-SKEW Lane to lane input skew 20 ns Table 10 PCIe AC Timing Characteristics

15 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Figure 6 GPIO AC Timing Waveform 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1 Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference GPIO GPIO[15:0]1 1. GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous. Tpw_13b2 2. The values for this symbol were determined by calculation, not by testing. None 50 — ns See Figure 6. Table 11 GPIO AC Timing Characteristics Signal Symbol Reference Edge Min Max Unit Timing Diagram Reference JTAG JTAG_TCK Tper_16a none 50.0 — ns See Figure 7. Thigh_16a, Tlow_16a 10.0 25.0 ns JTAG_TMS1, JTAG_TDI 1. The JTAG specification, IEEE 1149.1, reco mmends that JTAG_TMS should be held at 1 while the signal applied at JTAG_TRST_N changes from 0 to 1. Otherwise, a race may occur if JTAG_TRST_N is deasserted (going from low to high) on a rising edge of JTAG_TCK when JTAG_TMS is low, because the TAP controller might go to either the Run-Test/Idle state or stay in the Test-Logic-Reset state. Tsu_16b JTAG_TCK rising 2.4 — ns Thld_16b 1.0 — ns JTAG_TDO Tdo_16c JTAG_TCK falling — 20 ns Tdz_16c2 2. The values for this symbol were determined by calculation, not by testing. —2 0n s JTAG_TRST_N Tpw_16d 2 none 25.0 — ns Table 12 JTAG AC Timing Characteristics Tpw_13b GPIO (asynchronous input)

16 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Figure 7 JTAG AC Timing Waveform Recommended Operating Supply Voltages Power-Up Sequence This section describes the sequence in which various voltages must be applied to the part duri ng power-up to ensure proper func tionality. For the PES32T8, the power-up sequence must be as follows: 1. V DDI/O — 3.3V 2. V DDCore, VDDPE, VDDAPE — 1.0V 3. V TTPE — 1.5V When powering up, each voltage level must ramp and stabilize prior to applying the next voltage in the sequence to ensure internal latch-up issues are avoided. There are no maximum time limitations in ramping to valid power le vels. The power-down sequence must be in the rev erse order of the power-up sequence. Symbol Parameter Minimum Typical Maximum Unit VDDCORE Internal logic supply 0.9 1.0 1.1 V VDDI/O I/O supply e xcept for SerDes LVPECL/CML 3.0 3.3 3.6 V VDDPE PCI Express Digital Power 0.9 1.0 1.1 V VDDAPE PCI Express Analog Power 0.9 1.0 1.1 V VTTPE PCI Express Serial Data Transmit Termination Voltage 1.425 1.5 1.575 V VSS Common ground 0 0 0 V Table 13 PES32T8 Operating Voltages Tpw_16d Tdz_16cTdo_16c Thld_16b Tsu_16b Thld_16b Tsu_16b Tlow_16aTlow_16a Tper_16a Thigh_16a JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TDO JTAG_TRST_N

17 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Recommended Operating Temperature Power Consumption Typical power is measured under the following conditions: 25°C Am bient, 35% total link usage on all ports, typical voltages def ined in Table 13 (and also listed below). Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in Table 13 (and also listed below). Thermal Considerations This section describes thermal considerations for the PES32T8 (31mm2 BXG500 package). The data in Table 16 below contains information that is relevant to the thermal performance of the PES32T8 switch. Note: Parameter θJA(eff) is not the absolute thermal resistance for the package as defined by JEDEC (JESD-51). Because resistance can vary with the number of board layers, size of the board, and airflow, θJA(eff) is the effective thermal resistance. The values for effective θJA given above are based on a 10-layer, standard height, full length (4.3”x12.2”) PCIe add-in card. Grade Temperature Commercial 0 °C to +70°C Ambient Table 14 PES32T8 Operating Temperatures Number of active Lanes per Port Core Supply PCIe Digital Supply PCIe Analog Supply PCIe Termin- ation Supply I/O Supply Total Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.0V Max 1.1V Typ 1.5V Max 1.575V Typ 3.3V Max 3.6V Typ Power Max Power 8/8/8/4/4 or 8/8/8/8 mA 888 1014 1499 1660 611 627 763 832 1 1 4.1W 5.0W 8/8/4/4/4 mA 800 973 1284 1471 556 590 613 697 1 1 3.56W 4.4W Table 15 PES32T8 Power Consumption Symbol Parameter Value Units Conditions TJ(max) Junction Temperature 125 oCM a x i m u m TA(max) Ambient Temperature 70 oC Maximum for commercial-rated products θJA(effective) Effective Thermal Resistance, Junction-to-Ambient 9.3 oC/W Zero air flow 7.6 oC/W 1 m/S air flow 6.8 oC/W 2 m/S air flow θJB Thermal Resistance, Junction-to-Board 6 oC/W θJC Thermal Resistance, Junction-to-Case 0.7 oC/W P Power Dissipation of the Device 5.0 Watts Maximum Table 16 Thermal Specifications for PES32T8, 31x31 mm BXG500 Package

18 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Heat Sink Table 17 lists heat sink requirements for the PES32T8 under three common usage scenarios. As shown in this table, a heat sink is not required in most cases. Thermal Usage Examples The junction-to-ambient thermal resistance is a measure of a device’s ability to dissipate heat from the die to its surrounding s in the absence of a heat sink. The general formula to determine θJA is: θJA = (TJ - TA)/P Thermal reliability of a device is generally assured when the actual value of TJ in the specific system environment being considered is less than the maximum TJ specified for the device. Using an ambient temperature of 70oC and assuming a system with 1m/S airflow, the actual value of TJ is: TJ(actual) = TA + P * θJA(eff) = 70oC + 5.0W * 7.6W/oC = 108oC The actual TJ of 108oC is well below the maximum T J of 125oC specified for the device (shown in Table 16). Therefore, no heat sink is needed in this scenario. The formula is also useful from a system design perspective. It can be used to determine if a heat sink should b e added to the device based on some desired value of TJ. For example, if for reliability purposes the desired TJ is 100oC, then the maximum allowable TA is: TA(allowed) = TJ(desired) - (P * θJA(effective)) TA(allowed) = 100oC - (5.0W * 7.6W/oC) = 100oC - 38oC = 62oC An appropriate level of increased air flow and/or a heat sink c an be added to achieve this lower ambient temperature. Please co ntact ssdhelp@idt.com for further assistance. Air Flow Board Size Board Layers Heat Sink Requirement Zero 4.3”x6.6” (PCIe standard height, half length form factor) 10 or more No heat sink required Zero 3.9”x6.2” (ExpressModule form factor) 14 or more No heat sink required 1 m/S or more Any Any No heat sink required Table 17 Heat Sink Requirements Based on Air Flow and Board Characteristics

19 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Values based on systems running at recommended supply voltages, as shown in Table 13. Note: See Table 8, Pin Characteristics, for a complete I/O listing. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Serial Link PCIe Transmit VTX-DIFFp-p Differential peak-to-peak output voltage 800 1200 mV VTX-DE-RATIO De-emphasized differential output voltage -3 -4 dB VTX-DC-CM DC Common mode voltage -0.1 1 3.7 V VTX-CM-ACP RMS AC peak common mode output volt- age 20 mV VTX-CM-DC- active-idle-delta Abs delta of DC common mode voltage between L0 and idle 100 mV VTX-CM-DC-line- delta Abs delta of DC common mode voltage between D+ and D- 25 mV VTX-Idle-DiffP Electrical idle diff peak output 20 mV VTX-RCV-Detect Voltage change during receiver detection 600 mV RLTX-DIFF Transmitter Differential Return loss 12 dB RLTX-CM Transmitter Common Mode Return loss 6 dB ZTX-DEFF-DC DC Differential TX impedance 80 100 120 Ω ZOSE Single ended TX Impedance 40 50 60 Ω Transmitter Eye Diagram TX Eye Height (De-emphasized bits) 505 650 mV Transmitter Eye Diagram TX Eye Height (Transition bits) 800 950 mV PCIe Receive VRX-DIFFp-p Differential input voltage (peak-to-peak) 175 1200 mV VRX-CM-AC Receiver common-mode voltage for AC coupling 150 mV RLRX-DIFF Receiver Differential Return Loss 15 dB RLRX-CM Receiver Common Mode Return Loss 6 dB ZRX-DIFF-DC Differential input impedance (DC) 80 100 120 Ω ZRX-COMM-DC Single-ended input impedance 40 50 60 Ω ZRX-COMM-HIGH- Z-DC Powered down input common mode impedance (DC) 200k 350k Ω VRX-IDLE-DET- DIFFp-p Electrical idle detect threshold 65 175 mV PCIe REFCLK CIN Input Capacitance 1.5 — pF Table 18 DC Electrical Characteristics (Part 1 of 2)

20 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Other I/Os LOW Drive Output IOL —2 . 5— m A V OL = 0.4v IOH —- 5 . 5— m A V OH = 1.5V High Drive Output IOL —1 2 . 0— m A V OL = 0.4v IOH —- 2 0 . 0— m A V OH = 1.5V Schmitt Trig- ger Input (STI) VIL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Input V IL -0.3 — 0.8 V — VIH 2.0 — V DDIO + 0.5 Capacitance C IN —— 8 . 5 p F — Leakage Inputs — — + 10 μAV DDI/O (max) I/OLEAK W/O Pull-ups/downs —— + 10 μAV DDI/O (max) I/OLEAK WITH Pull-ups/downs —— + 80 μAV DDI/O (max) 1. Minimum, Typical, and Maximum values meet the requirements under PCI Specification 1.1. I/O Type Parameter Description Min 1 Typ1 Max1 Unit Conditions Table 18 DC Electrical Characteristics (Part 2 of 2)

21 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet The following table lists the pin numbers and signal names for the PES32T8 device. Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt A1 V SS B5 V SS C9 V SS D13 V SS A2 V DDCORE B6 V SS C10 V DDPE D14 PE6RN03 A3 V SS B7 V DDAPE C11 V TTPE D15 V SS A4 V DDCORE B8 PE6TP00 C12 V DDPE D16 PE7RN00 A5 V SS B9 V SS C13 V SS D17 V SS A6 V DDCORE B10 PE6TP01 C14 V DDPE D18 PE7RN01 A7 V SS B11 V DDAPE C15 V TTPE D19 V SS A8 PE6TN00 B12 PE6TP02 C16 V DDPE D20 PE7RN02 A9 V DDAPE B13 V SS C17 V SS D21 V SS A10 PE6TN01 B14 PE6TP03 C18 V DDPE D22 PE7RN03 A11 V SS B15 V DDAPE C19 V TTPE D23 V SS A12 PE6TN02 B16 PE7TP00 C20 V DDPE D24 MSMBSMODE A13 V SS B17 V SS C21 V SS D25 GPIO_15 A14 PE6TN03 B18 PE7TP01 C22 V DDPE D26 GPIO_11 1 A15 V SS B19 V DDAPE C23 V SS D27 V SS A16 PE7TN00 B20 PE7TP02 C24 REFCLKM D28 V DDCORE A17 V SS B21 V SS C25 V SS D29 V SS A18 PE7TN01 B22 PE7TP03 C26 GPIO_12 1 D30 V DDCORE A19 V SS B23 V SS C27 GPIO_09 1 E1 V SS A20 PE7TN02 B24 V SS C28 V DDCORE E2 V DDCORE A21 V DDAPE B25 V DDCORE C29 V SS E3 P01MERGEN A22 PE7TN03 B26 GPIO_14 C30 V SS E4 P23MERGEN A23 V SS B27 V SS D1 V DDCORE E5 P45MERGEN A24 V DDAPE B28 V SS D2 V DDIO E6 P67MERGEN A25 V DDIO B29 V DDCORE D3 V SS E7 V SS A26 V SS B30 V SS D4 V DDIO E8 PE6RP00 A27 V DDIO C1 V SS D5 V SS E9 V SS A28 V DDIO C2 V DDCORE D6 V DDIO E10 PE6RP01 A29 V DDCORE C3 V SS D7 V SS E11 V DDCORE A30 V SS C4 V DDCORE D8 PE6RN00 E12 PE6RP02 B1 V SS C5 V SS D9 V SS E13 V SS B2 V DDCORE C6 V DDCORE D10 PE6RN01 E14 PE6RP03 B3 V SS C7 V TTPE D11 V SS E15 V DDCORE B4 V DDCORE C8 V DDPE D12 PE6RN02 E16 PE7RP00 Table 19 PES32T8 500-pin Signal Pin-Out (Part 1 of 4)

22 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet E17 V SS H4 V SS M1 V SS R28 V DDPE E18 PE7RP01 H5 V DDCORE M2 V DDAPE R29 PE4TP03 E19 V DDCORE H26 V SS M3 V TTPE R30 PE4TN03 E20 PE7RP02 H27 V SS M4 V SS T1 V SS E21 V SS H28 V TTPE M5 V DDCORE T2 V DDAPE E22 PE7RP03 H29 V DDAPE M26 V DDCORE T3 V TTPE E23 V SS H30 V SS M27 V SS T4 V SS E24 V DDCORE J1 PE3TN03 M28 V TTPE T5 V DDCORE E25 GPIO_13 J2 PE3TP03 M29 V DDAPE T26 V DDCORE E26 GPIO_10 1 J3 V DDPE M30 V SS T27 V SS E27 GPIO_08 1 J4 PE3RN03 N1 PE3TN01 T28 V TTPE E28 V SS J5 PE3RP03 N2 PE3TP01 T29 V DDAPE E29 V DDIO J26 PE4RP00 N3 V DDPE T30 V SS E30 V SS J27 PE4RN00 N4 PE3RN01 U1 PE2TN03 F1 PEREFCLKN1 J28 V DDPE N5 PE3RP01 U2 PE2TP03 F2 V SS J29 PE4TP00 N26 PE4RP02 U3 V DDPE F3 V DDCORE J30 PE4TN00 N27 PE4RN02 U4 PE2RN03 F4 V SS K1 V DDAPE N28 V DDPE U5 PE2RP03 F5 V DDIO K2 V SS N29 PE4TP02 U26 PE5RP00 F26 V SS K3 V SS N30 PE4TN02 U27 PE5RN00 F27 V DDCORE K4 V SS P1 V SS U28 V DDPE F28 V DDCORE K5 V SS P2 V SS U29 PE5TP00 F29 V SS K26 V SS P3 V SS U30 PE5TN00 F30 PEREFCLKP2 K27 V SS P4 V SS V1 V SS G1 PEREFCLKP1 K28 V SS P5 V SS V2 V SS G2 V SS K29 V SS P26 V SS V3 V SS G3 V SS K30 V DDAPE P27 V SS V4 V SS G4 V SS L1 PE3TN02 P28 V SS V5 V SS G5 V SS L2 PE3TP02 P29 V SS V26 V SS G26 V SS L3 V DDPE P30 V SS V27 V SS G27 V SS L4 PE3RN02 R1 PE3TN00 V28 V SS G28 V SS L5 PE3RP02 R2 PE3TP00 V29 V SS G29 V SS L26 PE4RP01 R3 V DDPE V30 V SS G30 PEREFCLKN2 L27 PE4R N01 R4 PE3RN00 W1 PE2TN02 H1 V SS L28 V DDPE R5 PE3RP00 W2 PE2TP02 H2 V DDAPE L29 PE4TP01 R26 PE4RP03 W3 V DDPE H3 V TTPE L30 PE4TN01 R27 PE4RN03 W4 PE2RN02 Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES32T8 500-pin Signal Pin-Out (Part 2 of 4)

23 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet W5 PE2RP02 AC2 PE2TP00 AF9 PE1RP03 AG16 V SS W26 PE5RP01 AC3 V DDPE AF10 V SS AG17 PE0RN03 W27 PE5RN01 AC4 PE2RN 00 AF11 PE1RP02 AG18 V SS W28 V DDPE AC5 PE2RP00 AF12 V DDCORE AG19 PE0RN02 W29 PE5TP01 AC26 PE5RP0 3 AF13 PE1RP01 AG20 V SS W30 PE5TN01 AC27 PE5RN03 AF14 V SS AG21 PE0RN01 Y1 V SS AC28 V DDPE AF15 PE1RP00 AG22 V SS Y2 V DDAPE AC29 PE5TP03 AF16 V DDCORE AG23 PE0RN00 Y3 V TTPE AC30 PE5TN03 AF17 PE0RP03 AG24 V SS Y4 V SS AD1 V SS AF18 V SS AG25 SWMODE_3 Y5 V DDCORE AD2 V DDAPE AF19 PE0RP02 AG26 V SS Y26 V DDCORE AD3 V DDIO AF20 V DDCORE AG27 GPIO_04 1 Y27 V SS AD4 V DDIO AF21 PE0RP01 AG28 V DDCORE Y28 V TTPE AD5 JTAG_TCK AF22 V SS AG29 V SS Y29 V DDAPE AD26 GPIO_07 1 AF23 PE0RP00 AG30 V DDCORE Y30 V SS AD27 V SS AF24 CCLKDS AH1 V DDCORE AA1 PE2TN01 AD28 V SS AF25 SWMODE_2 AH2 V SS AA2 PE2TP01 AD29 V DDAPE AF26 GPIO_00 1 AH3 JTAG_TMS AA3 V DDPE AD30 V SS AF27 GPIO_05 1 AH4 MSMBADDR_3 AA4 PE2RN01 AE1 V DDCORE AF28 V SS AH5 MSMBDAT AA5 PE2RP01 AE2 V SS AF29 V DDIO AH6 SSMBADDR_3 AA26 PE5RP02 AE3 V SS AF30 V SS AH7 CCLKUS AA27 PE5RN02 AE4 JTAG_TDI AG1 V SS AH8 V DDPE AA28 V DDPE AE5 JTAG_TRST_N AG2 V DDCORE AH9 V DDPE AA29 PE5TP02 AE26 GPIO_03 1 AG3 JTAG_TDO AH10 V SS AA30 PE5TN02 AE27 GPIO_06 AG4 MSMBADDR_2 AH11 V DDPE AB1 V DDAPE AE28 V DDIO AG5 V SS AH12 V TTPE AB2 V SS AE29 V SS AG6 SSMBADDR_2 AH13 V DDPE AB3 V SS AE30 V DDCORE AG7 SSMBDAT AH14 V SS AB4 V SS AF1 V SS AG8 V SS AH15 V DDPE AB5 V SS AF2 V DDCORE AG9 PE1RN03 AH16 V TTPE AB26 V SS AF3 V SS AG10 V SS AH17 V DDPE AB27 V SS AF4 MSMBADDR_1 AG11 PE1RN02 AH18 V SS AB28 V SS AF5 MSMBADDR_4 AG12 V SS AH19 V DDPE AB29 V SS AF6 SSMBADDR_1 AG13 PE1RN01 AH20 V TTPE AB30 V DDAPE AF7 SSMBCLK AG14 V SS AH21 V DDPE AC1 PE2TN00 AF8 V SS AG15 PE1RN00 AH22 V SS Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES32T8 500-pin Signal Pin-Out (Part 3 of 4)

24 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Alternate Signal Functions AH23 V DDPE AJ10 V SS AJ27 GPIO_01 1 AK14 V SS AH24 V TTPE AJ11 PE1TP02 AJ28 V SS AK15 PE1TN00 AH25 SWMODE_1 AJ12 V DDAPE AJ29 V DDCORE AK16 V SS AH26 RSTHALT AJ13 PE1TP01 AJ30 V SS AK17 PE0TN03 AH27 GPIO_02 1 AJ14 V SS AK1 V SS AK18 V SS AH28 V DDCORE AJ15 PE1TP00 AK2 V DDCORE AK19 PE0TN02 AH29 V SS AJ16 V DDAPE AK3 V SS AK20 V SS AH30 V DDCORE AJ17 PE0TP03 AK4 V DDCORE AK21 PE0TN01 AJ1 V SS AJ18 V SS AK5 V SS AK22 V DDAPE AJ2 V DDIO AJ19 PE0TP02 AK6 V DDCORE AK23 PE0TN00 AJ3 V SS AJ20 V DDAPE AK7 V SS AK24 V SS AJ4 MSMBCLK AJ21 PE0TP01 AK8 V DDAPE AK25 V DDIO AJ5 V DDIO AJ22 V SS AK9 PE1TN03 AK26 V SS AJ6 SSMBADDR_5 AJ23 PE0TP00 AK10 V DDAPE AK27 V DDIO AJ7 V SS AJ24 V DDAPE AK11 PE1TN02 AK28 V SS AJ8 V DDCORE AJ25 SWMODE_0 AK12 V SS AK29 V DDCORE AJ9 PE1TP03 AJ26 PERSTN AK13 PE1TN01 AK30 V SS Pin GPIO Alternate Pin GPIO Alternate AF26 GPIO_00 P2RSTN AD26 GPIO_07 GPEN AJ27 GPIO_01 P4RSTN E27 GPIO_08 P1RSTN AH27 GPIO_02 IOEXPINTN0 C27 GPIO_09 P3RSTN AE26 GPIO_03 IOEXPINTN1 E26 GPIO_10 P5RSTN AG27 GPIO_04 IOEXPINTN2 D26 GPIO_11 P6RSTN AF27 GPIO_05 IOEXPINTN3 C26 GPIO_12 P7RSTN Table 20 PES32T8 Alternate Signal Functions Pin Function Alt Pin Function Alt Pin Function Alt Pin Function Alt Table 19 PES32T8 500-pin Signal Pin-Out (Part 4 of 4)

25 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Power Pins VDDCore V DDCore V DDIO V DDPE V DDPE V DDAPE V TTPE A2 Y26 A25 C8 AH17 A9 C7 A4 AE1 A27 C10 AH19 A21 C11 A6 AE30 A28 C12 AH21 A24 C15 A29 AF2 D2 C14 AH23 B7 C19 B2 AF12 D4 C16 B11 H3 B4 AF16 D6 C18 B15 H28 B 2 5A F 2 0E 2 9 C 2 0 B 1 9 M 3 B29 AG2 F5 C22 H2 M28 C2 AG28 AD3 J3 H29 T3 C4 AG30 AD4 J28 K1 T28 C6 AH1 AE28 L3 K30 Y3 C28 AH28 AF29 L28 M2 Y28 D1 AH30 AJ2 N3 M29 AH12 D28 AJ8 AJ5 N28 T2 AH16 D30 AJ29 AK25 R3 T29 AH20 E2 AK2 AK27 R28 Y2 AH24 E11 AK4 U3 Y29 E15 AK6 U28 AB1 E19 AK29 W3 AB30 E24 W28 AD2 F3 AA3 AD29 F27 AA28 AJ12 F28 AC3 AJ16 H5 AC28 AJ20 M5 AH8 AJ24 M26 AH9 AK8 T5 AH11 AK10 T26 AH13 AK22 Y5 AH15 Table 21 PES32T8 Power Pins

26 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Ground Pins Vss Vss V ss V ss V ss V ss A1 C17 F26 P4 AB27 AG26 A3 C21 F29 P5 AB28 AG29 A5 C23 G2 P26 AB29 AH2 A7 C25 G3 P27 AD1 AH10 A11 C29 G4 P28 AD27 AH14 A13 C30 G5 P29 AD28 AH18 A15 D3 G26 P30 AD30 AH22 A17 D5 G27 T1 AE2 AH29 A19 D7 G28 T4 AE3 AJ1 A23 D9 G29 T27 AE29 AJ3 A26 D11 H1 T30 AF1 AJ7 A30 D13 H4 V1 AF3 AJ10 B1 D15 H26 V2 AF8 AJ14 B3 D17 H27 V3 AF10 AJ18 B5 D19 H30 V4 AF14 AJ22 B6 D21 K2 V5 AF18 AJ28 B9 D23 K3 V26 AF22 AJ30 B13 D27 K4 V27 AF28 AK1 B17 D29 K5 V28 AF30 AK3 B21 E1 K26 V29 AG1 AK5 B23 E7 K27 V30 AG5 AK7 B24 E9 K28 Y1 AG8 AK12 B27 E13 K29 Y4 AG10 AK14 B28 E17 M1 Y27 AG12 AK16 B30 E21 M4 Y30 AG14 AK18 C1 E23 M27 AB2 AG16 AK20 C3 E28 M30 AB3 AG18 AK24 C5 E30 P1 AB4 AG20 AK26 C9 F2 P2 AB5 AG22 AK28 C13 F4 P3 AB26 AG24 AK30 Table 22 PES32T8 Ground Pins

27 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet Signals Listed Alphabetically Signal Name I/O Type Location Signal Category CCLKDS I AF24 System CCLKUS I AH7 GPIO_00 I/O AF26 General Purpose I/O GPIO_01 I/O AJ27 GPIO_02 I/O AH27 GPIO_03 I/O AE26 GPIO_04 I/O AG27 GPIO_05 I/O AF27 GPIO_06 I/O AE27 GPIO_07 I/O AD26 GPIO_08 I/O E27 GPIO_09 I/O C27 GPIO_10 I/O E26 GPIO_11 I/O D26 GPIO_12 I/O C26 GPIO_13 I/O E25 GPIO_14 I/O B26 GPIO_15 I/O D25 JTAG_TCK I AD5 Test JTAG_TDI I AE4 JTAG_TDO O AG3 JTAG_TMS I AH3 JTAG_TRST_N I AE5 MSMBADDR_1 I AF4 SMBus Interface MSMBADDR_2 I AG4 MSMBADDR_3 I AH4 MSMBADDR_4 I AF5 MSMBCLK I/O AJ4 MSMBDAT I/O AH5 MSMBSMODE I D24 System P01MERGEN I E3 P23MERGEN I E4 P45MERGEN I E5 P67MERGEN I E6 Table 23 89PES32T8 Alphabetical Signal List (Part 1 of 6)

28 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet PE0RN00 I AG23 PCI Express PE0RN01 I AG21 PE0RN02 I AG19 PE0RN03 I AG17 PE0RP00 I AF23 PE0RP01 I AF21 PE0RP02 I AF19 PE0RP03 I AF17 PE0TN00 O AK23 PE0TN01 O AK21 PE0TN02 O AK19 PE0TN03 O AK17 PE0TP00 O AJ23 PE0TP01 O AJ21 PE0TP02 O AJ19 PE0TP03 O AJ17 PE1RN00 I AG15 PE1RN01 I AG13 PE1RN02 I AG11 PE1RN03 I AG9 PE1RP00 I AF15 PE1RP01 I AF13 PE1RP02 I AF11 PE1RP03 I AF9 PE1TN00 O AK15 PE1TN01 O AK13 PE1TN02 O AK11 PE1TN03 O AK9 PE1TP00 O AJ15 PE1TP01 O AJ13 PE1TP02 O AJ11 PE1TP03 O AJ9 PE2RN00 I AC4 PE2RN01 I AA4 PE2RN02 I W4 PE2RN03 I U4 Signal Name I/O Type Location Signal Category Table 23 89PES32T8 Alphabetical Signal List (Part 2 of 6)

29 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet PE2RP00 I AC5 PCI Express (cont.) PE2RP01 I AA5 PE2RP02 I W5 PE2RP03 I U5 PE2TN00 O AC1 PE2TN01 O AA1 PE2TN02 O W1 PE2TN03 O U1 PE2TP00 O AC2 PE2TP01 O AA2 PE2TP02 O W2 PE2TP03 O U2 PE3RN00 I R4 PE3RN01 I N4 PE3RN02 I L4 PE3RN03 I J4 PE3RP00 I R5 PE3RP01 I N5 PE3RP02 I L5 PE3RP03 I J5 PE3TN00 O R1 PE3TN01 O N1 PE3TN02 O L1 PE3TN03 O J1 PE3TP00 O R2 PE3TP01 O N2 PE3TP02 O L2 PE3TP03 O J2 PE4RN00 I J27 PE4RN01 I L27 PE4RN02 I N27 PE4RN03 I R27 PE4RP00 I J26 PE4RP01 I L26 PE4RP02 I N26 PE4RP03 I R26 Signal Name I/O Type Location Signal Category Table 23 89PES32T8 Alphabetical Signal List (Part 3 of 6)

30 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet PE4TN00 O J30 PCI Express (cont.) PE4TN01 O L30 PE4TN02 O N30 PE4TN03 O R30 PE4TP00 O J29 PE4TP01 O L29 PE4TP02 O N29 PE4TP03 O R29 PE5RN00 I U27 PE5RN01 I W27 PE5RN02 I AA27 PE5RN03 I AC27 PE5RP00 I U26 PE5RP01 I W26 PE5RP02 I AA26 PE5RP03 I AC26 PE5TN00 O U30 PE5TN01 O W30 PE5TN02 O AA30 PE5TN03 O AC30 PE5TP00 O U29 PE5TP01 O W29 PE5TP02 O AA29 PE5TP03 O AC29 PE6RN00 I D8 PE6RN01 I D10 PE6RN02 I D12 PE6RN03 I D14 PE6RP00 E8 PE6RP01 II E10 PE6RP02 I E12 PE6RP03 I E14 PE6TN00 O A8 PE6TN01 O A10 PE6TN02 O A12 PE6TN03 O A14 Signal Name I/O Type Location Signal Category Table 23 89PES32T8 Alphabetical Signal List (Part 4 of 6)

31 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet PE6TP00 O B8 PCI Express (cont.) PE6TP01 O B10 PE6TP02 O B12 PE6TP03 O B14 PE7RN00 I D16 PE7RN01 I D18 PE7RN02 I D20 PE7RN03 I D22 PE7RP00 I E16 PE7RP01 I E18 PE7RP02 I E20 PE7RP03 I E22 PE7TN00 O A16 PE7TN01 O A18 PE7TN02 O A20 PE7TN03 O A22 PE7TP00 O B16 PE7TP01 O B18 PE7TP02 O B20 PE7TP03 O B22 PEREFCLKN1 I F1 PEREFCLKN2 I G30 PEREFCLKP1 I G1 PEREFCLKP2 I F30 PERSTN I AJ26 System REFCLKM I C24 PCI Express RSTHALT I AH26 System SSMBADDR_1 I AF6 SMBus Interface SSMBADDR_2 I AG6 SSMBADDR_3 I AH6 SSMBADDR_5 I AJ6 SSMBCLK I/0 AF7 SSMBDAT I/O AG7 Signal Name I/O Type Location Signal Category Table 23 89PES32T8 Alphabetical Signal List (Part 5 of 6)

32 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet SWMODE_0 I AJ25 System SWMODE_1 I AH25 SWMODE_2 I AF25 SWMODE_3 I AG25 V DDCORE, VDDAPE, VDDIO, VDDPE, VTTPE See Table 21 for a listing of power pins. VSS See Table 22 for a listing of ground pins. Signal Name I/O Type Location Signal Category Table 23 89PES32T8 Alphabetical Signal List (Part 6 of 6)

33 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet PES32T8 Pinout — Top View 12 3 4 567 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 Vss (Ground)VDDCore (Power) A B VDDI/O (Power) 17 18 19 20 21 22 23 24 25 26 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF VTTPE (Power)VDDPE (Power) VDDAPE (Power) Signals 27 28 29 30 AG AH AJ AK 1 2 3 4 5 6 7 8 9 1 0 1 11 2 1 31 4 1 5 1 6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X X XXXX X X X X X XX X X X X A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK

34 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet

35 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet

36 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet

Revision History

February 8, 2007: Initial publication. April 4, 2007: In Table 3, revised description for MSMBCLK signal. May 30, 2007: Changed device revision in Ordering Information from ZD to ZH. November 14, 2007: Added new parameter, Termination Resistor, to Table 9, Input Clock Requirements. March 25, 2008: Added θJB and θJC parameters to Table 16, Thermal Specifications.

37 of 37 March 25, 2008 IDT 89PES32T8 Data Sheet CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for Tech Support: email: ssdhelp@idt.com phone: 408-284-8208

Ordering Information

89HPES32T8ZHBX 500-ball BGA package, Commercial Temperature 89HPES32T8ZHBXG 500-ball Green BGA package, Commercial Temperature NN A AAA NNAN AA A Operating Voltage Device Family Product Package Temp Range H Blank Commercial Temperature (0°C to +70°C Ambient) Product Family

89 Serial Switching Product

32T8 32-lane, 8-port 1.0V +/- 0.1V Core Voltage Detail PCI Express SwitchPES Legend A = Alpha Character N = Numeric Character BXG500 500-ball BGA, Green BXG AA Device Revision ZH ZH revision

© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.