PES1600-12-080NA

PES1600-12-080NA BEL | Alldatasheet

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Technical content

The PES1600 -12-080NA is a 1600 Watt AC to DC, power -factor- corrected (PFC) power supply that converts standard AC power into a main output of +12 VDC for powering intermediate bus architectures (IBA) in high performance and reliability servers, routers, and network switches. The PES1600 -12-080NA utilizes full digital control architecture for greater efficiency, control, and functionality. This power supply meets international safety standards and displays the CE-Mark for the European Low Voltage Directive (LVD).

• Designed to meet Intel CRPS compatibility
• Best-in-class, meet 80 plus “Platinum” efficiency
• Auto-selected input voltage ranges: 90-140 VAC, 180-264 VAC
• AC input with active power factor correction
• 1600 W continuous output power capability
• Always-on 12 VSB / 3.5 A standby output
• Hot-plug capable
• Parallel operation with active current sharing
• Full digital controls for improved performance
• High power density design: 42 W/in3
• Small form factor: 80 x 40 x 195 in mm
• PMBus® communication interface for control, programming and monitoring
• Status LED with fault signaling
• Networking Switches
• Servers & Routers
• Telecommunications Disclamer: PMBus is a registered trademark of SMIF, Inc.

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resonance-soft-switching technology to reduce component stresses, providing increased system reliability and very high efficiency. and other high availability applications. The supply is fan cooled and ideally suited for integration with a matching airflow path. management controllers. It is protected with an active OR-ing device for maximum reliability. I2C bus. The I2C bus allows full monitoring of the supply, including input and output voltage, current, power, and inside temperatures. power demand and supply temperature and can be overridden through the I2C bus. Figure 1. PES1600-12-080NA Block Diagram cause permanent damage to the supply.

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions BCD.00941_AA General Condition: TA = 0… 55 °C, unless otherwise noted. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Vi nom AC Nominal Input Voltage Rated Voltage High Line (Vi nom HL) 200 230 240 VAC Rated Voltage Low Line (Vi nom LL) 100 115 127 VAC Vi nom DC DC Nominal Input Voltage Rated HVDC 240 VDC Vi DC DC Input Voltage range Normal operating (Vi min to Vi max ) 180 300 VDC Vi Input Voltage Ranges Normal operating (Vi min HL to Vi max HL), High Line 180 264 VAC Normal operating (Vi min LL to Vi max LL), Low Line 90 140 VAC Ii max Maximum Input Current VIN = 90 VAC, I1 =91.6 A, ISB =3.5 A 15 ARMS VIN = 180 VAC, I1 =133 A, ISB =3.5 A 10.5 ARMS Ii inrush Inrush Current Limitation Vi min to Vi max, TNTC = 25°C, 5 ms 50 Ap fi Input Frequency 47 50/60 63 Hz PF Power Factor Vi = 230 VAC, 50 Hz and 60 Hz, Vi = 115 VAC,60 Hz 10% Load 0.8 W/VA 20% Load 0.9 W/VA 50% Load 0.9 W/VA 100% Load 0.95 W/VA Vi on Turn-on Input Voltage1 Ramping up 85 90 VAC Vi off Turn-off Input Voltage1 Ramping down 80 85 VAC η Efficiency2 VIN = 230 VAC, 10% load 82 % VIN = 230 VAC, 20% load 90 92.5 % VIN = 230 VAC, 50% load 94 94.3 % VIN = 230 VAC, 100% load 91 92.7 % TV1 holdup Hold-up Time V1 VIN = 230 VAC, I1 =133 A, ISB =3.5 A 11 ms VIN = 115 VAC, I1 =91.6 A, ISB =3.5 A 11 ms TVSB holdup Hold-up Time VSB 12 VSB, full load 70 ms 1 The Front-End is provided with a typical hysteresis of 5 VAC during turn-on and turn-off within the ranges. PSU will restart once input voltage within the Vi on. 2 Efficiency measured without fan power per EPA server guidelines.

4.1 INPUT FUSE

Time-lag 20 A input fuse (5.4 x 22.5 mm) in series with the L -line inside the power supply protects against severe defects. The fuse is not accessible from the outside and is therefore not a serviceable part.

4.2 INRUSH CURRENT

The AC-DC power supply exhibits an X capacitance of only 4.7 µF , resulting in a low and short peak current, when the supply is connected to the mains. The internal bulk capacitor will be charged through a PTC which will limit the inrush current. NOTE: Do not repeat plug-in / out operations within a short time, or else the internal in -rush current limiting device (PTC) may not sufficiently cool down.

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4.3 INPUT UNDER-VOLTAGE

input voltage returns within the normal operating range, the supply will return to normal operation again.

4.4 POWER FACTOR CORRECTION

show a trapezoidal waveform.

4.5 EFFICIENCY

temperature regardless of the ambient temperature and load conditions. Figure 2. Efficiency vs. Load current (ratio metric loading) Figure 3. Power factor vs. Load current Figure 4. Inrush current, Vin = 230Vac, 90°

100 VAC /50 Hz in Amps

Table 1. Harmonic Limits for Class A Equipment

• Comment: for 95% sag condition, the load is 80%.

Table 2. AC Line Sag Transient Performance Table 3. AC Line Surge Transient Performance

4.6 INPUT LINE CURRENT HARMONIC

in Appliances and General Use Equipment Class A for harmonic line current content at full rated power.

4.7 AC LINE TRANSIENT SPECIFICATION

be defined to refer to conditions when the AC line voltage rises above nominal voltage. The power supply shall meet the requirements under the following AC line sag and surge conditions.

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tech.support@psbel.com General condition: TA = 0…55 °C, Vi = 230VAC unless otherwise noted. PARAMETER DESCRIPTION / CONDITION MIN NOM MAX UNIT Main Output V1 V1 nom Nominal Output Voltage 0.5 ∙ I1 nom, TA = 25°C 12.0 VDC V1 set Output Setpoint Accuracy -1 +1 %V1 nom dV1 load Load Regulation 0 to 100% I1 nom 480 mV dV1 line Line Regulation Vi min LL to Vi max HL 120 mV dV1 tot Total Regulation Vi min to Vi max, 0 to 100% I1 nom -5 +5 %V1 nom P1 nom Nominal Output Power Vi min HL to Vi max HL 1600 W Vi min LL to Vi max LL 1100 W I1 peak Peak Output Loading Vi min HL to Vi max HL (max 20s) 150 ADC Vi min HL to Vi max HL (max 100us) 205 ADC Vi min LL to Vi max LL (max 20s) 105 ADC I1 nom I1 nom red Output Current Vi min HL to Vi max HL 0.0 133 ADC Vi min LL to Vi max LL 0.0 91.6 ADC V1 pp Output Ripple Voltage3 Vi min to Vi max, 0 to 100% I1 nom, 20MHz Bandwidth 120 mVpp dI1 share Current Sharing Deviation from I1 tot / N, I1 > 20% -5 +5 % I1 nom VISHARE Current Share Bus Voltage I1 nom 8 VDC dV1 dyn Dynamic Load Regulation Test frequency between 50Hz and 5KHz at duty cycles from 10% to 90%, ΔI1 = 60% I1 nom, I1 = 3A … 100% I1nom, 2000μF capacitive loading dI1/dt = 0.25A/μs, recovery within 1% of V1nom 11.40 12.60 VDC trec Recovery Time 2 ms tV1 rise Output Voltage Rise Time V1 = 10…90% V1 nom 1 70 ms tV1 ovr sh Output Turn-on Overshoot Vi nom HL, 0 to 100% I1 nom 0.6 V dV1 sense Remote Sense Compensation for cable drop, 0 to 100% I1 nom 0.25 V CV1 load Capacitive Loading 22 mF Standby Output VSB VSB nom Nominal Output Voltage 0.5 ∙ISB nom, TA = 25°C 12.0 VDC VSB set Output Setpoint Accuracy -1 +1 %VSBnom dVsb load Load Regulation 0 to 100% ISB nom 480 mV dVsb line Line Regulation Vi min LL to Vi max HL 120 mV dVSB tot Total Regulation Vi min to Vi max, 0 to 100% ISB nom -5 +5 %VSBnom PSB nom Nominal Output Power Vi min to Vi max 42 W ISB peak Peak Output Loading Vi min LL to Vi max HL 4 ADC ISB nom Output Current Vi min to Vi max 0.0 3.5 ADC VSB pp Output Ripple Voltage 3 Vi min to Vi max, 0 to 100% ISB nom, 20 MHz bandwidth 120 mVpp dVSB dyn Dynamic Load Regulation ΔISB = 50% ISB nom, ISB = 0 … 100% ISB nom, dISB/dt = 0.25A/μs, recovery within 1% of VSB nom 11.40 12.60 VDC trec Recovery Time 2 ms tVSB rise Output Voltage Rise Time VSB = 10…90% VSB nom, 5 10 ms tVSB ovr sh Output Turn-on Overshoot Vi nom HL, 0 to 100% ISB nom 0.6 V CVSB load Capacitive Loading 1000 µF 3 Ripple noise and dynamic load measured with a 10 µF low ESR capacitor in parallel with a 0.1 µF ceramic capacitor at the point of measurement.

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Figure 11. Short circuit on V1 (0.4ms/Div) Figure 12. Load transient V1, 133 to 53.2A (0.8ms/div)

5.1 OUTPUT GROUND / CHASSIS CONNECTION

planes should be connected together at the power supplies ground pins. Figure 13. Common Low Impedance Ground Plane Figure 14. Separated Power and Signal Ground

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5.2 CLOSED LOOP STABILITY

The power supply shall be unconditionally stable under all line/load/transient load conditions including capacitive load ranges. A minimum of: 45 degrees phase margin and -10dB-gain margin is required. The power supply manufacturer shall provide proof of the unit’s closed-loop stability with local sensing through the submission of Bode plots. Closed -loop stability must be ensured at 10%, 20%, 50% and 100% loads as applicable, 0% is just for reference.

5.3 RESIDUAL VOLTAGE IMMUNITY IN STANDBY MODE

The power supply should be immune to any residual voltage placed on its outputs (Typically a leakage voltage through the system from standby output) up to 500mV. There shall be no additional heat generated, nor stressing of any internal components with this vo ltage applied to any individual or all outputs simultaneously. It also should not trip the protection circuits during turn on. The residual voltage at the power supply outputs for no load condition shall not exceed 100mV when AC voltage is applied and the PSON_L signal is de-asserted.

5.4 COMMON MODE NOISE

The common mode noise on any output shall not exceed 350mV pk-pk over the frequency band of 10Hz to 20MHz. The measurement shall be made across a 100 Ω resistor between each of DC outputs, including ground at the DC power connector and chassis ground (power subsystem enclosure), the test set -up shall use a FET probe such as Tektronix model P6046 or equivalent.

5.5 SOFT STARTING

The Power Supply shall contain control circuit which provides monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions.

5.6 ZERO LOAD STABILITY REQUIREMENTS

When the power subsystem operates in a no load condition, it does not need to meet the output regulation specification, but it must operate without any tripping of over-voltage or other fault circuitry. When the power subsystem is subsequently loaded, it must begin to regulate and source current without fault.

5.7 HOT SWAP REQUIREMENTS

Hot swapping a power supply is the process of inserting and extracting a power supply from an operating power system. During this process, the output voltages shall remain within the limits with the capacitive load specified. The hot swap test must be conducted when the system is operating under static, dynamic, and zero loading conditions. The power supply shall use a latching mechanism to prevent insertion and extraction of the power supply when the AC power cord is inserted into the power supply.

5.8 FORCED LOAD SHARING

The PES front-ends have an active current share scheme implemented for V1. All the ISHARE current share pins need to be interconnected in order to activate the sharing function. If a supply has an internal fault or is not turned on, it will d isconnect its ISHARE pin from the share bus. This will prevent dragging the output down (or up) in such cases. The current share function uses an analog bus to transmit and receive current share information. The controller implements a Master/Slave current share function. The power supply providing the largest current among the group is automatically the Master. The other supplies will operate as Slaves and increase their output current to a value close to the Master by slightl y increasing their output voltage. The voltage increase is limited to +250 mV. The output will share within 10% at full load. The 12VSB output is not required to actively share current between power supplies (passive sharing).

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5.9 RIPPLE / NOISE

The test set-up shall be following Figure 15.

1. LOAD THE OUTPUT WITH ITS MINIMUM
2. CONNECT THE PROBES AS SHOWN.
3. REPEAT THE MEASUREMENTS WITH THE

DIFFERENTIAL PROBE P6055 OR EQUIVALENT. Figure 15. Differential Noise Test Setup Note: Load must be isolated from the safety ground to Figure 15. Note: When performing this test, the probe clips and capacitors should be located close to the load.

6.1 PROTECTION CIRCUITS

6.2 OVER TEMPERATURE PROTECTION (OTP)

be at least 5°C higher than over temperature warning threshold level.

6.3 OVER VOLTAGE PROTECTION

the PSON_L input. 12VSB will be auto-recovered after removing OVP limit.

6.4 UNDER VOLTAGE DETECTION

be unlocked by disconnecting the supply from the AC mains or by toggling the PSON_L input.

6.5 OVER CURRENT LIMIT & OVER POWER PROTECTION (OCP & OPP)

The power supply shall have current limit to prevent the outputs from exceeding the values shown in Table 4 and Table 5. auto-recovered after removing OCP limit. Table 4. High Line Input Table 5. Low Line Input threshold is exceeded. SMB_ALERT_L must always latch for about 100msec before being released.

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Table 6. PMAX Testing Conditions

6.6 PEAK LOAD WITH ADDED SYSTEM BUFFER CAPACITANCE

The power supply shall be able to support higher peak power levels with added system buffer capacitance for up to 100µsec. Table 6 are PMAX testing conditions. I2C / PMBus® COMMUNICATION and document PES1600-12-080NA PMBus® Communication Manual.

8.1 ELECTRICAL CHARACTERISTICS

8.2 SENSE INPUTS

path. The maximum allowed voltage drop is 200 mV on the positive rail and 50 mV on the GND rail. the power supply will shut down.

8.3 PRESENT_L OUTPUT

into PRESENT_L should not exceed 5mA to guarantee a low level voltage if power supply is seated. Figure 16. PRESENT_L Connection

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8.4 PSON_L INPUT

either controlled by an open collector device or by a voltage source. Figure 17. PSON_L connection

8.5 PWOK_H OUTPUT

a LOW state. The start of the PWOK_H delay time shall inhibited as long as any power supply output is in current limit. Figure 18. PWOK_H connection

8.6 SMB_ALERT_L OUTPUT

The SMB_ALERT_L signal indicates that the power supply is experiencing a problem that the system agent should investigate. the specified limits. This signal is to be asserted in parallel with LED turning solid Yellow. STATUS_TEMPERATURE (7Dh) register. In case exhaust air temperature exceeds 70°C higher temp rating cord must be used.

Figure 19. SMB_ALERT_L Connection

8.7 VIN_OK_H OUTPUT

of the parametric PSU specification. The PSU shall de-assert (drive low) under input over-voltage condition. the PSU shall be capable of delivering all outputs within the regulation limits for at least 4mS before de-asserting PWOK_H(T1). Figure 20. VIN_OK_H Timing

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Note1: T2 is the minimum VIN_OK_H de-assertion dwell time that is initiated when the PSU has declared a loss of input voltage. Table 7. VIN_OK_H Timing Requirements

8.8 TIMING REQUIREMENTS

limits (Tvout_rise) within 1 to 70ms. For 12VSB, it is allowed to rise from 5.0 between 10ms. All outputs must rise monotonically. Figure 21. Turn On/Off Timing

• The 12VSB output voltage rise time shall be from 5.0 ms between 10 ms.

Table 8. Timing Requirements Table 9. LED Characteristics Table 10. LED Status

8.9 HOT_STANDBY

supply will operate in a load range having a better efficiency.

8.10 LED INDICATOR

and DC power presence and warning or fault conditions. Table 10 lists the different LED status.

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1 Cb = Capacitance of bus line in pF, typically in the range of 10…400 pF

Table 11. I2C / SMBus Specification

• The SDA/SCL IOs use 3V3 logic levels
• External pull-up resistors on SDA/SCL required for correct signal edges
• Full SMBus clock speed of 100 kbps
• Clock stretching limited to 1 ms
• SCL low time-out of >25 ms with recovery
• within 10 ms
• Recognizes any time Start/Stop bus conditions 3.3/5V Rpull-up TX RX SDA/SCL 3.3V 10kΩ DSP or EEPROM TX_EN

Figure 22. Physical layer of communication interface

Figure 23. I2C / SMBus Timing fixed addressing offset exists between the Controller and the EEPROM. Table 12. Address and Protocol Encoding

9.1 CONTROLLER AND EEPROM ACCESS

under different addresses, see ADDRESS SELECTION. The SDA/SCL lines are connected directly to the controller and EEPROM which are supplied by internal 3V3. The EEPROM provides 256 bytes of user memory. None of the bytes are used for the operation of the power supply.

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tech.support@psbel.com

9.2 EEPROM PROTOCOL

The EEPROM follows the industry communication protocols used for this type of device. Even though page write / read commands are defined, it is recommended to use the single byte write / read commands. WRITE The write command follows the SMBus 1.1 Write Byte protocol. After the device address with the write bit cleared a first byte with the data address to write to is sent followed by the data byte and the STOP condition. A new START condition on the bus should only occur after 5ms of the last STOP condition to allow the EEPROM to write the data into its memory. READ The read command follows the SMBus 1.1 Read Byte protocol. After the device address with the write bit cleared the data address byte is sent followed by a repeated start, the device address and the read bit set. The EEPROM will respond with the data byte at the specified location.

9.3 PMBus® PROTOCOL

The Power Management Bus (PMBus®) is an open standard protocol that defines means of communicating with power conversion and other devices. For more information, please see the System Management Interface Forum web site at: www.powerSIG.org. PMBus® command codes are not register addresses. They describe a specific command to be executed. The PES1600-12-080NA supply supports the following basic command structures:

• Clock stretching limited to 1 ms
• SCL low time-out of >25 ms with recovery within 10 ms
• Recognized any time Start/Stop bus conditions WRITE The write protocol is the SMBus 1.1 Write Byte/Word protocol. Note that the write protocol may end after the command byte or after the first data byte (Byte command) or then after sending 2 data bytes (Word command). In addition, Block write commands are supported with a total maximum length of 255 bytes. READ The read protocol is the SMBus 1.1 Read Byte/Word protocol. Note that the read protocol may request a single byte or word. In addition, Block read commands are supported with a total maximum length of 255 bytes. S Address W A Data Address A Data A P Data nA P S Address W A Data Address A S Address R A S Address W A Command A Data Low Byte1) A Data High Byte1) A P 1) Optional S Address W A Command A Byte 1 A Byte N A P Byte Count A S Address W A Command A Data (Low) Byte AS Address R A Data High Byte1) nA P 1) Optional

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9.4 POWER SUPPLY DIAGNOSTIC “EVENT RECORDER”

The power supply shall save the latest data and other pertinent data into nonvolatile memory when a critical event shuts down the power supply. This data shall be accessible via the PMBus® interface with an external source providing power to the 12Vstby output. Critical Events to trigger an update to the Event Recorder includes:

• Output OVP
• Output OCP
• Input OV/UV Fault
• Fan fault
• OTP
• Other faults to cause output shutdown. Refer to BCA.00199_PES1600-12-080NA PMBus® Communication Application Note for further information about the PMBus® commands to support this function.

9.5 FIRMWARE UPDATE

The power supply shall have the capability to update its firmware via the PMBus® interface while it is in standby mode. This FW can be updated when in the system and in standby mode and outside the system with power applied to the 12Vstby pins. BPS standard GUI supports the firmware upgrade function.

9.6 GRAPHICAL USER INTERFACE

Bel Power Solutions provides with its “I2C Utility” a Windows® XP/Vista/Win7 compatible graphical user interface allowing the programming and monitoring of the PES1600-12-080NA Front-End. The utility can be downloaded on: belfuse.com/power-solutions and supports both the PSMI and PMBus® protocols. The GUI allows automatic discovery of the units connected to the communication bus and will show them in the navigation tree. In the monitoring view the power supply can be controlled and monitored. If the GUI is used in conjunction with the YTM.00103 Evaluation Board it is also possible to control the PSON_L pin(s) of the power supply. S Address W A Command A Byte 1 A S Address R A Byte N nA PByte Count A

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Table 13. Temperature Sensor Location and Thresholds Figure 25. Monitoring dialog of the I2C Utility 080NA supply has been designed for horizontal operation. and is a function of output power and the inlet temperature. 10% mean speed). This condition may be treated as steady state fan speed condition. LED, PWOK_H and SMB_ALERT_L.

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A The apparatus shall continue to operate as intended. No degradation of performance. B The apparatus shall continue to operate as intended. No degradation of performance beyond spec limits. Table 14. Performance Criteria

11.1 IMMUNITY

11.2 EMISSION

Comment: All printed wiring boards and all connectors meet UL94V-0 level. Table 15. Requirements for Redundant Power Supply Configuration from electric strength field tests. temperature specifications and lifetime requirements. exception to the air exhaust side must be classified as “Handle, knobs, grips, etc. held for short periods of time only”.

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Table 16. Requirements for Non-Redundant Power Supply Configuration (Typical System Ambient) Table 17. Requirements for Non-Redundant Power Supply Configuration (High System Ambient)

13.1 HUMIDITY

NOTE: 95% relative humidity is achieved with a dry bulb temperature of 55°C and a wet bulb temperature of 54°C.

13.2 ALTITUDE

13.3 SHOCK AND VIBRATION

13.3.1 RANDOM VIBRATION – OPERATING

Sample Size: For all product classes and categories, the minimum number of samples shall be 3 devices. test at nominal input voltage and no load. For operating vibration testing, see Figure 28.

Figure 28. Class ll PCDs Operating Vibration Test: Acceleration vs Frequency Table 18. Operation Vibration Profile Charts specification during the entire test.

13.3.2 RANDOM VIBRATION - NON-OPERATING

devices packaged in their fully populated, bulk shipping package or individual packages of product. for a minimum of 30 minutes per axis.

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Comment: All components de-rating follow IPC9592B. The total acceleration for Class II PCDs is approximately 3.8g rms (See Table 19). Table 19. Non-Operating Vibration Profile Charts deformed sheet metal are not allowed. All units shall also pass a functional test. There are no requirements on the condition of the shipping package.

13.3.3 SHOCK – OPERATING

Sample Size: For all product types and product classes, the minimum number of samples shall be three devices. Part 2.27 Test Ea and guidance: Shock. Each tested device shall be exposed to three shocks in each of 3 axes. The amplitude of each shock shall be no less than 30 g with a half sine wave shape and a duration of 11mS. specification during the entire test.

13.3.4 THERMAL SHOCK (SHIPPING)

temperature extremes for each half cycle shall be 30 minutes.

Figure 29. Top, bottom and side view

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Figure 30. Front view Figure 31. Rear view Table 20. Output connector pin assignment

+86 755 298 85888 Europe, Middle East +353 61 225 977 North America +1 408 785 5200 © 2018 Bel Power Solutions BCD.00941_AA ITEM DESCRIPTION ORDERING PART NUMBER SOURCE I2C Utility Windows XP/Vista/7 compatible GUI to program, control and monitor Front-End power supplies (and other I2C units) N/A belfuse.com/power-solutions Evaluation Board Connector board to operate PES1600-12-080NA. Includes an on- board USB to I2C converter (use I2C Utility as desktop software). YTM.00103 belfuse.com/power-solutions Maximum electric strength testing is performed in the factory according to IEC/EN 60950, and UL 60950. Input-to-output electric strength tests should not be repeated in the field. Bel Power Solutions will not honor any warranty claims resulting from electric strength field tests. NUCLEAR AND MEDICAL APPLICATIONS - Products are not designed or intended for use as critical components in life support systems, equipment used in hazardous environments, or nuclear control systems. TECHNICAL REVISIONS - The appearance of products, including safety agency certifications pictured on labels, may change depending on the date manufactured. Specifications are subject to change without notice.