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TECHNICAL DATA SHEET PEM001

60 GHz Transmitter (Tx) Waveguide Module

Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV The PEM001 is a highly integrated millimeter wave transmitter that covers the 60 GHz global unlicensed spectrum allocations packaged in a standard waveguide module. Transmitter architecture is a double conversion, sliding IF with wide bandwidth capability through the upconversion chain from baseband to carrier. The I/Q interface accepts analog baseband signals which provides for flexibility in design and applications. The baseband input optionally supports FSK/MSK modulation for non- coherent applications. The transmitter incorporates a complete waveguide interface with low-loss transition between the chip and the WR15 waveguide port. The integrated package is small and lightweight, with a simple to use multi-pin ST4 connector for power, reference clock, digital control port and baseband signals. Either of two reference clocks can be used for setting 540 MHz or 500 MHz channel spacing. Features:

  • Complete millimeter wave transmitter
  • WR-15, UG-385/U flange
  • Operates in the 57 to 66 GHz unlicensed band
  • 12 dBm typical output power
  • Up to 1.8 GHz modulation bandwidth
  • I/Q analog baseband interface
  • On chip synthesizer covers 57 to 64.8 GHz
  • 500 MHz or 540 MHz step size
  • 285.714 MHz clock for 500 MHz step size
  • 308.572 MHz clock for 540 MHz step size
  • Power, control, signals on ST4 connector
  • Temperature sensor

Applications

  • Any Channel (500 MHz or 540 MHz) 57-64.8 GHz
  • Multi-Gbps Digital Communications
  • HD Video Transmission
  • Millimeter Wave Radar
  • Millimeter Wave Imaging
  • Development for 802.11ad and 802.11aj
  • ATE Equipment for 60 GHz Manufacturing Test PEM001

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV .354" (9.00 mm) GG 1.057" (26.85 mm) WR-15 UG-385/U Flange .750" (19.05 mm) .792" (20.12 mm) GG .315" (8.00 mm) Samtec ST4-20 Connector .591" (15.00 mm) .394" (10.00 mm) Pin 1 Figure 1 PEM001 Mechanical Dimensions PEM001

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Samtec ST4-20 Mating Connector: Samtec SS4-20-3.00-L-D-K-TR GG Pin 1 BB_QM1 BB_QP BB_IM BB_IP FMM_Q FMP_Q FMM_I FMP_I REFCLKM REFCLKP Q1_B_C Q1_E RESET ENABLE CLK DATA SCANOUT VDD VCC_PA VCC_PA VDD VCC 2.7V 2.7V 2.7V 2.7V 2.7V 2.7V 2.7V 1.5V 2.7V 1.5V VCC VCC VCC VCC VCC VCC VCC Figure 2 PEM001 Interface Connector Pinout PEM001

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 1 Performance Specifications* Parameter Unit Comment I/Q Balance Phase I/Q Balance Amplitude Min Typ Max Frequency Range 57.0 64.8 GHz Channel Spacing 540 MHz 308.571 MHz Reference Channel Spacing 500 MHz 285.714 MHz Reference Gain, Max Gain, Range dB dB Gain, Step Size 1.25 dB P1dB 12 dBm Psat 15 dBm Image Rejection 34 dB Sideband Suppression 20 dB Carrier Suppression 20 dB Phase Noise @ 100 kHz -72 dBc/Hz Phase Noise @ 1 MHz -86 Phase Noise @ 10 MHz -111 Phase Noise @ 100 MHz -125 Phase Noise @ 1 GHz -127 dBc/Hz dBc/Hz dBc/Hz dBc/Hz PLL Loop Bandwidth 200 kHz ± 3 degrees ± 1 dB *Test Conditions: Reference Frequency 308.571 MHz Temperature 25°C I/Q Input Signal Level Referenced to -31 dBm x4 at each 50 ohm input port IF Bandwidth Max Output Referenced to WR15 output port Modulation Bandwidth 1.8 GHz Max BW setting, double-sided at 3 dB Gain = Pout - Pin (I/Q differential input) 3x LO Suppression 32 dB

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 2 Recommended Operating Conditions Description Unit Power Supplies V

1 Reference clock power level specified at 100 ohms differential

2 Baseband voltage at each of the individual baseband inputs (I +/-, Q +/-, FMI +/-, FMQ +/-)

3 Temperature sensor is a 2N3904 NPN transistor die connected as a diode junction

ST4 Pin # 8,22,24,26, 28,30,32 10,34 2.72.565 2.835 1.51.425 1.575 V Serial Control Port Logic High Serial Control Port Logic Low DATA CLOCK ENABLE RESET SCANOUT DATA CLOCK ENABLE RESET SCANOUT 1.3 1.5751.0 0.1 0.33-.05 V V Reference Clock 1 REFCLKM REFCLKP 0-5 3 dBm BB_QM BB_QP BB_IM BB_QP I and Q Baseband 2 Operating Temperature -40 85 °C Temperature Sensor 3 Q1_E Q1_B_C 5 25 100 mVPP Vcc 2.7V Supply Current Icc Idd 193 mA 8 mAVdd 1.5V Supply Current TA Serial Control Port Speed 100 MHz Vcc_PA 12,14,16,18 4.03.9 4.1 V Vcc_PA 4V Supply Current I PA 66 mA FMM_Q FMP_Q FMM_I FMP_I FM/MSK Baseband 2 200 500 750 mVPP

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 3 Absolute Maximum Ratings Table 3 Absolute Maximum Ratings

Description

ST4 Pin # 8,22,24,26, 28,30,32 10,34 2.85 V 1.6 V Serial Control Port Logic High Serial Control Port Logic Low DATA CLOCK ENABLE RESET1 SCANOUT DATA CLOCK ENABLE SCANOUT 1.575 V -.05 V Reference Clock REFCLKM REFCLKP 5 dBm I and Q Baseband Operating Temperature -40 to 85 C Storage Temperature TA 750 mVPP Power Dissipation 1100 mW TS -55 to 150 C GND ± 50 mV5,11,17,23,29,35 PD RESET1

1 Assertion of RESET, active high, asynchronously resets all registers

Vcc_PA FMM_Q FMP_Q FMM_I FMP_I FM, MSK Baseband 750 mVPP 12,14,16,18 4.2 V BB_QM BB_QP BB_IM BB_QP

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Transmitter Architecture The PEM001 transmitter uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at 1/7 the RF carrier frequency, and the VCO is at 2/7 the RF carrier frequency. The LO is 3x the VCO frequency. The LO and IF are generated from a built-in synthesizer that has a step size at the RF carrier frequency of either 500 MHz or 540 MHz depending upon which reference clock frequency is used. The 540 MHz step size uses a 308.571 MHz reference, and the 500 MHz step uses a 285.714 MHz frequency. The IEEE channels for 802.11ad and 802.11aj are supported when the 540 MHz step size is used. I and Q analog baseband signals are upconverted to the IF frequency at the input mixers. The IF signal is filtered with a variable gain amplifier and filter with approximately 20 dB range, which is then mixed with the LO. A notch filter attenuates the image frequency. The output of the mixer is fed to the PA stage which is coupled to the low-loss waveguide transition. There are optional FSK/MSK baseband data inputs for non-coherent modulation applications. The overall phase noise and I/Q balance specifications are sufficient for up to 16 QAM operation. Configuration and settings are controlled through a digital serial interface port. The block diagram below shows the various stages and circuits in the module. BB_IP PA Var IF Filter IF VGA Div BB_IM BB_QP BB_QM FMP_Q FMM_Q FMP_I FMM_I REFCLKP REFCLKM Serial Control Registers +1.5 +2.7 +4 ENABLE DATA RESET WR-15 Waveguide UG-385/U Flange Synthesizer 57.0 to 64.8 GHz 0.5 or 0.54 GHz step CLOCK SCANOUT Figure 3 PEM001 Block Diagram

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Synthesizer Design The PEM001 transmitter uses a double conversion superheterodyne architecture with a sliding IF. The IF frequency is at 1/7 the RF carrier frequency, and the VCO is at 2/7 the RF carrier frequency. The LO is 3x the VCO frequency. The tables below show the RF carrier, IF, VCO and LO for the frequency range from 57 GHz to 64.80 GHz at 540 MHz and 500 MHz channel spacing respectively. The reference clock for the synthesizer at 540 MHz spacing is 308.571 MHz; for 500 MHz spacing it is 285.714 MHz. The loop bandwidth of the synthesizer phase lock loop is 200 kHz.

540 MHz Spacing 500 MHz Spacing

57.24 8.177 16.354 49.063 57.78 8.254 16.509 49.526 58.32 8.331 16.663 49.989 58.86 8.409 16.817 50.451 59.40 8.486 16.971 50.914 59.94 8.563 17.126 51.377 60.48 8.640 17.280 51.840 61.02 8.717 17.434 52.303 61.56 8.794 17.589 52.766 62.10 8.871 17.743 53.229 62.64 8.949 17.897 53.691 63.18 9.026 18.051 54.154 63.72 9.103 18.206 54.617 64.26 9.180 18.360 55.080 64.80 9.257 18.514 55.543 fRF IF VCO LO 57.00 8.143 16.286 48.857 57.50 8.214 16.429 49.286 58.00 8.286 16.571 49.714 58.50 8.357 16.714 50.143 59.00 8.429 16.857 50.571 59.50 8.500 17.000 51.000 60.00 8.571 17.413 51.429 60.50 8.643 17.286 51.587 61.00 8.714 17.429 52.286 61.50 8.786 17.571 52.714 62.00 8.857 17.714 53.143 62.50 8.929 18.587 53.571 63.00 9.000 18.000 54.000 63.50 9.071 18.143 54.429 64.00 9.143 18.286 54.857 Figure 4 Synthesizer RF, IF, VCO and LO Frequencies

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Digital Control Registers and Serial Interface Protocol - Write Operation The PEM001 is configured via the serial control port which transfers data synchronously to or from (write or read operation) a register location. Register locations are organized into 16, byte-wide (8-bit) locations. The register locations are written to or read from one byte at a time as shown in Figures 5 and 6 respectively. Figure 5 shows the sequence of the digital control signals for the ENABLE, CLOCK and DATA input pins (ST4 connector, pins 39, 36 and 38 respectively) to write a single byte into the control register. After the ENABLE signal goes low, the first of 18 data bits (bit 0) is placed on the data pin, and 2 ns or more after the DATA signal stabilizes, the CLOCK signal goes high which clocks in data bit 0. The DATA signal must remain stable for at least 2 ns after the rising edge of the CLOCK. The signal levels are 1.5V CMOS, 50 kΩ impedance, with a maximum clock rate of 100 MHz. A write operation requires an 18 bit field associated with 18 clock pulses as shown in Figure 5. The 18 bit field contains the 8-bit data (LSB is clocked in first), followed by the byte address (BYTE 0 through BYTE 15, 000000 to 001111, LSB first, only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (write = 1), and the module address which distinguishes between a transmitter module and receiver module (for the V60RXWG3 receiver, RX module = 1 11). After clock pulse 17 (18 total pulses), the ENABLE signal is returned to a high state to load the register byte into the module. The CLOCK signal must be stable in the low state at least 2 ns prior to the rising edge of the ENABLE signal. ENABLE CLOCK 0 1 2 17 DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Data LSB MSB Byte Address LSB MSB R/W LSB MSB TX/RX Module Figure 5 Write Operation Timing Diagram

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Digital Control Registers and Serial Interface Protocol - Read Operation Figure 6 shows the sequence of control signals at the ENABLE, CLOCK and DATA pins to read a single byte at a register location. A read operation requires a 27 bit field: The first 18 bits are used to clock in the bits on the DATA input pin. The first 8 bits during a read operation are “don’t care” bits as they are placeholders for the 8-bit byte data which would be present during a write operation. The following 10 bits are composed of the byte address (BYTE 0 through BYTE 15, 000000 to 001111, LSB first, only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (read = 0), and the module address which distinguishes between a transmitter module and receiver module (for the PEM001 transmitter, TX module = 110, LSB first). After clock pulse 17 (18 total pulses), the ENABLE signal is returned to a high state while the clock signal is low, then a single clock pulse (pulse 18) is sent during the ENABLE signal high period. The ENABLE signal then returns to the low state while the CLOCK signal is low. At each of the subsequent 8 CLOCK pulses, the 8-bit data from the specified register location is available at the SCANOUT pin, LSB first. Note that the DATA signal must remain in the low state during the period from clock pulse 18 through 26. Following clock pulse 26, the ENABLE signal goes high while the CLOCK signal is low to end the read operation. ENABLE CLOCK 0 1 2 17 DATA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17LSB MSB LSB MSB LSB MSBSCAN OUT 0 1 2 3 4 5 6 7 Read Data Data Byte Address R/W TX/RX Module LSB MSB Figure 6 Read Operation Timing Diagram

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 4.1 Register Byte Functions Table 4.1 Register Byte Functions Bit Name BYTE 0 7 pa_pwrdn pa_pwrdn_fast6 mixer_pwrdn divider_pwrdn if_bgmux_pwrdn if_mixer_pwrdn driver_pwrdn ifvga_pwrdn Active high to power down PA circuits not controlled by bit <6> Active high to power down PA core in < 1 us Active high to power down IF to RF mixer Active high to power down local oscillator divider Active high to power down one of three on-chip refs (IF) and associated mux Active high to power down baseband to IF mixers Active high to power down PA predriver Active high to power down IF variable gain amplifier BYTE 1 Function BYTE 2 ipc_pwrdn fdb_11 Active high to power down module current reference generator Reserved; bits <7:4> = 1111 for normal operation tripler_pwrdn Active high to power down frequency tripler ifvga_q_cntrl_2 ifvga_q_cntrl_1 ifvga_q_cntrl_0 not used not used not used Not used; bits <2:0> = xxx fdb_10 fdb_9 fdb_8 pa_sel_vgbs_3 pa_sel_vgbs_2 pa_sel_vgbs_1 pa_sel_vgbs_0 PA output transistors base voltage regulator; bits <3:0> = 0000 for normal operation IF filter Q in the VGA amplifier; bits <2:0> = 000 for highest Q and gain For reduced Q and wider bandwidth, bits <2:0> = 001,100 ,101,111 in sequence

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 4.2 Register Byte Functions Table 4.2 Register Byte Functions Bit Name BYTE 3 Reserved: bits <3:0> = 1111 for normal operation BYTE 4 Function BYTE 5 Reserved: bits <7:4> = 0001 for normal operation fdb_7 fdb_6 fdb_5 fdb_4 fdb_3 fdb_2 fdb_1 fdb_0 pa_sel_vref_3 pa_sel_vref_2 pa_sel_vref_1 pa_sel_vref_0 PA output transistors bias current; bits <7:4> = 0011 for normal operation driver_bias_2 driver_bias_1 driver_bias_0 PA predriver bias current; bits <3:1> = 111 for normal operation driver_bias2_2 PA predriver2 bias current; bit <0> = 1 for normal operation not used Not used; bits <7:4> = xxxx not used not used not used bg_monitor_set if_refsel Reserved: bits <3:2> = 01 for normal operation enable_fm Active high to enable FM/MSK modulator inputs; bit <1> = 0 for normal I/Q not used Not used; bit <0> = x

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 4.3 Register Byte Functions Bit Name BYTE 6 tripler_bias_13 BYTE 7 Function BYTE 8 Frequency tripler bias (upper 8 bit portion): bits <7:0> = 10111111 default tripler_bias_12 tripler_bias_11 tripler_bias_10 tripler_bias_9 tripler_bias_8 tripler_bias_7 tripler_bias_6 ifvga_bias_2 IF VGA bias ; bits <7:4> = 1000 for normal operationifvga_bias_1 ifvga_bias_0 ifvga_tune_4 ifvga_tune_3 ifvga_tune_2 ifvga_tune_1 ifvga_vga_adj_3 IF VGA gain control bits; bits <7:4> = 0000 highest gain, 1111 lowest gai nifvga_vga_adj_2 ifvga_vga_adj_1 ifvga_vga_adj_0 Attenuation 1.25 dB/step, ≈ 20 dB maximum rfmix_tune_3 IF filter alignment in the RF mixer; bits <3:0> = 1111 for normal operation rfmix_tune_2 rfmix_tune_1 rfmix_tune_0 ifvga_bias_3 IF VGA filter ; bits <3:0> = 1111 for normal operation

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 4.4 Register Byte Functions Bit Name BYTE 9 BYTE 10 Function BYTE 11 Synthesizer divider ratio bits 3:0 (see Tables 5.1 and 5.2) rdacin_5 VCO amplitude DAC; bits<7:2> = 111100 for normal operation Synthesizer reset; bit <1> = 0 for normal operation Synthesizer divider ratio bit 4 (see Tables 5.1 and 5.2) band_2 rfseldiv VCO band tuning bits 2:0 (see Tables 5.1 and 5.2) Reserved; bit <0> = 1 for normal operation driver_bias2_1 rdacin_4 rdacin_3 rdacin_2 rdacin_1 rdacin_0 synreset divratio_4 divratio_3 divratio_2 divratio_1 divratio_0 band_1 band_0 tripler_bias_5 tripler_bias_4 tripler_bias_3 tripler_bias_2 tripler_bias_1 tripler_bias_0 Frequency tripler bias (lower 6 bit portion): bits <7:2> = 011011 default driver_bias2_0 PA predriver2 bias current; bits <1:0> = 11 for normal operation

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 4.5 Register Byte Functions Bit Name BYTE 12 BYTE 13 Function BYTE 14 pd_cal cpbias_2 cpbias_1 cpbias_0 Synthesizer charge pump bias; bits <7:5> = 010 for normal operation vrsel_3 vrsel_2 vrsel_1 vrsel_0 refselvco Synthesizer lock detector window width; bits <4:1> = 1111 for normal operation Reserved; bit <0> = 1 for normal operation muxref div_4 en_dc ini pd_div_15 pd_div_27 pd_qp pd_vco Reserved; bit <7> = 1 for normal operation Enable synthesizer divider bit 4; bit <6> = 0 for normal operation Synthesizer reference input DC coupling; bit <5> = 0 for normal operation Reserved; bit <4> = 0 for normal operation Active high to power down 1.5V circuits in synthesizer divider Active high to power down 2.7V circuits in synthesizer divider Active high to power down synthesizer charge pump Active high to power down synthesizer VCO Active high to power down VCO calibration; bit <7> = 0 for no rmal operation muxout Multiplexer control for ability to read byte 15; bit <6> = 1 for normal operation pdcalc15 Active high to power down VCO ALC; bit <5> = 1 for normal operation pload Active high to load adjustment of VCO; bit <4> = 1 for normal operation wide_1 wide_2 Control for VCO ALC loop; bits <3:2> = 01 for normal operation slew_1 slew_0 Slew rate control of sub-integer N divider; bits <1:0> = 10 fo r normal operation

TECHNICAL DATA SHEET PEM001 Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications: 60 GHz Transmitter (Tx) Waveguide Module PEM001 PEM001 REV Table 4.6 Register Byte Functions Table 4.6 Register Byte Functions Bit Name BYTE 15 7 comp_p Function Reserved (read only) rdacmsb_2 comp_n Synthesizer lock indication (read only): bits <7:6> = 01 locked, = 11 above window, = 00 below window, = 10 disallowed indicating error rdacmsb_1 rdacmsb_0 rdacmux_0 rdacmux_1 rdacmux_2 Table 5.1 540 MHz Channels Channel Divider 57.24 10101 Byte 10 001 Band1 11110001 11110001 Byte 11 57.78 58.32 58.86 59.40 59.94 60.48 61.02 61.56 62.10 62.64 63.18 63.72 64.26 64.802 10100 10011 10010 10001 10000 11111 00000 00001 00010 00011 00100 00101 00110 00111 001 010 010 011 011 100 100 101 101 110 110 111 111 111 01010011 01000011 00110101 00100101 00010111 00000111 11111001 00001001 00011011 00101011 00111101 01001101 01011111 01101111 01111111 11110001 11110001 11110001 11110001 11110001 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 Table 5.1 540 MHz Channels Reference: 308.571 MHz Note 1: Band setting typical, may change from module to module and temperature. Note 2: Operation above 64 GHz not guaranteed over full operating temperature range. Channel Divider 57.0 00001 Byte 10 000 Band1 11110000 11110000 Byte 11 57.5 58.0 58.5 59.0 59.5 60.0 60.5 61.0 61.5 62.0 62.5 63.0 63.5 64.0 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 001 001 010 010 011 011 100 100 101 101 110 110 111 00010001 00100001 00110011 01000011 01010101 01100101 01110111 10000111 10011001 10101001 10111011 11001011 11011101 11101101 11111111 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 Referenc e: 285.714 MHz Note 1: Band setting typical, may change from module to module and temperature.

TECHNICAL DATA SHEET PEM001 Table 5.1 500 MHz Channels Channel Divider 57.24 10101 Byte 10 001 Band1 11110001 11110001 Byte 11 57.78 58.32 58.86 59.40 59.94 60.48 61.02 61.56 62.10 62.64 63.18 63.72 64.26 64.802 10100 10011 10010 10001 10000 11111 00000 00001 00010 00011 00100 00101 00110 00111 001 010 010 011 011 100 100 101 101 110 110 111 111 111 01010011 01000011 00110101 00100101 00010111 00000111 11111001 00001001 00011011 00101011 00111101 01001101 01011111 01101111 01111111 11110001 11110001 11110001 11110001 11110001 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 Table 5.1 540 MHz Channels Reference: 308.571 MHz Note 1: Band setting typical, may change from module to module and temperature. Note 2: Operation above 64 GHz not guaranteed over full operating temperature range. Channel Divider 57.0 00001 Byte 10 000 Band1 11110000 11110000 Byte 11 57.5 58.0 58.5 59.0 59.5 60.0 60.5 61.0 61.5 62.0 62.5 63.0 63.5 64.0 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 001 001 010 010 011 011 100 100 101 101 110 110 111 00010001 00100001 00110011 01000011 01010101 01100101 01110111 10000111 10011001 10101001 10111011 11001011 11011101 11101101 11111111 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 11110000 Referenc e: 285.714 MHz Note 1: Band setting typical, may change from module to module and temperature. 60 GHz Transmitter (Tx) Waveguide Module from Pasternack Enterprises has same day shipment for domestic and International orders. Our RF, microwave and fiber optic products maintain a 99% availability and are part of the broadest selection in the industry. Click the following link (or enter part number in “SEARCH” on website) to obtain additional part information including price, inventory and certifications:

60 GHz Transmitter (Tx) Waveguide Module PEM001

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18© 2013 Pasternack Enterprises All Rights Reserved PEM001 REV Millimeter Wave Transmitter Module Operating From 57 GHz To 64 GHz PEM001 CAD Drawing