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SICOFI ®4-µC Four Channel Codec Filter with PCM and Microcontroller Interface PEB 2466 Version 2.2 PEF 2466 Version 2.2 Hardware Reference Manual, DS 1, Feb. 2001 Wired Communications Never stop thinking.
Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
SICOFI ®4-µC Four Channel Codec Filter with PCM and Microcontroller Interface PEB 2466 Version 2.2 PEF 2466 Version 2.2 Hardware Reference Manual, DS 1, Feb. 2001 Never stop thinking.
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC ®-P, ISAC ®-S, ISAC ®-S TE, ISAC ®-P TE, ITAC ®, IWE ®, MUSAC ®-A, OCTAT®-P, QUAT ®-S, SICAT ®, SICOFI ®, SICOFI ®-2, SICOFI ®-4, SICOFI ®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. PEB 2466 PEF 2466 Revision History: Current Version 2001-02-20 DS 1 Previous Version: Data Sheet 02.97 DS2 (V 1.2) Delta Sheet 11.98 DS2 (V 1.4) Errata Sheet 05.98 DS1 (V 1.4) Page Subjects (major changes since last revision)
Hardware Reference Manual 2001-02-20
Hardware Reference Manual 2001-02-20
Hardware Reference Manual 2001-02-20
Hardware Reference Manual 2001-02-20 Table 30 Channel-Specific Configuration Register (CR) Map (Read & Write) . . 40
Hardware Reference Manual 1 2001-02-20 Preface This document provides detailed technical information about the SICOFI ®4-µC. It is intended for anyone considering or using the device for system design or board layout for a broad range of analog telephony applications. All content applies to both the standard PEB 2466 and the extended temperature version, PEF 2466, unless specified. Organization of this Document This Hardware Reference Manual is organized as follows: Chapter 1, Overview Includes a general description of the architecture, feature list, and logic symbol. Chapter 2, Pin Descriptions Illustrates the Pin Configuration and provides detailed functional descriptions. Chapter 3, Functional Description Provides a block diagram and summarizes the major functional blocks. Chapter 4, Operational Description Begins with a state diagram and description of the operating states of all four channels and concludes with detailed transmission characteristics. Chapter 5, Interface Descriptions Describes the Analog, PCM, Signaling, and Serial Microcontroller interfaces. Chapter 6, Programming Overview Illustrates the register model and coefficient RAM structure, provides a register map and summary, and identifies the programming command sequences. Chapter 7, Application Hints Describes the development system available for the PEB 2466, and provides guidelines and schematics for board layout. Chapter 8, Electrical Characteristics and Timing Diagrams Provides detailed tables for the electrical characteristics and includes timing diagrams for the Analog, PCM, Serial Microcontroller, and Signaling interfaces. Chapter 9, Test Configuration Describes the test loops and cut-offs available for functional tests and diagnostics. Chapter 10, Package Outlines Illustrates the P-MQFP-64 package in which the PEB 2466 is manufactured. The Appendix Includes a glossary and an index. Related Documentation Other documentation for the PEB 2466 includes a Product Brief, a Product Overview, a Programmer’s Reference Manual , and assorted Application Notes . Similar documentation is also available for the other members of the SICOFI Codec family including the PSB 2132, PSB 2134, and PEB 2266. Documentation is available by accessing our website: http://www.infineon.com/sicofi
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1 Overview
The four-channel codec filter PEB 2466 SICOFI®4-µC is built around a central DSP-core which provides independent filter structures for all channels. Its analog I/O pins are used to connect to external subscriber line interface circuits (SLICs). Their signals are internally routed to the analog-to-digital and digital-to-analog converters (ADC, DAC). The signaling pins carry line status and control information to and from the SLICs. Two programmable clock outputs are available. The SICOFI ®4-µC connects to the digital switching and transmission system through two PCM Highways. The digitized voice band signals are available as A-Law or µ-Law codes within selectable 8-bit time slots. The SICOFI®4-µC modes, features, and filter characteristics are programmed through a serial interface to a microcontroller. The access mechanism is very simple, and can be implemented with as few as three I/O ports. The PEB 2466 is available for standard temperature range applications (0 °C to +70 °C); the PEF 2466 is available for extended temperature range applications (-40 °C to +85 °C). Figure 1 SICOFI ®4-µC Architecture SLIC 1 ADC - DAC Signaling SLIC 2 ADC - DAC Signaling SLIC 3 ADC - DAC Signaling SLIC 4 ADC - DAC Signaling Highway A Highway B Status and Control Registers CRAMPLL, Clocking Serial Microcontroller Interface t/r t/r t/r t/r PEB 2466 SICOFI4-µC Digital Filters Channel 1 Digital Filters Channel 2 Digital Filters Channel 3 Digital Filters Channel 4 DSP Core PCM Interface 2466_201
Hardware Reference Manual 3 2001-02-20 Four Channel Codec Filter with PCM and Microcontroller Interface SICOFI ®4-µC PEB 2466 PEF 2466 Version 2.2 CMOS Type Package PEB 2466 Version 2.2 P-MQFP-64 PEF 2466 Version 2.2 P-MQFP-64
1.1 Features
Four-channel single chip codec with digital filters High analog driving capability (300 Ω, 50 pF) for direct driving of transformers Digital Signal Processing (DSP) technique Programmable digital filters to adapt transmission behavior, especially for: – AC impedance matching – Transhybrid balancing – Frequency response – Signal levels – A/µ-Law compression and expansion Fulfills international (e.g. ITU-T Q.552, G.712) and country-specific requirements High performance ADC and DAC for excellent linearity and dynamic gain Programmable Analog Interface to electronic SLICs or transformer solutions Seven SLIC-signaling I/O pins per channel with programmable debouncing Two PCM Highways accessible by on-chip PCM Interface with Programmable time slot assignment and variable data rates from 128 kbit/s to 8 Mbit/s Easy to use 4-pin Serial Microcontroller Interface (SPI compatible) for read/write access Single supply voltage (5 V) Advanced low-power mixed-signal CMOS technology Two programmable tone generators per channel (DTMF possible) Level metering function for system tests and for analog input signal testing Advanced on-chip functions for device and system diagnostics and manufacturing test – Five digital loops – Four analog loops Support tools include: – Hardware development board — STUT 2466 – QSICOS Coefficient Calculation and Register Configuration Software Standard P-MQFP-64 package
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1.2 Logic Symbol
Figure 2 SICOFI ®4-µC Logic Symbol
1.3 Typical Applications
Many applications will benefit from the versatility of the SICOFI ®4-µC codec and filter. The inherent flexibility enables several products to be developed around one basic architecture, thus affording potentially significant savings in time to market, inventory costs, and support administration. The following list represents some of the typical applications for which the SICOFI®4-µC codec was designed: Analog linecards for Central Offices and PBXs, Small PBX or Key Systems, Digital Loop Carrier (DLC) Systems, Digital Added Main Lines (DAML) Systems, Fiber-to-the-Curb (FTTC) Systems, Radio-in-the-Loop (RITL) Systems, and any Multi-channel, digital voice processing, storage, or communication applications. Refer to the Product Overview, Chapter 5 Application Hints for more information. Analog Interface INT12 RESET# VOUT2 Channel Channel VIN2 VOUT1 VIN1 SICOFI®4-µC PEB 2466 CHCLK2 CHCLK1 Microcontroller Interface DOUT DIN DCLK CS# INT34 VOUT4 Channel Channel VIN4 VOUT3 VIN3 SI1_0 SI1_1 SO1_0 SO1_1 SB1_0 SB1_1 SB1_2 SI2_0 SI2_1 SO2_0 SO2_1 SB2_0 SB2_1 SB2_2 Signaling Interface Ch. 1&2 Channel Channel SI3_0 SI3_1 SO3_0 SO3_1 SB3_0 SB3_1 SB3_2 SI4_0 SI4_1 SO4_0 SO4_1 SB4_0 SB4_1 SB4_2 Channel Channel Signaling Interface Ch. 3&4 PCLK DRB DXB TCB# DXA TCA# MCLK DRA FSC PCM Clocks Master Clock Highway A Highway B PCM Interface 2466_203
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2 Pin Descriptions
2.1 Pin Diagram
(top view) Figure 3 Pin Configuration of SICOFI ®4-µC 1 2 345 6 78 9 10 11 12 13 14 15 16 SICOFI®4-µC PEB 2466-H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 CHCLK1 INT12 SI1_1 SI1_0 SB1_2 SB1_1 SB1_0 SO1_1 SO1_0 SO2_0 SO2_1 SB2_0 SB2_1 SB2_2 SI2_0 SI2_1 PCLK FSC DRB DXB TCB# DRA DXA TCA# V DDD RESET# MCLK GNDD DOUT DIN DCLK CS# CHCLK2 INT34 SI4_1 SI4_0 SB4_2 SB4_1 SB4_0 SO4_1 SO4_0 SO3_0 SO3_1 SB3_0 SB3_1 SB3_2 SI3_0 SI3_1 VIN4 VIN3 VIN2 VIN1 GNDA4 VOUT4 VDDA34 VOUT3 GNDA3 VDDREF VREF GNDA2 VOUT2 VDDA12 VOUT1 GNDA1 2466_204 P-MQFP-64
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2.2 Pin Definitions and Functions
Table 1 Pin Definitions and Functions Pin Symbol Type Function Ch.
1 SI3_1 I Signaling Input, Channel 3 Pin 1 3
2 SI3_0 I Signaling Input, Channel 3 Pin 0 3
3 SB3_2 I/O Bi-directional Signaling, Channel 3 Pin 2 3
4 SB3_1 I/O Bi-directional Signaling, Channel 3 Pin 1 3
5 SB3_0 I/O Bi-directional Signaling, Channel 3 Pin 0 3
6 SO3_1 O Signaling Output, Channel 3 Pin 1 3
7 SO3_0 O Signaling Output, Channel 3 Pin 0 3
8 SO4_0 O Signaling Output, Channel 4 Pin 0 4
9 SO4_1 O Signaling Output, Channel 4 Pin 1 4
10 SB4_0 I/O Bi-directional Signaling, Channel 4 Pin 0 4
11 SB4_1 I/O Bi-directional Signaling, Channel 4 Pin 1 4
12 SB4_2 I/O Bi-directional Signaling, Channel 4 Pin 2 4
13 SI4_0 I Signaling Input, Channel 4 Pin 0 4
14 SI4_1 I Signaling Input, Channel 4 Pin 1 4
15 INT34 O Interrupt Output Channels 3 and 4
Active high. 3, 4
16 CHCLK2 O Chopper Clock Output 2
Provides 256, 512, or 16384 kHz signal; sync. to MCLK. all
17 CS# I
Microcontroller Interface chip select, enable to read or write; active low all
18 DCLK I
Microcontroller Interface data clock, shifts data from or to device; maximum clock rate 8192 kHz. all
19 DIN I
Microcontroller Interface control data input pin; DCLK determines data rate. all
20 DOUT O
Microcontroller Interface control data output pin; DCLK determines data rate: DOUT is high impedance "Z" if no data is transmitted from the SICOFI®4-µC. all
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21 GNDD I
Ground reference for all digital signals. Internally isolated from GNDA1,2,3,4. all
22 MCLK I
1536, 2048, 4096 or 8192 kHz must be applied for any operation (selected in Register XR5). MCLK, PCLK, FSC must be synchronous. all
23 RESET# I Reset Input
Forces the device to default setting mode; active low. all
24 VDDD I Digital Supply Voltage
+5 V supply for digital circuits (use 100 nF blocking cap.). all
25 TCA# O
PCM Interface: active if data is transmitted via DXA; active low, open drain. all
26 DXA O
Data Transmit to PCM-Highway A PCM Interface: PCM data for each channel is transmitted in 8-bit bursts every 125 µs. all
27 DRA I
Data Receive from PCM-Highway A PCM Interface: PCM data for each channel is received in 8-bit bursts every 125 µs. all
28 TCB# O
PCM Interface: active if data is transmitted via DXB; active low, open drain. all
29 DXB O
Data Transmit to PCM-highway B PCM Interface: data for each channel is transmitted in 8-bit bursts every 125 µs. all
30 DRB I
Data Receive from PCM-highway B PCM Interface: data for each channel is received in 8-bit bursts every 125 µs. all
31 FSC I
Frame Synchronization Clock 8 kHz; reference for individual time slots, indicates start of PCM frame; MCLK, PCLK, FSC must be synchronous. all
32 PCLK I
128 to 8192 kHz; determines the rate at which PCM data is shifted into or out of the PCM-ports. MCLK, PCLK, FSC must be synchronous. all Pin Symbol Type Function Ch.
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33 CHCLK1 O
Provides programmable (2 … 28 ms) output signal (synchronous to MCLK). all
34 INT12 O Interrupt Output, Channels 1 and 2
Active high. 1, 2
35 SI1_1 I Signaling Input Channel 1, Pin 1 1
36 SI1_0 I Signaling Input Channel 1, Pin 0 1
37 SB1_2 I/O Bi-directional Signaling, Channel 1 Pin 2 1
38 SB1_1 I/O Bi-directional Signaling, Channel 1 Pin 1 1
39 SB1_0 I/O Bi-directional Signaling, Channel 1 Pin 0 1
40 SO1_1 O Signaling Output, Channel 1, Pin 1 1
41 SO1_0 O Signaling Output, Channel 1, Pin 0 1
42 SO2_0 O Signaling Output, Channel 2, Pin 0 2
43 SO2_1 O Signaling Output, Channel 2, Pin 1 2
44 SB2_0 I/O Bi-directional Signaling, Channel 2 Pin 0 2
45 SB2_1 I/O Bi-directional Signaling, Channel 2 Pin 1 2
46 SB2_2 I/O Bi-directional Signaling, Channel 2 Pin 2 2
47 SI2_0 I Signaling Input, Channel 2, Pin 0 2
48 SI2_1 I Signaling Input, Channel 2, Pin 1 2
49 VIN1 I Analog Voice (Voltage) Input, Channel 1
Requires a coupling capacitor >39 nF to the SLIC. 1
50 GNDA1 I Analog Ground, Channel 1
Not internally connected to GNDD or GNDA2,3,4. 1
51 VOUT1 O
Analog Voice (Voltage) Output, Channel 1 Requires a coupling capacitor to the SLIC. The capacitor value depends on the SLIC’s input impedance. (See Chapter 5.1 Analog Interface)
52 VDDA12 I Analog Supply Voltage, Channels 1 and 2
+5 V (100 nF blocking capacitor required). 1, 2
53 VOUT2 O
Analog Voice (Voltage) Output, Channel 2 Requires a coupling capacitor to the SLIC. The capacitor value depends on the SLIC’s input impedance. (See Chapter 5.1 Analog Interface) Pin Symbol Type Function Ch.
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54 GNDA2 I Analog Ground, Channel 2
Not internally connected to GNDD or GNDA 1,3,4. 2
55 VIN2 I Analog Voice (Voltage) Input, Channel 2
Requires a coupling capacitor >39 nF to the SLIC. 2
56 VREF I/O Reference Voltage
Must connect to a 220 nF cap. to ground. all
57 VDDREF I Analog Supply Reference Voltage
+5 V (100 nF blocking capacitor required). all
58 VIN3 I Analog Voice (Voltage) Input, Channel 3
Requires a coupling capacitor >39 nF to the SLIC. 3
59 GNDA3 I Analog Ground, Channel 3
Not internally connected to GNDD or GNDA1,2,4. 3
60 VOUT3 O
Analog Voice (Voltage) Output, Channel 3 Requires a coupling capacitor to the SLIC. The capacitor value depends on the SLIC’s input impedance. (See Chapter 5.1 Analog Interface)
61 VDDA34 I Analog Supply Voltage, Channels 3 and 4
+5 V (100 nF blocking capacitor required). 3
62 VOUT4 O
Analog Voice (Voltage) Output, Channel 4 Requires a coupling capacitor to the SLIC. The capacitor value depends on the SLIC’s input impedance. (See Chapter 5.1 Analog Interface)
63 GNDA4 I Analog Ground, Channel 4
Not internally connected to GNDD or GNDA1,2,3. 4
64 VIN4 I Analog Voice (Voltage) Input, Channel 4
Requires a coupling capacitor >39 nF to the SLIC. 4 Pin Symbol Type Function Ch.
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3 Functional Description
The telephone subscriber loop is a bi-directional two-wire line. The Subscriber Line Interface Circuit (SLIC) on the network side converts the two-wire interface to a four-wire interface with separate receive and transmit signals, which connect to the SICOFI®4-µC. The SLIC can be either a transformer or an electronic circuit with operational amplifiers. It must have a defined input impedance towards the subscriber line for maximum signal power transfer and return loss. The requirements for the input impedance vary from country to country and demand impedance matching to the different environments. Country-specific adaptations are also required for the transhybrid loss, which is a loss between the transmit and the receive ports of the two-wire to four-wire hybrid.
3.1 DSP-based Architecture
The impedance matching and transhybrid balancing functions are performed by loop filters between the transmit path (analog to PCM) and the receive path (PCM to analog). The filter characteristics must be adjusted according to the local requirements of each market. In the analog domain, filters must be optimized in hardware; this is generally both tedious and time-consuming. This is not the case with the DSP-based SICOFI ®4- µC four-channel codec. Its integrated signal processor implements the impedance matching and transhybrid balancing functions as digital, programmable filters. It also performs frequency response corrections and level adjustments to enable the design of a truly universal and internationally applicable telephone linecard. Transmission characteristics and frequency behavior are enhanced by the accuracy of the digital filters, which do not fluctuate over temperature or with age. As an additional benefit of its DSP-based architecture, the PEB 2466 also provides two tone generators per channel. An on-chip level-metering unit allows line-characterization without extra hardware; it can also be used to detect specific tones, e.g., modem tones.
3.2 Programming and Control
A very simple Microcontroller Interface is used to program the SICOFI ®4-µC functions. The same port provides access to 28 general purpose I/O pins of the Signaling Interface. This allows efficient and convenient monitoring and control of other linecard functions, such as on-/off-hook detection, ground-key detection, switching of ring signals and test relays. The Serial Microcontroller Interface provides a programming and control interface and is generic and non-proprietary for use with any microcontroller. It can be implemented with as few as three signal lines, since the data receive and data transmit pins may be strapped together.
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4 Operational Description
Each channel of the SICOFI ®4-µC can be in one of two stable states: “Standby” and “Operating”. These states can be switched by programming Bit 0 (PU) in the channel-specific configuration register CR1. “Standby” is a power-saving state. Keeping all unused channels in this state reduces the overall system power dissipation. The third state, “Reset”, is transient and is reached after applying power to the device (Power On), after asserting a logic low signal to the RESET#-pin (HW-Reset), or after issuing an XOP command with Bit 7 (RST) set to ‘1’ (SW-Reset). All four channels would be affected in any case.
4.1 Operating States
Figure 5 SICOFI ®4-µC State Diagram
4.1.1 Power On
All input pins must be at GND level before applying VDD to the SICOFI®4-µC. Otherwise, the device may not enter the Reset State. In this case, the SICOFI®4-µC can be reset by HW- or SW-Reset, or can be initialized by setting all registers to zero.
4.1.2 Hardware Reset
Voltage levels lower than 1.2 V applied to pin 23 (RESET#) for more than 3 µs will reset the SICOFI ®4-µC. Spikes that are shorter than 1 µs will be ignored. When RESET# is released the SICOFI®4-µC will enter Standby State. 2466_206 Operating Ch.2 Standby Ch.2 Power Up Ch.2 Power Down Ch.2 Operating Ch.3 Standby Ch.3 Power Up Ch.3 Power Down Ch.3 Operating Ch.4 Standby Ch.4 Power Up Ch.4 Power Down Ch.4 Operating Ch.1 Standby Ch.1 Power Up Ch.1 Power Down Ch.1 Reset (all channels) Power-On HW-Reset SW-Reset
Hardware Reference Manual 13 2001-02-20 Table 2 Register Values and Accessibility Table 3 Input and Output Pin Behavior Register SICOFI®4-µC State Reset Standby Operating CR0 ... CR4 00 H user configurable user configurable XR0 ... XR7 00 H user configurable user configurable CRAM unchanged user configurable user configurable Pin SICOFI®4-µC State Reset Standby Operating DIN ignored serial input serial input DOUT high impedance serial output serial output DRA, DRB ignored ignored active receive time slot DXA, DXB high impedance high impedance active transmit time slot TCA#, TCB# high high low during active transmit time slot VOUT1 , VOUT2 VOUT3 , VOUT4 high impedance high impedance analog output VIN1 , VIN2 VIN3 , VIN4 ignored ignored analog input SBx_y configured as input programmable as input or output programmable as input or output SOx_y GNDD digital output digital output SIx_y ignored digital input digital input CHCLK1 high programmable frequency programmable frequency CHCLK2 high programmable freq. (not 16384 kHz) programmable frequency
Hardware Reference Manual 14 2001-02-20 Table 4 Power Dissipation
4.2 Transmission Characteristics
4.2.1 Overload Point
The overload point of the SICOFI ®4-µC A/D converters is at 2.223 V. This is the peak amplitude of a sine wave level of 1.572 Vrms. Higher input signal levels will be distorted. Theoretical load capacities for A-Law and µ-Law encoded signals are defined in ITU-T Recommendation G.711. These values correspond to the SICOFI®4-µC overload point: Table 5 Maximum Signal Levels 4.2.2 0 dBm0-Levels The analog voltage levels corresponding to a 0 dBm0 sine wave signal can be calculated from the maximum signal levels shown in Table 5. Table 6 Analog Voltage Levels Corresponding to 0 dBm0-Level Note: Periodic PCM codes for a 1 kHz sine wave signal with 0 dBm0 level can be found in ITU-T G.711. No. of Channels Operating Typical Power Dissipation None 2.5 mW 1 70 mW 2 90 mW 3 110 mW 4 130 mW Encoding Law PCM Interface Analog Interface Theoretical Load Capacity (according to ITU-T G.711) Max. Sine Wave Level (SICOFI ®4-µC Overload Point) A-Law 3.14 dBm0
1.572 Vrms
µ-Law 3.17 dBm0 Encoding Law Analog Sine Wave Level corresponding to 0 dBm0 PCM Level A-Law 1.572 Vrms*10^(-3.14/20) = 1.095 V rms µ-Law 1.572 Vrms*10^(-3.17/20) = 1.091 V rms
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4.2.3 Compressor Gain Relative to Coding Law
The µ-Law compressor unit of the SICOFI®4-µC automatically adds 1.94 dB gain, which has to be considered for the total gain calculation. The accumulated gain of all programmable transmit filters (AX1+AX2+FRX) must not exceed 7 dB if the device is set to µ-Law operation. If the device is set to A-Law operation, then the accumulated gain must not exceed 9 dB. Figure 6 Analog and PCM Signal Levels in A-Law Mode Figure 7 Analog and PCM Signal Levels in µ-Law Mode A-Law Compressor Transmit A-Law Expander Receive 0d B m 0 1014 Hz 0d B m 0 DXA/B DXA/BA/D 0d B Gain D/A 0d B Gain VOUT VIN1014 Hz
1.095 Vrms
2466_207 A/D µ -Law Compressor [+1.94 dB] Transmit D/A µ -Law Expander Receive VOUT VIN1014 Hz
1.091 Vrms
1.94 dBm0 1014 Hz 0d B m 0 DXA/B DXA/B0d B Gain 0d B Gain 2466_208
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4.2.4 Operating Conditions
The specifications to which the SICOFI®4-µC are tested are tighter than the ITU-T Q.552 Specification to guardband various SLIC implementations. The guaranteed transmission characteristics of the SICOFI ®4-µC under test conditions ensure that the final linecard design will meet the ITU-T specification. The figures in this document are based on the subscriber-line board requirements. Proper adjustment of the programmable filters (transhybrid balancing, impedance matching, frequency-response correction) requires a complete knowledge of the analog environment in which the SICOFI ®4-µC is to be used. Unless otherwise stated, the transmission characteristics are guaranteed within the following operating conditions: TA = 0 °C to 70 °C (PEB 2466), TA = -40 °C to 85 °C (PEF 2466); VDD = 5 V ± 5%; GNDA1,2,3,4 = GNDD = 0 V; Load on VOUT: RL > 300 Ω; CL < 50 pF; H(IM) = H(TH) = 0; H(R1) = H(FRX) = H(FRR) = 1; HPR and HPX enabled; AR = 0 to –9 dB (AR = AR1 + AR2 + FRR + R1); AX = 0 to +9 dB for A-Law, AX = 0 to +7 dB for µ-Law (AX = AX1 + AX2 + FRX); f = 1014 Hz; 0 dBm0; A-Law or µ-Law; AGX = 0 dB, +6.02 dB; and AGR = 0 dB, –6.02 dB. Figure 8 Simplified Signal Flow Diagram ADC DAC Receive Path Transmit Path Analog Output Analog Input PCM Input PCM Output IM AGR R1 AR2 FRR AR1 EXP CMPAX1FRXAX2AGX TH HPX HPR 2466_209
4.2.5 Gain Accuracy
4.2.6 Gain Tracking (Receive and Transmit)
Table 8. All values are relative to the gain of a 0 dBm0 input signal.
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4.2.7 Frequency Response
Table 9 Attenuation with Frequency in Transmit and Receive Direction
4.2.8 Group Delay
4.2.8.1 Group Delay, Absolute Values
Table 10 shows the limit values for the Absolute Group Delay. The maximum delays are valid when the SICOFI®4-µC is operating with H(TH) = H(IM) = 0, and H(FRR) = H(FRX) = 1, and include the delay through the A/D and D/A converters. The typical delays are the average of all different time slot delays during one PCM frame. Table 10 Group Delay, Absolute Values Input Frequency Receive Loss Transmit Loss Unit Test Conditions min. max. min. max.
0 Hz to 100 Hz 0 > 2 dB 0 dBm0 input signal
level. 1014 Hz reference frequency
100 Hz to 200 Hz 0 0 dB
200 Hz to 300 Hz -0.125 -0.125 1 dB > 3.4 kHz 0 0 dB Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Transmit Delay DXA 300 375 450 µs 0 dBm0 input signal level, fTest at TGmin.Receive Delay DRA 300 375 450 µs
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4.2.8.2 Group Delay Distortion with Frequency
The Group Delay Distortion in transmit and receive direction will stay within the limits shown in Table 11. Group Delay Distortion values are referenced to the minimum value of Group Delay (TGmin). Table 11 Group Delay Distortion with Frequency
4.2.9 Noise
Table 12 Idle Channel Noise in Transmit Direction Table 13 Idle Channel Noise in Receive Direction Frequency Symbol Limit Values Unit Test Conditions min. typ. max.
500 Hz to 600 Hz ∆tG 300 µs 0 dBm0 input signal level,
reference point is at TGmin.600 Hz to 1.0 kHz ∆tG 150 µs 1.0 kHz to 2.6 kHz ∆tG 100 µs 2.6 kHz to 3.0 kHz ∆tG 300 µs Parameter Symbol Limit Values Unit min. typ. max. A-Law, psophometric (VIN =0V ) NTP –67.4 dBm0p µ-Law, C-message (VIN =0V ) NTC 17.5 dBmc µ-Law, C-message (VIN =0V ) NTC 17.5 dBrnC0 Parameter Symbol Limit Values Unit min. typ. max. A-Law, psophometric (idle code + 0) NRP –85 –78.0 dBm0p µ-Law, C-message (idle code + 0) NRC 5 12.0 dBmc µ-Law, C-message (idle code + 0) NRC 5 12.0 dBrnC0
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4.2.10 Harmonic and Intermodulation Distortion
Table 14 Harmonic and Intermodulation Distortion
4.2.11 Total Distortion
Table 15 Signal-to-Total Distortion Ratio Measured with Sine Wave Figure 9 Total Distortion Measured with Sine-Wave, Receive and Transmit Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Harmonic Distortion 2nd, 3rd order HD –50 –44 dB 0 dBm0; f = 1014 Hz Intermodulation IMD IMD –46 –56 dB dB Equal-level, 4-tone method (EIA-464) at composite level of -13 dBm0; f = 300 Hz to 3400 Hz Input Level Symbol Min. Values Unit Test Conditions A-Law µ-Law -45 dB S/D 24.5 27 dB sine wave f=1014 Hz, receive and transmit, µ-Law: C-message weighted, A-Law: psophometrically weighted. -40 dB S/D 29.5 31 dB -30 dB S/D 35.5 35.5 dB > -28 dB S/D 36.4 36.4 dB -600 Input Level -50 -40 -30 -20 -10 0 dBm0 dB 24.5 -45 -28 35.5 29.5 A-Law -Lawµ 36.4 S/D 2466_210
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4.2.12 Single Frequency Distortion
Any resulting signal with a frequency different from the test input signal will stay at least 28 dB below the input signal level.
4.2.13 Overload Compression
This is measured with a 1014 Hz sine-wave signal. The overload point in µ-Law Mode is at 3.17 dBm0. Figure 12 Overload Compression (µ -Law Coding, Transmit Direction)
4.2.14 Crosstalk
Table 17 Crosstalk Between Channels Test Input Signal Frequency Range max. Input Level Receive Direction 300 Hz to 3.4kHz 0 dBm0 Transmit Direction 0 Hz to 12 kHz 0 dBm0 Parameter Symbol Limit Values Unit Test Conditions min. typ. max. Crosstalk, 0dBm0 CT – 85 – 80 dB f= 200 Hz to 3400 Hz, any combination of directions and channels Fundamental Input Power Fundamental dBm0 0.25 -0.25 1234567 d B m 0 9 Output Power 2466_213
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4.2.15 Out-of-Band Discrimination in Transmit Direction
With any 0 dBm0 sine-wave signal below 100 Hz and in the range from 3.4 kHz to 100 kHz (out-of-band signal) applied to an analog input (V INx), the level of any resulting frequency component at the digital output will stay at least X dB (see Table 18) below the output level of a 0 dBm0 1kHz sine-wave reference signal at the analog input. Table 18 Out-of-Band Signals Applied to the Analog Inputs (V INx) The Hardware Filters behind the A/D Converters reject teletax pulses with their poles at 12 kHz ±150 Hz and 16 kHz ±150 Hz. Figure 13 Out-of-Band Discrimination in Transmit Direction Input Frequency Min. Output Signal Rejection X Unit Test Conditions
0 Hz to 60 Hz 25 dB 0 dBm0 sine-wave input
signal on VIN60 Hz to 100 Hz 10 dB 3.4 kHz to 4 kHz dB 4 kHz 15 dB 4 kHz to 4.6 kHz dB 4.6 kHz to 100 kHz 40 dB 14– π 4000 f– 18– π 4000 f– sin 7 9---– kHz f 1000.06 0.1 3.4 4 4.6 6 10 18 dB Transmit Out-of-Band Discrimination X 2466_214
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4.2.16 Out-of-Band Discrimination in Receive Direction
With any 0 dBm0 sine-wave frequency in the range from 300 Hz to 3.99 kHz applied to the digital input (PCM time slot), the level of any resulting out-of-band signal at the analog output will stay at least X dB (see Table 19) below the output level of a 0 dBm0 1kHz sine-wave reference signal at the digital input. Table 19 Out-of-Band Signals at the Analog Outputs (V OUTx) Figure 14 Analog Output: Out-of-Band Signals Output Frequency Min. Output Signal Rejection X Unit Test Conditions 3.4 kHz to 4.6 kHz dB 0 dBm0 sine-wave input signal on digital input (PCM time slot) 4.6 kHz to 10.55 kHz dB 4 kHz 15 dB 4.6 kHz 28 dB >10.55 kHz 57 dB 14– π 4000 f– 35 22 f 4600– kHz f 1000.06 0.1 3.4 4 4.6 6 10 18 dB Receive Out-of-Band Discrimination X 10.55 8 16 2466_215
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4.2.17 Out-of-Band Idle Channel Noise at Analog Output
With an idle code (any sequence of constant PCM octets) applied to the digital input, the level of any resulting out-of-band power spectral density at the analog output, measured with 3 kHz bandwidth, will be not greater than the limit curve shown in Figure 15. Figure 15 Analog Output: Out-of-Band Idle Channel Noise -100 f 1012 10 310 410kHz -90 -80 -70 -60 -50 -40 dBm0 -55 -78 O u to fB a n dN o i s e 2466_216
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4.2.18 Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain, group delay, and deviations inherent to the A/D- and D/A-converters, as well as to all external components used on a linecard (SLIC, OP’s etc.). Transhybrid loss test setup: The SICOFI®4-µC test loop “DLB-ANA” is selected (see Figure 34), which connects the analog output with the analog input. The programmable filters FRR, AR, FRX, AX are by-passed. The IM-filter is disabled, (H(IM)=0). The balancing filter TH is enabled with optimized coefficients for this configuration (VOUT = VIN). A 0 dBm0 sine wave signal with a frequency in the range of 300 Hz to 3400 Hz is applied to the digital input. The signal levels of the resulting echo at the digital output will stay below the values shown in Table 20. Table 20 Transhybrid Loss Input Frequency Symbol Transhybrid Loss Unit Test Condition min. typ.
300 Hz THL300 27 40 dB TA = 25 °C; VDD = 5 V
AGX = AGR = 0 dB; typical variation of amplitude: ± 0.15 dB delay: ± 0.5 µs.
500 Hz THL500 30 45 dB
2500 Hz THL2500 29 40 dB
3000 Hz THL3000 27 35 dB
3400 Hz THL3400 27 35 dB
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5 Interface Description
The SICOFI®4-µC provides four interfaces: Analog Interface, PCM Interface, Signaling Interface, and Serial Microcontroller Interface. A general description of these interface is given in the Product Overview, Chapter 4. Refer to the Programmers Reference Manual for information on the configuration and operation of the four interfaces. The subsequent chapters in this manual explain how to connect the SICOFI ®4-µC to subscriber line interface circuits (SLICs), microcontrollers, and PCM highways.
5.1 Analog Interface
The Analog Interface in combination with a Subscriber Line Interface Circuit (SLIC) forms a configurable tip & ring (t/r) telephone line. The AC transmission characteristic of the SICOFI®4-µC— SLIC combination can be controlled by programming the digital filter structures inside the SICOFI®4-µC. The correct filter coefficients are determined by the targeted AC transmission behavior (e.g. Telco specification) and by the transfer functions of the SLIC. The SICOFI®4-µC can be interfaced directly to electronic SLICs or transformer solutions. The high driving capability of up to 300 Ohms eliminates the need for an external amplifier that is normally used with transformer SLICs. The peak amplitude of the analog inputs and outputs is at 2.223 V (overload point). Out-of-band signals applied to the analog inputs are suppressed by the on-chip digital hardware filters. The poles of these filters are fixed at 12 kHz and 16 kHz which suppresses the echo signal from teletax pulses very efficiently: As long as the amplitude of the teletax echo stays below the overload threshold of 2.223 Vp (1.57 Vrms), the voice signal in the transmit path will not be disturbed. Thus, the on-chip hardware filters can eliminate the need for external teletax filters.
5.1.1 Coupling Capacitors at the Analog Interface
A coupling capacitor >39 nF must be used on the VIN-pins in the transmit direction. The required value for the coupling capacitor on the VOUT-pins depends on the input resistance of the SLIC-circuitry ( RLoad). It has to be chosen to fulfil the frequency response requirement in the receive direction. Figure 16 can be used to determine an appropriate value for the coupling capacitor (CExt1).
Hardware Reference Manual 28 2001-02-20 Figure 16 Analog Interface to Four Subscriber Line Interface Circuits (SLICs) RLoad Ext1C 10 -3 10 23 10 410 -210 -110 110 210 010 F Ω µ 510 610 CExt1= fmin·RLoad fmin = 250 Hz 5756 > 39nF VDDA12 VDDA34 VREF VDDREF 6152 SICOFI4-µC 100nF220nF CExt1 VIN1 VOUT1 Channel 1 GNDA1 VIN3 VOUT3 Channel 3 GNDA3 Channel 2 VIN2 VOUT2 GNDA2 Channel 4 VIN4 VOUT4 GNDA4 CExt1 CExt1 > 39nF > 39nF 100nF 100nF 100nF 100nF > 39nF CExt1 SLIC 1 t/r RLoad SLIC 3 t/r RLoad SLIC 2 t/r RLoad SLIC 4 t/r RLoad 2466_217
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5.1.2 Analog Interface Pins
Table 21 Analog Interface Pins Symbol Pin Function VIN1 49 Analog Input, Channel 1, 2 Requires a coupling capacitor >39 nF to the SLIC, see Figure 16.VIN2 55 VIN3 58 Analog Input, Channel 3, 4 Requires a coupling capacitor >39 nF to the SLIC, see Figure 16.VIN4 64 VOUT1 51 Analog Output, Channel 1, 2 Requires a coupling capacitor to the SLIC. The capacitor’s value depends on the input impedance of the SLIC, see Figure 16.VOUT2 53 VOUT3 60 Analog Output, Channel 3, 4 Requires a coupling capacitor to the SLIC. The capacitor’s value depends on the input impedance of the SLIC, see Figure 16.VOUT4 62 GNDA1 50 Analog Ground, Channel 1, 2 Not internally connected to GNDD or the other GNDAx. GNDA2 54 GNDA3 59 Analog Ground, Channel 3, 4 Not internally connected to GNDD or the other GNDAx. GNDA4 63 VDDA12 52 Analog Supply Voltage, Channels 1+2 +5 V (100 nF blocking capacitor required, see Figure 16). VDDA34 61 Analog Supply Voltage, Channels 3+ 4 +5 V (100 nF blocking capacitor required, see Figure 16). VDDREF 57 Analog Supply Reference Voltage, +5 V (100 nF blocking capacitor required, see Figure 16). VREF 56 Reference Voltage Must connect to a 220 nF cap. to ground, see Figure 16.
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5.2 PCM Interface
The SICOFI®4-µC provides an industry–standard PCM Interface with access to two PCM highways. The PCM Interface has the following features: Data rate from 128 kbit/s to 8 Mbit/s per highway, 2 to 128 time slots per frame per highway, PCM data format serialized 8 bits with MSB first, Configurable A-Law or µ-Law coding, Independently configurable time slot and highway for each channel and direction, PCM clock speed of once or twice the bit rates, Programmable sampling slopes, and Programmable frame delay.
5.2.1 PCM Interface Pins
Table 22 PCM Interface Pins
5.2.2 PCM Receive and Transmit Example
Figure 17 and Figure 18 illustrate the time slot and bit positions resulting from the programming example below: Symbol Pin Function PCLK 32 PCM-Clock, 128 kHz to 8192 kHz; shared for both highways. FSC 31 Frame Synchronization Clock, 8 kHz; shared for both highways. DRA 27 Receive Data input for PCM-highway A. DRB 30 Receive Data input for PCM-highway B. DXA 26 Transmit Data output for PCM-highway A, open drain. DXB 29 Transmit Data output for PCM-highway B, open drain. TCA# 25 Transmit Control output for highway A, low when DXA is active. TCB# 28 Transmit Control output for highway B, low when DXB is active.
Hardware Reference Manual 31 2001-02-20 Table 23 PCM Register Configuration Example Figure 17 PCM Interface Example: Location of Time Slots Channel CR4 Receive Setting CR5 Transmit Setting 1 0000 0000 DRA, time slot 0 0000 0000 DXA, time slot 0 2 0000 1111 DRA, time slot 15 0001 0010 DXA, time slot 18 3 0000 1000 DRA, time slot 8 0001 0011 DXA, time slot 19 4 0001 1010 DRA, time slot 26 0000 0011 DXA, time slot 3 all XR6=0000 0000; single clock mode, no PCM offset; PCLK=2048 kHz. TCA# Detail A FSC DXA DRA PCLK High 'Z' High 'Z' Time Slot01 125 µs 3181 5 2 6 18 19 2466_218
Hardware Reference Manual 32 2001-02-20 Figure 18 PCM Interface Example: Detail A The pins DRA/B and DXA/B may be strapped together to form a multiplexed bi-directional PCM port.
5.3 Signaling Interface
The SICOFI®4-µC Signaling Interface is used to monitor and control supervision and signaling functions on up to four subscriber lines. The device generates interrupt signals to indicate signaling status changes on any of the input pins. The Signaling Interface consists of the following I/O pins and functions: 28 signaling pins (2 input pins, 2 output pins, and 3 user-configurable bi-directional pins per channel), Debouncing functions, 2 interrupts (one for each channel-pair), and 2 clock output signals (user configurable). DRA PCLK FSC DXA TCA# High 'Z' High 'Z' Voice Data Voice Data C l o c k 01234567 01234567Bit 2466_219
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5.3.1 Signaling Interface Pins
Figure 19 Signaling Example: Four Subscriber Lines SI1_0 SI1_1 SB1_2 SO1_1 SB1_1 Channel 1 SO1_0 SB1_0 Channel 3 SI3_0 SI3_1 SB3_2 SO3_1 SB3_1 SO3_0 SB3_0 SICOFI4-µC SI2_0 SI2_1 SB2_2 SO2_1 SB2_1 Channel 2 SO2_0 SB2_0 Channel 4 SI4_0 SI4_1 SB4_2 SO4_1 SB4_1 SO4_0 SB4_0 INT 12 INT 34 t/r t/r t/r t/r Operating Mode Off-Hook Det. Ring Relay Status LED Operating Mode SLIC 2 Off-Hook Det. Ring Relay Status LED Ring Relay Status LED SLIC 4 Ring Relay Status LED Ground Key Det. Ground Key Det. SLIC 3SLIC 1 Operating Mode Off-Hook Det. Ground Key Det. Operating Mode Off-Hook Det. Ground Key Det. CHCLK1 CHCLK2 43 9 33 16 1534 Microcontroller 2466_220
Hardware Reference Manual 34 2001-02-20 Table 24 Signaling Interface: Pins and Functions for SLIC Interfaces
5.3.2 Debouncing Functions and Interrupt Generation
All signaling inputs are sampled at programmable intervals (Field N in register XR4). If all the inputs assigned to one channel-pair (1&2 or 3&4) have been stable for two subsequent samples their values are stored in the signaling registers and the associated interrupt output (INT12 or INT34) is set high. Refer to the Programmer’s Reference Manual for further details on this function.
5.3.3 Clock Output Signals
Two programmable Chopper Clock Output signals are provided by the PEB 2466: CHCLK1 (Pin 33) is configured in register XR4.Field T (bits XR4.3 to XR4.0) CHCLK2 (Pin 16) is configured in register XR5.CHCLK2 (bits XR5.3 and XR5.2) Both Chopper Clock Output signals are only available if a valid Master Clock signal is applied to pin MCLK. CHCLK2 = 16,384 kHz: Requires at least one channel in POWER-UP state. Symbol Pin Function Ch1 Ch2 Ch3 Ch4 SIx_0 36 47 2 13 Signaling Input Channel x, Pin 0. SIx_1 35 48 1 14 Signaling Input Channel x, Pin 1. SOx_0 41 42 7 8 Signaling Output, Channel x, Pin 0. SOx_1 40 43 6 9 Signaling Output, Channel x, Pin 1. SBx_0 39 44 5 10 Bi-directional Signaling, Channel x, Pin 0. SBx_1 38 45 4 11 Bi-directional Signaling, Channel x, Pin 1. SBx_2 37 46 3 12 Bi-directional Signaling, Channel x, Pin 2. INT12 34 - Interrupt Output, Channels 1+2, active high. INT34 - 15 Interrupt Output, Channels 3+4, active high.
Hardware Reference Manual 35 2001-02-20 Table 25 Clock Programming
5.4 Serial Microcontroller Interface
The Serial Microcontroller Interface is used to access the SICOFI ®4-µC’s internal registers and the Coefficient RAM (CRAM). The Serial Microcontroller Interface consists of four pins: two data pins (DIN, DOUT), one clock pin (DCLK) and one pin for chip select (CS#). If DIN and DOUT are strapped together, only three microcontroller I/O pins are required to build this interface. Figure 20 Serial Microcontroller Interface CHCLK1 CHCLK2 XR4.Field T Output (Pin 33) XR5.CHCLK2 Output (Pin 16)
0000 High level (+5V) 00 High level (+5V)
Clock period = T *2ms (min. 2 ms, max. 28 ms) 01 512 kHz signal 10 256 kHz signal
1111 Low level (0V) 11 16384 kHz signal
SICOFI4-µC Microcontroller Out InOut Out CS# DOUTDCLK DIN SICOFI4-µC Microcontroller Out Out I/O CS# DOUTDCLK DIN Configuration A: Separate DIN, DOUT Configuration B: Bi-Directional Data 2466_221
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5.4.1 Serial Microcontroller Interface Pins
Table 26 Serial Microcontroller Interface: Pins and Functions
5.4.2 Write Access
Following a falling edge of CS#, the first eight bits received on DIN specify the type of command. The data bytes following a write command are stored in the selected configuration registers or the selected part of the Coefficient RAM. The number of data bytes depends on the type of command. After every command CS# must be set to ’1’. Figure 21 Example for a Two-Byte Write Access
5.4.3 Read Access
If the first eight bits received via DIN represent a read command, the SICOFI ®4-µC will initiate its response via DOUT. An identification byte (81 H) is followed by the requested number of data bytes (contents of configuration registers or contents of the CRAM). During execution of a read command, the device will ignore data on DIN. After every command CS# must be set to ’1’. Symbol Pin Function CS# 17 Chip Select, enable to read or write data, active low. DCLK 18 Data Clock, shifts data from or to device; max. clock rate is 8192 kHz. DIN 19 Control Data Input; sampled with rising edge of DCLK. DOUT 20 Control Data Output; bits are shifted with the falling edge of DCLK; DOUT is in high impedance state when no data is transmitted from the SICOFI ®4-µC. 76543210 0 12345670 1234567DIN DOUT DCLK CS# Write Command Data Byte 1 Data Byte 2 High 'Z' 2466_222
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5.4.4 Three-Wire Access
DIN and DOUT may be strapped together and connected to a single I/O pin of the microcontroller. The interface remains fully functional with only three wire connections. After every command CS# must be set to ’1’. Figure 24 Bi-Directional Data Signal: DIN and DOUT Strapped Together DATA DCLK CS# Read Command Identification 81 H High 'Z' Data Byte 1 76543210 76543210 76543210 2466_225
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6 Programming Overview
The transmission characteristics and interfaces of the PEB 2466 can be adapted to various environments. Configuring the functional blocks and programming the digital filter behavior is accomplished by loading values to the Configuration Registers and the Coefficient RAM (CRAM). Software utilities are available to determine the appropriate register and CRAM values (see Programmer’s Reference Manual).
6.1 Programming Overview
The SICOFI®4-µC has eight Common Configuration Registers (XR0 to XR7). Settings in these registers affect all four channels. Each of the four channels has six Channel-Specific Configuration Registers (CR0 to CR5). Settings in these registers affect only the designated channel. The filters of each channel are individually programmable through channel-specific coefficients in CRAM. There are four global sets of TH Filter coefficients that can be assigned to any channel.
6.1.1 Register Model
Channel-specific and Common Configuration Registers and coefficients are shown in Table 27. Table 27 Register Model Channel 1 Channel 2 Channel 3 Channel 4 Type XR0 to XR7 (8 bytes) common CR0 to CR5 (6 bytes) CR0 to CR5 (6 bytes) CR0 to CR5 (6 bytes) CR0 to CR5 (6 bytes) channel-specific IM, FRR, FRX, AR, AX, TG1, TG2 Coefficients (48 bytes) IM, FRR, FRX, AR, AX, TG1, TG2 Coefficients (48 bytes) IM, FRR, FRX, AR, AX, TG1, TG2 Coefficients (48 bytes) IM, FRR, FRX, AR, AX, TG1, TG2 Coefficients (48 bytes) TH Coefficient Set 1 (24 bytes) one coefficient set per channel TH Coefficient Set 2 (24 bytes) TH Coefficient Set 3 (24 bytes) TH Coefficient Set 4 (24 bytes)
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6.1.2 Register Maps
Table 28 Read Access to Common Configuration Register (XR) Map Table 29 Write Access to Common Configuration Register (XR) Map Table 30 Channel-Specific Configuration Register (CR) Map (Read & Write) B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 XR0 SI4_1 SI4_0 SI3_1 SI3_0 SI2_1 SI2_0 SI1_1 SI1_0 XR1 SB4_1 SB4_0 SB3_1 SB3_0 SB2_1 SB2_0 SB1_1 SB1_0 XR2 PSB4_1 PSB4_0 PSB3_1 PSB3_0 PSB2_1 PSB2_0 PSB1_1 PSB1_0 XR3 SB4_2 SB3_2 SB2_2 SB1_2 PSB4_2 PSB3_2 PSB2_2 PSB1_2 XR4 Signal Debounce CHCLK1 XR5 MCLK-SEL CRSH-A CRSH-B CHCLK2 Version XR6 C-Mode X-S R-S DRV_0 Shift PCM-OFFSET XR7 O F 7O F 6O F 5O F 4O F 3O F 2O F 1O F 0 B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 XR0 SO4_1 SO4_0 SO3_1 SO3_0 SO2_1 SO2_0 SO1_1 SO1_0 XR1 SB4_1 SB4_0 SB3_1 SB3_0 SB2_1 SB2_0 SB1_1 SB1_0 XR2 PSB4_1 PSB4_0 PSB3_1 PSB3_0 PSB2_1 PSB2_0 PSB1_1 PSB1_0 XR3 SB4_2 SB3_2 SB2_2 SB1_2 PSB4_2 PSB3_2 PSB2_2 PSB1_2 XR4 Signal Debounce CHCLK1 XR5 MCLK-SEL CRSH-A CRSH-B CHCLK2 Version XR6 C-Mode X-S R-S DRV_0 Shift PCM-OFFSET XR7 O F 7O F 6O F 5O F 4O F 3O F 2O F 1O F 0 B i t 7B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 CR0 TH IM/R1 FRX FRR AX AR TH-SEL CR1 ETG2 ETG1 PTG2 PTG1 LAW 0 0 PU CR2 COT/R 0 IDR LM LMR V+T CR3 TEST-Loops AGX AGR D-HPX D-HPR CR4 R-way RS6 RS5 RS4 RS3 RS2 RS1 RS0 CR5 X-way XS6 XS5 XS4 XS3 XS2 XS1 XS0
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6.1.3 CRAM Structure
Coefficient RAM (CRAM) is used to store the individual coefficients calculated for each channel. The coefficients can be written and read through the Microcontroller Interface. The IM, FRX, FRR, AX, AR, TG1, TG2, and TH coefficients are accessed through the Coefficient Operation (COP) Command Sequences which include the channel address (see Programmer’s Reference Manual Chapter 6.5). Channel-specific coefficients always belong to their designated channel. Common coefficients (TH) can be assigned to any of the four channels through field TH-SEL in CR0 (see Figure 25). Figure 25 Channel-Specific and Common Coefficients Table 31 Coefficient RAM (CRAM) Structure per Channel IM Part 1 8 Coefficient Bytes IM Part 2 8 Coefficient Bytes FRX 8 Coefficient Bytes FRR 8 Coefficient Bytes AX 4 Coefficient Bytes AR 4 Coefficient Bytes TG1 4 Coefficient Bytes TG2 4 Coefficient Bytes Common Coefficients Channel Specific Coefficients Set 1 TH Part 1, 2, 3 Set 2 TH Part 1, 2, 3 Set 3 TH Part 1, 2, 3 Set 4 TH Part 1, 2, 3 Channel Specific Coefficients Channel 1 IM Part 1 & 2, FRX, FRR, AX, AR, TG1, TG2 Channel 2 IM Part 1 & 2, FRX, FRR, AX, AR, TG1, TG2 Channel 3 IM Part 1 & 2, FRX, FRR, AX, AR, TG1, TG2 Channel 4 IM Part 1 & 2, FRX, FRR, AX, AR, TG1, TG2 2466_226
Hardware Reference Manual 42 2001-02-20 Table 32 Coefficient RAM (CRAM) Structure per Set
6.2 Types of Commands and Data Bytes
Coefficients and register contents are programmed and accessed through command sequences via the Microcontroller Interface. There are three types of command sequences: Extended Operation (XOP) for access to the Common Configuration Registers (XR0 to XR7) including the Control Registers for the signaling interface. Status Operation (SOP) for access to the Channel-Specific Registers (CR0 to CR5), e.g. enabling and disabling of filters, time slot assignment, and test loops. Coefficient Operation (COP) for access to the CRAM structures. Coefficients can be written to the SICOFI®4-µC, and also read back. Table 33 Types of Commands and Data Bytes. With the first byte received via DIN, a command type is selected through bits 3 and 4. A two-bit address field (AD) in the COP and SOP commands allows access to the channel-specific structures (CRAM and CR registers). Since the XR Registers are common for all channels, no address field is required within the XOP command byte. All three commands allow read and write access, which is indicated by bit 5 (RW). The bit fields LSEL and CODE specify the type and the length of data that follows the command. TH Part 1 8 Coefficient Bytes TH Part 2 8 Coefficient Bytes TH Part 3 8 Coefficient Bytes 76543210 XOP RST 0 RW 11 LSEL SOP AD RW 10 LSEL COP AD RW 0 CODE
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7 Application Hints
7.1 Support Tools
7.1.1 Development Board
The Evaluation Package EASY 2466 includes the following hardware: One SICOFI ®4-µC Evaluation Board STUT 2466 with connectors for four optional SLIC daughter cards and BNC connectors to a PCM backplane. One microcontroller board EVC50x with RS-232 interface that translates data from a PC to SICOFI®4-µC format. Two SLIC Babyboards STUT 5502 with HARRIS SLIC HC 5502 mounted. The QSICOS software enables the calculation of the coefficients and the download of the setup file to the evaluation board. This setup allows measurements and optimization of the actual behavior of a complete transmission system. The EASY 2466 evaluation system connects directly to industry-standard test equipment. Figure 26 Development System with STUT 2466 Evaluation Board PCM in PCM out Clock out 4 wire in 2 wire 4 wire out SLC2 SLC1 SLC4 SLC3 out in in/ out in/ out ST2 ST1 SICOFI2/4 -µC/-TE PCM PCLK FSC Evaluation Board EVC50x sw1 Power Supply reset EVC SLIC (STUT5502) ST3 COM 1 DC Loop-Holding circuit FSC in tip ring PC SICOFIx -µC/-TE Eval. Board V1.4 STUT 2466 PCM-4
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7.2 Guidelines for Board Design
7.2.1 Filter Capacitors
For high frequency noise rejection, use 100 nF SMD ceramic capacitors on pins VDDA12, VDDA34 and VDDREF and connect to GND. Additional 2.2 µF tantalum capacitors are recommended. Use one 100 nF SMD ceramic capacitor on pin VDDD and connect to GNDD. Use a 1 µF – 10 µF tantalum capacitor from +5 V supply to GND (central blocking). Note: All blocking capacitors MUST be placed as close as possible to the SICOFI®4-µC pins. Figure 27 SICOFI ®4-µC Test Circuit Configuration SICOFI4-µC PEB 2466-H PCLK FSC DRB DXB TCB# DRA DXA TCA# VDDD RESET# MCLK GNDD DOUT DIN DCLK CS#VIN4 VIN3 VIN2 GNDA4 VOUT4 VDDA34 VOUT3 GNDA3 VDDREF VREF GNDA2 VOUT2 VDDA12 VOUT1 GNDA1 VIN1 CHCLK1 INT12 SI1_1 SI1_0 SB1_2 SB1_1 SB1_0 SO1_1 SO1_0 SO2_0 SO2_1 SB2_0 SB2_1 SB2_2 SI2_0 SI2_1 CHCLK2 INT34 SI4_1 SI4_0 SB4_2 SB4_1 SB4_0 SO4_1 SO4_0 SO3_0 SO3_1 SB3_0 SB3_1 SB3_2 SI3_0 SI3_1 1-10µF100nF 10K PCM Interface Micro- controller Interface Signaling Interface, Channels 1&2 Signaling Interface, Channels 3&4 Analog Interface 2.2µF 100nF 11 6 3348 5 x 680K5 x 680K 5 x 680K 5 x 680K 1µF 10µ F 2.2µF 100nF 1µF 220nF 2.2µF 100nF 2.2µF 100nF 1µF 10µF 2.2µF 100nF 1µF 10µF 10µF 4.7K 4.7K 2466_228
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7.3 Proposal for SICOFI ®4-µC Board Design
For a new layout design it is recommended to use a separate ground-layer which gives the possibilty to connect all ground-pins of the SICOFI ®4-µC (GNDA and GNDD) low- ohmic together. Furthermore, an optimum board layout should follow these recommendations Separate all digital supply lines from analog supply lines as far as possible Applying the standard practice regarding blocking capacitors is recommended Place all SLIC circuits as close as possible to the Vinx/Voutx pins of the SICOFI Separate all analog circuitry (especially SLIC and Vinx/Voutx) as far as possible from any digital signal source (esp. clock signals) Figure 28 Proposal for a ground concept VDD is the grey colored layer and the Ground-plane is the black colored layer. The Ground-plane should be on both sides of the board on the top and on the ground layer. 49 51 5352 55 56 5857 60 6261 64 100 nF GND 1-10 F Tantal VDD µ PEB 2466 H Ground- plane DDD GNDD V 1718192024 22232526272829303132 GN DA2 GNDA3 GND A4 VDDA12 GNDA1 VDDREF VREF Connector Connector next to the connector pins DDA34V Ceramic nF Ceramic nF100 nF100 nF220 635954 Ceramic 100 Ceramic The ground-plane should be used for shielding SICOFI4-µC V2.2
Electrical Characteristics and Timing Diagrams Hardware Reference Manual 46 2001-02-20
8 Electrical Characteristics and Timing Diagrams
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
8.1 Absolute Maximum Ratings
Conditionmin. max. VDD referred to GNDD –0.3 7.0 V GNDA to GNDD –0.6 0.6 V Analog input and output voltage Referred to VDD = 5 V; Referred to GNDA = 0 V –5.3 –0.3 0.3 5.3 V V All digital input voltages Referred to GNDD = 0 V; (VDD =5 V ) Referred to VDD = 5 V; (GNDD = 0 V) –0.3 –5.3 5.3 0.3 V V DC input and output current at any input or output pin (free from latch-up) 10 mA Storage temperature TSTG –60 125 °C Ambient temperature under bias TA –10 80 °C Power dissipation (package) PD 1W
Electrical Characteristics and Timing Diagrams Hardware Reference Manual 47 2001-02-20
8.2 Operating Range
VDD = 5 V ±5%; GNDD = 0 V; GNDA = 0 V; TA = 0 °C to +70 °C (PEF 2466: -40 °C to +85 °C) Parameter Symbol Limit Values Unit Test Condition min. typ. max. VDD supply current: IDD FSC = 8 kHz, Standby (PEB 2466) 0.5 1.0 mA PCLK = MCLK = Standby (PEF 2466) 0.5 1.5 mA 2.048 MHz, 1 channel operating 14 25 mA no loads, 2 channels operating 18 30 mA PCM idle codes, 3 channels operating 22 35 mA V IN= 0V. 4 channels operating 26 40 mA Power supply rejection ratio (either direction) PSRR 30 dB Ripple: sine wave
1014 Hz, 70 mVrms,
on every supply pin, AGX=AGR=AX=AR=0dB (see Chapter 4.2.4)
8.3 Digital Interface
VDD = 5 V ± 5%; GNDD = 0 V; GNDA = 0 V TA = 0 °C to +70 °C (PEF 2466: -40 °C to +85 °C); Parameter Symbol Limit Values Unit Test Condition min. max. Input voltages: Low level VIL –0.3 0.8 V High level VIH 2.0 V Output voltages: Low level VOL 0.45 V IOL = – 2m A Low level VOL 0.8 V IOL = – 5m A High level VOH 4.4 V IOH = 0.4 mA High level VOH 4.0 V IOH = 2 mA High level VOH 2.4 V IOH = 5 mA Input leakage current VIL ±1µ A –0.3 ≤ VIN ≤ VDD
Electrical Characteristics and Timing Diagrams Hardware Reference Manual 48 2001-02-20
8.4.1 Coupling Capacitors at the Analog Interface
Coupling capacitors are required on pins VIN and VOUT. The recommended value for VIN is >39 nF. The required value for the VOUT capacitor depends on the input impedance of the SLIC (see Figure 16 in Chapter 5.1).
8.5 Reset Timing
To reset the SICOFI®4-µC to Reset State, logic low pulses applied to pin RESET# must be below 1.2 V (TTL-Schmitt-Trigger Input) and must persist longer than 3 µs. Note: Spikes shorter than 1 µs will be ignored.
8.4 Analog Interface
VDD = 5 V ±5%; GNDD = 0 V; GNDA = 0 V; TA = 0 °C to +70 °C (PEF 2466: -40 °C to +85 °C) Parameter Symbol Limit Values Unit Test Condition min. typ. max. Input resistance PEF 2466 PEB 2466 Ri 160 160 270 270 500 380 kΩ kΩ 0 ≤ VIN ≤ VDD Output resistance RO 0.25 Ω Output load RL CL 300 Ω pF Input leakage current IIL ±0.1 ±1.0 µA 0 ≤ VIN ≤ VDD Input offset voltage VIO ±50 mV Output offset voltage VOO ±50 mV Input voltage range (AC) VIN ±2.223 V
Electrical Characteristics and Timing Diagrams Hardware Reference Manual 49 2001-02-20
8.6 PCM-Interface Timing
8.6.1 Single Clocking Mode
Figure 29 PCM Interface Timing in Single Clocking Mode Parameter Symbol Limit Values Unit min. typ. max. Period of PCLK tPCLK 1/8192 1/128 ms PCLK high time tPCLKh 0.4*tPCLK tPCLK/2 0.6* tPCLK µs Period FSC tFSC 125 µs FSC setup time tFSC_s 10 50 ns FSC hold time tFSC_h 40 50 ns DRA/B setup time tDR_s 10 50 ns DRA/B hold time tDR_h 10 50 ns DXA/B delay time 1) 1) Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by external components CLoad and RPullup.: t C_Load = 0.4ns*C Load/pF tC*R = R Pullup*CLoad; RPullup>1.5kΩ tdDX 25 tdDX_min + tC_Load ns DXA/B delay time to high Z tdDXhz 25 50 ns TCA#/TCB# delay time on tdTCon 25 tdTCon_min + tC_Load ns TCA#/TCB# delay time off tdTCoff 25 tdTCoff_min + tC*R ns t PCLK PCLK FSC DRA/B DXA/B FSC_St PCLKht High Imp. t DR_S DR_Ht t dDX dDXhzt tFSC_H FSCt TCA#/TCB# dTCont t dTCoff 50% 2466_229
Electrical Characteristics and Timing Diagrams Hardware Reference Manual 50 2001-02-20
8.6.2 Double Clocking Mode
Figure 30 PCM Interface Timing in Double Clocking Mode Parameter Symbol Limit Values Unit min. typ. max. Period of PCLK tPCLK 1/8192 1/256 ms PCLK high time tPCLKh 0.4*tPCLK tPCLK/2 0.6* tPCLK µs Period FSC tFSC 125 µs FSC setup time tFSC_s 10 50 ns FSC hold time tFSC_h 40 50 ns DRA/B setup time tDR_s 10 50 ns DRA/B hold time tDR_h 10 50 ns DXA/B delay time 1) 1) Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by external components CLoad and RPullup.: t C_Load = 0.4ns*C Load/pF, tC*R = R Pullup*CLoad; RPullup>1.5kΩ tdDX 25 tdDX_min + tC_Load ns DXA/B delay time to high Z tdDXhz 25 50 ns TCA#/TCB# delay time on tdTCon 25 tdTCon_min + tC_Load ns TCA#/TCB# delay time off tdTCoff 25 tdTCoff_min + tC*R ns t PCLK PCLK FSC DRA/B DXA/B FSC_St PCLKht High Imp. t DR_S DR_Ht tdDX dDXhzt tFSC_H FSCt TCA#/TCB# dTCont tdDTCoff 50% 2466_230
Electrical Characteristics and Timing Diagrams Hardware Reference Manual 51 2001-02-20
8.7 Microcontroller Interface Timing
Figure 31 Timing of the Microcontroller Interface Parameter Symbol Limit Values Unit min. typ. max. Period of DCLK tDCLK 1/8192 ms DCLK high time tDCLKh 0.4*tDCLK tDCLK/2 0.6* tDCLK µs CS# setup time tCS_s 10 50 ns CS# hold time tCS_h 30 50 ns DIN setup time tDIN_s 10 50 ns DIN hold time tDIN_h 10 50 ns DOUT delay time 1) 1) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing, and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load). tdDOUT 30 tdDOUT_min + tC_Load ns DOUT delay time to high Z tdDOUThz 30 50 ns DCLK CS# DIN DOUT CS_St High Imp. t DIN_S DIN_Ht t dDOUT dDOUThz t t DCLKhDCLKt t CS_h 50% 2466_231
Electrical Characteristics and Timing Diagrams Hardware Reference Manual 52 2001-02-20
8.8 Signaling Interface Timing
8.8.1 Timing from the µC Interface to the SO/SB-pins
Figure 32 Signaling Output Timing (data downstream)
8.8.2 Timing from the SI/SB-pins to the µC Interface
The register update and interrupt behavior resulting from signaling input changes (data upstream – pins SI and SB, if programmed as signaling inputs) depend on internal sampling clocks, counters and register settings. See Chapter 5.3.2 for a functional description. Parameter Symbol Limit Values Unit min. typ. max. SO/SB delay time 1) 1) All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing, and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load). tdSout 30 tdSout_min+ tC_Load ns SB to ‘Z’ - time tdSBZ 40 100 ns SB to ‘drive’-time tdSBD 40 tdSBD_min+ tC_Load ns DCLK Bit 2DIN SO/SB Output Old Value New Value SB (Output Input) Output)(Input SB dSBDt High Imp. tdSBZ tdSout High Imp. Bit 1 Bit 0 2466_232
Hardware Reference Manual 53 2001-02-20 9T e s t M o d e s Each SICOFI®4-µC channel has four test loops that feed the analog input signal back to the analog output (analog test loops), and five test loops that feed the PCM input signal back to the PCM output. Note: The signal path can also be cut off at two different points per receive and transmit direction.
9.1 Analog Loops
The four analog loops feed signals from the transmit path back into the receive path. Figure 33 shows the locations of the analog loops. Figure 33 Analog Loops Table 34 Analog Loop Programming in Register CR3, Bits 7 to 4 Test-Loops Analog Loops (CR3.7 = 0) 0000 All loops are disabled (normal operation). 0001 ALB-PFI Analog Loop Back via PREFI-POFI is selected. 0011 ALB-4M Analog Loop Back via 4 MHz is selected.
0100 ALB-PCM Analog Loop Back via 8 kHz (PCM) is selected and in all
channels active. (required slope setting in XR6.6, XR6.5 = 00 or 11). 0101 ALB-8K Analog Loop Back via 8 kHz (linear) is selected. Receive Path Transmit Path Analog Output Analog Input PCM Input PCM Output IM1 TH Digital Gain 2 Digital Gain 2 IM2 Frequency Response Digital Gain 1 Frequency Response Digital Gain 1 HPX HPR ADC DAC AGX AGR CMP EXP ALB-PFI ALB-4M ALB-8K ALB-PCM 2466_233
Hardware Reference Manual 54 2001-02-20
9.2 Digital Loops
The digital loops feed signals from the receive path back to the transmit path. There are five digital loops, which are shown in Figure 34. Figure 34 Digital Loops Table 35 Digital Loop Programming in Register CR3, Bits 7 to 4 Test-Loops Digital Loops (CR3.7 = 1) 1000 DLB-ANA Digital Loop Back via analog port is selected. 1001 DLB-4M Digital Loop Back via 4 MHz is selected. 1100 DLB-128K Digital Loop Back via 128 kHz is selected. 1101 DLB-64K Digital Loop Back via 64 kHz is selected. 1111 DLB-PCM Digital Loop Back via PCM Registers is selected. Receive Path Transmit Path Analog Output Analog Input PCM Input PCM Output IM1 TH Digital Gain 2 Digital Gain 2 DLB-PCM DLB-64K DLB-ANA DLB-4M IM2 DLB-128K Frequency Response Digital Gain 1 Frequency Response Digital Gain 1 HPX HPR ADC DAC AGX AGR CMP EXP 2466_234
Hardware Reference Manual 55 2001-02-20
9.3 Cut-Off ’s
The transmit path and the receive path can be cut off at two locations each. Figure 35 shows the locations in the signal paths. Figure 35 Cut-Off ’s Table 36 Cut-Off Programming in Register CR2, Bits 7 to 5. COT/R Cut-Off ’s in the Transmit and the Receive Paths 000 All Cut-offs disabled (Normal Operation). 001 COT16 Cut Off Transmit path at 16 kHz (input of TH-Filter).
010 COT8 Cut Off Transmit path at 8 kHz (shortens the input of the
compressor unit to ground, resulting in PCM idle codes in the transmit time slot). 101 COR4M Cut Off Receive path at 4 MHz (POFI-output). 110 COR64 Cut Off Receive path at 64 kHz (IM-filter input). Receive Path Transmit Path Analog Output Analog Input PCM Input PCM Output IM1 TH Digital Gain 2 Digital Gain 2 IM2 Frequency Response Digital Gain 1 Frequency Response Digital Gain 1 HPX HPR ADC DAC AGX AGR CMP EXP COT8COT16 COR64 COR4M 2466_235
Hardware Reference Manual 56 2001-02-20 P-MQFP-64 (Plastic Metric Quad Flat Package) GPM05250 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mmSMD = Surface Mounted Device
Hardware Reference Manual 57 2001-02-20
11 Glossary
ADC Analog-to-Digital Converter CMOS Complementary Metal Oxide Semiconductor CO Central Office COT Central Office Terminal CRAM Coefficient RAM DAC Digital-to-Analog Converter DC Direct Current DLC Digital Loop Carrier DSP Digital Signal Processor DTMF Dual Tone Multi Frequency FIR Finite Impulse Response FTTC Fiber-To-The-Curb IIR Infinite Impulse Response IOM-2 ISDN-Oriented Modular 2nd Generation ITU International Telecommunication Union ITU-T International Telecommunication Union-Telecommunication Standardization Sector (formerly CCITT) PBX Private Branch Exchange PCM Pulse Code Modulation PSTN Public Switched Telephone Network PTT Post Telephone Telegraph QSICOS Quad SICOFI Coefficient Software RITL Radio-In-The-Loop RT Remote Terminal SICOFI Signal Processor Codec Filter SLIC Subscriber Line Interface Circuit t/r tip/ring
Hardware Reference Manual 58 2001-02-20 Index Symbols Numerics A B C Channel-specific registers . 11, 12, 39, 40 Coefficient calculation & Coefficient Operation (COP) command . . . 42 Common configuration registers . . 11, 39, 40
Hardware Reference Manual 59 2001-02-20 D Digital switching & transmission system . . . 2 E Extended Operation (XOP) command . . .42 F Frequency response corrections . . 10, 16
Hardware Reference Manual 60 2001-02-20 G H I K L M Microcontroller Interface . . 10, 35, 41, 42 N
Hardware Reference Manual 61 2001-02-20 O P Q R
Hardware Reference Manual 62 2001-02-20 S Serial Microcontroller Interface . . . 10, 27, 35 Status Operation (SOP) command . . . 42 Subscriber line interface circuits . . . 2, 10, 27 Supervision and signaling functions . . 32 T
Hardware Reference Manual 63 2001-02-20 Transhybrid balancing . . 3, 10, 11, 16, 26 Transmission characteristics. . . 10, 14, 16, 39 V W X
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