PEB22504

PEB22504 INFINEON | Alldatasheet

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QuadLIU™ Quad Line Interface Unit for E1 ⁄T1 ⁄J1 PEB 22504 Version 1.1 Data Sheet, DS4, February 2001 Datacom Never stop thinking.

Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 München, Germany © Infineon Technologies AG 2/19/01. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

QuadLIU™ Quad Line Interface Unit for E1 ⁄T1 ⁄J1 PEB 22504 Version 1.1 Data Sheet, DS4, February 2001 Never stop thinking.

For questions on technology, delivery, and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com PEB 22504 Previous Version: Data Sheet, DS3, 2000-09 Page Subjects (major changes since last revision)

5 V supply mode is not supported

60 Global Configuration Register

99 Power Supply Range

121 External Line Frontend Calculator

100 Transmiter output current

101 Receiver sensitivity

QuadLIU V1.1 Data Sheet 5 2001-02 Preface The Quad Line Interface Unit PEB 22504 (QuadLIU™) is a flexible line interface unit for a wide area of telecommunication and data communication applications. The device contains four complete channels on one chip to save board space and power consumption. This document provides complete reference information to configure E1, T1, and J1 applications. Organization of this Document This Data Sheet is organized as follows:  Chapter 1, Overview Gives a general description of the product and its family, lists the key features, and presents some typical applications.  Chapter 2, Pin Descriptions Lists pin locations with associated signals, categorizes signals according to function, and describes signals.  Chapter 3, Functional Description This chapter describes the functional blocks and principal operation modes.  Chapter 4, Interface Description Describes the various device interfaces.  Chapter 5, Operational Description Shows the operation modes and how they are to be initialized.  Chapter 6, Register Description Gives a detailed description of all implemented registers and how to use them in different applications/configurations.  Chapter 7, Electrical Characteristics Specifies maximum ratings, DC and AC characteristics.  Chapter 8, Package Outlines Shows the mechanical values of the device package.  Chapter 9, Appendix Gives an example for overvoltage protection and information about application notes and other support.

QuadLIU V1.1 Data Sheet 6 2001-02  Chapter 10, Glossary  Index Related Documentation This document refers to the following international standards (in alphabetical/numerical order): ANSI/EIA-656 ( page 119) ANSI T1.102 ( page 115) ANSI T1.231 ( page 71,page 89,page 90) ANSI T1.403 ( page 50,page 90) AT&T TR43802 ( page 40) AT&T TR62411 ( page 40,page 44,page 49) ESD Ass. Standard EOS/ESD-5.1-1993 (page 98) ETSI ETS 300 011 ( page 40) ETSI ETS 300 233 ( page 39,page 40,page 89) ETSI TBR12 ( page 40,page 42) ETSI TBR13 ( page 40,page 42) FCC68 ( page 47) IEEE 1149.1 ( page 33) ITU-T G.703 ( page 40) ITU-T G.736-739 ( page 40) ITU-T G.775 ( page 39,page 39,page 89,page 89) ITU-T G.823 ( page 40) ITU-T G.824 ( page 40) ITU-T I.431 ( page 40,page 42,page 44,page 47) MIL-Std. 883D ( page 98) Telcordia TR-NWT-1089 TR-TSY 009 ( page 40) TR-TSY 253 ( page 40) TR-TSY 499 ( page 40) UL 1459

QuadLIU V1.1 Data Sheet 7 2001-02 Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to com.docu_comments@infineon.com Please provide in thesubjectof your e-mail: device name (QuadLIU™), device number (PEB 22504), device version (Version 1.1), and in thebody of your e-mail: document type (Data Sheet), issue date (2001-02) and document revision number (DS4).

QuadLIU V1.1 Table of Contents Page Data Sheet 8 2001-02

QuadLIU V1.1 Table of Contents Page Data Sheet 9 2001-02

QuadLIU V1.1 List of Tables Page Data Sheet 11 2001-02

QuadLIU V1.1 Overview Data Sheet 12 2001-02

1 Overview

The QuadLIU™ PEB 22504 Quad Line Interface Unit is a device to connect four E1/T1/ J1 framer devices to four analog or digital lines. The line interface is selectable for long- haul or short-haul applications and fulfills the relevant standards for E1, T1, and J1 systems. The QuadLIU™ comes in a high-density P-TQFP-100-3 package (SMD) to save a significant amount of board space compared to a configuration using single line-interface circuits. Crystal-less jitter attenuation with only one master clock source further reduces the amount of required external components. Equipped with a flexible microcontroller interface, it fits to any control processor environment.

Quad Line Interface Unit for E1⁄T1⁄J1 QuadLIU™ PEB 22504 Version 1.1 CMOS Type Package PEB 22504 P-TQFP-100-3

1.1 Features

 H igh-density generic interface for all E1/T1/J1

applications

 Quad analog receive and transmit circuitry for long- and short-haul applications  Clock and data recovery using an integrated digital phase-locked loop  Programmable transmit pulse shapes for E1, T1 and J1 signals  Maximum line attenuation up to -36 dB at 1024 kH z( E 1 ) and up to -36 dB at 772 kH z( T 1 / J 1 )  Noise- and crosstalk-filter, line attenuation status  Programmable Line Build-Out for CSU signals according to ANSI T1.403 and FCC68 0dB, -7.5dB, -15dB, -22.5 dB  Low transmitter output impedances for high transmit return loss  Tristate function of the analog transmit line outputs  Transmit line monitor protecting the device from damage  Jitter specifications of ITU-T I.431 , G.703 , G.736, G.823, ETS 300011, TBR12/13 and AT&T TR62411 met  Tolerates more than 0.4 UI high frequency input jitter  Crystal-less wander and jitter attenuation/compensation  Flexible master clock frequency in the range of 1.02 to 20 MH z  Power-down function per channel  Dual- or single-rail digital inputs and outputs to the framer interface  Unipolar CMI for interfacing fiber-optical transmission routes  Selectable line codes (H DB3, B8ZS, AMI with zero code suppression)  Loss-of-signal indication with programmable thresholds according to ITU-T G.775, ETS300233, ANSI T1. 403 and T1.231  Clock generator for jitter-free system/transmit clocks per channel  Local loop, remote loop and digital loop back for diagnostic purposes

QuadLIU V1.1 Overview Data Sheet 14 2001-02  Alarm and performance monitoring per second  Two 16-bit counters for code violations and PRBS bit errors  Insertion and extraction of Alarm Indication Signals (AIS)  Elastic store for receive or transmit clock wander and jitter compensation  Controlled slip capability and slip indication  Programmable elastic buffer size: 256 bits/128 bits/64 bits/32 bits/bypass  Programmable in-band loop code detection and generation according to TR 62411  Pseudo-Random Bit Sequence (PRBS) generator and monitor  Flexible software controlled device configuration Microprocessor Interface Mode  8-bit microprocessor bus interface (Intel or Motorola type)  All registers directly accessible  Multiplexed and non-multiplexed address bus operations  H ardware and software reset options  One-second timer General  Boundary scan standard IEEE 1149.1  P-TQFP-100-3 package (body size 14 mm× 14 mm)  Single power supply: 3.3 V  Temperature range: -40°C to+85°C  Low power device, typical power consumption 100 mW per channel  Wireless Basestations  ATM and frame relay gateways  CSUs, DSUs  Internet access equipment  LAN/WAN Router  ISDN-PRI, PABX  Digital Access Cross-connect Systems (DACS) S D H /SONET ADD/DROP Multiplexer

QuadLIU V1.1 Overview Data Sheet 15 2001-02

1.2 Logic Symbol

RCL K(1-4) RDOP(1-4) RDON(1-4) TCL K(1-4) XDIP(1-4) XDIN/TRIST(1-4) MFP(1-4) FSC SYNC VDDR (1-4) VSSR (1-4) RL1(1-4) RL2(1-4) V DD X(1-4) VSS X(1-4) XL1(1-4) XL2(1-4) TDI TMS TC K TRS TDO VDD (1-5) VSS (1-5) MCL K RES MODE A(0-6) D(0-7) ALE RD/DS WR/RW CS INT F0021

QuadLIU V1.1 Overview Data Sheet 16 2001-02

1.3 Typical Applications

Figure 2shows a multiple link application using the QuadLIU™.Figure 3shows a repeater application. Figure 2 QuadLIU Application F0195 QuadLIUTM PEB 22504 Framer ASIC Microprocessor System H ighway 4xE 1 / T 1 / J 1 Receive & Transmit

QuadLIU V1.1 Overview Data Sheet 17 2001-02 Figure 3 QuadLIU Repeater Application F0069 QuadLIUTM RL1 RL2 RDOP RDON XL1 XL2 XDIP XDIN Bidirectional Line#1 RL1 RL2 XL1 XL2 Bidirectional Line#2 RDOP RDON XDIP XDIN RCL K TCL K TCL K RCL K

QuadLIU V1.1 Pin Descriptions Data Sheet 18 2001-02

2 Pin Descriptions

2.1 Pin Diagram

Figure 4 Pin Configuration F0063 VSS X 5155 100 1 5 10 15 20 XL1.1 TMS TDI TRS VSS MCL K VDD SYNC FSC RES VSSR RL2.1 RL1.1/ROID1 VDDR XL2.1 VDD X RL2.2 VSSR TDO TC K RL1.2/ROID2 VDDR XL2.2 VDD X XL1.2 MFP1 RDOP1 RDON1 RCL K1 VDD VSS MFP2 RDOP2 RDON2 RCL K2 RD/DS WR/RW CS MFP3 RDOP3 RDON3 RCL K3 V DD VSS MFP4 RDOP4 RDON4 RCL K4 V SS X XL1.3 VDD X XL2.3 VDDR RL1.3/ROID3 RL2.3 V SSR MODE VDD VSS V SSR RL2.4 RL1.4/ROID4 V DDR XL2.4 VDD X XL1.4 VSS X TCL K4 XDIN4/TRIST4 XDIP4 TCL K3 XDIN3/TRIST3 XDIP3 TCL K2 XDIN2/TRIST2 XDIP2 TCL K1 XDIN1/TRIST1 XDIP1 VDD VSS INT ALE V SS X 60657075 QuadLIU TM PEB 22504 P-TQFP-100-3 (top view)

QuadLIU V1.1 Pin Descriptions Data Sheet 19 2001-02

2.2 Pin Definitions and Functions

Table 1 Control Pin Functions Pin No. Signal Input (I) Output (O) Supply (S) Function 93...99 A(0:6) I + PU Address Bus Selects one of the internal registers for read or write. 59...62 65...68 D(0:3) D(4:7) I/O+ PU Data Bus Eight-bit-wide bi-directional bus to be connected to the microprocessor data bus.

92 ALE I + PU Address Latch Enable

A high on this line indicates an address on the external address/data bus. The address information provided on lines A(6:0) is internally latched with the falling edge of ALE. This function allows the device to be connected directly to a multiplexed address/data bus. In this case, pins A(6:0) must be connected externally to the data bus pins. In case of demultiplexed mode, this pin has to be connected to V SS or VDD directly.

39 CS I+ PU Chip Select

A low signal selects the device for read/ write operations 37 RD I+ PU Read Enable/Data Strobe (Intel bus mode, MODE=low) This signal indicates a read operation. When the device is selected via CS ,t h eR D signal enables the bus drivers to output data from an internal register addressed via A(6:0) on to Data Bus. DS I+ PU Data Strobe (Motorola bus mode, MODE=high) This pin serves as input to control read/ write operations.

QuadLIU V1.1 Pin Descriptions Data Sheet 20 2001-02

38 WR I+ PU WRite Enable/Read-Write Select

(Intel bus mode, MODE=low) This signal indicates a write operation. When CS is active the device loads an internal register with data provided via the Data Bus. RW I+ PU Read/Write Enable (Motorola bus mode, MODE=high) This signal distinguishes between read and write operations.

91 INT O/oD INTerrupt Request

General interrupt request output for all interrupt sources. These interrupt sources can be masked individually via register IMR0/1. Interrupt status is reported via register CIS (Channel Interrupt Status) and ISR0/1. Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by using register IPC. Table 1 Control Pin Functions (cont’d) Pin No. Signal Input (I) Output (O) Supply (S) Function

QuadLIU V1.1 Pin Descriptions Data Sheet 21 2001-02 27, 33, 40, 46 MFP(1:4) Multi Function Port Depending on programming of bits LIM4.PC(2:0) this multifunction port provides different status information of the device as shown in this table below. MFP1 corresponds to channel 1, MFP4 to channel 4. LOS(1:4) O Loss-of-Signal Indication LIM4.PC(2:0)= 000 Active high, if a loss-of-signal alarm is detected. This signal corresponds directly to bit LSR0.LOS. ALOS(1:4) O Analog Loss-of-Signal Indication LIM4.PC(2:0)= 001 Active high, if the input level at RL1/2 drops below the programmed receive input threshold which is defined by register LIM2.RIL(2:0). PRBSS (1:4) O PRBS Synchronization Status LIM4.PC(2:0)= 010 Active high if the Pseudo-Random Bit Sequence (PRBS) synchronization is achieved. This signal corresponds directly to bit LSR0.PRBSS. BPV(1:4) O Bipolar Violation Indication LIM4.PC(2:0)= 011 Active high if a bipolar violation is detected. This signal corresponds directly to the increment signal of the code violation error counter. Table 1 Control Pin Functions (cont’d) Pin No. Signal Input (I) Output (O) Supply (S) Function

QuadLIU V1.1 Pin Descriptions Data Sheet 22 2001-02 27, 33, 40, 46 (cont’d) XLS(1:4) O Transmit Line Status LIM4.PC(2:0)= 100 Active high if the transmit line current limiter exceeds its maximum value. PinsXL1/2 are automatically tristated until the current drops below its maximum value ( or the “short” disappears). This signal corresponds directly to bit LSR1.XLS. AIS(1:4) O Alarm Indication Signal LIM4.PC(2:0)= 101 Active high if the alarm indication signal is detected. This signal corresponds directly to bit LSR0.AIS.

10 SYNC I + PU Clock Synchronization

Reference clock for the internal DCOs of the device. Selectable via register GCR.SSF(1:0). Active high pulse input. 9F S C O Frame Synchronization Pulse The synchronization pulse is active low for one 2.048 (E1)/1.544 MH z (T1/J1) cycle (pulse width= 488/648 ns). FSC is derived from the jitter attenuation DCO, which must be active for FSCoutput (8-kH zm a s t e r mode only, GCR.SSF(1:0)= 10). Active low pulse output. 87, 84, 81, 78 TRIST(1:4) I+ PU Transmit Line Tristate If the single-rail data stream is selected by bit LIM0.XC(1:0), a high at these pins set the appropriateXL1/2 outputs into tristate. TRISTi setsXL1.i/2.i of channel i into tristate, where i= 1t o4 . Table 1 Control Pin Functions (cont’d) Pin No. Signal Input (I) Output (O) Supply (S) Function

QuadLIU V1.1 Pin Descriptions Data Sheet 23 2001-02 Table 2 Signal Pin Functions Pin No. Signal Input (I) Output (O) Supply (S) Function 5, 21, 55, 71 RL1(1:4) I (analog) Line Receiver 1 (LIM1.ECMIR = 0, default) Analog input from the external transformer (receive bipolar ring). ROID(1:4) I Receive Optical Interface Data (LIM1.ECMIR = 1) CMI data received from fiber-optical interface with 2048 (E1)/ 1544 kbit/s (T1/ J1). An internal DPLL extracts the receive route clock from the incoming data pulse. The duty cycle of the receiving signal has to be closely to 50% . RL2 has to be connected to V SS or VDD . 6, 20, 56, 70 RL2(1:4) I (analog) Line Receiver 2 (LIM1.ECMIR = 0, default) Analog input from the external transformer (receive bipolar tip). 1, 25, 51, 75XL1(1:4) O (analog) Transmit Line 1(transmit bipolar ring) (LIM1.ECMIX= 0, default) Analog output to the external transformer. XOID(1:4) O (LIM1.ECMI X= 1) Single-ail CMI output 3, 23, 53, 73XL2 (1:4) O (analog) Transmit Line 2(transmit bipolar tip) (LIM1.ECMIX= 0, default) Analog output to the external transformer. If single-rail CMI output is selected (LIM1.ECMIX= 1), this pis is undefined and has to be left open.

QuadLIU V1.1 Pin Descriptions Data Sheet 24 2001-02 28, 34, 41, 47 RDOP(1:4) O Receive Data Output/Positive Received data at RL1/2 is sent on RDOP/ RDON in NR Z format to the framer interface. Clocking of data is done with the rising or falling edge of RCLK(1:4), selected by bit LIM4.RPE. RDOP/RDON are set low if a loss-of-signal alarm is detected. The source of the received data is selected by bit LIM2.RD(1:0). LIM2.RD(1:0)= 00: Data recovered by the DPLL is AMI/H DB3/B8 ZS decoded and output on RDOP;RDON is not defined. LIM2.RD(1:0)= 01: Dual-rail data recovered by the DPLL, not AMI/H DB3/ B8ZS decoded, is output on RDOP/RDON. LIM2.RD(1:0)= 10: Sliced data, not recovered by the DPLL is output on RDOP/ RDON. A “1” on RDOP corresponds to a positive pulse on RL1/RL2. A “1” on RDON corresponds to a negative pulse on RL1/ RL2. 29, 35, 42, 48 RDON(1:4) O Receive Data Output/Negative LIM1.RDON(1:0)= 00 (see above) BPV(1:4) O Bipolar Violation Indication LIM1.RDON(1:0)= 01 SCL KOO System Clock Output LIM1.RDON(1:0)= 10 SCL KII + PU System Clock Input LIM1.RDON(1:0)= 11 Read clock for jitter attenuater buffer if internal DCO is not used (seeFigure 10on page 38). Table 2 Signal Pin Functions (cont’d) Pin No. Signal Input (I) Output (O) Supply (S) Function

QuadLIU V1.1 Pin Descriptions Data Sheet 25 2001-02 88, 85, 82, 79XDIP(1:4) I + PU Transmit Data In Positive Transmit data received from the framer interface is output onXL1/2. NRZ data has to be provided onXDIP. Latching of data is done with the rising or falling transitions of TCL K according to LIM4.TPE. 87, 84, 81, 78XDIN(1:4) I + PU Transmit Data In Negative If the dual-rail data stream is selected by bits LIM0.XC(1:0) transmit data received from the framer interface is output onXL1/ 2. NRZ data (AMI negative data) has to be provided onXDIN. Latching of data is done with rising or falling transitions of TCLK according to bit LIM4.TPE. 30, 36, 43, 49 RCLK(1:4) O Receive Clock The output functions of these ports are defined by register CMR.RS(1:0): CMR.RS(1:0) = 00: Receive Clock extracted from the incoming data pulses. CMR.RS(1:0) = 01: Receive Clock extracted from the incoming data pulses. RCLK i ss e th i g hi nc a s eo f loss-of-signal (LSR0.LOS=1). Selected by GCR.R1S(1:0), one of the four RCL K(1:4) is output on RCLK1. The clock frequency is 2.048 (E1)/

1.544 MH z( T 1 / J 1 )

(1:4) O CMR.RS(1:0) = 10: Output of de-jittered system clock sourced by DCO. Clock frequency: 2.048 (E1) or 1.544 MH z (T1/J1). SeeFigure 10on page 38. Table 2 Signal Pin Functions (cont’d) Pin No. Signal Input (I) Output (O) Supply (S) Function

QuadLIU V1.1 Pin Descriptions Data Sheet 26 2001-02 86, 83, 80, 77 TCLK(1:4) I + PU Transmit Clock Input of the working clock for the transmitter with a frequency of 2.048 (E1)/ 1.544 MH z( T 1 / J 1 ) .

12 MCL K I Master Clock

A reference clock between 1.02 MH z and

20 MH z must be provided on this pin (32

ppm accuracy). 8R E S I Hardware Reset A low signal on this pin forces the device into reset state. During reset, an active clock is needed on pin MCLK.

58 MODE I + PU Operation Mode Select

0 = Intel bus 1 = Motorola bus Table 2 Signal Pin Functions (cont’d) Pin No. Signal Input (I) Output (O) Supply (S) Function

QuadLIU V1.1 Pin Descriptions Data Sheet 27 2001-02 Note: oD = open-drain output PU = input or input/output comprising an internal pullup device To override the internal pullup by an external pulldown, a resistor value of 22 kΩ is recommended. Unused pins containing pullups can be left open. Unused receive channels have to be connected to a fixed level (VDDR or VSSR ). Table 3 Power Supply Pins Pin No. Signal Input (I) Output (O) Supply (S) Function 4, 22, 54, 72 V DDR S (analog) Positive Power Supply for the analog receiver 7, 19, 57, 69 VSSR S (analog) Power Supply Ground for the analog receiver 2, 24, 52, 74 VDD X S (analog) Positive Power Supply for the analog transmitter 26, 50, 76, 100 VSS X S (analog) Power Supply Ground for the analog transmitter 11, 31, 44, 63, 89 VDD S Positive Power Supply for digital subcircuits 13, 32, 45, 64, 90 VSS S Power Supply Ground for digital subcircuits Table 4 Boundary Scan Pins Pin No. Signal Input (I) Output (O) Supply (S) Function

14 TRS

I+ PU Test Reset(Boundary Scan) active low;if the JTAG boundary scan is not used, this pin must be connected to RES or VSS .

15 TDI I + PU Test Data Input(Boundary Scan)

16 TMS I + PU Test Mode Select(Boundary Scan)

17 TC K I+ PU Test Clock(Boundary Scan)

18 TDO O Test Data Output(Boundary Scan)

QuadLIU V1.1 Functional Description Data Sheet 28 2001-02

3 Functional Description

3.1 Functional Overview

The QuadLIU™ device contains analog and digital function blocks that are configured and controlled by an external microprocessor or microcontroller. The main interfaces are  Receive-line Interface  Transmit-line Interface F r a m e r i n t e r f a c e  Microprocessor interface  Boundary scan interface as well as several control lines for reset and clocking purpose. The main internal functional blocks are  Analog line receiver with equalizer network and clock/data recovery  Analog line driver with programmable pulse shaper and line build out  Central clock-generation module  Jitter attenuator in receive or transmit direction  Test functions (e.g., loop switching local - remote - digital)  Register access interface  Boundary scan control

QuadLIU V1.1 Functional Description Data Sheet 29 2001-02

3.2 Block Diagram

JATT1) JATT1) Equalizer Peak Detection Slicer Clock & Data Recovery Local Loop Digital Loop Remote Loop Clocking Unit IBL PRBS Generator Line Driver Pulse Shaper Transmit Line Monitor AIS RL1 / ROID RL2 XL2 XL1 /XOID A(6:0) D(7:0) RD/DS WR/RW CS ALE MODE RES INT MFP(4:1) TDI TMS TC K TRS TDO RCL K RDOP RDON TCLK XDIP XDIN1)JATT in receive or transmit direction alternatively 2)Monitor and Generator in receive or transmit direction alternatively C o m m o nt oa l l channels One of four channels TCLK SYNC MCL K Port Control F0043 Microprocessor Interface Device Reset Boundary Scan Control

QuadLIU V1.1 Functional Description Data Sheet 30 2001-02

3.3 Functional Blocks

3.3.1 Microprocessor Control Unit

The communication between the CPU and the QuadLIU™ is done via a set of directly accessible registers. The interface may be configured as Intel or Motorola type (by control pin MODE) with a data bus width of 8 bits. The CPU transfers data to/from the QuadLIU™, sets the operating modes, controls function sequences, and gets status information by writing or reading control/status registers.Table 5shows how the ALE (A ddressLatchEnable) and MODE lines are used to control the interface type. Switching of ALE allows the QuadLIU™ to be connected directly to a multiplexed address/data bus.

3.3.1.1 Interrupt Interface

Special events in the QuadLIU™ are indicated by means of a single interrupt output, which requests the CPU to read status information from the QuadLIU™, or to transfer data to the QuadLIU™. The pin characteristic (open drain, push-pull) is programmable. Since only one INT request output is provided, the cause of an interrupt must be determined by the CPU by reading the QuadLIU™’s interrupt status registers CIS and ISR(1:0). The interrupt on pin INT and the interrupt status bits are reset by reading the interrupt status registers. Registers ISR0 and ISR1 are “cleared on read“. The structure of the interrupt status registers is shown inFigure 6. Table 5 Selectable Bus and Microprocessor Interface Configuration ALE MODE Microprocessor interface Bus Structure V SS or VDD high Motorola demultiplexed VSS or VDD low Intel demultiplexed switching low Intel multiplexed

QuadLIU V1.1 Functional Description Data Sheet 31 2001-02 Figure 6 Interrupt Status Registers Each interrupt indication of register ISR0 and ISR1 can be masked selectively by setting the corresponding bit in the mask registers IMR0 and IMR1. If the interrupt status bits are masked, they neither generate an interrupt on pin INT nor are they visible in ISR(1:0). The non-maskableC hannelInterruptStatus (CIS) register serves as a pointer to pending ISRs. After the QuadLIU™ has requested an interrupt by activating its INT pin, the CPU should first read the CIS register to identify the requesting channel by bit GISx (G lobal InterruptStatus bit of channel x) After that the corresponding interrupt status register ISR(1:0) of the requesting channel should be examined. After reading the interrupt status registers ISR(1:0), the pointer in CIS is cleared or updated if another interrupt requires service. Ifallpending interrupts are acknowledged by reading the ISRs, CIS is reset and pin INT goes inactive. Updating of ISR(1:0) and CIS is prohibited only during read access. Masked Interrupts Visible in Status Registers The CIS register indicates those channels with active interrupt indications. An additional mode (“visible mode”) may be selected via bit LIM4.VIS. In this mode, masked interrupt status bits neither generate an interrupt on pin INT nor are they visible in CIS,but are displayed in the corresponding ISR(s) ISR(1:0). This mode is useful when some interrupt status bits are to be polled in the individual ISRs. F0042 GIS4 GIS1GIS2GIS3 C H 1: IMR0 / IMR1 C H 1: ISR0 / ISR1 C H 2: IMR0 / IMR1 C H 2: ISR0 / ISR1 C H 4: IMR0 / IMR1 C H 4: ISR0 / ISR1 C H 3: IMR0 / IMR1 C H 3: ISR0 / ISR1 Channel Interrupt Status Register (CIS)

QuadLIU V1.1 Functional Description Data Sheet 32 2001-02 Note: In the visible mode, all active interrupt status bits, whether the corresponding actual interrupt is masked or not, are reset when the interrupt status register is read. Thus, when polling of some interrupt status bits is desired, care must be taken that unmasked interrupts are not lost in the process. All unmasked interrupt statuses are treated as in normal mode. Please note that whenever polling is used, all interrupt status registers concerned have to be polled individually (no “hierarchical” polling is possible), since CIS contains information on only those interrupts that were actually generated, i.e., unmasked interrupts.

QuadLIU V1.1 Functional Description Data Sheet 33 2001-02

3.3.2 Boundary Scan Unit

In the QuadLIU™ aTestA ccessPort (TAP) controller is implemented. The essential part of the TAP is a finite state machine (16 states) controlling the different operational modes of the boundary scan. Both, TAP controller and boundary scan, meet the requirements in the JTAG standard IEEE 1149.1.Figure 7gives an overview. Figure 7 Block Diagram of Test Access Port and Boundary Scan After switching on the device (power-on), a reset signal has to be applied to TRS ,w h i c h forces the TAP controller into test logic reset state. For normal operation without boundary scan access, the boundary reset pin TRScan be tied to the device reset pin RES. The boundary length is 150. F0115 TRS TC K TMS TDI TDO clock test control data in enable data out Clock Generation Reset TAP Controller finite state machine instruction register test signal generator TAP controller reset Identification Register (32 bits) control bus Boundary Scan (n bits) n BD data in BD data out ID data out

QuadLIU V1.1 Functional Description Data Sheet 34 2001-02 If no boundary scan operation is used, TRShas to be connected to RSTor VSS .T M S , TC K and TDI do not need to be connected since pullup transistors ensure high input levels in this case. Test handling (boundary scan operation) is performed via the pins TCK (Test Clock), TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the TAP controller is not in its reset state, that means TRSis connected toVDD or it remains unconnected due to its internal pull up. Test data at TDI is loaded with a clock signal connected to TCK."1" or "0" on TMS causes a transition from one controller state to another;constant"1"on TMS leads to normal operation of the chip. An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells (data out and enable) and an I/O-pin (I/O) uses three cells (data in, data out and enable). Note that most functional output and input pins of the QuadLIU™ are tested as I/O pins in boundary scan, hence using three cells. The desired test mode is selected by serially loading a 8-bit instruction code into the instruction register via TDI (LSB first). EXTEST is used to examine the interconnection of the devices on the board. In this test mode at first all input pins capture the current level on the corresponding external interconnection line, whereas all output pins are held at constant values ("0"or"1"). Then the contents of the boundary scan is shifted to TDO. At the same time the next scan vector is loaded from TDI. Subsequently all output pins are updated according to the new boundary scan contents and all input pins again capture the current external level afterwards, and so on. SAMPLE is a test mode which provides a snapshot of pin levels during normal operation. IDCODE : A 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). T h eL S Bi sf i x e dt o"1". The ID code field is set to: 0001 0000 0000 0101 1010 0000 1000 0011 Version= 1 H ,Part Number= 005AH , Manufacturer= 083H (including LSB, fixed to"1") BYPASS : A bit entering TDI is shifted to TDO after one TCK clock cycle. An alphabetical overview of all TAP controller operation codes is given inTable 6. Table 6 TAP Controller Instruction Codes TAP Instruction Instruction Code BYPASS 11111111 EXTEST 00000000 IDCODE 00000100 SAMPLE 00000001 reserved for device test 01010011

QuadLIU V1.1 Functional Description Data Sheet 35 2001-02

3.3.3 Master Clocking Unit

The QuadLIU™ provides a flexible clocking unit that can use a stable reference clock in the range of 1.02 MH zt o2 0MH z supplied on pin MCLK. The clocking unit has to be tuned to the selected reference frequency by setting the G lobalC lockM ode registers (GCM(6:1)) accordingly. The calculation formulas for the appropriate register settings can be found in Chapter 6.2on page 87. All required clocks for E1 and T1/J1 operation are generated internally by this circuit. The global setting depends only on the selected master clock frequency, and is the same for E1 and T1/J1 because both clock rates are provided simultaneously. The flexible master clock unit can be disabled (GCM2.VFREQ_EN= 0, which is the default configuration after hardware reset). In this case, a fixed reference clock of 2.048 M H z( E 1 )o r1 . 5 4 4MH z (T1/J1) has to be supplied on pin MCLK. Note: E1 or T1/J1 mode can be selected independently for each channel if flexible clocking is selected (GCM2.VFREQ_EN = 1). To meet the transmit clock and data accuracy requirements of E1/T1 in free running mode, the MCL K reference clock itself must have an accuracy of± 32 ppm. The synthesized clock can be controlled on pin RCLK. Figure 8 Flexible Master Clock Unit FL0002 Flexible Master Clock Unit GCM1 - GCM6 MCL K E1 Clocks T1/J1 Clocks

QuadLIU V1.1 Interface Description Data Sheet 36 2001-02

4 Interface Description

4.1 Receiver

Figure 9 Receiver Configuration

4.1.1 Receive Line Interface

Several data input types are supported:  Ternary coded signals received at multifunction ports RL1 and RL2 from a - 10 dB or -36 dB (E1)/-36 dB (T1/J1) ternary interface. The ternary interface is selected if LIM1.ECMIR is reset.  CMI coded data on port ROID received from a fiber-optical interface. The optical interface is selected if LIM1.ECMIR is set. The signal at the ternary interface is received on both ends of a transformer. The line termination impedance 75Ω /120Ω/100 Ω is selectable by switching resistors in parallel. This selection does not require a change of transformers.

4.1.2 Short-haul/Long-haul Interface

The QuadLIU™ has an integrated short- and long-haul line interface consisting of a receive equalization network and noise filtering. Table 7 Examples of External Component Values (Receive) Parameter Characteristic Impedance [ Ω ] E1 T1 J1 75 120 100 110 R1 (± 1 % )[Ω ] 75 120 100 110 t2 :t1 1:1 1:1 1:1 1:1 ITS10571 Line t2 t1 1R QuadLIU RL1 RL2

QuadLIU V1.1 Interface Description Data Sheet 37 2001-02

4.1.3 Receive Equalization Network

The QuadLIU™ automatically recovers the signals received on pins RL1/2 in a range of up to -36 dB. The maximum reachable length with a 22 AWG twisted-pair cable is 6000 feet (T1/J1). After reset the QuadLIU™ is in short-haul mode, and received signals are recovered up to a cable attenuation of -10 dB. Switching to long-haul mode is done by setting of register bit LIM1.EQON. Noise filters eliminate the higher frequency part of the received signals. The incoming data is peak-detected and sliced at 45, 50, 55, or 67% of the peak value (programmable in four steps by LIM2.SLT(1:0)) to produce the digital data stream. The received data is then forwarded to the clock and data recovery unit (DPLL) or optionally transferred to ports RDOP/RDON directly (see LIM2.RD(1:0)). The current equalizer status is indicated by register RES (R eceiveEqualizerStatus).

4.1.4 Receive Line Attenuation Indication

RES reports the current receive line attenuation in 25 steps of approximately 1.7 dB (E1)/ 1.4 dB (T1/J1) each. The least significant five bits of this register indicate the cable attenuation in dB. These five bits are only valid together with the most significant two bits (RES.EV(1:0)= 01) .

QuadLIU V1.1 Interface Description Data Sheet 38 2001-02

4.1.5 Receive Clock and Data Recovery

The analog received signal on port RL1/2 is equalized and then peak-detected to produce a digital signal. The receive clock and data recovery subcircuit extracts the route clock RCLK from the data stream received on the RL1/2 or ROID lines, and converts the data stream into a dual-rail bit stream. The clock and data recovery works with the internally generated high-frequency clock based on MCLK. Normally, the clock that is output on pin RCLK is the recovered clock from the signal provided on RL1/2, and has a duty cycle close to 50% . The free run frequency is defined by the master clock setting [2.048 MH z (E1)/1.544 MH z( T 1 / J 1 )] in periods with no signal. The intrinsic jitter generated in the absence of any input jitter is not more than 0.02 UI (U nitIntervals). Figure 10 Receive Clock System

4.1.6 Receive Line Coding

In E1 applications,H DB3 and AMI coding is provided for the data received from the ternary interface. In T1 mode, B8ZS and AMI code is supported. In case of the optical interface, CMI Code (1T2B) withH DB3/B8 ZS postprocessing is provided. If the DPLL is not bypassed, the receive route clock is recovered from the data stream. The CMI decoder does not correct any errors. TheH DB3 code is used along with double violation detection or extended code violation detection (optional, see LIM0.EXZ E). In B8ZSo r AMI, code all code violations are detected. Detected errors increment the code violation counter (16 bits length). Equalizer Slicer DPLL JATT DCO DecoderJATT LOS RCL K2...4 RCL K1RCL K2 RCL K4 RCL K3 RDOP RDON/BPV/ SCL KO/ SCL KI RCL K of 3 other channels RCL K SCL KO BPV NR Z data MCL K SYNC RL1 RL2 SCL KI F0065

QuadLIU V1.1 Interface Description Data Sheet 39 2001-02

4.1.7 Pulse-Density Detector

Pulse-density violations of the received signal are detected according to ANSI T1.403. Violations are indicated (LSR0.PDEN, ISR0.PDENI) if the incoming signal contains:  More than 15 consecutive zerosor  Fewer than N ones in each and every time window of 8× (N+1) digit time slots with N taking on all values of 1 to 23. The indication is cleared, if the pulse-density fulfills the requirement within 23 received ones.

4.1.8 Alarm Handling

The receive line interface includes alarm detection for AIS (A larmIndicationSignal) and LOS (Loss O fSignal).

4.1.8.1 AIS (Blue Alarm) Detection

The AIS is detected according to ITU-T G.775 and ANSI T1.231. In E1 applications, the alarm is set when the incoming signal has fewer than three zeros in each of two consecutive 512-bit periods. In T1 applications, the AIS alarm is set when fewer than 6 zeros are detected within a time interval of 3 ms received on RL1/2. AIS detection also works in the presence of a bit error rate of up to 10-3. An AIS alarm is indicated in aLineStatusR egister (LSR0.AIS) and anInterruptStatus R egister (ISR0.AIS).

4.1.8.2 LOS (Red Alarm) Detection

There are different definitions for detecting LOS alarms in the ITU-T G.775, ETS 300233, ANSI T1.403 and T1.231. The QuadLIU™ covers all these standards. The LOS indication is performed by generating an interrupt (if not masked) and activating a status bit. Additionally, a LOS status change interrupt is programmable via register LIM4.SCI.  Detection: In digital receive interface mode (LIM1.ECMIR= 1), an alarm is generated if the incoming data stream has no pulses (no transitions) for a certain number (N) of consecutive pulse periods. “No pulse” means a logical zero on pin ROID. In analog receive interface mode (LIM1.ECMIR= 0), a pulse with an amplitude less than Q dB below nominal is the criteria for “no pulse”. The receive signal level Q is programmable via three control bits, LIM2.RIL(2:0), related to the differential voltage between pins RL1 and RL2 (see DC Characteristics on page100). The number N can be set via an 8-bit register, PCD. The contents of the PCD register is multiplied by 16; the product equals the number of pulse periods until the alarm has to be detected (16

QuadLIU V1.1 Interface Description Data Sheet 40 2001-02 to 4096 pulse periods). ETS 300233, which requires detection intervals of at least 1 ms, can be fulfilled.  Recovery: The recovery procedure starts after detection of a logical"one" (digital receive interface) or a pulse (analog receive interface) with an amplitude more than Q dB (defined by LIM2.RIL(2:0)) of the nominal pulse. The value in the 8 bit register PCR defines the number of pulses (1 to 255) required to clear the LOS alarm. Additional recovery conditions may be programmed by register LIM5.LOSR(1:0).

4.1.9 Jitter Attenuator

The internal PLL (Phase-Locked Loop) circuitry called DCO (D igitallyC ontrolled O scillator) generates a “jitter-free“ output clock which is directly depending on the phase difference between the incoming clock and the jitter-attenuated clock. The jitter attenuator can be placed on the receive or transmit path of each channel individually. The working clock is an internally generated high-frequency clock based on the clock provided on pin MCLK. The jitter attenuator meets the requirements of ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/13, AT&T TR62411, AT&T TR43802, TR-TSY 009, TR-TSY 253 and TR-TSY 499. The receive jitter attenuator can be synchronized either to the extracted receive clock RCLK, or to a 2.048 (E1)/1.544 M H z( T 1 / J 1 ) / 8KH z (E1/T1/J1) clock provided on pin SYNC. The transmit jitter attenuator synchronizes with either the clock provided on pin TCLK, or the receive clock RCLK (remote loop/loop-timed). Received data is written into the elastic buffer with RCLK and is read out with the de- jittered clock sourced by DCO (if JATT in receive direction is selected). The jitter attenuated clock can be output on pin RCLK.A n8 - kH z clock is provided on pin FSC Transmit data is written into the elastic buffer with TCLK and is read out with the de- jittered clock sourced by DCO (if JATT in transmit direction is selected). In the loop-timed clock configuration (CMR.ELT) the DCO circuitry generates a transmit clock that is frequency synchronized to RCLK. The DCO circuitry attenuates the incoming jittered clock starting at 2H z( E 1 ) / 6H z (T1⁄J1) jitter frequency with 20 dB/decade fall-off. Wander with a jitter frequency below 2/6H z is passed unattenuated. The intrinsic jitter in the absence of any input jitter is less than 0.02 UI. The DCO accepts gapped clocks, which are used in ATM or SDH /SONET applications. For some applications, it might be useful to start jitter attenuation at lower frequencies. Therefore the corner frequency is switchable by the factor of ten down to 0.2/0.6H z (CMR.SCF).

QuadLIU V1.1 Interface Description Data Sheet 41 2001-02 The jitter attenuator works in two different modes:  Slave mode In slave mode (CMR.MAS= 0), the DCO is synchronized with the recovered route clock. In case of LOS (receive mode) or transmit clock is lost (transmit mode, bit LSR1.TCS = 1), the DCO switches to master mode automatically. If bit CMR.DCS is set, automatic switching from RCLK/TCLK to SYNC is disabled.  Master mode In master mode (CMR.MAS= 1) the jitter attenuator is in free-running mode if no clock is supplied on pin SYNC . If there is a clock with a frequency of 2.048 (E1)/1.544 MH z (T1/J1)/8 kH z (E1/T1/J1) on the SYNC input, the DCO is synchronized with this input signal. In some applications, it might be useful to synchronize to a gapped clock sourced by pin SYNC. In this case, the DCO circuitry would be centered to the nominal frequency. Optionally the QuadLIU™ offers the ability to disable the centering the DCO circuitry (LIM4.DCF = 1). Table 8shows the clock modes with the corresponding synchronization sources. Table 8 Clocking Modes Mode Internal LOS active or TCS set SYNC Input DCO 1)Output Clock Master no V DD Free-running (DCO centered) Master no 1.544 M H z Synchronized with SYNC input2) GCR.SSF(1:0) = 01 Master no 2.048 M H z Synchronized with SYNC input2) GCR.SSF(1:0) = 00 Master no 8 k H z Synchronized with SYNC input GCR.SSF(1:0) = 10 Slave no V DD Synchronized with line RCLK/TCLK(4:1), selected by CMR.DSS(1:0) Slave no 1.544 M H z Synchronized with line RCLK/TCLK(4:1), selected by CMR.DSS(1:0)2) Slave no 2.048 M H z Synchronized with line RCLK/TCLK(4:1) , selected by CMR.DSS(1:0)2) Slave yes V DD Free running (DCO centered)

QuadLIU V1.1 Interface Description Data Sheet 42 2001-02 The jitter attenuator meets the jitter transfer requirements of ITU-T I.431 and G.735-739 (refer toFigure 11). Figure 11 Jitter Attenuation Performance Also the requirements of ETSI TBR12/13 are satisfied. The DCO starts jitter attenuation at about 2H z to ensure adequate margin against TBR12/13 output jitter limit with 15 UI input at 20H z. Slave yes 1.544 M H z Synchronized with SYNC input2) GCR.SSF(1:0) = 01 Slave yes 2.048 M H z Synchronized with SYNC input2) GCR.SSF(1:0) = 00 1) The DCO can be used either in receive or transmit direction (seeFigure 10and Figure 14) 2) If flexible clocking mode is selected (GCM2.VFREQ_EN= 1), the SYNC frequency can be selected independent of E1 or T1/J1 mode. Table 8 Clocking Modes (cont’d) Mode Internal LOS active or TCS set SYNC Input DCO 1)Output Clock ITD10570 -60 Frequency Attenuation 10 100 1000 10000 100000 Hz ITU G.736 Template -50 -40 -30 -20 -10 dB LIU

QuadLIU V1.1 Interface Description Data Sheet 43 2001-02

4.1.10 Jitter Tolerance

The QuadLIU™ receiver’s tolerance to input jitter complies with ITU for CEPT applications.Figure 12shows the curves of different input jitter specifications as well as the QuadLIU™ performance. Figure 12 Jitter Tolerance Jitter Amplitude Jitter Frequency 1 10 100 1000 10000 100000 H z UI 0.1 100 1000 AT&T TR 62411 TR-NWT 000499 Cat II ITU-T G.823 ITU-T I.431 QuadLIU F0 05 2

QuadLIU V1.1 Interface Description Data Sheet 44 2001-02

4.1.11 Output Jitter

In the absence of any input jitter, the QuadLIU™ generates the output jitter as specified inTable 9.

4.1.12 Elastic Buffer

The elastic buffer can be placed in receive or transmit direction to generate a “jitter-free” data stream. Different buffer sizes can be programmed by LOOP.BS(1:0):  00: 256 bits  01: 128 bits  10: 64 bits  11: 32 bits Slips are performed in all buffer modes. After a slip is detected, the read pointer is adjusted to one half of the current buffer size. A slip condition is detected when the write pointer and the read pointer of the memory are nearly coincident. If a slip condition is detected, a negative slip or a positive slip is performed. For a negative slip, one half of the current buffer size is skipped. For a positive slip, one half of the current buffer size is read out twice. A positive or negative slip is indicated in the interrupt status bits ISR0.SLP and ISR0.SLN. When bit CMDR.CEB is set, the data delay through the elastic buffer is set to half of the current buffer size. Table 9 Output Jitter Specification Measurement Filter Bandwidth Output Jitter (UI peak to peak)Lower Cutoff Upper Cutoff AT&T TR62411 10 H z8 k H z < 0.015 8k H z4 0 k H z < 0.015 10 H z4 0 k H z < 0.015 ITU-T I.431 20 H z1 0 0 k H z < 0.015 700 H z1 0 0 k H z < 0.015 Broadband < 0.02

QuadLIU V1.1 Interface Description Data Sheet 45 2001-02

4.2 Transmitter

The serial bit stream is then processed by the transmitter which has the following functions:  AIS generation (A larmIndicationSignal)  Generation of AMI, B8ZS,H DB3 or CMI coded signals  Generation of IBL (In-B and Loop) code  Generation of PRBS (Pseudo-R andom B inarySequence)

4.2.1 Transmit Line Interface

The analog transmitter transforms the unipolar bit stream to ternary (alternate bipolar) return-to-zero signals of the appropriate programmable pulse shape. The unipolar data is provided by the digital transmitter. Figure 13 Transmitter Configuration Table 10 Examples of External Component Values (Transmit) Parameter Characteristic Impedance [ Ω ] E1 T1 J1 75 120 100 110 t2 : t1 1:2 . 4 1:2 . 4 1:2 . 4 1:2 . 4 XPM2.XLHC 1111 ITS10568 Line t1 t2 XL2 XL1 QuadLIU

QuadLIU V1.1 Interface Description Data Sheet 46 2001-02 In transmit direction, only the ternary or CMI interface is supported:  Ternary signal The received data stream on pinsXDIP orXDIP/N is converted into a ternary signal which is output on pinsXL1 and XL2. In E1 mode theH D B 3a n dA M Il i n ec o d ei s employed. In T1 mode, B8ZS and AMI with or without zero code suppression is supported (selected by LIM0.XC(1:0);the encoder can also be disabled).  CMI signal The received data stream is converted into a CMI signal withH D B 3( E 1 )o rB 8ZS( T 1 / J1) precoding.

4.2.2 Transmit Clock System

Figure 14 Transmit Clock System The jitter attenuator can be placed in the receive or transmit path. If placed in the transmit path, data is clocked into the JATT buffer with the transmit clock TCLK. If automatic clock-switching is enabled (LIM5.ACS= 1), TCLK is replaced by the SYNC clock automatically, if TCLK is missing. The active edge of TCLK (or SYNC, if TCLK is missing) c a nb ep r o g r a m m e db yL I M 4 . T P E .

4.2.3 Pulse-Density Enforcer

The integrated pulse-density enforcer can be activated (LIM0.PDE= 1) to ensure the outgoing signal fulfills the pulse-density requirements of ANSI T1.403:  No more than 15 consecutive zeros  At least N ones in every time window of 8× (N+1) digit time slots, with N taking on all values of 1 to 23. DCO MCL K SYNC Pulse Shaper Line Driver RCL K SCL KI En- coder XL1 XL2 XDIP XDIN TCL K TCL K of 3 other channels SYNC F0066 JATTJATT

QuadLIU V1.1 Interface Description Data Sheet 47 2001-02

4.2.4 Programmable Pulse Shaper and Line Build-Out

In long-haul applications, the transmit pulse masks are optionally generated according to FCC68 and ANSI T1.403 for T1 applications. To reduce the crosstalk on the received signals, the QuadLIU™ can place a transmit attenuator in the data path (LBO,LineB uild O ut). Transmit attenuation is selectable to be 0 , -7.5, -15 or -22.5 dB (selected by register LIM3.LBO(2:1)). ANSI T1.403 defines only 0 to -15 dB (T1/J1 mode only). The QuadLIU™ includes a programmable pulse shaper to satisfy the requirements of ITU-T I.431 , ANSI T1. 102, and various DS1, DSX-1 specifications are met. The amplitude of the pulse shaper is programmable individually via the microprocessor interface to allow a large number of different pulse templates. Adaption to the line length is selected by programming the registersXPM(2:0) as shown onpage 77. To reduce power consumption, the output stage biasing can be reduced (LIM5.XLB = 1). This leads to slightly reduced slopes.

QuadLIU V1.1 Interface Description Data Sheet 48 2001-02

4.2.5 Transmit Line Monitor

The transmit line monitor compares the transmit line current onXL1 andXL2 with an on- chip transmit line current limiter. The monitor detects faults on the primary side of the transformer indicated by a highly-increased transmit line current (more than about 120 mA for at least three"1" pulses), and protects the device from damage by automatically setting the transmit line driverXL1/2 in a high-impedance state. The current limiter checks the actual current value ofXL1/2, and if the transmit line current drops below the detection limit, the high-impedance state is cleared. Two conditions are detected by the monitor: transmit line ones density (more than 31 consecutive zeros) indicated by LSR1.XLO and transmit line high currrent indicated by LSR1.XLS. In both cases a transmit line monitor status change interrupt is provided. The transmit line monitor function can be disabled by LIM5.XLM = 0 to reduce power consumption. Figure 15 Transmit Line Monitor Configuration

4.3 Framer Interface

The system side interface to the receive framer interface is realized by RDOP, RDON and RCL K. Data on RDOP/N is clocked with either the rising or falling edge of RCLK (LIM4.RPE, seeFigure 10on page 38). Data from the framer interface is sampled atXDIP andXDIN on the active edge of TCLK. The active edge can be the rising or fallingedge of TCLK (LIM4.TPE). An automatic clock-switching mode can be enabled (LIM5.ACS= 1) to switch automatically to the clock provided on pin SYNC if TCLK is missing. The selected edge (rising⁄falling) also applies to SYNC, if selected by automatic switching. ITS10936 Pulse Shaper Monitor Line TRI XDATA XL1 XL2

QuadLIU V1.1 Interface Description Data Sheet 49 2001-02

4.4 Maintenance Functions

4.4.1 Error Counter

The QuadLIU™ offers two error counters. Each of them is 16 bits long. They record code violations and PRBS errors. Both error counters are buffered. Updating of the buffer is done in two modes:  Every one-second interval  On demand via handshake by writing to register CMDR In the one-second-mode an internal/external one-second timer updates these buffers and resets the counter to accumulating the error events. The error counter cannot overflow. Error events occuring during reset don’t get lost.

4.4.2 One-Second Timer

A one-second timer interrupt can be generated per channel internally to indicate that the enabled alarm status bits or the error counters have to be checked. The one-second timer is part of the monitor block and is related to the selected clock source (RCLK, SCL KO, SCLKIo rT C LK).

4.4.3 Pseudo-Random Bit Sequence Generation and Monitor

The QuadLIU™ has the ability to generate and monitor a 215-1 or 220-1 PRBS with maximum zero restriction according to ITU-T O.151 and AT&T TR62411. The generated PRBS pattern is transmitted directly or inverted. The PRBS monitor senses the PRBS pattern in the receive or transmit data stream. Synchronization is done with inverted and non-inverted PRBS patterns. The current synchronization status is reported in status and interrupt status registers. Data streams consisting of continuous ones or zeros also lead to the indication of synchronous state. Each PRBS bit error increments the PRBS error counter (BECL/H ). Synchronization is reached within 400 ms at a probability of 99.9% i nt h ep r e s e n c eo fab i te r r o rr a t e of≤ 10 -1.

QuadLIU V1.1 Interface Description Data Sheet 50 2001-02

4.4.4 In-Band Loop Generation and Detection

The QuadLIU™ generates an unframed IBL (In-B and Loop) pattern and detects a framed or unframed IBL pattern according to ANSI T1. 403. The detection works even in the presence of bit errors at a rate of up to 10 -2. The loop-up and loop-down patterns are programmable individually from 2 to 8 bits in length (LCR1.LAC(1:0) and LCR1.LDC(1:0)). Programming of loop codes is done in registers LCR2 and LCR3, using default values 00001 for activation and 001 for deactivation of the loop. The in-band loop generator and monitor can be placed either on the receive or transmit path independently (LIM3.GTP, LIM3.MTP). The monitor is enabled by setting LIM3.EPRM = 1. If the in-band loop code has been detected for at least 5 s, the QuadLIU™ optionally switches the remote loop on or off according to ANSI T1.403 (LIM0.ARL= 1). The current state of the remote loop is indicated in a status register. Replacing the receive or transmit data with the in-band loop codes is done by LCR1.XLD/XLA. Status and interrupt-status bits inform the user whether loop-up or loop-down code was detected.

QuadLIU V1.1 Interface Description Data Sheet 51 2001-02

4.4.5 Remote Loop

In the remote loop-back mode, the clock and data recovered from the line inputs RL1/2 or ROID are routed back to the line outputsXL1/2 orX OID via the analog or digital transmitter. As in normal mode, they are also processed by the synchronizer and then sent to the system interface. The remote loop-back mode is selected by setting the control bits LOOP.RL, LOOP.EJATT and LOOP.XJATT. Received data may be looped with or without the transmit jitter attenuator (JATT). Figure 16 Remote Loop Signal Flow Note: If an external loop shall be switched between RDON/RDOP/RCLK and XDIN/ XDIP/TCLK, the setup/hold time requirements described in the AC characteristics have to be observed. To relax the timing, the edge selection of either the receive or transmit path can be inverted (see register description of LIM4), or an inverter can be placed between RCLK and TCLK externally. ITS10982 DecoderPeak Detector RL1 RL2 Clock and DataEqualizer Recovery JATT RDON RDOP XL2 XL1 Shaper Pulse JATT Encoder RCLK TCLK XDIP XDINLine Driver Remote Loop 1) JATT either in transmit or receive direction1) JATT either in transmit direction, receive direction or bypassed

QuadLIU V1.1 Interface Description Data Sheet 52 2001-02

4.4.6 Local Loop

The local loop-back mode, selected by LOOP.LL= 1, disconnects the receive lines RL1 ⁄2 or ROID from the receiver. It is used in analog input applications (LIM1.ECMIR = 0). Instead of the signals coming from the line, data provided by the system interface is routed through the analog receiver back to the framer interface. The bit stream is transmitted without disturbance on the transmit line. An AIS to the distant end can be enabled by setting LIM1.XAIS without influencing the data looped back to the system interface. The signal codes for transmitter and receiver have to be programmed to be identical. Figure 17 Local Loop Signal Flow ITS10984 DecoderPeak Detector RL1 RL2 Clock and DataEqualizer Recovery JATT RDON RDOP XL2 XL1 Shaper Pulse JATT Encoder RCLK TCLK XDIP XDINLine Driver Local Loop 1) JATT either in transmit or receive direction AIS

QuadLIU V1.1 Interface Description Data Sheet 53 2001-02

4.4.7 Digital Loop

The digital loop-back mode, selected by LOOP.DLB= 1, also disconnects the receive lines RL1/2 from the receiver. It is used in digital input applications (LIM1.ECMIR= 1). Instead of the signals coming from the line, the data provided by framer interface is routed through the clock and data recovery circuit back to the framer interface without touching the analog receiver part. The bit stream is transmitted onXL1/2 without disturbance. An AIS to the distant end can be enabled by setting LIM1.XAIS without influencing the data looped back to the framer interface. The serial codes for transmitter and receiver have to be programmed identically. Figure 18 Digital Loop Signal FLow ITS10983 DecoderPeak Detector RL1 RL2 Clock and DataEqualizer Recovery JATT RDON RDOP XL2 XL1 Shaper Pulse JATT Encoder RCLK TCLK XDIP XDINLine Driver Digital Loop 1) JATT either in transmit or receive direction AIS

QuadLIU V1.1 Interface Description Data Sheet 54 2001-02

4.4.8 Alarm Simulation

Alarm simulation does not affect the normal operation of the device.H owever, real alarm conditions are not reported to the processor or to the remote end when the device is in the alarm simulation mode. The alarm simulation is initiated by setting the bit LIM0.SIM. The following alarms are simulated:  Loss of Signal LOS (red alarm)  Alarm Indication Signal AIS (blue alarm)  Slip indication  Code violation counter (AMI, B8ZS,H DB3 Code) increment  Pulse-density violation  Transmit clock (TCLK)l o s t  PRBS synchronous state indication and PRBS error counter increment Setting of the bit LIM0.SIM initiates alarm simulation, interrupt status bits are set. Error counting and indication occurs while this bit is set. After it is reset, all simulated error conditions disappear, but the generated interrupt statuses are still pending until the corresponding interrupt status register is read. Alarms such as AIS and LOS are cleared automatically. Interrupt status register and error counters are cleared automatically on read.

QuadLIU V1.1 Interface Description Data Sheet 55 2001-02

4.4.9 Transmit Data Performance Monitoring

Alternatively to the receive data performance monitoring (BPV, EXZ , LOS), this function can be switched into the transmit direction to supervise data received on pinsXDIP and XDIN (LIM5.XDPM = 1). Transmit data performance monitoring is available only in bypass mode (LIM2.RD(1:0)= 10), and is not available in remote loop configuration. The principle data flow is shown inFigure 19. Figure 19 Transmit Data Performance Monitoring F0138 DECDPLL LOS CVC MU X MU X XDPM MU X MU X LIM2.RD(1:0) RDOP RDON RDIP RDIN XDIP XDIN TCL K SYNC TPETCS XDOP XDON LIM2.RD(1:0) ENCLine Driver CVC Code Violation Counter DEC H DB3/B8 ZS decoder ENC H DB3/B8 ZS encoder LOS Loss-of-signal detection RDIP/RDIN and X DOP/ X DON are internal signals between analog and digital part of the circuit.

QuadLIU V1.1 Operational Description Data Sheet 56 2001-02

5 Operational Description

5.1 Operational Overview

The QuadLIU™ can be operated in one of two modes, which is either E1 mode or T1/J1 mode. The device is programmable via a microprocessor interface which enables byte access to all control and status registers. The QuadLIU™ must be initially programmed after reset. General guidelines for initialization are described in“Basic Initialization Settings” on page 57. The status registers are read-only and are updated continuously. Usually the processor reads the status registers periodically to analyze the alarm status. SIgnals (for example RL1/2 receive line) should not be applied before the device is powered up.

5.2 Device Reset

The QuadLIU™ is forced to the reset state if a low signal is input on pin RES(for minimum period, see“Reset” on page 105). During reset, the QuadLIU™ needs an active clock on pin MCLK. All output stages are in a high-impedance state, all internal flip-flops are reset, and most of the control registers are initialized to default values. After reset, the device is initialized to E1 operation.

5.3 Device Initialization

5.3.1 Reset Values

After reset, the QuadLIU™ is initialized with register values listed inTable 11. Table 11 Initial Values after Reset Register Reset Value Meaning GCR 80 H FSC is sourced by channel 1, RCL K1 clock source: Channel 1 GCR2 00 H E1 mode for all four channels, INT function is open drain LIM0 00 H AMI coding LIM1 00 H Power up LIM2 40 H LOS threshold -20 dB, receive threshold 55%

QuadLIU V1.1 Operational Description Data Sheet 57 2001-02

5.3.2 Basic Initialization Settings

For a correct start up of the primary access interface, a set of parameters specific to the system and hardware environment must be programmed after RESgoes inactive. Both the basic and the operational parameters must be programmedbeforethe activation procedure of the PCM line starts. Such procedures are specified in ITU-T and ETSI recommendations (e.g. fault conditions and consequent actions). Setting optional parameters makes sense mainly when basic operation via the PCM line is guaranteed. Table 12gives an overview of the most important parameters in terms of signals and control bits that are to be programmed in one of the above steps. The sequence is recommended but not mandatory. Parameters for the basic and operational set up, for example, may be programmed simultaneously. LIM5 04 H Detailed mode selection LOOP 00 H Elastic buffer size: 256 bit Local loop off, remote loop off PCD C0 H Pulse count"0"for LOS detection is 192 PCR 18 H Pulse count"1"for LOS recovery is 24 in 192-bit interval LCR1 40 H Down code 6 bit, up code 5 bit length LCR2 09 H In band loop deactivate code is 001 LCR3 01 H In band loop activate code is 00001 XPM(2:0) 73 H ,02H ,00H E1 transmit pulse mask for 120 Ohm IMR0, IMR1 FFH ,F FH All interrupts are disabled CMR 08 H DCO reference clock: channel 1, RCLK output: DPLL clock, DCO enabled, DCO internal reference clock, Slave mode Table 11 Initial Values after Reset(cont’d) Register Reset Value Meaning

QuadLIU V1.1 Operational Description Data Sheet 58 2001-02 Note: Read access to unused register addresses might return random values and therefore must not be done. Undefined bit positions at defined register addresses might return random values and must be masked before the register value is used for further computing. Writing to unused register addresses or reserved registers may produce unpredictable results. Table 12 Initialization Parameters Basic Set Up Registers to be Programmed Mode select T1/J1 Short-haul Long-haul GCR2.PMODx = 1;x = 1t o4 GCR2.PMODx = 0;x = 1t o4 LIM1.EQON = 0 LIM1.EQON = 1 Master clock frequency select GCM(6:1) Specification of line interface, clock generation and pulse mask LIM0 LIM1 XPM(2:0) Output driver enable XPM2.XLT = 0 Line interface coding LIM0. XC(1:0) LIM0.RC(1:0) Loss-of-signal detection/recovery conditions PCD PCR Jitter attenuation LOOP.EJATT LOOP. XJATT

QuadLIU V1.1 Register Description Data Sheet 59 2001-02

6 Register Description

6.1 Control Register Addresses

Table 13 Control Register Addresses Address (hexadecimal) Register Type Comment Page Ch 1 Ch 2 Ch 3 Ch 4

00 GCR R/W Global Configuration Register 60

20 GCR2 R/W Global Configuration Register 2 61

01 21 41 61 LIM0 R/W Line Interface Mode 0 62 02 22 42 62 LIM1 R/W Line Interface Mode 1 64 03 23 43 63 LIM2 R/W Line Interface Mode 2 66 04 24 44 64 LIM3 R/W Line Interface Mode 3 67 05 25 45 65 LIM4 R/W Line Interface Mode 4 68 06 26 46 66 LIM5 R/W Line Interface Mode 5 70 07 27 47 67 CMR R/W Clock Mode Register 72 08 28 48 68 LOOP R/W Loop Register 74 09 29 49 69 XPM0 R/W Transmit Pulse Mask 0 76 0A 2A 4A 6A XPM1 R/W Transmit Pulse Mask 1 76 0B 2B 4B 6B XPM2 R/W Transmit Pulse Mask 2 76 0C 2C 4C 6C PCD R/W Pulse Count Detection 79 0D 2D 4D 6D PCR R/W Pulse Count Recovery 79 0E 2E 4E 6E LCR1 R/W Loop Code Register 1 80 0F 2F 4F 6F LCR2 R/W Loop Code Register 2 81 10 30 50 70 LCR3 R/W Loop Code Register 3 81 11 31 51 71 IMR0 R/W Interrupt Mask Register 0 82 12 32 52 72 IMR1 R/W Interrupt Mask Register 1 82 13 33 53 73 CMDR R/W Command Register 83 3D GCM1 R/W Global Clock Mode 1 84 3E GCM2 R/W Global Clock Mode 2 84 3F GCM3 R/W Global Clock Mode 3 85 5D GCM4 R/W Global Clock Mode 4 85

QuadLIU V1.1 Register Description Data Sheet 60 2001-02

6.2 Detailed Description of Control Registers

Global Configuration Register (Read/Write) Address: 00H Value after reset: 80H GCR.(7:6) reserved ,must be cleared SSF(1:0) Select SYNC Frequency The frequency of the reference clock for the DCO circuitry provided on pin SYNC is selected by these bits. 00 = External SYNC frequency: 2.048 MH z (default) 01 = External SYNC frequency: 1.544 MH z 10 = External SYNC frequency: 8 kH z (master mode only) 11 = Not defined 5E GCM5 R/W Global Clock Mode 5 86 5F GCM6 R/W Global Clock Mode 6 86 GCR 0 0 SSF1 SSF0 FSC1 FSC0 R1S1 R1S0 Table 13 Control Register Addresses (cont’d) Address (hexadecimal) Register Type Comment Page Ch 1 Ch 2 Ch 3 Ch 4

QuadLIU V1.1 Register Description Data Sheet 61 2001-02 FSC(1:0) FSC Source One of the four internally generated de-jittered 8-kH z clocks is output on port FSC. 00 = Sourced by channel 1 (default) 01 = Sourced by channel 2 10 = Sourced by channel 3 11 = Sourced by channel 4 R1S(1:0) RCL K 1S o u r c e One of the four internally generated receive route clocks is output on port RCLK1 (available for RCLK1 only, not for RCLK(2:4)). 00 = Extracted receive clock of channel 1 (default) 01 = Extracted receive clock of channel 2 10 = Extracted receive clock of channel 3 11 = Extracted receive clock of channel 4 Global Configuration Register 2 (Read/Write) Address: 20H Value after reset: 00H N o t e : U n u s e db i t sh a v et ob ec l e a r e d . GCR2.7 reserved GCR2.6 reserved IC(1:0) Interrupt Pin Control x0 = Open drain, active low (default) 01 = Push-pull, active low 11 = Push-pull, active high PMOD(4:1) E1 or T1/J1 Mode of channel (4:1) 0 = E1 mode (default) 1 = T1/J1 mode GCR2 0 0 IC1 IC0 PMOD4 PMOD3 PMOD2 PMOD1

QuadLIU V1.1 Register Description Data Sheet 62 2001-02 Line Interface Mode 0 (Read/Write) Addresses: 01H ,2 1H ,4 1H ,6 1H Value after reset: 00H XC(1:0) Transmit Code Serial codes for transmitter and receiver can be programmed independently. The single-rail data stream received on portXDIP is encoded as follows: 00 = AMI 01 =H DB3 code for E1 applications 10 = B8ZS code for T1/J1 applications 11 = Encoder is bypassed,XDIN is used as “data input negative" After any modification of bitsXC(1:0), a software reset is required (CMDR.RES = 1). If the encoder is bypassed, hardware tristate function is not available. RC(1:0) Receive Code The recovered data is decoded and transmitted on pin RDOP inN on- R eturn-to-Zero (NRZ) format (single-rail or unipolar data). 00 = AMI 01 =H DB3 code for E1 applications 10 = B8ZS code for T1 applications 11 = Decoder is bypassed;RDON is used as"data output negative" CMI coding is selected by setting LIM1.ECMIR= 1. After any modification of bits RC(1:0), a software reset is required (CMDR.RES = 1). LIM0 XC1 XC0 RC1 RC0 E XZ EP D E A R L S I M

QuadLIU V1.1 Register Description Data Sheet 63 2001-02 EX ZE Excessive Zeros Detection Enable Selects line code error detection mode. E1 mode (GCR2.PMODx = 0): 0 = Only double violations are detected. 1 = Extended code violation detection: 0000 strings are detected additionally. Thereafter, incrementation of code violation counter CVC is done after receiving an additional four zeros. T1/J1 mode (GCR2.PMODx = 1): 0 = Only bipolar violations are detected. 1 = Bipolar violations and zero strings of 8 or more contiguous zeros in B8ZS code, or more than 15 contiguous zeros in AMI code, are detected additionally and counted in the CVC. PDE Pulse-Density Enforcer Selects pulse-density enforcement mode for AMI signals. Pulse- density according to ANSI T1.403 is enforced automatically. 0 = Disabled 1 = Enabled ARL Automatic Remote Loop 0 = Disables automatic on/off switching for the remote loop upon detecting the in-band loop activate/deactivate code. 1 = Enables automatic on/off switching for the remote loop upon detecting the in-band loop activate/deactivate code. Activate and deactivate codes are user-programmable. When the in- band loop activate code (e.g. 00001) is detected for at least 5 s, the remote loop is automatically switched on until the deactivate code (e.g. 001) is detected for 5 s or the bit LIM0.ARL is cleared. Automatic remote loop switching can be activated with or without jitter attenuation, depending on bit LOOP.EJATT. SIM Alarm Simulation 0 = Internal alarm simulation inactive. 1 = Internal alarm simulation active. Initiates internal error simulation of alarm indication signal, loss-of-signal, slip, code violations, PRBS errors and loss of transmit clock. The CVC and BECL/H error counters are incremented.

QuadLIU V1.1 Register Description Data Sheet 64 2001-02 Line Interface Mode 1 (Read/Write) Addresses: 02H ,2 2H ,4 2H ,6 2H Value after reset: 00H PD Power Down Switches the appropriate channel between power-up and power- down mode. 0 = Power up 1 = Power down EQON Receive Equalizer On 0 = -10 dB Receiver: short-haul mode 1 = -43 dB Receiver: long-haul mode (E1) -36 dB Receiver: long-haul mode (T1/J1) ECMIR Enable CMI Receive Interface 0 = The ternary interface is selected. Multifunction ports RL1/2 become analog inputs. 1 = The digital CMI receive interface is selected. Received data is latched on multifunction port ROID. RDON(1:0) RDON Pin Input/Output Multiplexer Select 00 = RDON output 01 = BPV output (bipolar violations) 10 = SCL KO output 11 = SCL KI input LIM1 PD EQON ECMIR RDON1 RDON0 ECM ECMI XX AIS

QuadLIU V1.1 Register Description Data Sheet 65 2001-02 ECM Error Counter Mode The function of the error counters is determined by this bit. 0 = Before reading an error counter, the corresponding bit in the command register (CMDR) has to be set. The low byte of the error counter should always be read before the high byte. The error counter is reset with the rising edge of the corresponding bits (DBEC, DCVC) in the CMDR register. 1 = Every second the error counter is latched and then reset automatically. The latched error counter state must be read within the next second, otherwise data is overwritten. Avoid reading the error counter during updating. ECMIX Enable CMI Transmit Interface 0 = The ternary interface is selected.XL1/2 are used as analog outputs. 1 = The digital CMI receive interface is selected. Transmitted data is output on portXOID. XAIS Transmit AIS towards Remote End 0 = Normal transmit operation. 1 = Sends AIS via portsXL1/XL2 towards the remote end. The outgoing data stream which can be looped back via the local loop to the framer interface is not affected.

QuadLIU V1.1 Register Description Data Sheet 66 2001-02 Line Interface Mode 2 (Read/Write) Addresses: 03H ,2 3H ,4 3H ,6 3H Value after reset: 40H RIL(2:0) Receive Input Threshold Only valid if analog line interface is selected (LIM1.ECMIR= 0) . "No signal"is declared if the voltage between pins RL1 and RL2 drops below the limit programmed through bits RIL(2:0) and the received data stream has no transition for a period defined in the PCD register. Please see the selectable voltage levels in chapterChapter 7.3on page 102. Note: LIM2.RIL(2:0) must be programmed before LIM1.EQON = 1 is set (long-haul mode). SLT(1:0) Receive Slicer Threshold 00 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 55% of the peak amplitude (default). 01 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 67% of the peak amplitude. 10 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 50% of the peak amplitude. 11 = The receive slicer generates a mark (digital one) if the voltage on RL1/2 exceeds 45% of the peak amplitude. LIM2 RIL2 RIL1 RIL0 SLT1 SLT0 0 RD1 RD0

QuadLIU V1.1 Register Description Data Sheet 67 2001-02 RD(1:0) Select Receive Data Output These bits select the different stages of the received data path. 00 = Received data is decoded (H DB3/B8 ZS/AMI) and output on RDOP/N. 01 = Data recovered by the DPLL (not decoded) is output on RDOP/N. 10 = Sliced data is transferred directly to RDOP/N. 11 = Sliced data is directly transferred to RDOP/N and the bypassed receive path logic is switched off to reduce power consumption unless remote loop is activated. Line Interface Mode 3 (Read/Write) Addresses: 04 H ,2 4H ,4 4H ,6 4H Value after reset: 00H LBO(2:1) Line Build-Out (T1 mode only) In long-haul applications, LIM1.EQON= 1, a transmit filter can be optionally placed in the transmit path to attenuate the signal level on pinsXL1/2. Selecting the transmitter attenuation is possible in steps of 7.5 dB at 772kH z, which meets FCC Part 68 and ANSI T1.403. To meet the line build-out characteristics defined by ANSI T1.403, registersXPM(2:0) should be programmed as follows: 00 = 0d B GTP PRBS/IBL Generator in Transmit Path 0 = The PRBS/IBL generator is placed in the receive path. 1 = The PRBS/IBL generator is placed in the transmit path. MTP PRBS/IBL Monitor in Transmit Path 0 = The PRBS/IBL monitor is placed in the receive path. 1 = The PRBS/IBL monitor is placed in the transmit path. LIM3 LBO2 LBO1 GTP MTP EPRM X PRBS IPRBS SPRBS

QuadLIU V1.1 Register Description Data Sheet 68 2001-02 EPRM Enable PRBS Monitor 0 = The PRBS monitor is disabled. 1 = The PRBS monitor is enabled. XPRBS Transmit Pseudo-Random Bit Sequence (PRBS) 0 = Normal transmit operation 1 = A “1” in this bit position enables transmission of a pseudo- random bit sequence. Depending on bit SPRBS, the PRBS is generated according to 215 -1 or 220-1 (ITU-T O.151). IPRBS Invert Pseudo-Random Bit Sequence PRBS 0 = The generated PRBS data is not inverted. 1 = The PRBS data is inverted. SPRBS Select Pseudo-Random Bit Sequence Algorithm 0 = Pseudo-random bit sequence algorithm: 215 -1 1 = Pseudo-random bit sequence algorithm: 220 -1 with maximum 14 consecutive zeros restriction. Line Interface Mode 4 (Read/Write) Addresses: 05H ,2 5H ,4 5H ,6 5H Value after reset: 00H RPE RCL K Positive Edge 0 = RDOP/N are output with the falling edge of the RCLK clock. 1 = RDOP/N are output with the rising edge of the RCLK clock. TPE Positive Sample Edge of TCL K 0 =X DIP/N are latched with the falling edge of the TCLK clock. 1 =X DIP/N are latched with the rising edge of the TCLK clock. VIS Masked Interrupts Visible 0 = Masked interrupt status bits are not visible in registers ISR(0:1). 1 = Masked interrupt status bits are visible in ISR(0:1), but they are not visible in register CIS. Interrupt request pin INT stays inactive. LIM4 RPE TPE VIS SCI DCF PC2 PC1 PC0

QuadLIU V1.1 Register Description Data Sheet 69 2001-02 SCI Status Change Interrupt 0 = Interrupts are generated either at the beginning or end of the internal interrupt event. 1 = The following interrupts are activated if enabled upon detection and recovering of the internal interrupt source: ISR0.LOS , ISR0.AIS, ISR0.PDENI, ISR1.LTC DCF Disable Center Frequency of DCO circuitry Only valid if master mode (CMR.MAS= 1) is selected. 0 = Automatic centering of the DCO circuitry is enabled. 1 = Automatic centering of the DCO circuitry is disabled. PC(2:0) MFP Port Configuration These bits select the output pin function of multifunction port MFP. 000 = Loss-of-signal (red alarm) indication 001 = Analog loss-of-signal indication 010 = Pseudo-random bit sequence synchronization status 011 = Bipolar violation indication 100 = Transmit line short status 101 = Alarm indication signal 110 = Not defined 111 = Not defined

QuadLIU V1.1 Register Description Data Sheet 70 2001-02 Line Interface Mode 5 (Read/Write) Addresses: 06H ,2 6H ,4 6H ,6 6H Value after reset: 04H ACS Automatic Clock-Switching If TCLK is missing, the transmit clock can optionally be switched to the SYNC clock automatically. 0 = Automatic switching is disabled (default); if TCLK is missing, XL1/2 are undefined. 1 = Automatic switching is enabled; if TCLK is missing, SYNC is used, if SYNC is also missing,XL1/2 are undefined. XDPM Transmit Data Performance Monitoring To verify transmit data, the receive line supervision circuitry can be switched to the transmit path. If selected, data input on pinsXDIP/ XDIN is checked forB iPolarViolations (BPV),EX zessiveZeros (EXZ ) and Loss O fSignal (LOS). 0 = Receive path (default) 1 = Transmit path Note: Transmit data performance monitoring is not possible in remote loop configuration. LIM2.RD(1:0) = 10 is required. XLB Transmit Line Biasing The analog circuit of the transmit line driver can be switched into a power saving mode. This slightly reduces the output slopes on XL1/2. 0 = Normal operation (default) 1 = Power-saving operation XLM Transmit Line Monitor Enable The transmit line monitor circuit can be switched off to reduce power consumption. 0 = Transmit line monitor is off. 1 = Transmit line monitor is active (default). LIM5 ACS XDPM X LB XLM LOSR1 LOSR0

QuadLIU V1.1 Register Description Data Sheet 71 2001-02 LOSR(1:0) Loss-of-Signal Recovery Condition 00 = The LOS alarm is cleared if the predefined pulse-density (register PCR) is detected during the time interval which is defined by register PCD. 01 = In addition to the recovery condition described above a LOS alarm is cleared only if the pulse-density requirement (defined by PCR and PCD) is fulfilled and no more than 15 contiguous zeros are detected during the recovery interval. 10 = A LOS alarm is not terminated, if at the end of the pulse position interval any subinterval of 100 pulse positions contains no pulses of either polarity (ANSI T1.231). This means, clearing a LOS alarm is done only if the pulse-density requirement (defined by PCR and PCD) is fulfilled and no more than 99 contiguous zeros are detected during the recovery interval. 11 = In addition to the recovery condition described for"00" aL O S alarm is cleared only if the pulse-density requirement (defined by PCR and PCD) is fulfilled and no more than 8 contiguous zeros are detected during the recovery interval.

QuadLIU V1.1 Register Description Data Sheet 72 2001-02 Clock Mode Register (Read/Write). Addresses: 07H ,2 7H ,4 7H ,6 7H Value after reset: 08H ,5 8H ,A8H ,F8H DSS(1:0) DCO Synchronization Clock Source DCO in receive path: These bits select the reference clock source for the DCO circuitry. 00 = Receive reference clock generated by the DPLL of channel 1 01 = Receive reference clock generated by the DPLL of channel 2 10 = Receive reference clock generated by the DPLL of channel 3 11 = Receive reference clock generated by the DPLL of channel 4 DCO in transmit path: These bits select the reference clock source for the DCO circuitry. 00 = Reference clock for the DCO is TCLK1 01 = Reference clock for the DCO is TCLK2 10 = Reference clock for the DCO is TCLK3 11 = Reference clock for the DCO is TCLK4 Note: After Reset all DCO circuitries synchronize with the clock sourced by the DPLL of channel 1 . Each channel has to be configured individually. If CMR.MAS is set, the DCO circuitry synchronizes with the clock applied on port SYNC. CMR DSS1 DSS0 RS1 RS0 DCS SCF ELT MAS

QuadLIU V1.1 Register Description Data Sheet 73 2001-02 RS(1:0) Select RCL K Source These bits select the source of RCLK. 00 = Extracted receive clock generated by the DPLL is used If jitter attenuation is selected in receive direction and external SCL KI is not used (LOOP.XJATT = 0, LOOP.EJATT = 1, LIM1.RDON(1:0) ≠ 11), de-jittered 2.048 (E1)/1.544 MH z( T 1 / J1) clock generated by the internal DCO circuitry is used. 01 = Extracted receive clock;in case of an active LOS alarm RCLK is set high. 10 = De-jittered 2.048 (E1)/1.544 MH z (T1/J1) clock generated by the internal DCO circuitry is used. 11 = Not defined DCS Disable Clock-Switching In slave mode (CMR.MAS = 0), the DCO is synchronized with the recovered route clock. In case of LOS (receive mode) or LSR1.TCS = 1 (transmit mode), the DCO switches to the clock sourced by port SYNC. If this bit is set, automatic switching from RCL K (receive mode) or TCLK (transmit mode) to SYNC is disabled (default). SCF Select Corner Frequency of DCO Setting this bit reduces the corner frequency of the DCO circuit by the factor of ten from 2H z( E 1 ) / 6H z (T1/J1) to 0.2H z( E 1 ) / 0 . 6H z( T 1 ) . Note: Reduction of the corner frequency of the DCO circuitry increases the time required for synchronization. ELT Enable Loop-Timed 0 = Normal operation 1 = Transmit clock is generated from the clock supplied by MCLK, which is synchronized with the extracted receive route clock. In this configuration, the transmit elastic buffer has to be enabled. MAS Master Mode 0 = Slave mode 1 = Master mode on. Setting this bit the DCO circuitry is frequency synchronized with the clock (2.048 MH z, 1.544 MH zo r8kH z) supplied on pin SYNC. If this pin is connected to V SS or VDD , the DCO circuitry is centered and no receive jitter attenuation is performed. The generated clocks are stable.

QuadLIU V1.1 Register Description Data Sheet 74 2001-02 Loop Register (Read/Write) Addresses: 08H ,2 8H ,4 8H ,6 8H Value after reset: 00H XJATT Jitter Attenuator Position 0 = The elastic buffer is placed in the receive path. 1 = The elastic buffer is placed in the transmit path. EJATT Enable Jitter Attenuator 0 = The elastic buffer is disabled. 1 = The elastic buffer is enabled. RL Remote Loop 0 = Remote loop is switched off. 1 = Remote loop is switched on. The remote loop-back mode disconnects the transmit data received onXDIP/N from the transmitter. Received data on pins RL1/2 is looped back to the line interface with or without jitter attenuation. The decoder and encoder are ignored. If LIM0.ARL (automatic remote loop) is selected and no valid ARL condition is decoded, the remote loop stays active until RL is reset (higher priority of RL compared to ARL) LL Local Loop Analog line applications (LIM1.ECMIR= 0) 0 = Local loop is switched off. 1 = Local loop is switched on. Data received on portsXDIP/N is looped back through the analog receiver to pins RDOP/N. An alarm indication signal (blue signal) can be sent to the remote end (LIM1.XAIS). Data received on ports RL1/2 is ignored. Receiver and transmitter coding must be identical. DLB Digital Loop-Back Digital line applications (LIM1.ECMIR= 1) 0 = Digital loop-back disabled. 1 = Digital loop-back enabled. Data received on portsXDIP/N is looped back to pins RDOP/N. Optinally an alarm indication signal (blue signal) can be sent to the remote end (LIM1.XAIS). LOOP XJATT EJATT RL LL DLB LOSDAT BS1 BS0

QuadLIU V1.1 Register Description Data Sheet 75 2001-02 Data received on ports RL1/2 is ignored. Receiver and transmitter coding must be identical. LOSDAT Data Stream Clear in Case of LOS 0 = If LOS is detected, data is processed, bit errors may occur 1 = If LOS is detected, data is cleared to avoid bit errors BS(1:0) Buffer Size 00 = 256 bits 01 = 128 bits 10 = 64 bits 11 = 32 bits

QuadLIU V1.1 Register Description Data Sheet 76 2001-02 Transmit Pulse Mask (0:2) (Read/Write) AddressesXPM0: 09H ,2 9H ,4 9H ,6 9H AddressesXPM1: 0AH ,2 AH ,4 AH ,6 AH AddressesXPM2: 0BH ,2 BH ,4 BH ,6 BH Value after reset: 73H ,0 2H ,0 0H The transmit pulse shape is output on pinsXL1 andXL2. The level of the pulse shape is programmed via registersXPM(2:0) to create a custom waveform. In order to get an optimized pulse shape for the external transformers, each pulse shape is internally devided into four sub-pulse shapes. In each sub-pulse shape, a programmable 5-bit value defines the level of the analog voltage on pinsXL1 and XL2. Together four 5-bit values have to be programmed to form one complete transmit pulse shape. The four 5- bit values are sent in the following sequence: XP04 to 00:First pulse shape level XP14 to 10: Second pulse shape level XP24 to 20: Third pulse shape level XP34 to 30: Fourth pulse shape level Changing the LSB of each subpulse in registersXPM(2:0) changes the amplitude of the differential voltage onXL1/2 by approximately 80 mV. XPM0 XP12 XP11 XP10 XP04 XP03 XP02 X P01 XP00 XPM1 XP30 XP24 XP23 XP22 XP21 XP20 X P14 XP13 XPM2 XLLP XLT DA XLT XLH C XP34 XP33 X P32 XP31

QuadLIU V1.1 Register Description Data Sheet 77 2001-02 Example for E1 mode: 120 Ω interface and wired as shown inFigure 13on page 45. XPM04 to 00: 1BH XPM14 to 10: 1BH XPM24 to 20: 00H XPM34 to 30: 00H Programming values forXPM(0:2): 7BH ,0 3H ,0 0H Example for T1 mode The XPM values are valid for the following external circuitry: Transformer ratio: 1:2.4; Cable: PULB 22AWG (100Ω ); Serial resistors: 2Ω . Table 14 Pulse Shaper Programming Range in m Range in ft. XPM0 XPM1 XPM2 XP04- XP00 XP14- XP10 XP24- XP20 XP34- XP30 hexadecimal decimal 0 to 40 0 to 133 D7 1E 11 23 22 7 2 40 to 81 133 to 266 D8 22 11 24 22 8 2 81 to 122 266 to 399 FC 2A 11 28 23 10 2 122 to 162 399 to 533 FD C6 11 29 23 17 3 162 to 200 533 to 655 DF D6 11 31 22 21 3

QuadLIU V1.1 Register Description Data Sheet 78 2001-02 XLLP Reserved 0 = Normal operation 1 = Reserved (not to be used) XLT Transmit Line Tristate 0 = Normal operation 1 = Transmit lineXL1/XL2 is switched into high-impedance state. If this bit is set, the transmit line monitor status information is frozen. This bit is functionally ored with pin TRIST unlessXDIN function is used during decoder bypass. DAXLT Disable Automatic Tristating of XL1/2 0 = Normal operation. If a short is detected on pinsXL1/2, the transmit line monitor sets theXL1/2 outputs into a high- impedance state. 1 = If a short is detected onXL1/2 pins, automatically setting these pins into a high-impedance (by theXL-monitor) state is disabled. XLHC Transmit Line High Current 0 = Output current less than 50 mA 1 = Output current more than 50 mA To be selected for T1/J1 mode or E1 mode.

QuadLIU V1.1 Register Description Data Sheet 79 2001-02 Pulse Count Detection Register (Read/Write) Addresses: 0CH ,2 CH ,4 CH ,6 CH Value after reset: C0H PCD(7:0) Pulse Count Detection An LOS alarm is detected if the incoming data stream has no transitions for a programmable number T of consecutive pulse positions. The number T is programmable via the PCD register and c a nb ec a l c u l a t e da sf o l l o w s : T = 16 × (PCD +1);with 0≤ PCD ≤ 255. The maximum time is 256× 16 × 488 ns= 2 ms in E1 mode, or 256 × 16 × 648 ns= 2.65 ms in T1 mode. Every detected pulse resets the internal pulse counter. The counter is clocked with the receive clock RCLK. Pulse Count Recovery (Read/Write) Addresses: 0D H ,2 DH ,4 DH ,6 DH Value after reset: 18H PCR(7:0) Pulse Count Recovery An LOS alarm is cleared if a pulse-density is detected in the received bit stream. The number of pulses M which must occur in the predefined PCD time interval is programmable via the PCR register, and can be calculated as follows: M = N + 1 ;with 0≤ N ≤ 255. The time interval starts with the first detected pulse transition. With every received pulse, a counter is incremented and the actual counter is compared with the contents of PCR register. If the pulse number is greater or equal to the PCR value, the LOS alarm is reset. Otherwise the alarm stays active. In this case, the next detected pulse transition starts a new time interval. PCD PCD7 PCD0 PCR PCR7 PCR0

QuadLIU V1.1 Register Description Data Sheet 80 2001-02 Loop Code Register 1 (Read/Write)1) Addresses: 0EH ,2 EH ,4 EH ,6 EH Value after reset: 40H LDCL(1:0) Length Deactivate (Down) Code These bits defines the length of the user-programmable LLB deactivate code, which is programmable in register LCR2. 00 = 5b i t 01 = 6 bit (default) 10 = 7b i t 11 = 8b i t If a shorter pattern length is required, select a multiple of the required length and repeat the pattern in LCR2. LACL(1:0) Length Activate (Up) Code These bits defines the length of the user-programmable LLB activate code, which is programmable in register LCR3. 00 = 5 bit (default) 01 = 6b i t 10 = 7b i t 11 = 8b i t If a shorter pattern length is required, select a multiple of the required length and repeat the pattern in LCR3. XLD Transmit LLB Deactivate (Down) Code 0 = Normal operation (default) 1 = Normal data is replaced by the LLB deactivation code continuously until this bit is reset. LCR1.XLA and LIM3.XPRBS must be cleared. LLB deactivate code can be inserted in receive (LIM3.GTP= 0) or transmit direction (LIM3.GTP= 1). 1) Terms "LineLoop B ack"(LLB) and"In B and Loop"(IBL) are synonyms. LCR1 LDCL1 LDCL0 LACL1 LACL0 XLD XLA

QuadLIU V1.1 Register Description Data Sheet 81 2001-02 XLA Transmit LLB Activate (Up) Code 0 = Normal operation (default) 1 = Normal data is replaced by the LLB activate code continuously until this bit is reset. LCR1.XLD and LIM3.XPRBS must be cleared. LLB activate code can be inserted in receive (LIM3.GTP= 0) or transmit direction (LIM3.GTP= 1). Loop Code Register 2 (Read/Write) Addresses: 0F H ,2 FH ,4 FH ,6 FH Value after reset: 09H LDC(7:0) Line Loop-Back Deactivate Code If enabled by bit LCR1.XLD, the LLB deactivate code is repeated automatically until the LLB generator is stopped. Transmit data is overwritten by the LLB code. LDC0 is transmittted last. If the selected code length is less than 8 bits, the leftmost bits of LCR2 are ignored. For correct operations, bit LIM3.XPRBS has to be cleared. The default setting is (00)001001 (6-bit mode is default in LCR1). This generates the standard deactivation code"001". Loop Code Register 3 (Read/Write) Addresses: 10 H ,3 0H ,5 0H ,7 0H Value after reset: 01H LAC(7:0) Line Loop-Back Activate Code If enabled by bit LCR1.XLA, the LLB activate code is repeated automatically until the LLB generator is stopped. Transmit data is overwritten by the LLB code. LAC0 is transmittted last. If the selected code length is less than 8 bits, the leftmost bits of LCR3 are ignored. For correct operations, bit LIM3.XPRBS has to be cleared. The LCR2 LDC7 LDC0 LCR3 LAC7 LAC0

QuadLIU V1.1 Register Description Data Sheet 82 2001-02 default setting is (000)00001 (5-bit mode is default in LCR1). This generates the standard activate code"00001". Example: Transmit LLB/IBL activate Code= 00001 Register setting LCR1: xx00xx01 Register setting LCR3: xxx00001 Interrupt Mask Register (0:1) (Read/Write) Addresses IMR0: 11 H ,3 1H ,5 1H ,7 1H Addresses IMR1: 12H ,3 2H ,5 2H ,7 2H Value after reset: FFH ,F FH IMR(0:1) Interrupt Mask Register Each interrupt source can generate an interrupt signal on port INT. A "1"in a bit position of IMR(0:1) sets the mask active for the interrupt status in ISR(0:1). Masked interrupt statuses neither generate a signal on INT, nor are they visible in register CIS. Moreover, they are – not displayed in the ISR if bit LIM4.VIS is cleared – displayed in the ISR if bit LIM4.VIS is set Note: After reset, all interrupts aredisabled. See register ISR0/1 for detailed description of bit functions. IMR0 LLBSCM XLSCM PRBSSCM SLNM SLPM PDENM AISM LOSM IMR1 LTCM SECM

QuadLIU V1.1 Register Description Data Sheet 83 2001-02 Command Register (Read/Write) Addresses: 13H ,3 3H ,5 3H ,7 3H Value after reset: 00H Note: The maximum time between writing to the CMDR register and the execution of the command takes 2.5 periods of the current line data rate. Register bits are set by software and reset by hardware automatically after the required operation has been completed. Register bits in CMDR cannot be reset by software. RES Reset Receiver and Transmitter The receive and the transmit line interface (except the clock and data recovery unit DPLL) are reset. The contents of the control registers is not deleted. IBV Insert Bipolar Violations Setting this bit forces a bipolar violation in the transmit data stream. Violations are inserted at the next possible position. Ones preceded by two or more zeros are not converted into violations. Example (V= inserted violation): 001000010100 is converted to 001000010V00 IPE Insert PRBS Error Setting this bit forces a PRBS error in the outgoing data stream (if PRBS transmission is enabled). CEB Center Elastic Buffer Setting this bit forces the delay through the elastic buffer to half of the current buffer size (LOOP.BS1/0). DBEC Disable Pseudo-Random Binary Sequence Error Counter This bit is only valid if LIM1.ECM is cleared. It must be set before reading the error counter. This bit is reset automatically if the corresponding error counter high byte has been read. With the rising edge of this bit the error counter is latched and then cleared. DCVC Disable Code Violation Counter See bit DBEC. CMDR RES IBV IPE CEB DBEC DCVC

QuadLIU V1.1 Register Description Data Sheet 84 2001-02 Global Clock Mode Register 1 (Read/Write) Address: 3DH Value after reset: 00H PHD _E1(0:7) Frequency Ad just for E1 For details, see “Flexible Clock Mode Settings”o npage 87. Global Clock Mode Register 2 (Read/Write) Address: 3EH Value after reset: 00H DVM _E1(0:2) Divider Mode for E1 000 = Not valid 001 = DIV_E1 = 3 010 = DIV_E1 = 41 / 6 011 = DIV_E1 = 4 100 = DIV_E1 = 5.5 101 = DIV_E1 = 51 / 3 110 = DIV_E1 = 52 / 3 111 = Not valid VFREQ _EN Variable Frequency Enable 0 = Fixed clock frequency of 2.048 (E1) or 1.544 MH z( T 1 / J 1 ) 1 = Variable master clock frequency PHD _E1(8:11) Frequency Ad just for E1 For details, see “Flexible Clock Mode Settings”o npage 87. GCM1 PH D_E17 P H D_E16 P H D_E15 P H D_E14 P H D_E13 P H D_E12 P H D_E11 P H D_E10 GCM2 DVM_E12 DVM_E11 DVM_E10 VFREQ_EN P H D_E111 P H D_E110 P H D_E19 P H D_E18

QuadLIU V1.1 Register Description Data Sheet 85 2001-02 Global Clock Mode Register 3 (Read/Write) Address: 3FH Value after reset: 00H PHD _T1(0:7) Frequency Ad just for T1 For details, see “Flexible Clock Mode Settings”o npage 87. Global Clock Mode Register 4 (Read/Write) Address: 5DH Value after reset: 00H DVM _T1(0:2) Divider Mode for T1 000 = Not valid 001 = DIV_T1 = 3 010 = DIV_T1 = 41 / 6 011 = DIV_T1 = 4 100 = DIV_T1 = 5.5 101 = DIV_T1 = 51 / 3 110 = DIV_T1 = 52 / 3 111 = Not valid PHD _T1(8:11) Frequency Ad just for T1 For details, see “Flexible Clock Mode Settings”o npage 87. GCM3 PH D_T1 PH D_T1 PH D_T1 PH D_T1 PH D_T1 PH D_T1 PH D_T1 PH D_T1 GCM4 DVM_T12 DVM_T11 DVM_T10 0 P H D_T1 PH D_T1 PH D_T1 PH D_T1

QuadLIU V1.1 Register Description Data Sheet 86 2001-02 Global Clock Mode Register 5 (Read/Write) Address: 5EH Value after reset: 00H MCL K_ LOW Master Clock Range Low 0 = Master clock frequency divided by (PLL_M+ 1) is greater than or equal to 1.5 MH z 1 = Master clock frequency divided by (PLL_M+ 1) is less than

1.5 MH z

PLL _M(0:4) PLL Dividing Factor M For details, see “Flexible Clock Mode Settings”o npage 87. Note: Write operations to GCM5 initiate a PLL reset (see below). Global Clock Mode Register 6 (Read/Write) Address: 5FH Value after reset: 00H PLL _N(0:4) PLL Dividing Factor N For details, see “Flexible Clock Mode Settings”o npage 87. Note: Write operations to GCM6 initiate a PLL reset (see below). GCM5 MCL K_ LOW PLL_M PLL_M PLL_M PLL_M PLL_M GCM6 PLL_N PLL_N PLL_N PLL_N PLL_N

QuadLIU V1.1 Register Description Data Sheet 87 2001-02 Flexible Clock Mode Settings If flexible master clock mode is used (VFREQ_EN= 1), the according register settings can be calculated as follows (a windows-based program for automatic calculation is available, seeChapter 9.2on page 119). For some of the standard frequencies see the table below. 1. PLL_Ma n dP L L_N must satisfy the equations: a. 1.5 MH z ≤ f MCL K/(PLL_M + 1)≤ 2.048 MH z b. If a. is not possible, set MCLK_LOW and fulfill 1.02 MH z ≤ fMCL K/(PLL_M + 1)≤ 1.5 MH z c. 65 MH z ≤ fMCL K × (2×PLL_N + 2)/(PLL_M+ 1)≤ 69.7 MH z (as high as possible within this range) 2. Selection of best dividing mode: foutE1 = (fMCL K × (2×PLL_N +2)/(PLL_M+1) )/DIV_E1 (target E1: 16.384 MH z) foutT1= (fMCL K × (2×PLL_N +2)/(PLL_M+1) )/DIV_T1 (target T1: 12.352 MH z) If the target frequency cannot be reached exactly, the dividing mode has to be selected to reach a frequency that is as near as possible to the target frequency. 3. Calculation of correction value(frequency mismatch correction) PH D_E1 = 6 × 4096 × [DIV_E1 - (2×PLL_N +2)/(PLL_M+1)× (fMCL K /16.384 MH z)] PH D_T1 = 6 × 4096 × [DIV_T1 - (2×PLL_N +2)/(PLL_M+1)× (fMCL K/12.352 MH z)] The result of these equations is between -2048 and+2047. Negative values are represented in 2s-complement format (e.g., -2000D = 830H ;+2000D = 7D0 H ). Table 15 Clock Mode Register Settings for E1 or T1/J1 fMCL K [MHz] GCM1 GCM2 GCM3 GCM4 GCM5 GCM6

1.544 F0 H 51H 00H 80H 00H 15H

2.048 00 H 58H D2 H C2 H 00H 10H 8.192 00 H 58H D2 H C2 H 03H 10H 10.000 90 H 51H 81H 8FH 04H 10H

12.352 F0 H 51H 00H 80H 07H 15H

QuadLIU V1.1 Register Description Data Sheet 88 2001-02

6.3 Status Register Addresses

Table 16 Status Register Addresses Address (hexadecimal) Register Type Comment Page Ch 1 Ch 2 Ch 3 Ch 4 14 34 54 74 LSR0 R Line Status Register 0 89 15 35 55 75 LSR1 R Line Status Register 1 91 16 36 56 76 RES R Receive Equalizer Status 92 17 37 57 77 ISR0 R Interrupt Status Register 0 93 18 38 58 78 ISR1 R Interrupt Status Register 1 94 19 39 59 79 CVCL R Code Violation Counter Low 96 1A 3A 5A 7A CVC H R Code Violation CounterH igh 96 1B 3B 5B 7B BECL R PRBS Bit Error Counter Low 97 1C 3C 5C 7C BEC H R PRBS Bit Error CounterH igh 97

60 CIS R Channel Interrupt Status 95

7F VSTR R Version Status Register 1) 1) The device version number for PEB 22504 V1.1 is 00h.

QuadLIU V1.1 Register Description Data Sheet 89 2001-02

6.4 Detailed Description of Status Registers

Line Status Register 0 (Read) Addresses: 14H ,3 4H ,5 4H ,7 4H LOS Loss-of-Signal (Red Alarm) The loss-of-signal (LOS) detection offers the flexibility to fulfill allmost all LOS requirements on the market (e.g. ANSI T1.403/231, TR-WT-499, ITU-T G.775, ETS 300233). Detection: This bit is set when the incoming signal has no transitions in a time interval of T consecutive pulses, where T is programmable via PCD register. Total count of consecutive pulses: 16< T < 4096. The receive signal level where “no transition” is declared is defined by the programmed value of LIM2.RIL(2:0). Recovery: The bit is reset when the incoming signal has transitions with signal levels greater than the programmed receive input level (LIM2.RIL(2:0)) for at least M pulse periods defined by register PCR in the PCD time interval. An interrupt status bit (ISR0.LOS) is set with the rising edge of this bit. For additional recovery conditions according to ANSI T1.231, refer also to register LIM5.LOSR(1:0). The bit is also set during alarm simulation, and is reset if LIM0.SIM is cleared and no alarm condition exists. AIS Alarm Indication Signal (Blue Alarm) The AIS alarm is detected according to ITU-T G.775 and ANSI T1.231 standards. E1 mode: This bit is set when the incoming signal has fewer than three zeros in each of two consecutive 512-bit periods. This bit is cleared when each of two consecutive 512-bit periods contains three or more zeros. LSR0 LOS AIS PDEN E XZ D RLS PRBSS LLBAD LLBDD

QuadLIU V1.1 Register Description Data Sheet 90 2001-02 T1/J1 mode: This bit is set when fewer than six zeros are detected within a time interval of 3 ms received on RL1/2. The bit is also set during alarm simulation, and reset if LIM0.SIM is cleared and no alarm condition exists. An interrupt status bit (ISR0.AIS) is set with the rising edge of this bit. PDEN Pulse-Density Violation This bit indicates that the pulse-density of the received data stream defined by ANSI T1.403 is violated. More than 15 consectuive zeros or fewer than N ones are detected in each time window of 8× (N+1) digit time slots with N taking on all values of 1 to 23. The bit is cleared if the pulse-density fulfills the above requirement within 23 received ones or automatically after a read access. The bit is also set during alarm simulation. EX ZD Exzessive Zeros Detected Significant only if exzessive zero detection is enabled by setting LIM0.EXZ E = 1. Detection is done according to ANSI T1.231 requirements. The bit is set after detection of more than three (H DB3 ;E1), seven (B8ZS ;T1/J1) or 15 (AMI;T1/J1) contiguous zeros in the received bit stream. This bit is cleared when read. RLS Remote Loop Status Any change of this bit causes an ISR0.LLBSC interrupt. 0 = The remote loop is inactive. If enabled by bit LIM0.ARL, the remote loop is switched off automatically upon detection of the in-band loop deactivate code for at least 5 s, according to ANSI T1. 403 requirements. 1 = The remote loop is active (closed). If enabled by bit LIM0.ARL, the remote loop is switched on automatically upon detection of the in-band loop activate code for at least 5 s. PRBSS Pseudo-Random Binary Sequence Status The current status of the PRBS synchronizer is indicated in this bit. It is set if the synchronous state is reached, even in the presence of a bit error rate less than or equal to 10 -1. A data stream containing all zeros with or without framing bits is also a valid pseudo-random bit sequence. The bit is also set during alarm simulation.

QuadLIU V1.1 Register Description Data Sheet 91 2001-02 LLBDD Line Loop-Back Deactivation Signal Detected This bit is set if the LLB deactivate signal is detected and then received over a period of more than 25 ms (E1) or 33.16 ms (T1) ,with a bit error rate less than 10 -2. The bit remains set as long as the bit error rate does not exceed 10-2. If automatic remote loop switching is disabled (LIM0.ARL= 0), any change of this bit causes an LLBSC interrupt. LLBAD Line Loop-Back Activation Signal Detected This bit is set if the LLB activate signal is detected and then received over a period of more than 25 ms (E1) or 33.16 ms (T1), with a bit error rate less than 10-2. The bit remains set as long as the bit error rate does not exceed 10-2. If automatic remote loop switching is disabled (LIM0.ARL= 0), any change of this bit causes an LLBSC interrupt. Line Status Register 1(Read) Addresses: 15H ,3 5H ,5 5H ,7 5H TCS Transmit Clock Status This bit is set if the transmit clock derived from TCLK failed to occur for at least eight TCLK periods. The DCO reference is switched to SYNC if not disabled by CMR.DCS. The transmit linesXL1/2 are tristated automatically. With the first detected edge of the transmit clock, this bit is cleared and tristating ofXL1/2 is disabled. Additionally, the interrupt status bit ISR1.LTC is set. MCLK must be active because the reference frequency to detect a TCLK loss is derived from this clock. The bit is also set during alarm simulation. XLS Transmit Line Short Significant only if the ternary line interface is selected by LIM1.ECMIX= 0. 0 = Normal operation. No short is detected. 1 = The XL1 andXL2 are shortened for at least three pulses. As a reaction of the short, pinsXL1 andXL2 are automatically forced into a high-impedance state if bitXPM2.DA XLT is reset. After 128 consecutive pulse periods, outputsXL1/2 are activated again and the LSR1 TCS XLS XLO

QuadLIU V1.1 Register Description Data Sheet 92 2001-02 internal transmit current limiter is checked. If a short betweenXL1/2 is still active, outputsXL1/2 are in high-impedance state again. When the short disappears, pinsXL1/2 are activated automatically and this bit is reset. With any change of this bit, an interrupt ISR0.XLSC is generated. IfXPM2.XLT is set, this bit is frozen. XLO Transmit Line Open 0 = Normal operation 1 = This bit is set if at least 32 consecutive zeros were sent via pins XL1/XL2. This bit is reset with the first transmitted pulse. An interrupt ISR0.XL S Ci ss e tw i t ht h er i s i n ge d g eo ft h i sb i t .I f XPM2.XLT is set, this bit is frozen. Receive Equalizer Status (Read) Addresses: 16H ,3 6H ,5 6H ,7 6H EV(1:0) Equalizer Status Valid These bits inform the user about the current state of the receive equalization network. Only valid if LIM1.EQON is set. 00 = Equalizer status not valid, still adapting 01 = Equalizer status valid 10 = Equalizer status not valid 11 = Equalizer status valid but high noise floor RES(4:0) Receive Equalizer Status These bits display current line attenuation status in steps of approximately 1.4 (T1⁄J1)⁄1.7 (E1) dB. Only valid if bits EV(1:0)= 01. Accuracy:± 2 digits, based on temperature influence and noise amplitude variations. 00000 = Minimum gain (0 dB) ... 11001 = Maximum equalizer gain Note: For maximum receiver sensitivity set bits LIM2.RIL(2:0) = 110 RES EV1 EV0 RES4 RES3 RES2 RES1 RES0

QuadLIU V1.1 Register Description Data Sheet 93 2001-02 Interrupt Status Register 0 (Read) Addresses: 17H ,3 7H ,5 7H ,7 7H Value after reset: 00H All bits are reset when ISR0 is read. If bit LIM4.VIS is set, interrupt statuses in ISR0 may be flagged although they are masked via register IMR0.H owever, these masked interrupt statuses neither generate a signal on INT, nor are they visible in register CIS. LLBSC Line Loop Back Status Change Depending on bit LIM0.ARL the interrupt source is changed. LIM0.ARL = 0 : This bit is set if the LLB activate signal or the LLB deactivate signal is detected over a period of 25 ms/33.16 ms (E1/T1) with a bit error rate less than 10-2. The LLBSC bit is also set if the current detection status is left, i.e., if the bit error rate exceeds 10-2. LIM0.ARL = 1 : This bit is set high with any change of state of bit LSR0.RLS. XLSC Transmit Line Status Change XLSC is set with the rising edge of the bit LSR1.XLO or with any change of bit LSR1.XLS. The actual status of the transmit line monitor can be read from LSR1.XLS and LSR1.XLO. PRBSSC PRBS Status Change This bit is set with any change of state of the PRBS synchronizer. The current status of the PRBS synchronizer is indicated in LSR0.PRBSS. SLN Slip Negative The frequency of the receive route clock is greater than the frequency of the receive framer interface working clock based on 2.048 MH z (E1)/1.544 MH z (T1/J1). Data is skipped. SLN is also set during alarm simulation. ISR0 LLBSC XLSC PRBSSC SLN SLP PDENI AIS LOS

QuadLIU V1.1 Register Description Data Sheet 94 2001-02 SLP Slip Positive The frequency of the receive route clock is less than the frequency of the receive framer interface working clock, which is a multiple of or equal to 2.048 MH z( E 1 )⁄1.544 MH z (T1/J1). Data is repeated. SLP is also set during alarm simulation. PDENI Pulse-Density Violation Interrupt This bit is set if a pulse-density violation is detected(LSR0.PDEN= 1). The bit is set during alarm simulation. AIS Alarm Indication Signal (Blue Alarm) This bit is set when an alarm indication signal is detected and bit LSR0.AIS is set. It is also set during alarm simulation. If LIM4.SCI is set, this interrupt status bit is set with every change of LSR0.AIS. LOS Loss-of-Signal (Red Alarm) This bit is set when a loss-of-signal alarm is detected in the received bit stream and LSR0.LOS is set. It is also set during alarm simulation. If LIM4.SCI is set, this interrupt status bit is set with every change of LSR0.LOS. Interrupt Status Register 1 (Read) Addresses: 18 H ,3 8H ,5 8H ,7 8H All bits are reset when ISR1 is read. If bit LIM4.VIS is set, interrupt statuses in ISR1 may be flagged although they are masked via register IMR1.H owever, these masked interrupt statuses neither generate a signal on INT, nor are they visible in register CIS. LTC Loss of Transmit Clock This bit is set when a loss of transmit clock is detected and bit LSR1.TCS is set. It is also set during alarm simulation. If LIM4.SCI is set, this interrupt status bit is set with every change of LSR1.TCS. ISR1 LTC SEC

QuadLIU V1.1 Register Description Data Sheet 95 2001-02 SEC One-Second Timer The internal one-second timer has expired. The timer is derived from clock RCLK,S C LKO, SCL KIo rT C LK, depending on the monitor block configuration. The selected clock source has to supply a constant clock to ensure the correct function of the second timer. Channel Interrupt Status Register (Read) Address: 60H Value after reset: 00H This status register points to pending interrupts sourced by ISR1 and ISR0 of each channel. GIS4 Global interrupt status of register ISR1/0 of channel 4 GIS3 Global interrupt status of register ISR1/0 of channel 3 GIS2 Global interrupt status of register ISR1/0 of channel 2 GIS1 Global interrupt status of register ISR1/0 of channel 1 CIS GIS4 GIS3 GIS2 GIS1

QuadLIU V1.1 Register Description Data Sheet 96 2001-02 Code Violation Counter (Read) Addresses CVCL: 19H ,3 9H ,5 9H ,7 9H Addresses CVCH :1 AH ,3 AH ,5 AH ,7 AH CV(15:0) Code Violations E1 mode: If theH DB3 or the CMI code is selected, the 16-bit counter is incremented if violations of theH DB3 code are detected. The error detection mode is determined by programming the bit LIM0.EXZ E. If simple AMI coding is enabled (LIM0.RC(1:0)= 00), all bipolar violations are counted. T1 mode: If the B8ZS code (bit LIM0.RC(1:0)= 10, GCR2.PMODx = 1) is selected, the 16-bit counter is incremented upon detection of violations that are not due to zero substitution. If LIM0.EXZ Ei ss e t , excessive zero strings (more than seven contiguous zeros) are detected and counted. If simple AMI coding is enabled (LIM0.RC(1:0)= 00), all bipolar violations are counted. If LIM0.EXZ E is set, excessive zero strings (more than 15 contiguous zeros) are detected and counted. During alarm simulation, the counter is incremented every four bits received up to its saturation. Clearing and updating the counter is done according to bit LIM1.ECM. If this bit is cleared, the error counter buffer is permanently updated. For correct read access of the error counter, bit CMDR.DCVC has to be set. With the rising edge of this bit, updating of the buffer is stopped and the error counter is cleared. Bit CMDR.DCVC is reset automatically with a read access to the error counter high byte. If LIM1.ECM is set every second (interrupt ISR1.SEC), the error counter is latched and then reset automatically. The latched error counter state has to be read within the next second. CVCL CV7 CV0 CVC H CV15 CV8

QuadLIU V1.1 Register Description Data Sheet 97 2001-02 PRBS Bit Error Counter (Read) Addresses CVCL: 1BH ,3 BH ,5 BH ,7 BH Addresses CVCH :1 CH ,3 CH ,5 CH ,7 CH BEC(15:0) PRBS Bit Error Counter This 16-bit counter is incremented with every received PRBS bit error in the PRBS synchronous state LSR0.PRBSS= 1. Clearing and updating of the counter is done according to bit LIM1.ECM. If this bit is cleared, the error counter buffer is permanently updated. For correct read access of the error counter bit CMDR.DBEC has to be set. With the rising edge of this bit, updating the buffer is stopped and the error counter is cleared. Bit CMDR.DBEC is reset automatically with a read access to the error counter high byte. If LIM1.ECM is set every second (interrupt ISR1.SEC) the error counter is latched and then cleared automatically. The latched error counter state has to be read within the next second. Version Status Register (Read) Address: 7F H VN(7:0) Version Number of the Chip 00H =Version 1.1 BECL BEC7 BEC0 BEC H BEC15 BEC8 VSTR VN7 VN6 VN5 VN4 VN3 VN2 VN1 VN0

QuadLIU V1.1

Electrical Characteristics

7 Electrical Characteristics

7.1 Absolute Maximum Ratings

Note: Stresses greater than those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may reduce device reliability. Table 17 Maximum Ratings Parameter Symbol Limit Values Unit Ambient temperature under bias TA –4 0t o8 5 °C Storage temperature Tstg –6 5t o1 5 0 °C IC supply voltage (digital) VDD – 0.4 to 6.5 V IC supply voltage receive (analog) VDDR – 0.4 to 6.5 V IC supply voltage transmit (analog) VDD X – 0.4 to 6.5 V Voltage on any pin with respect to groundVS – 0.4 to 6.5 V ESD robustness1) H BM: 1.5 kΩ , 100 pF 1) According to MIL-Std 883D, method 3015.7 and ESD Ass. Standard EOS/ESD-5.1-1993. VESD, H BM 2000 V

QuadLIU V1.1

7.2 Operating Range

Note: In the operating range, the functions given in the circuit description are fulfilled. VDD ,VDDR and VDDX have to be connected to the same voltage level, VSS ,VSSR and VSSX have to be connected to ground level. Table 18 Power Supply Range Parameter Symbol Limit Values Unit Test Condition min. max. Ambient temperature TA -40 85 °C Supply voltages V DD V DDR V DD X 3.13 3.46 V 1) 1) Voltage ripple on analog supply less than 50 mV Digital input voltages V ID 05 . 2 5 V Ground V SS V SSR V SS X 00V

QuadLIU V1.1

7.3 DC Characteristics

Parameter Symbol Limit Values Unit Notes min. max. Input low voltage V ILSW –0 . 4 0 . 8 V 1) Input high voltage V IH SW 2.0 5.25 V 1) Output low voltage V OL 0.45 V IOL =+ 2m A 1) Output high voltage V O H 2.4 V IO H = -2m A 1) Average power supply current (Analog line interface) IDDE1 165 mA E1 application 2) IDDT1 200 mA T1/J1 application 3) Average power supply current (Digital line interface) IDD 35 mA Input leakage current IIL11 1 µA VIN =V DD Input leakage current IIL12 1 µA VIN =V SS Input leakage current IIL21 2.5 µA VIN =V DD ;only XL1,XL2 Input leakage current IIL22 2.5 µA VIN =V SS ;only XL1,XL2 Input pullup current IIPU 22 5 µA VIN =V SS ; VDD = 5.0V (typ.: 12µA) 22 5 µA VIN =V SS ; VDD = 3.3V (typ.: 12µA) Output leakage current IO Z 1 µA VOUT = tristate1) VSS < Vmeas <V DD measures against VDD and VSS Transmitter output impedance R X 3 Ω applies toXL1and XL25) Transmitter output currentIX 105 mA XL1,XL2 Transmitter output voltageV X 2.5 V VDD = 3.3V6)

QuadLIU V1.1 Differential peak voltage of am a r k (betweenXL1 andXL2) VD X 2.15 V XL1,XL2 VDD = 3.3V Receiver differential peak voltage of a mark (between RL1 and RL2) VR VDDR + 0.3 V RL1, RL2 Receiver input impedanceZR 50 (typical value) kΩ 5) Receiver sensitivity SRS H 0 -10 dB RL1, RL2 LIM0.EQON = 0 (short-haul) Receiver sensitivity SRL H 0 -36 dB RL1, RL2 LIM0.EQON = 1 (T1/J1, long-haul) -36 RL1, RL2 LIM0.EQON = 1 (E1, long-haul) Receiver input thresholdVRT H (typical value) LIM2.SLT(1:0) = 11 = 10 = 00 = 01 Table 19 DC Parameters (cont’d) Parameter (cont’d) Symbol Limit Values Unit Notes min. max.

QuadLIU V1.1 Note: Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply atTA =2 5°C and 3.3V supply voltage. Loss-O f-Signal (LOS) detection limit in short- haul mode V LOSS H 0.90 0.70 0.60 0.40 0.30 0.20 0.15 0.10 (typical values) V RIL(2:0) = 000 RIL(2:0)= 001 RIL(2:0)= 010 RIL(2:0)= 011 RIL(2:0)= 100 RIL(2:0)= 101 RIL(2:0)= 110 RIL(2:0)= 111 LOS detection limit in long-haul mode V LOSL H 1.70 0.85 0.85 0.45 0.45 0.20 0.10 not defined (typical values) V RIL(2:0) = 000 RIL(2:0)= 001 RIL(2:0)= 010 RIL(2:0)= 011 RIL(2:0)= 100 RIL(2:0)= 101 RIL(2:0)= 110 RIL(2:0)= 111 1) Applies to all pins except analog pins RLx, TLx 2) Wiring conditions and external circuit configuration according toFigure 13on page 45 for E1 mode 120Ω ; PRBS signal;four channels active;values of registersXPM(2:0)= 00H ,0 3H ,7 BH 3) Wiring conditions and external circuit configuration according toFigure 13on page 45 for T1 mode;PRBS signal;four channels active;values of registersXPM(2:0)= 11H ,1 EH ,D 7H 4) Applies to all pins except RCLK,S C LKR, RL1, RL2,XL1,XL2 5) Parameter not tested in production 6) Depending on external configuration 7) Differential input voltage between pins RL1 and RL2;depends on programming of register LIM2.RIL(2:0) Table 19 DC Parameters (cont’d) Parameter (cont’d) Symbol Limit Values Unit Notes min. max.

QuadLIU V1.1

7.4 AC Characteristics

7.4.1 Master Clock Timing

Table 20 MCL K Timing Parameter Values No. Parameter Limit Values Unit Condition min. typ. max.

1 Clock period of MCL K 488 ns E1, fixed mode

648 ns T1/J1, fixed mode 50 980.4 ns flexible mode

2 H igh phase of MCLK 40 %

3 Low phase of MCL K 40 %

Clock accuracy 32 28 ppm 1) 2) 1) to reach an internal clock accuracy of 32 ppm 2) depends on master clock frequency selection / rounding of clock divider setting F0007 MCL K 2 3

QuadLIU V1.1

7.4.2 JTAG Boundary Scan Interface

Figure 21 JTAG Boundary Scan Timing Identification Register : 32 bit;Version: 1H; Part Number: 59H , Manufacturer: 083H Table 21 JTAG Boundary Scan Timing Parameter Values No. Parameter Limit Values Unit min. max.

80 TC K period 250 ns

81 TC K high time 80 ns

82 TC K low time 80 ns

83 TMS setup time 40 ns

84 TMS hold time 40 ns

85 TDI setup time 40 ns

86 TDI hold time 40 ns

87 TDO valid delay 100 ns

88 TRS

88~~

QuadLIU V1.1

7.4.3 Reset

7.4.4 Microprocessor Interface

7.4.4.1 Intel Bus Interface Mode

Figure 23 Intel Non-Multiplexed Address Timing Table 22 Reset Timing Parameter Values No. Parameter Limit Values Unit min. max. 1R E S pulse width low 10 1) 1) while MCLK is running µs F0008 RES WR RD CS BHE Ax 3 3A ITT10975

QuadLIU V1.1 Figure 26 Intel Write Cycle Timing Table 23 Intel Bus Interface Timing Parameter Values No. Parameter Limit Values Unit min. max.

1 Address 1) setup time 15 ns

2 Address hold time 0 ns

4 Address stable before ALE inactive 20 ns

5 Address hold after ALE inactive 10 ns

6 ALE pulse width 30 ns

7 Address latch setup time before cmd active 0 ns

7A ALE to command inactive delay 30 ns 8R D pulse width 80 ns 9R D control interval 70 ns

10 Data 2)valid after RDactive 75 ns

11 Data hold after RD inactive 10 ns

12 WR to RDor RDto WR control interval 70 ns

13 WR pulse width 80 ns

14 WR control interval 70 ns

D8) D7 D0... (D15... ITT06471 WR RD CS 13 14

QuadLIU V1.1

7.4.4.2 Motorola Bus Interface Mode

Figure 27 Motorola Read Cycle Timing

15 Data stable before WR inactive 30 ns

16 Data hold after WR inactive 10 ns

1) Ax refers to address lines A(6:0) 2) Dx refers to data line D(7:0) Table 23 Intel Bus Interface Timing Parameter Values(cont’d) No. Parameter Limit Values Unit min. max. F0062 CS Ax Dx DS RW 19A 20 2122 24 25

QuadLIU V1.1 Figure 28 Motorola Write Cycle Timing Table 24 Motorola Bus Interface Timing Parameter Values No. Parameter Limit Values Unit min. max.

17 Address setup time before DS active 15 ns

18 Address hold after DS inactive 0 ns

19 CS active before DSactive 0 ns

19A CS hold after DSinactive 0 ns

20 RW stable before DSactive 10 ns

21 RW hold after DSinactive 0 ns

22 DS pulse width (read access) 80 ns

22A DS pulse width (write access) 70 ns

23 DS control interval 70 ns

24 Data valid after DS active (read access) 75 ns

25 Data hold after DS inactive (read access) 10 ns

26 Data stable before DS active (write access) 30 ns

27 Data hold after DS inactive (write access) 10 ns

... (D15 D7... D8) RW CS Ax BLE 22A ITT10974 19A

QuadLIU V1.1

7.4.5 Framer Interface

Figure 29 TCL K Input Timing Table 25 TCL K Timing Parameter Values No. Parameter Limit Values Unit min. typ. max. 1T C L K period E1 (2.048 MH z) 488 ns TCL K period T1/J1 (1.544 MH z) 648 ns 2T C L K high 40 % 3T C L K low 40 %

4 XDIP,XDIN setup time 20 ns

5 XDIP,XDIN hold time 20 ns

TCL K (TPE=0) TCL K (TPE=1) XDIP,XDIN 4 5 2 3 data change edge

QuadLIU V1.1 Figure 30 RCL K Output Timing Table 26 RCL K Timing Parameter Values No. Parameter Limit Values Unit min. typ. max. 1 RCL K period E1 (2.048 MH z) 488 ns RCL K period T1/J1 (1.544 MH z) 648 ns

2 RCL K high 40 %

3 RCL K low 40 %

4 RDOP, RDON setup time -10 ns

5 RDOP, RDON hold time 200 ns

RCL K (RPE=1) RCL K (RPE=0) RDOP, RDON 4 5 2 3 data change edge

QuadLIU V1.1 Table 27 SYNC Timing Parameter Values No. Parameter Limit Values Unit min. typ. max. 1 SYNC period (SYNC = 2.048 MH z) 488 µs SYNC period (SYNC = 1.544 MH z) 648 µs SYNC period (SYNC = 8k H z) 125 ms

2 SYNC low time 20 %

QuadLIU V1.1 Table 28 FSC Timing Parameter Values No. Parameter Limit Values Unit min. typ. max. 1F S C period 125 µs 2F S C low time E1 488 ns FSC low time T1/J1 648 ns

3 RCL K to FSCdelay E1 370 ns

RCL K to FSCdelay T1/J1 280 ns F0053 FSC RCL K

QuadLIU V1.1

7.4.6 Pulse Templates - Transmitter

7.4.6.1 Pulse Template E1

Figure 33 E1 Pulse Shape at Transmitter Output ITD00573 10 % 10 %%10 10 % %1010 % 20 % 269 ns (244 + 25) (244 - 50) ns194 219 ns (244 - 25) ns244 (244 + 244) ns488 50 % %V=100 Nominal Pulse %2020 %

QuadLIU V1.1

7.4.6.2 Pulse Template T1

Table 29 T1 Pulse Template (ANSI T1.102) Maximum Curve Minimum Curve Time [ns] Level [ % ]1) 1) 100 % value must be in the range of 2.4 V and 3.6 V; tested at 0 ft and 655 ft using PIC 22AWG cable characteristics. Time [ns] Level [ % ] 050 - 5 2 5 053 5 0 - 5 325 80 350 50 325 115 400 95 425 115 500 95 500 105 600 90 675 105 650 50 725 -7 650 -45 1100 5 800 -45 1250 5 925 -20 1100 -5 1250 -5 ITD00574 %100=V 50 % -50 % 0 250 500 750 1000 ns t Normalized Amplitude

QuadLIU V1.1

7.5 Capacitances

7.6 Package Characteristics

Figure 35 Thermal Behaviour of Package Table 30 Pin Capacitances Parameter Symbol Limit Values Unit Notes min. max. Input capacitance1) 1) not tested in production C IN 51 0 p F Output capacitance1) C OUT 8 15 pF all except XLx.y Output capacitance1) C OUT 82 0 p F XLx.y Table 31 Package Characteristic Values Parameter Symbol Limit Values Unit Notes min. typ. max. Thermal resistance1) 1) R th= (Tjunction-Tambient)/Power Not tested in production. Rth 44 K/W single layer PCB, no convection

36 K/W air flow 200 LFPM

32 K/W air flow 500 LFPM

Junction temperature Rj 125 °C F0051

QuadLIU V1.1

7.7 Test Configuration

Figure 36 Input/Output Waveforms for AC Testing Typical characteristics are mean values expected over the production spread. If not specified otherwise, typical characteristics apply atTA = 25 °Ca n dVDD = 3.3V. Table 32 AC Test Conditions Parameter Symbol Test Values Unit Notes Load capacitance C L 50 pF Input voltage high VIH 2.4 V all except RLx.y Input voltage low VIL 0.4 V all except RLx.y Test voltage high VTH 2.0 V all except XLx.y Test voltage low VTL 0.8 V all except XLx.y F0067 Timing Test Points VTH VTL Device under Test C L Test Levels VIH VIL Drive Levels

QuadLIU V1.1 Package Outlines Data Sheet 118 2001-02

8 Package Outlines

(Plastic Metric Quad Flat Package) GPP09189 SMD = Surface Mounted Device Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm

QuadLIU V1.1 Appendix Data Sheet 119 2001-02 9A p p e n d i x

9.1 Application Notes

Online access to supporting information is available on the internet page: http://www.infineon.com/falc On the same page you find as well the  Boundary Scan File for QuadLIU™ Version 1.1 (BSDL File)

9.2 Software Support

The following tool package is provided together with the QuadLIU™ Evaluation System EASY22504:  Flexible Master Clock Calculator  External Line Front End Calculator  IBIS Model for QuadLIU™ V1.1 (according to ANSI/EIA-656) To make system design easier, two software tools are available. The first is the “Master Clock Frequency Calculator", which calculates the required register settings depending on the external master clock frequency (Figure 37). The second is the “External Line Front End Calculator” which provides an easy method to optimize the external components depending on the selected application type. Calculation results are traced and can be stored in a file or printed out for documentation (Figure 38). The tools run under a Windows ® environment. Screenshots of the programs are shown in the figures below.

QuadLIU V1.1 Appendix Data Sheet 120 2001-02 Figure 37 Master Clock Frequency Calculator F0126

QuadLIU V1.1 Appendix Data Sheet 121 2001-02 Figure 38 External Line Frontend Calculator F0194

QuadLIU V1.1 Glossary Data Sheet 122 2001-02

10 Glossary

ADC Analog-to-Digital Converter AIS Alarm Indication Signal (blue alarm) AGC Automatic Gain Control ALOS Analog Loss-Of-Signal AMI Alternate Mark Inversion ANSI American National Standards Institute ATM Asynchronous Transfer Mode B8ZS Line coding to avoid too long strings of consecutive ’0’ BER Bit Error Rate Bellcore BELL COmmunications REsearch (see: Telcordia) BPV BiPolar Violation CVC Code Violation Counter DCO Digitally Controlled Oscillator DL Digital Loop DPLL Digitally controlled Phase-Locked Loop DS1 Digital Signal level 1 ESD ElectroStatic Discharge EASY EvAluation SYstem for FALC/LIU products EQ EQualizer ETSI European Telecommunication Standards Institute FALC ® Framing And Line interface Component FCC US Federal Communication Commission H BM H uman Body Model for ESD classification H DB3 H igh-Density Bipolar of order 3 IBIS I/O Buffer Information Specification (ANSI/EIA-656) IBL In Band Loop ( =LLB) ISDN Intergrated sevices digital network ITU International Telecommunications Union JATT Jitter ATTenuator

QuadLIU V1.1 Glossary Data Sheet 123 2001-02 JTAG Joined Test Action Group LBO Line Build Out LCV Line Code Violation LIU Line Interface Unit LL Local Loop LLB Line Loop Back ( = IBL) LOS Loss-Of-Signal (red alarm) LSB Least Significant Bit MSB Most Significant Bit NR Z N o nR e t u r nt oZero signal PDV Pulse-Density Violation PLL Phase-Locked Loop PRBS Pseudo Ramdom Binary Sequence P-TQFP Plastic Thin metric Quad Flat Pack (device package) RAI Remote Alarm Indication (yellow alarm) RL Remote Loop Sidactor Overvoltage protection device for transmission lines TAP Test Access Port Telcordia New organization name, former ’Bellcore’ UI Unit Interval

QuadLIU V1.1 Data Sheet 124 2001-02 Index A ACS 46, 70 AIS 39, 89, 93 AISM 82 AlarmH andling 39 Alarm Simulation 54 ANSI T1.102 47 ANSI T1.231 13, 39, 71, 89, 90 ANSI T1.403 13, 39, 47, 50, 67, 89, 90 ANSI/EIA-656 119 Application Notes 119 Applications 16 ARL 50, 62 B Blue Alarm 39 Boundary Scan 33, 104, 119 Buffer 44 C CEB 83 CIS 30 Clock and Data Recovery 38 Clock Mode Register Settings 87 Clocking Modes 41 Clocking Unit 35 CMDR 83 CMR 72 CV 96 D Data Strobe 19 DBEC 83 DCF 68 DCO 40, 41 DCS 72 DCVC 83 Digital Loop 53 DLB 53 DSS 72 DSS0 72 DSS1 72 E EASY22504 119 ECM 64 ECMIR 64 ECMI X 64 ELT 72 EPRM 67 EQON 64 Equalizer 37 Error Counter 49 ESD 98 ETS 300011 13 ETS 300233 13, 39, 40, 89 EV 92 External Line Front End Calculator 119 EXZ D8 9 EXZ E6 2 F FCC Part68 67 Flexible Clock Mode Settings 87 Flexible Master Clock 119 FSC0 60 FSC1 60 G gapped clocks 40 GCM1 84 GCM2 84 GCM3 85 GCM4 85 GCM5 86 GCM6 86 GCR 60, 61 GCR2 61 GIS 95 GTP 67 I IBIS Model 119

QuadLIU V1.1 Data Sheet 125 2001-02 IBV 83 IC 61 IEEE 1149.1 14, 33 IMR0 82 IMR1 82 In-Band Loop 50 Initialization in E1 Mode 56 INT 30 Interrupt Interface 30 IPE 83 IPRBS 67 ITU-T G.703 40 ITU-T G.735 42 ITU-T G.736 13, 40 ITU-T G.775 13, 39, 89 ITU-T G.823 13, 40 ITU-T I.431 13, 40, 42, 47 ITU-T O.151 49, 68 J JATT 40 Jitter 40 Jitter Attenuator 40 Jitter Tolerance 43 L LAC 81 LACL 80 LBO1 67 LBO2 67 LCR1 80 LCR2 81 LCR3 81 LDC 81 LDCL 80 LIM0 62 LIM1 64 LIM2 66 LIM3 67 LIM4 68 LIM5 70 Line Build-Out 47 Line Coding 38 LL 52 LLBAD 89 LLBDD 89 LLBSC 93 LLBSCM 82 Local Loop 52 Long H aul 36 LOOP 74 loop down 50 loop up 50 LOS 89, 93, 102 LOSM 82 LOSR0 70 LOSR1 70 Loss-of-Signal 39 LTC 94 LTCM 82 M MAS 72 Master Clock Range 86 MCL K_L O W8 6 Microprocessor Interface 30, 105 MIL-Std 883D 98 MTP 67 O One-Second Timer 49 Output Jitter 44 P Payload Loop Back 54 PC0 68 PC1 68 PC2 68 PCD 79 PCR 79 PD 64 PDE 46, 62 PDEN 39, 89 PDENI 93 PMOD 61 P-MQFP-80-1 118

QuadLIU V1.1 Data Sheet 126 2001-02 PRBSS 89 PRBSSC 93 PRBSSCM 82 Pseudo-Random Bit Sequence 49 Pulse Density 39, 46 Pulse Shaper 47 Pulse Template 114, 115 R R1S0 60 R1S1 60 RC0 62 RC1 62 RD0 66 RD1 66 RDON0 64 RDON1 64 Read/Write Enable 20 Receive Equalization Network 37 Receive Line Attenuation Indication 37 Receive Line Interface 36 Receiver Configuration 36, 45 Red Alarm 39 Register Addresses 59, 88 Remote Loop 51 RES 83 Reset 56, 105 RIL0 66 RIL1 66 RIL2 66 RLS 89 RPE 68 RS0 72 RS1 72 S SCF 72 SCI 68 SEC 94 SECM 82 ShortH aul 36 SIM 62 Single Channel Loop Back 54 SLN 93 SLNM 82 SLP 93 SLPM 82 SLT0 66 SLT1 66 SPRBS 67 SSF0 60 SSF1 60 Status Register 88 Supply voltage 99 T TBR12 13, 40, 42 TBR13 13, 40, 42 TCS 91 Test Access Port 33 TPE 46, 68 TR43802 40 TR62411 13, 14, 40, 49 Transmit Clock 46 Transmit Data Monitoring 55 Transmit Line Interface 45 Transmit Line Monitor 48 Transmit Pulse Mask 76 TR-WT-499 89 V Version Number 97 Version Status Register 97 VFREQ_EN 84 VIS 68 VN 97 W Wander 40 X XAIS 64 XC0 62 XC1 62 XDPM 70 XLA 80

QuadLIU V1.1 Data Sheet 127 2001-02 XLB 70 XLD 80 XLM 70 XLO 91 XLS 91 XLSC 93 XLSCM 82 XPM0 76 XPM1 76 XPM2 76 XPRBS 67

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