PEB1760 INFINEON | Alldatasheet

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Technical content

Features

I Multi-Rate SONET/SDH framer with STS/AU and VT/TU pointer processing capabilities I Processes a single STS-12/STM-4 or a quad STS-3/STM-1 I Supports 1+1 line protection I Payload Pointer interpretation and generation I Fully SONET/SDH compliant I Provides full performance moni- toring for high- and low-order paths I Provides high-order and low-order virtual concatenation according to ITU-T G.707 I Supports up to 64 virtual concate- nated groups (VCG) I Flexible concatenation of up to 12 high-order paths and up to 64 low-order paths into any virtual concatenation group I Supports up to 336 VT1.5 or

252 TU12 low-order paths

I Provides following mapping schemes: - AU-4 / VC-4 / TUG-3 - AU-3 / VC-3 or STS-1 / STS-SPE I External buffer for up to 48 ms differential delay compensation I Different VCG group types are defined: -N × VC-12, N × VC-11, N × VT1.5 SPE, N × VT2 SPE (N ≤ 64) -N × VC-3, N × STS1 SPE (N ≤ 12) -N × VC-4, N × STS3c SPE (N ≤ 4) I Provides flexible mapping of any VCG into any VC-4/STS-3 I Fully integrated support for the Link Capacity Adjustment Scheme (LCAS) protocol according to ITU-T G. 7042 I Provides hitless increase and decrease of multiple members VCG SPI-3 Interface I 64 logical channels each of them running in 32-bit mode I Packet mode with variable block length

Published by Infineon Technologies AG How to reach us: http://www.infineon.com Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81669 München © Infineon Technologies AG 2003. All Rights Reserved. Template: pb_tmplt.fm/4/2003-07-01 Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office. Warnings Due to technical requirements components may contain dan- gerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life- support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or main- tain and sustain and/or protect human life. If they fail, it is rea- sonable to assume that the health of the user or other persons may be endangered. P RODUCT B RIEF Ethernet Switch TDM Switch SMII SMII SMII TBI TBI Quad STM-1 Single STM-4 working & protect Up to 2 TBI or 16 SMII MetroMapperTM 622 STM-4 / STS-12 VC-LCAS Mapper&Framer Application Example Ethernet over SDH/SONET Ordering No. B115-H8290-X-X-7600 Printed in Germany PS 1003.5 R&L Features (cont’d) Encapsulation/Decapsulation I Provides GFP-F mapping according to T1X1.5 / ITU-T G. 7041 I PPP processing according to IETF RFC 1662 I LAPS processing according to ITU-T X.85+X.86 I 64 logical channels, each of them can be independently configured to oper- ate in one of the three encapsulation protocols I PPP protocol support: MPLS Unicast & IP Version 4/6 I LAPS protocol support: Ethernet and IP Version 4/6 I FCS generation/checking I Optional payload scrambling I Idle frame insertion/deletion I GFP Client management frame inser- tion/detection I Comprehensive statistic counters for packets I Packet import/export from/to CPU interface Layer 2 I Supported on both SDH and Ethernet ports I IEEE802.1q VLAN tag operations per port/VLAN pair I Up to 4096 port/VLAN pairs in total I VLAN update include tag, retag and replace of VLAN IDs I 0 or 1 VLAN can be inserted/removed I Supports VLAN double tagging I IETF Ethernet Martini MPLS label encapsulation per port/VLAN pair I Supports IP/MPLS and Ethernet packets I Per port tunneling mode I Per port Ethernet MAC termination mode with packet classification as Ethernet, IP, MPLS or Layer-2 control packets Ethernet I Two Gigabit Ethernet MACs with TBI Interfaces I Sixteen Ethernet/Fast Ethernet with integrated SS-SMII Interfaces I Per port MIB statistic counter per direction I MAC pause frame control per port via: - Flexible leaky bucket implementation - Current RxFIFO threshold level - Under software control I Flow control makes use of external memory for both directions I Fixed Rx Buffer size: 32 kB for FE and 256 kB for GE ports I Received flow control frames are passed through or discarded I Jumbo packets supported I All Ethernet ports may operate in MAC or PHY mode: - PHY mode allows glueless connec- tions to another MAC/Ethernet switch I Each Ethernet port maps to a single VCG Diagnostics I Various loop back modes for system debugging implemented - Per SDH/SONET port Rx to Tx - Per Ethernet port in to out - SPI-3 input to SPI-3 output Interfaces I Source synchronous STS-12/STM-4 or quad STS-3/STM-1 interfaces for working and protected links operating at 155 MHz I/Os I OIF compliant SPI-3 interface I Two TBI interfaces for GE I 16 SS-SMII interfaces for FE I Depending on application, up to

5 SRAM interfaces 32/36 bits data

I IEEE 1149.1 JTAG boundary scan interface I 1.5 V Core I 2.5 V and 3.3 V IOs I 1020 pin FCBGA package