PE811

STMPE811_V01 STMICROELECTRONICS | Alldatasheet

Document overview

• Manufacturer or author: STMICROELECTRONICS
• PDF pages: 66

Technical content

Datasheet sections

• 1 STMPE811 functional overview
• 2 Pin configuration and f unctions
• 2.1 Pin functions
• 3 I2C and SPI interface
• 3.1 Interface selection
• 4 I2C interface
• 4.1 I2C features
• 4.2 Data input
• 4.3 Read operation
• 4.4 Write operations
• 5 SPI interface
• 5.1 SPI protocol definition
• 5.1.1 Register reading
• 5.1.2 Register write
• 5.1.3 Termination of data transfer
• 5.2 SPI timing modes
• 5.2.1 SPI timing definition
• 6 STMPE811 registers
• 7 System and identificati on registers
• 8 Interrupt system
• 9 Analog-to-digital converte r
• 10 Touchscreen controller
• 10.1 Driver and switch control unit
• 11 Touchscreen controller programming sequence

Features

■ 8 GPIOs ■ 1.8 - 3.3 V operating voltage ■ Integrated 4-wire touchscreen controller ■ Interrupt output pin ■ Wakeup feature on each I/O ■ SPI and I2C interface ■ Up to 2 devices sharing the same bus in I2C mode (1 address line) ■ 8-input 12-bit ADC ■ 128-depth buffer touchscreen controller ■ Touchscreen movement detection algorithm ■ 25 kV air-gap ESD protection (system level) ■ 4 kV HBM ESD protection (device level)

Applications

■ Portable media players ■ Game consoles ■ Mobile and smartphones ■ GPS

Description

The STMPE811 is a GPIO (general purpose input/output) port expander able to interface a main digital ASIC via the two-line bidirectional bus 2C). A separate GPIO expander is often used in mobile multimedia platforms to solve the problems of the limited amount of GPIOs typically available on the digital engine. The STMPE811 offers great flexibility, as each I/O can be configured as input, output or specific functions. The device has been designed with very low quiescent current and includes a wakeup feature for each I/O, to optimize the power consumption of the device. A 4-wire touchscreen controller is built into the STMPE811. The touchscreen controller is enhanced with a movement tracking algorithm (to avoid excessive data), a 128 x 32 bit buffer and programmable active window feature. QFN16 (3x3) Table 1. Device summary

Table 21. DC electrical characteristics (-40 °C to 85 °C) all GPIOs comply to JEDEC standard JESD-

1 STMPE811 functional overview

• I2C and SPI interface
• Analog-to-digital converver (ADC)
• Touchscreen controller (TSC)
• Driver and switch control unit
• Temperature sensor
• GPIO controller

Figure 1. STMPE811 functional block diagram

2 Pin configuration and functions

Figure 2. STMPE811 pin configuration (top through view) Table 2. Pin assignments

1 Y - Y -/GPIO-7

2 INT Interrupt output (V CC domain), open drain

3 A0/Data Out I 2C address in Reset, Data out in SPI mode (VCC domain)

7 Data in SPI Data In (V CC domain)

8 IN0 IN0/GPIO-0

10 GND Ground

11 IN2 IN2/GPIO-2

12 IN3 IN3/GPIO-3

13 X+ X+/GPIO-4

14 Vio Supply for touchscreen driver and GPIO

15 Y+ Y+/GPIO-5

16 X- X-/GPIO-6

2.1 Pin functions

Table 3. Pin configuration for IN2, IN3 Table 4. Pin configuration for X+, Y+, X-, Y-

3 I 2C and SPI interface

3.1 Interface selection

the selection of interface protocol at reset state. Figure 3. STMPE811 interface Table 5. Interface selection pins

3 Address 0 Data out CPHA for SPI

5 SDATA CS CPOL_N for SPI

4 I 2C interface

Figure 4. STMPE811 I 2C interface responding to the transaction. Figure 5. I 2C timing diagram Table 6. I 2C address

Table 7. I 2C timing

4.1 I 2C features

The features that are supported by the I2C interface are listed below:

• I2C slave device
• Operates at 1.8 V
• Compliant to Philips I2C specification version 2.1
• Supports standard (up to 100 Kbps) and fast (up to 400 Kbps) modes Start condition A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and does not respond to any transaction unless one is encountered. Stop condition A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates communication between the slave device and the bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I 2C transaction. A Stop condition at the end of a write command stops the write operation to registers. Acknowledge bit The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it does not acknowledge the receipt of the data.

4.2 Data input

only when SCLK is driven low. Figure 6. Read and write modes (random and sequential) Table 8. Operating modes every byte of data being read. for the address ranges that are auto and non-increment.

4.3 Read operation

A write is first performed to load the register address into the Address Counter but without sending a Stop condition. Then, the bus master sends a reStart condition and repeats the Device Address with the R/W bit set to 1. The slave device acknowledges and outputs the content of the addressed byte. If no additional data is to be read, the bus master must not acknowledge the byte and terminates the transfer with a Stop condition. If the bus master acknowledges the data byte, then it can continue to perform the data reading. To terminate the stream of data bytes, the bus master must not acknowledge the last output byte, and be followed by a Stop condition. If the address of the register written into the Address Counter falls within the range of addresses that has the auto-increment function, the data being read are coming from consecutive addresses, which the internal Address Counter automatically increments after each byte output. After the last memory address, the Address Counter 'rolls-over' and the device continues to output data from the memory address of 0x00. Similarly, for the register address that falls within a non-increment range of addresses, the output data byte comes from the same address (which is the address referred by the Address Counter). Acknowledgement in read operation For the above read command, the slave device waits, after each byte read, for an acknowledgement during the ninth bit time. If the bus master does not drive the SDA to a low state, then the slave device terminates and switches back to its idle mode, waiting for the next command.

4.4 Write operations

A write is first performed to load the register address into the Address Counter without sending a Stop condition. After the bus master receives an acknowledgement from the slave device, it may start to send a data byte to the register (referred by the Address Counter). The slave device again acknowledges and the bus master terminates the transfer with a Stop condition. If the bus master needs to write more data, it can continue the write operation without issuing the Stop condition. Whether the Address Counter autoincrements or not after each data byte write depends on the address of the register written into the Address Counter. After the bus master writes the last data byte and the slave device acknowledges the receipt of the last data, the bus master may terminate the write operation by sending a Stop condition. When the Address Counter reaches the last memory address, it 'rolls-over' to the next data byte write.

5 SPI interface

The SPI (serial peripheral interface) in STMPE811 uses a 4-wire communication connection (DATA IN, DATA OUT, CLK, CS). In the diagram, “Data in” is referred to as MOSI (master out slave in) and “DATA out” is referred to as MISO (master in slave out).

5.1 SPI protocol definition

The SPI follows a byte-sized transfer protocol. All transfers begin with an assertion of CS_n signal (falling edge). The protocol for reading and writing is different and the selection between a read and a write cycle is dependent on the first captured bit on the slave device. A '1' denotes a read operation and a '0' denotes a write operation. The SPI protocol defined in this section is shown in Figure 3. The following are the main features supported by this SPI implementation.

• Support of 1 MHz maximum clock frequency.
• Support for autoincrement of address for both read and write.
• Full duplex support for read operation.
• Daisy chain configuration support for write operation.
• Robust implementation that can filter glitches of up to 50 ns on the CS_n and SCL pins.
• Support for all 4 modes of SPI as defined by the CPHA, CPOL bits on SPICON.

5.1.1 Register reading

The following steps need to be followed for the register read through the SPI. 1. Assert CS_n by driving a '0' on this pin. 2. Drive a '1' on the first SCL launch clock on MOSI to select a read operation. 3. The next 7 bits on MOSI denote the 7-bit register address (MSB first). 4. The next address byte can now be transmitted on the MOSI. If the autoincrement bit is set, the following address transmitted on the MOSI is ignored. Internally, the address is incremented. If the autoincrement bit is not set, then the following byte denotes the address of the register to be read next. 5. Read data is transmitted by the slave device on the MISO (MSB first), starting from the launch clock following the last address bit on the MOSI. 6. Full duplex read operation is achieved by transmitting the next address on MOSI while the data from the previous address is available on MISO. 7. To end the read operation, a dummy address of all 0's is sent on MOSI.

5.1.2 Register write

The following steps need to be followed for register write through SPI. 1. Assert CS_n by driving a '0' on this pin. 2. Drive a '0' on the first SCL launch clock on MOSI to select a write operation. 3. The next 7 bits on MOSI denote the 7-bit register address (MSB first). 4. The next byte on the MOSI denotes data to be written. 5. The following transmissions on MOSI are considered byte-sized data. The register address to which the following data is written depends on whether the autoincrement bit in the SPICON register is set. If this bit has been set previously, the register address is incremented for data writes.

5.1.3 Termination of data transfer

A transfer can be terminated before the last launch edge by deasserting the CS_n signal. If the last launch clock is detected, it is assumed that the data transfer is successful.

5.2 SPI timing modes

the next transaction defined by the CS_n pin being deasserted and asserted.

5.2.1 SPI timing definition

Table 9. SPI timing modes Table 10. SPI timing specification

Figure 7. SPI timing specification Table 10. SPI timing specification (continued)

6 STMPE811 registers

register map and then provides detailed descriptions of register types. Table 11. Register summary map table

Table 11. Register summary map table (continued)

7 System and identification registers

Table 12. System and identification registers map

STMPE811 System and identification registers Doc ID 14489 Rev 5 23/66 SYS_CTRL1 Reset control Address: 0x03 Type: R/W Reset: 0x00 Description: The reset control register enables to reset the device SYS_CTRL2 Clock control Address: 0x04 Type: R/W Reset: 0x0F Description: This register enables to switch off the clock supply 76543 2 1 0 RESERVED SOFT_RESET HIBERNATE [7:2] RESERVED [1] SOFT_RESET: Reset the STMPE811 using the serial communication interface [0] HIBERNATE: Force the device into hibernation mode. Forcing the device into hibernation mode by writing ‘1’ to this bit would disable the hot-key feature. If the hot-key feature is required, use the default auto-hibernation mode. 76543 2 1 0 [7:4] RESERVED [3] TS_OFF: Switch off the clock supply to the temperature sensor 1: Switches off the clock supply to the temperature sensor [2] GPIO_OFF: Switch off the clock supply to the GPIO 1: Switches off the clock supply to the GPIO [1] TSC_OFF: Switch off the clock supplyto the touchscreen controller 1: Switches off the clock supply to the touchscreen controller [0] ADC_OFF: Switch off the clock supply to the ADC 1: Switches off the clock supply to the ADC

System and identification registers STMPE811 24/66 Doc ID 14489 Rev 5 SPI_CFG SPI interface configuration Address: 0x08 Type: R/W Reset: 0x01 Description: SPI interface configuration register 76543 2 1 0 RESERVED AUTO_INCR SPI_CLK_MOD1 SPI_CLK_MOD0 [7:3] RESERVED [2] AUTO_INCR: This bit defines whether the SPI transaction follows an addressing scheme that internally autoincrements or not [1] SPI_CLK_MOD1: This bit reflects the value of the SCAD/A0 pin during power-up reset [0] SPI_CLK_MOD0: This bit reflects the value of the SCAD/A0 pin during power-up reset

8 Interrupt system

Figure 8. Interrupt system diagram

INT_CTRL Interrupt control register Address: 0x09 Type: R/W Reset: 0x00 Description: The interrupt control register is used to enable the interruption from a system-related interrupt source to the host. 76543 2 1 0 RESERVED INT_POLARITY INT_TYPE GLOBAL_INT [7:3] RESERVED [2] INT_POLARITY: This bit sets the INT pin polarity 1: Active high/rising edge 0: Active low/falling edge [1] INT_TYPE: This bit sets the type of interrupt signal required by the host 1: Edge interrupt 0: Level interrupt [0] GLOBAL_INT: This is master enable for the interrupt system 1: Global interrupt 0: Stops all interrupts

INT_EN Interrupt enable register Address: 0x0A Type: R/W Reset: 0x00 Description: The interrupt enable register is used to enable the interruption from a system related interrupt source to the host. INT_STA Interrupt status register Address: 0x0B Type: R Reset: 0x10 Description: The interrupt status register monitors the status of the interruption from a particular interrupt source to the host. Regardless of whether the INT_EN bits are enabled, the INT_STA bits are still updated. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect. 76543 2 1 0 GPIO ADC TEMP_SENS FIFO_EMPTY FIFO_FULL FIFO_0FLOW FIFO_TH TOUCH_DET [7] GPIO: Any enabled GPIO interrupts [6] ADC: Any enabled ADC interrupts [5] TEMP_SENS: Temperature threshold triggering [4] FIFO_EMPTY: FIFO is empty [3] FIFO_FULL: FIFO is full [2] FIFO_OFLOW: FIFO is overflowed [1] FIFO_TH: FIFO is equal or above threshold value. [0] TOUCH_DET: Touch is detected 76543 2 1 0 GPIO ADC TEMP_SENS FIFO_EMPTY FIFO_FULL FIFO_OFLOW FIFO_TH TOUCH_DET [7] GPIO: Any enabled GPIO interrupts [6] ADC: Any enabled ADC interrupts [5] TEMP_SENS: Temperature threshold triggering [4] FIFO_EMPTY: FIFO is empty [3] FIFO_FULL: FIFO is full [2] FIFO_OFLOW: FIFO is overflowed [1] FIFO_TH: FIFO is equal or above threshold value. This bit is set when FIFO level equals to threshold value. It will only be asserted again if FIFO level drops to < threshold value, and increased back to threshold value. [0] TOUCH_DET: Touch is detected

GPIO_INT_EN GPIO interrupt enable register Address: 0x0C Type: R/W Reset: 0x00 Description: The GPIO interrupt register enables the GPIO interruption of a particular GPIO source to the host. GPIO_INT_STA GPIO interrupt status register Address: 0x0D Type: R Reset: 0x00 Description: The GPIO interrupt status register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless of whether or not the GPIO_INT_STA bits are enabled, the corresponding GPIO_STA bits are still updated. The ISG[7:0] bits are the interrupt status bits corresponding to the GPIO[7:0] pins. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect. 76543 2 1 0 IEG[x] [7:0] IEG[x]: Interrupt enable GPIO mask (where x = 7 to 0) 1: Writing ‘1’ to the IE[x] bit enables the interruption to the host 76543 2 1 0 ISG[x] [7:0] ISG[x]: GPIO interrupt status (where x = 7 to 0) Read: Interrupt status of the GPIO[x]. Reading the register clears any bits that have been set to '1' Write: Writing to this register has no effect

ADC_INT_EN ADC interrupt enable register Address: 0x0E Type: R/W Reset: 0x00 Description: The ADC enable register enables the interruption of a particular ADC source to the host. ADC_INT_STA ADC interrupt status register Address: 0x0F Type: R Reset: 0x00 Description: The ADC interrupt status register monitors the status of the interruption from a particular ADC source to the host. Regardless of whether or not the ADC_INT_EN bits are enabled, the corresponding ADC_STA bits are still updated. The ISA[7:0] bits are the interrupt status bits corresponding to the ADC[7:0] pins. Writing '1' to this register clears the corresponding bits. Writing '0' has no effect. 76543 2 1 0 IEAC[x] [7:0] IEAC[x]: Interrupt enable ADC mask (where x = 7 to 0) 1: Writing ‘1’ to the IE[x] bit enables the interruption to the host 76543 2 1 0 ISA[x] [7:0] ISA[x]: ADC interrupt status (where x = 7 to 0) Read: Interrupt status of the ADC[x]. Reading the register clears any bits that have been set to '1' Write: Writing to this register has no effect. Note: Refer to Table 13 for the associated ADC intput pins to each ADC channels.

9 Analog-to-digital converter

of controlling a 4-wire resistive touchscreen. Table 13. ADC controller register summary table

STMPE811 Analog-to-digital converter Doc ID 14489 Rev 5 31/66 ADC_CTRL1 ADC control 1 Address: 0x20 Type: R/W Reset: 0x1C Description: ADC control register. 7 6 5 4 3 210 RESERVED SAMPLE_TIME2 SAMPLE_TIME1 SAMPLE_TIME0 MOD_12B RESERVED REF_SEL RESERVED [7] RESERVED [6:4] SAMPLE_TIMEn: ADC conversion time in number of clock 000: 36 001: 44 010: 56 011: 64 100: 80 101: 96 110: 124 111: Not valid [3] MOD_12B: Selects 10 or 12-bit ADC operation 1: 12 bit ADC 0: 10 bit ADC [2] RESERVED [1] REF_SEL: Selects between internal or external reference for the ADC 1: External reference 0: Internal reference [0] RESERVED

Analog-to-digital converter STMPE811 32/66 Doc ID 14489 Rev 5 ADC_CTRL2 ADC control 2 Address: 0x21 Type: R/W Reset: 0x01 Description: ADC control. ADC_CAPT ADC channel data capture Address: 0x22 Type: R/W Reset: 0xFF Description: To initiate ADC data acquisition. 76543 2 1 0 RESERVED ADC_FREQ_1 ADC_FREQ_0 [7] RESERVED [6] RESERVED [5] RESERVED [4] RESERVED [3] RESERVED [2] RESERVED [1:0] ADC_FREQ: Selects the clock speed of ADC 00: 1.625 MHz typ. 01: 3.25 MHz typ. 10: 6.5 MHz typ. 11: 6.5 MHz typ. 76543 2 1 0 CH[7:0] [7:0] CH[7:0]: ADC channel data capture Write '1' to initiate data acquisition for the corresponding channel. Writing '0' has no effect. Reads '1' if conversion is completed. Reads '0' if conversion is in progress.

and the clock division field 'Freq'. Table 14. ADC conversion time

6.5 MHz

3.25 MHz

1.625 MHz

10 Touchscreen controller

and interrupt the connected CPU only when a pre-defined event occurs. Figure 9. Touchscreen controller block diagram

10.1 Driver and switch control unit

the coordination of this unit, a stream of data is produced at a selected frequency. is limited to these values. Tolerance of these current setting is +/- 25%. is shorter than the tracking index, it is discarded. to ensure that a slow touch is not discarded.

Table 15. Touchscreen controller register summary table

STMPE811 Touchscreen controller Doc ID 14489 Rev 5 37/66 TSC_CTRL touchscreen controller control register Address: 0x40 Type: R/W Reset: 0x90 Description: 4-wire touchscreen controller (TSC) setup. 76543 2 1 0 TSC_STA TRACK OP_MOD EN [7] TSC_STA: TSC status Reads '1' when touch is detected Reads '0' when touch is not detected Writing to this register has no effect [6:4] TRACK: Tracking index 000: No window tracking 001: 4 010: 8 011: 16 100: 32 101: 64 110: 92 111: 127 [3:1] OP_MOD: TSC operating mode 000: X, Y , Z acquisition 001: X, Y only 010: X only 011: Y only 100: Z only This field cannot be written on, when EN = 1 [0] EN: Enable TSC

Touchscreen controller STMPE811 38/66 Doc ID 14489 Rev 5 TSC_CFG Touchscreen controller configuration register Address: 0x41 Type: R/W Description: Touchscreen controller configuration register. 76543 2 1 0 AVE_CTRL_1 AVE_CTRL_0 TOUCH_DET _DELAY_2 TOUCH_DET _DELAY_1 TOUCH_DET _DELAY_0 SETTLING_2 SETTLING_1 SETTLING_0 [7:6] [ AVE_CTRL_1/0: Average control 00=1 sample 01=2 samples 10=4 samples 11=8 samples [5:3] TOUCH_DET_DELAY_2/1/0: Touch detect delay 000 - 10 μs 001 - 50 μs 010 = 100 μs 011 = 500 μs 1 0 0=1m s 1 0 1=5m s 110 = 10 ms 111 = 50 ms [2:0] SETTLING: Panel driver settling time (1) 000 = 10 μs 001 = 100 μs 010 = 500 μS 0 1 1= 1m s 1 0 0=5m s 101 = 10 ms 110 = 50 ms 1 1 1= 1 0 0m s 1. For large panels (> 6”), a capacitor of 10 nF is reco mmended at the touchscreen terminals for noise filtering. In this case, settling time of 1 ms or more is recommended.

STMPE811 Touchscreen controller Doc ID 14489 Rev 5 39/66 WDW_TR_X Window setup for top right X Address: 0x42 Type: R/W Reset: 0x0FFF Description: Window setup for top right X coordinates. WDW_TR_Y Window setup for top right Y Address: 0x44 Type: R/W Reset: 0x0FFF Description: Window setup for top right Y coordinates. 7 6543 2 1 0 TR_X [11:0] [11:0] TR_X: Bit 11:0 of top right X coordinates 7 6543 2 1 0 TR_Y [11:0] [11:0] TR_X: Bit 11:0 of top right Y coordinates

Touchscreen controller STMPE811 40/66 Doc ID 14489 Rev 5 WDW_BL_X Window setup for bottom left X Address: 0x46 Type: R/W Reset: 0x0000 Description: Window setup for bottom left X coordinates. WDW_BL_Y Window setup for bottom left Y Address: 0x48 Type: R/W Reset: 0x0000 Description: Window setup for bottom left Y coordinates. FIFO_TH FIFO threshold Address: 0x4A Type: R/W Reset: 0x00 Description: Triggers an interrupt upon reaching or exceeding the threshold value. This field must not be set as zero. 7 6543 2 1 0 BL_X [11:0] [11:0] BL_X: Bit 11:0 of bottom left X coordinates 7 6543 2 1 0 BL_Y [11:0] [11:0] BL_X: Bit 11:0 of bottom left Y coordinates 76543 2 1 0 FIFO_TH [7:0] FIFO_TH: touchscreen controller FIFO threshold

STMPE811 Touchscreen controller Doc ID 14489 Rev 5 41/66 FIFO_STA FIFO status Address: 0x4B Type: R/W Reset: 0x20 Description: Current status of FIFO.. FIFO_SIZE FIFO size Address: 0x4C Type: R Reset: 0x00 Description: Current number of samples available. 7654 3 2 1 0 FIFO_OFLOW FIFO_FULL FIFO_EMPTY F IFO_TH_TRIG RESERVED FIFO_RESET [7] FIFO_OFLOW: Reads 1 if FIFO is overflow [6] FIFO_FULL: Reads 1 if FIFO is full [5] FIFO_EMPTY: Reads 1 if FIFO is empty [4] FIFO_TH_TRIG: 0 = Current FIFO size is still below the threshold value 1 = Current FIFO size is at or beyond the threshold value [3:1] RESERVED [0] FIFO_RESET: Write '0' : FIFO put out of reset mode Write '1' : Resets FIFO. All data in FIFO are cleared. When TSC is enabled, FIFO resets automatically. 76543 2 1 0 RESERVED FIFO_SIZE [7:0] FIFO_SIZE: Number of samples available

Touchscreen controller STMPE811 42/66 Doc ID 14489 Rev 5 TSC_DATA_X TSC_DATA_X Address: 0x4D Type: R Reset: 0x0000 Description: Bit 11:0 of X data. 1 1 1 0 9876543 2 1 0 DATAY[11:0] [11:0] DATAY[11:0]: Bit 11:0 of X data

STMPE811 Touchscreen controller Doc ID 14489 Rev 5 43/66 TSC_DATA_Y TSC_DATA_Y Address: 0x4F Type: R Reset: 0x0000 Description: Bit 11:0 of Y data. TSC_DATA_Z TSC_DATA_Z Address: 0x51 Type: R Reset: 0x0000 Description: Bit 7:0 of Z data. 1 1 1 0 9876543 2 1 0 DATAY[11:0] [11:0] DATAY[11:0]: bit 11:0 of Y data 76543 2 1 0 DATAZ[7:0] [7:0] DATAZ[7:0]: bit 7:0 of Z data

each "packed sample" depends on which mode the touchscreen controller is operating in.

• Autoincrement
• Non autoincrement To access the 128-sets buffer, the non autoincrement mode should be used. 76543 2 1 0 DATA [11:0] DATA: data bytes from TSC FIFO

Table 16. Touchscreen controller DATA register

STMPE811 Touchscreen controller Doc ID 14489 Rev 5 45/66 TSC_FRACTION_Z Touchscreen controller FRACTION_Z Address: 0x56 Type: R Reset: 0x00 Description: This register allows to select the range and accuracy of the pressure measurement 76543 2 1 0 RESERVED FRACTION_Z [7:3] RESERVED [2:0] FRACTION_Z: 000: Fractional part is 0, whole part is 8 001: Fractional part is 1, whole part is 7 010: Fractional part is 2, whole part is 6 011: Fractional part is 3, whole part is 5 100: Fractional part is 4, whole part is 4 101: Fractional part is 5, whole part is 3 110: Fractional part is 6, whole part is 2 111: Fractional part is 7, whole part is 1

Touchscreen controller STMPE811 46/66 Doc ID 14489 Rev 5 TSC_I_DRIVE Touchscreen controller drive I Address: 0x58 Type: R/W Reset: 0x00 Description: This register sets the current limit value of the touchscreen drivers TSC_SHIELD Touchscreen controller shield Address: 0x59 Type: R Reset: 0x00 Description: Writing each bit would ground the corresponding touchscreen wire 76543 2 1 0 RESERVED DRIVE [7:1] RESERVED [0] DRIVE: maximum current on the touchscreen controller (TSC) driving channel 0: 20 mA typical, 35 mA max 1: 50 mA typical, 80 mA max 76543 2 1 0 RESERVED X+ X- Y+ Y - [7:4] RESERVED [3:0] SHIELD[3:0]: Write 1 to GND X+, X-, Y+, Y - lines

STMPE811 Touchscreen controller programming sequence Doc ID 14489 Rev 5 47/66

11 Touchscreen controlle r programming sequence

The following are the steps to configure the touchscreen controller (TSC): a) Disable the clock gating for the touch screen controller and ADC in the SYS_CFG2 register. b) Configure the touchscreen operating mode and the window tracking index. c) A touch detection status may also be enabled through enabling the corresponding interrupt flag. With this interrupt, the user is informed through an interrupt when the touch is detected as well as lifted. d) Configure the TSC_CFG register to specify the “panel voltage settling time”, touch detection delays and the averaging method used. e) A windowing feature may also be enabled through TSCWdwTRX, TSCWdwTRY , TSCWdwBLX and TSCWdwBL Y registers. By default, the windowing covers the entire touch panel. f) Configure the TSC_FIFO_TH register to specify the threshold value to cause an interrupt. The corresponding interrupt bit in the interrupt module must also be enabled. This interrupt bit should be masked off during data fetching from the FIFO in order to prevent an unnecessary trigger of this interrupt. Upon completion of the data fetching, this bit can be re-enabled g) By default, the FIFO_RESET bit in th e TSC_FIFO_CTRL_STA register holds the FIFO in Reset mode. Upon enabling the touchscreen controller (through the EN bit in TSC_CTRL), this FIFO reset is automatically deasserted. The FIFO status may be observed from the TSC_FIFO_CTRL_STA register or alternatively through the interrupt. h) Once the data is filled beyond the FIFO threshold value, an interrupt is triggered (assuming the corresponding interrupt is being enabled). The user is required to continuously read out the data set until the current FIFO size is below the threshold, then, the user may clear the interrupt flag. As long as the current FIFO size exceeds the threshold value, an interrupt from the touchscreen controller is sent to the interrupt module. Therefore, even if the interrupt flag is cleared, the interrupt flag is automatically asserted, as long as the FIFO size exceeds the threshold value. i) The current FIFO size can be obtained from the TSC_FIFO_Sz register. This information may assists the user in how many data sets are to be read out from the FIFO, if the user intends to read all in one shot. The user may also read a data set by a data set. j) The TSC_DATA_X register holds the X-coordinates. This register can be used in all touchscreen operating modes. k) The TSC_DATA_Y register holds the Y -coordinates. TSC_DATA_Y register holds the Y -coordinates. l) The TSC_DATA_Z register holds the Z value. TSC_DATA_Z register holds the Z- coordinates. m) The TSCDATA_XYZ register holds the X, Y and Z values. These values are packed into 4 bytes. This register can only be used when the touchscreen operating mode is 000 and 001. This register is to facilitate less byte read. n) For the TSC_FRACT_Z register, the user may configure it based on the touchscreen panel resistance. This allows the user to specify the resolution of the

Touchscreen controller programming sequence STMPE811 48/66 Doc ID 14489 Rev 5 Z value. With the Z value obtained from the register, the user simply needs to multiply the Z value with the touchscreen panel resistance to obtain the touch resistance. o) The TSC_DATA register allows facilitatio n of another reading format with minimum I 2C transaction overhead by using the non autoincrement mode (or equivalent mode in SPI). The data format is the same as TSC_DATA_XYZ, with the exception that all the data fetched are from the same address. p) Enable the EN bit of the TSC_CTRL register to start the touch detection and data acquisition. q) During the auto-hibernate mode, a touch detection can cause a wake-up to the device only when the TSC is enabled and the touch detect status interrupt mask is enabled. r) In order to prevent confusion, it is recommended that the user not mix the data fetching format (TSC_DATA_X, TSC_DATA_Y , TSC_DATA_Z, TSC_DATA_XYZ and TSC_DATA) between one reading and the next. s) It is also recommended that the user should perform a FIFO reset and TSC disabling when the ADC or TSC setting are reconfigured.

12 Temperature sensor

Table 17. Touchscreen parameters

Temperature sensor STMPE811 50/66 Doc ID 14489 Rev 5 TEMP_DATA Temperature data Address: 0x61 is MSB, 0x62 is LSB Type: R Reset: 0x00 Description: Temperature data access port TEMP_TH Temperature threshold Address: 0x63 is MSB, 0x64 is LSB Type: R/W Reset: 0x00 Description: Threshold for temperature controlled interrupt 1 1 1 0 9876543 2 1 0 TEMPERATURE [11:0] TEMPERATURE: Temperature reading Absolute temperature = ( VIO * temperature [11:0] ) / 7.51 (12-bit ADC) = ( VIO * temperature [9:0] ) / 7.51 (10-bit ADC) Note that VIO is used as a reference in temperature acquisition. Variations in VIO directly affect the accuracy of temperature acquired. 1 1 1 0 9876543 2 1 0 TEMP_TH [11:0] TEMP_TH: temperature threshold

13 GPIO controller

registers and their respective addresses are listed in the following table. All GPIO registers are named as GPIO-x, where x represents the functional group. Table 18. GPIO control registers

GPIO_SET_PIN GPIO set pin register Address: 0x10 Type: R/W Reset: 0x00 Description: GPIO set pin register. Writing 1 to this bit causes the corresponding GPIO to go to 1 state. Writing 0 has no effect. GPIO_CLR_PIN Clear pin state register Address: 0x11 Type: R/W Reset: 0x00 Description: GPIO clear pin state register. Writing ‘1’ to this bit causes the corresponding GPIO to go to 0 state. Writing ‘0’ has no effect. GPIO_MP_STA GPIO monito r pin state register Address: 0x12 Type: R/W Reset: 0x00 Description: GPIO monitor pin state. Reading this bit yields the current state of the bit. Writing has no effect. GPIO_DIR GPIO set pin direction Address: 0x13 Type: R/W Reset: 0x00 Description: GPIO set pin direction register. Writing ‘0’ sets the corresponding GPIO to input state, and ‘1’ sets it to output state. All bits are ‘0’ on reset.

GPIO_ED_STA GPIO edge detect status Address: 0x14 Type: R/W Reset: 0x00 Description: GPIO edge detect status register. An edge transition has been detected. GPIO_RE Rising edge register Address: 0x15 Type: R/W Reset: 0x00 Description: GPIO rising edge detection enable register. Setting this bit to ‘1’ would enable the detection of the rising edge transition. The detection would be reflected in the GPIO edge detect status register. GPIO_FE Falling edge detect ion enable register Address: 0x16 Type: R/W Reset: 0x00 Description: Setting this bit to ‘1’ would enable the detection of the falling edge transition. The detection would be reflected in the GPIO edge detect status register. GPIO_ALT_FUNCT Alternate function register Address: 0x17 Type: R/W Reset: 0x0F Description: Alternate function register. "‘0’ sets the corresponding pin to function as touchscreen/ADC, and ‘1’ sets it into GPIO mode.

13.0.1 Power supply

The STMPE811 GPIO operates from a separate supply pin (VIO). This dedicated supply pin provides a level-shifting feature to the STMPE811. The GPIO remains valid until VIO is removed. The host system may choose to turn off Vcc supply while keeping VIO supplied. However it is not allowed to turn off supply to VIO, while keeping the Vcc supplied. The touchscreen is always powered by VIO. For better resolution and noise immunity, VIO above 2.8 V is advised.

13.0.2 Power-up reset (POR)

The STMPE811 is equipped with an internal POR circuit that holds the device in reset state, until the VIO supply input is valid. The internal POR is tied to the VIO supply pin. On power-up reset, all GPIOs are set as input.

14 Maximum rating

extended periods may affect the device’s reliability. Table 19. Absolute maximum ratings

14.1 Recommended op erating conditions

Table 20. Power consumption

Table 21. DC electrical characteristics (-40 ° C to 85 ° C) all GPIOs comply to JEDEC Table 22. AC electrical characteristics (-40 ° C to 85 ° C)

Table 23. ADC spec ification (-40 ° C to 85 ° C) Table 24. Switch drivers specification

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Figure 12. Package outline for QFN16 (3 x 3 x 1 mm) - 0.50 pitch

Table 26. Exposed pad variation

Figure 13. Recommended footprint Table 27. Footprint dimensions

Figure 14. Carrier tape for QFN16 (3 x 3 x 1 mm) - 0.50 pitch

Figure 15. Reel information for QFN16 (3 x 3 x 1 mm) - 0.50 pitch

Table 28. Document revision history 09-Jun-2008 1 Initial release. Document status promoted from preliminary data to datasheet. Modified: title and package silhouette in the cover page. Section 16: Package mechanical data. related to the TSC_DATA_X register. summary table and removed Table 25. 18-Apr-2011 5 Updated: Temperature sensors registers information.