Driver IC

PDRV8426EPWPR

Texas Instruments

DRV8426E/P Dual H-Bridge Motor Drivers With Integrated Current Sense and Smart Tune Technology

Manufacturer: Texas Instruments

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Technical content

1 Features

Integrated current sense functionality – No sense resistors required – ±5% Full-scale current accuracy
4.5- to 33-V Operating supply voltage range
Multiple control interface options – PHASE/ENABLE – PWM
Smart tune decay technology, fast and mixed decay options
Low RDS(ON): – 900 mΩ HS + LS at 24 V, 25°C
High Current Capacity Per Bridge – 2.5-A peak, 1.5-A Full-Scale, 1.1-A rms
Configurable Off-Time PWM Chopping – 7, 16, 24 or 32 μs
Supports 1.8-V, 3.3-V, 5.0-V logic inputs
Low-current sleep mode (2 µA)
Spread spectrum clocking for low electromagnetic interference (EMI)
Inrush current limiting in brushed-DC applications
Small package and footprint
Protection features – VM undervoltage lockout (UVLO) – Charge pump undervoltage (CPUV) – Overcurrent protection (OCP) – Thermal shutdown (OTSD) – Fault condition output (nFAULT)

2 Applications

Printers and scanners
ATMs, currency counters, and EPOS
Office and home automation
Factory automation and robotics
Major and small home appliances
Vacuum, humanoid, and toy robotics

3 Description

drivers for a wide variety of industrial applications. bridge (dependent on PCB design). Figure 1. DRV8426E Figure 2. DRV8426P

11.3 Receiving Notification of Documentation Updates 31

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES May 2020 * Initial release.

5 Pin Configuration and Functions

PWP PowerPAD™ Package 28-Pin HTSSOP Top View DRV8426E 24-Pin VQFN with Exposed Thermal PAD Top View DRV8426E PWP PowerPAD™ Package 28-Pin HTSSOP Top View DRV8426P 24-Pin VQFN with Exposed Thermal PAD Top View DRV8426P

ADVANCE□INFORMATION DRV8426E, DRV8426P SLOSE56 –MAY 2020 www.ti.com Product Folder Links: DRV8426E DRV8426P Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Pin Functions PIN TYPE DESCRIPTION NAME PWP RGE DRV84 26E DRV8426P DRV84 26E DRV8426P ADECAY 21 21 16 16 I Decay mode setting pin. Set the decay mode for bridge A; see ; quad-level pin. AEN 25 — 20 — I Bridge A enable input. Logic high enables bridge A; logic low disables the bridge Hi-Z. AIN1 — 25 — 20 I Bridge A PWM input. Logic controls the state of H-bridge A; internal pulldown. AIN2 — 24 — 19 I Bridge B PWM input. Logic controls the state of H-bridge B; internal pulldown. AOUT1 4, 5 4, 5 3 3 O Winding A output. Connect to motor winding. AOUT2 6, 7 6, 7 4 4 O Winding A output. Connect to motor winding. APH 24 — 19 — I Bridge A phase input. Logic high drives current from AOUT1 to AOUT2. VREFA 18 18 13 13 I Reference voltage input. Voltage on this pin sets the full scale chopping current in H-bridge A. BDECAY 20 20 15 15 I Decay mode setting pin. Set the decay mode for bridge B; see ; quad-level pin. BEN 23 — 18 — I Bridge B enable input. Logic high enables bridge B; logic low disables the bridge Hi-Z. BIN1 — 23 — 18 I Bridge B PWM input. Logic controls the state of H-bridge B; internal pulldown. BIN2 — 22 — 17 I Bridge B PWM input. Logic controls the state of H-bridge B; internal pulldown. BOUT1 10, 11 10, 11 6 6 O Winding B output. Connect to motor winding. BOUT2 8, 9 8, 9 5 5 O Winding B output. Connect to motor winding. BPH 22 — 17 — I Bridge B phase input. Logic high drives current from BOUT1 to BOUT2. VREFB 17 17 12 12 I Reference voltage input. Voltage on this pin sets the full scale chopping current in H-bridge B. CPH 28 28 23 23 PWR Charge pump switching node. Connect a X7R, 0.022-μF, VM- rated ceramic capacitor from CPH to CPL.CPL 27 27 22 22 GND 14 14 9 9 PWR Device ground. Connect to system ground. TOFF 19 19 14 14 I Sets the decay mode off-time during current chopping; quad- level pin. Also sets the ripple current in smart tune ripple control mode. DVDD 15 15 10 10 PWR Logic supply voltage. Connect a X7R, 0.47-μF, 6.3-V or 10-V rated ceramic capacitor to GND. VCP 1 1 24 24 O Charge pump output. Connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM. VM 2, 13 2, 13 1, 8 1, 8 PWR Power supply. Connect to motor supply voltage and bypass to GND with two 0.01-μF ceramic capacitors (one for each pin) plus a bulk capacitor rated for VM. PGND 3, 12 3, 12 2, 7 2, 7 PWR Power ground. Connect to system ground. nFAULT 16 16 11 11 O Fault indication. Pulled logic low with fault condition; open-drain output requires an external pullup resistor. nSLEEP 26 26 21 21 I Sleep mode input. Logic high to enable device; logic low to enter low-power sleep mode; internal pulldown resistor. An nSLEEP low pulse clears faults. PAD - - - - - Thermal pad. Connect to system ground.

ADVANCE□INFORMATION DRV8426E, DRV8426P www.ti.com SLOSE56 –MAY 2020 Product Folder Links: DRV8426E DRV8426P Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range referenced with respect to GND (unless otherwise noted) (1) MIN MAX UNIT Power supply voltage (VM) –0.3 35 V Charge pump voltage (VCP, CPH) –0.3 VVM + 7 V Charge pump negative switching pin (CPL) –0.3 VVM V nSLEEP pin voltage (nSLEEP) –0.3 VVM V Internal regulator voltage (DVDD) –0.3 5.75 V Control pin voltage (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nFAULT, ADECAY, BDECAY, TOFF) –0.3 5.75 V Open drain output current (nFAULT) 0 10 mA Reference input pin voltage (VREFA, VREFB) –0.3 5.75 V Continuous phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) –1 VVM + 1 V Transient 100 ns phase node pin voltage (AOUT1, AOUT2, BOUT1, BOUT2) –3 VVM + 3 V Peak drive current (AOUT1, AOUT2, BOUT1, BOUT2) Internally Limited A Operating ambient temperature, TA –40 125 °C Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C

6.2 ESD Ratings

V(ES Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101 Corner pins for PWP (1, 14, 15, and 28) ±750 Other pins ±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VVM Supply voltage range for normal (DC) operation 4.5 33 V VI Logic level input voltage 0 5.5 V VREF Reference rms voltage range (VREFA, VREFB) 0.05 3.3 V ƒPWM Applied PWM signal (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2) 0 100 kHz IFS Motor full-scale current (xOUTx) 0 1.5 A Irms Motor RMS current (xOUTx) 0 1.1 A TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) PWP (HTSSOP) RGE (VQFN) UNIT

28 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 33.5 44.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.7 37.4 °C/W RθJB Junction-to-board thermal resistance 13.7 21.4 °C/W ψJT Junction-to-top characterization parameter 0.8 1.1 °C/W ψJB Junction-to-board characterization parameter 13.7 21.4 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.1 7.1 °C/W

6.5 Electrical Characteristics

Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (VM, DVDD) IVM VM operating supply current nSLEEP = 1, No motor load 5 6.5 mA IVMQ VM sleep mode supply current nSLEEP = 0 2 4 μA tSLEEP Sleep time nSLEEP = 0 to sleep-mode 120 μs tRESET nSLEEP reset pulse nSLEEP low to clear fault 20 40 μs tWAKE Wake-up time nSLEEP = 1 to output transition 0.8 1.2 ms tON Turn-on time VM > UVLO to output transition 0.8 1.2 ms VDVDD Internal regulator voltage No external load, 6 V < VVM < 33 V 4.5 5 5.5 V CHARGE PUMP (VCP, CPH, CPL) VVCP VCP operating voltage VVM + 5 V f(VCP) Charge pump switching frequency VVM > UVLO; nSLEEP = 1 360 kHz LOGIC-LEVEL INPUTS (APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nSLEEP) VIL Input logic-low voltage 0 0.6 V VIH Input logic-high voltage 1.5 5.5 V VHYS Input logic hysteresis 150 mV IIL Input logic-low current VIN = 0 V –1 1 μA IIH Input logic-high current VIN = 5 V 100 μA tPD Propagation delay xPH, xEN, xINx input to current change 800 ns QUAD-LEVEL INPUTS (ADECAY, BDECAY, TOFF) VI1 Input logic-low voltage Tied to GND 0 0.6 V VI2 330kΩ ± 5% to GND 1 1.25 1.4 V VI3 Input Hi-Z voltage Hi-Z (>500kΩ to GND) 1.8 2 2.2 V VI4 Input logic-high voltage Tied to DVDD 2.7 5.5 V IO Output pull-up current 10 μA CONTROL OUTPUTS (nFAULT) VOL Output logic-low voltage IO = 5 mA 0.5 V IOH Output logic-high leakage VVM = 24 V –1 1 μA MOTOR DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) RDS(ONH) High-side FET on resistance VVM = 24 V, TJ = 25 °C, IO = -1 A 450 550 mΩ VVM = 24 V, TJ = 125 °C, IO = -1 A 700 850 mΩ VVM = 24 V, TJ = 150 °C, IO = -1 A 780 950 mΩ RDS(ONL) Low-side FET on resistance VVM = 24 V, TJ = 25 °C, IO = 1 A 450 550 mΩ VVM = 24 V, TJ = 125 °C, IO = 1 A 700 850 mΩ VVM = 24 V, TJ = 150 °C, IO = 1 A 780 950 mΩ tSR Output slew rate VM = 24V, IO = 1 A, Between 10% and 90% 240 V/µs PWM CURRENT CONTROL (VREFA, VREFB) KV Transimpedance gain VREF = 3.3 V 2.09 2.2 2.31 V/A tOFF PWM off-time TOFF = 0 7 μs TOFF = 1 16 TOFF = Hi-Z 24 TOFF = 330 kΩ to GND 32

ADVANCE□INFORMATION DRV8426E, DRV8426P SLOSE56 –MAY 2020 www.ti.com Product Folder Links: DRV8426E DRV8426P Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) Typical values are at TA = 25°C and VVM = 24 V. All limits are over recommended operating conditions, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ΔITRIP Current trip accuracy IO = 1.5 A, 10% to 20% current setting –15 15 %IO = 1.5 A, 20% to 67% current setting –10 10 IO = 1.5 A, 68% to 100% current setting -5 5 IO,CH AOUT and BOUT current matching IO = 1.5 A –2.5 2.5 % PROTECTION CIRCUITS VUVLO VM UVLO lockout VM falling, UVLO falling 4.1 4.25 4.35 V VM rising, UVLO rising 4.2 4.35 4.45 VUVLO,HYS Undervoltage hysteresis Rising to falling threshold 100 mV VCPUV Charge pump undervoltage VCP falling VVM + 2 V IOCP Overcurrent protection Current through any FET 2.5 A tOCP Overcurrent deglitch time 1.25 μs TOTSD Thermal shutdown Die temperature TJ 150 165 180 °C THYS_OTSD Thermal shutdown hysteresis Die temperature TJ 20 °C

7 Detailed Description

7.1 Overview

The DRV8426E/P are integrated motor driver solutions for bipolar stepper motors or dual brushed-DC motors. The devices integrate two N-channel power MOSFET H-bridges, integrated current sense and regulation circuitry. The DRV8426E/P can be powered with a supply voltage between 4.5 and 33 V. The DRV8426E/P are capable of providing an output current up to 2.5-A peak, 1.5-A full-scale, or 1.1-A root mean square (rms). The actual full-scale and rms current depends on the ambient temperature, supply voltage, and PCB thermal capability. The DRV8426E/P devices use an integrated current-sense architecture which eliminates the need for two external power sense resistors. This architecture removes the power dissipated in the sense resistors by using a current mirror approach and using the internal power MOSFETs for current sensing. The current regulation set point is adjusted by the voltage at the VREFA and VREFB pins. These features reduce external component cost, board PCB size, and system power consumption. A simple PH/EN (DRV8426E) or PWM (DRV8426P) interface allows easy interfacing to the controller circuit. The current regulation is highly configurable, with several decay modes of operation. The decay mode can be selected as a smart tune Dynamic Decay, smart tune Ripple Control, mixed, or fast decay. The smart tune decay modes automatically adjust the decay setting to minimize current ripple while still reacting quickly to step changes. This feature greatly simplifies stepper driver integration into a motor drive system. The PWM off-time, tOFF, can be adjusted to 7, 16, 24, or 32 μs. A low-power sleep mode is included which allows the system to save power when not driving the motor.

7.2 Functional Block Diagrams

Figure 3. DRV8426E Block Diagram

Figure 4. DRV8426P Block Diagram

7.3 Feature Description

Table 1 shows the recommended values of the external components for the driver. Table 1. External Components

7.3.1 PWM Motor Drivers

Figure 5. PWM Motor Driver Block Diagram

7.3.2 Bridge Control

Table 2. DRV8426E (PH/EN) Control Interface

0 X X Hi-Z Hi-Z Sleep mode; H-bridge disabled Hi-Z

Table 3. DRV8426P (PWM) Control Interface

7.3.3 Current Regulation

The current through the motor windings is regulated by an adjustable, off-time PWM current-regulation circuit. decrease the current. After the off-time expires, the bridge is re-enabled, starting another PWM cycle. Table 4. Off-Time Settings chopping comparator, the VREFx input is attenuated by a factor of Kv. The chopping current (IFS) can be calculated as IFS (A) = VREFx (V) / KV (V/A) = VREFx (V) / 2.2 (V/A).

7.3.4 Decay Modes

chopping threshold is reached. This is shown in Figure 6, Item 1. the bridge. This is shown in Figure 6, Item 3. Figure 6. Decay Modes The decay mode is selected by setting the quad-level ADECAY and BDECAY pins as shown in Table 5. Table 5. Decay Mode Settings

0 Smart tune Dynamic Decay

1 Smart tune Ripple Control

mode for H-bridge B (BOUT1, BOUT2).

7.3.4.1 Mixed Decay

Figure 7. Mixed Decay Mode Mixed decay begins as fast decay for 30% of tOFF, followed by slow decay for the remainder of tOFF. mixed decay settles to the new ITRIP level faster than slow decay.

7.3.4.2 Fast Decay

Figure 8. Fast/Fast Decay Mode zero in order to prevent current flow in the reverse direction. current steps is much faster than slow decay since the current is allowed to decrease much faster.

7.3.4.3 Smart tune Dynamic Decay

Motor winding resistance and inductance
Motor aging effects
Motor dynamic speed and load
Motor supply voltage variation
Low-current versus high-current dI/dt

Figure 9. Smart tune Dynamic Decay Mode best decay setting that results in the lowest ripple for the motor. falling steps, smart tune Dynamic Decay automatically switches to fast decay to reach the next step quickly. fixed frequency in the current regulation scheme.

7.3.4.4 Smart tune Ripple Control

Figure 10. Smart tune Ripple Control Decay Mode current to recirculate. In this mode, tOFF varies depending on the current level and operating conditions. scheme to achieve small current ripple in the current regulation. The ripple current in this decay mode is 11mA + 1% of the ITRIP at a specific microstep level.

7.3.4.5 Blanking time

time of the PWM. The blanking time is approximately 1 µs.

7.3.5 Charge Pump

capacitor is required between the CPH and CPL pins to act as the flying capacitor.

Figure 11. Charge Pump Block Diagram

7.3.6 Linear Voltage Regulators

Figure 12. Linear Voltage Regulator Block Diagram or in sleep mode: the DVDD regulator is disabled and current does not flow through the input pulldown resistors. For reference, logic level inputs have a typical pulldown of 200 kΩ. The nSLEEP pin cannot be tied to DVDD, else the device will never exit sleep mode.

7.3.7 Logic and Quad-Level Pin Diagrams

Figure 13. Logic-level Input Pin Diagram Quad-level logic pins TOFF, ADECAY, and BDECAY have the following structure as shown in Figure 14. Figure 14. Quad-Level Input Pin Diagram Figure 15. nFAULT Pin

7.3.8 Protection Circuits

device overtemperature events.

7.3.8.1 VM Undervoltage Lockout (UVLO)

7.3.8.2 VCP Undervoltage Lockout (CPUV)

(motor-driver operation and nFAULT released) when the VCP undervoltage condition is removed.

7.3.8.3 Overcurrent Protection (OCP)

removed, normal operation resumes after applying an nSLEEP reset pulse or a power cycling. (Hi-Z) when the device enters sleep mode.

7.3.8.4 Thermal Shutdown (OTSD)

Table 6. Fault Condition Summary

7.4 Device Functional Modes

7.4.1 Sleep Mode (nSLEEP = 0)

7.4.2 Operating Mode (nSLEEP = 1)

before the device is ready for inputs.

affect the status of the charge pump or other functional blocks. Figure 16. nSLEEP Reset Pulse Table 7 lists a summary of the functional modes. Table 7. Functional Modes Summary

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8426E/P is used in stepper or brushed motor control.

8.2 Typical Application

used to drive a stepper motor. Figure 17. Typical Application Schematic

8.2.1 Design Requirements

Table 8 lists the design input parameters for system design.

Table 8. Design Parameters

8.2.2 Detailed Design Procedure

8.2.2.1 Current Regulation

used to provide VREFx through a resistor divider. voltage, and RL is the motor winding resistance.

8.2.2.2 Stepper Motor Speed

frequency of the input waveform. θstep can be found in the stepper motor data sheet or written on the motor itself. Table 8, ƒstep can be calculated as 800 Hz.

8.2.2.3 Decay Modes

winding in one of the decay modes for TOFF. After TOFF, a new drive phase starts.

8.3 Alternate Application

external controller to the xEN/xIN1 and xPH/xIN2 pins. Figure 18. Typical Application Schematic

8.3.1 Design Requirements

Table 9 gives design input parameters for system design. Table 9. Design Parameters

8.3.2 Detailed Design Procedure

8.3.2.1 Current Regulation

The maximum current (ITRIP) is set by the VREFx analog voltage. When starting a brushed-DC motor, a large inrush current may occur because there is no back-EMF. Current regulation will act to limit this inrush current and prevent high current on startup.

9 Power Supply Recommendations

bulk capacitor must be included on VM.

9.1 Bulk Capacitance

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

The highest current required by the motor system
The power supply’s capacitance and ability to source current
The amount of parasitic inductance between the power supply and motor system
The acceptable voltage ripple
The type of motor used (brushed DC, brushless DC, stepper)
The motor braking method The inductance between the power supply and motor drive system will limit the rate current can change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate sized bulk capacitor. The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases when the motor transfers energy to the supply.

Figure 19. Example Setup of Motor Drive System With External Power Supply

10 Layout

10.1 Layout Guidelines

The VM pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.01 µF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or ground plane connection to the device GND pin. The VM pin must be bypassed to ground using a bulk capacitor rated for VM. This component can be an electrolytic capacitor. A low-ESR ceramic capacitor must be placed in between the CPL and CPH pins. A value of 0.022 µF rated for VM is recommended. Place this component as close to the pins as possible. A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.22 µF rated for 16 V is recommended. Place this component as close to the pins as possible. Bypass the DVDD pin to ground with a low-ESR ceramic capacitor. A value of 0.47 µF rated for 6.3 V is recommended. Place this bypassing capacitor as close to the pin as possible. The thermal PAD must be connected to system ground.

11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
Texas Instruments, PowerPAD™ Made Easy application report
Texas Instruments, Current Recirculation and Decay Modes application report
Texas Instruments, Calculating Motor Driver Power Dissipation application report
Texas Instruments, Understanding Motor Driver Current Ratings application report
Texas Instruments, High Resolution Microstepping Driver With the DRV88xx Series application report

11.2 Related Links

resources, tools and software, and quick access to order now. Table 10. Related Links

11.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.4 Community Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

11.6 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com PACKAGE OUTLINE C SEE TERMINAL DETAIL 24X 0.3 0.2 2.45 0.1 24X 0.5 0.3

1 MAX

(0.2) TYP 0.05 0.00 20X 0.5 2.5 2X 2.5 A 4.1 3.9 B 4.1 3.9 0.3 0.2 0.5 0.3 VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 PIN 1 INDEX AREA 0.08 C SEATING PLANE 6 13 7 12 24 19 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 EXPOSED THERMAL PAD

25 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 DETAIL OPTIONAL TERMINAL TYPICAL ADVANCE□INFORMATION DRV8426E, DRV8426P www.ti.com SLOSE56 –MAY 2020 Product Folder Links: DRV8426E DRV8426P Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

24X (0.25) 24X (0.6) ( 0.2) TYP VIA 20X (0.5) (3.8) (3.8) ( 2.45) (R0.05) TYP (0.975) TYP VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 SYMM 7 12 1924 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) EXPOSED METAL ADVANCE□INFORMATION DRV8426E, DRV8426P SLOSE56 –MAY 2020 www.ti.com Product Folder Links: DRV8426E DRV8426P Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN 24X (0.6) 24X (0.25) 20X (0.5) (3.8) (3.8) 4X ( 1.08) (0.64) TYP (0.64) TYP (R0.05) TYP VQFN - 1 mm max heightRGE0024B PLASTIC QUAD FLATPACK - NO LEAD 4219013/A 05/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP BASED ON 0.125 mm THICK STENCIL SOLDER PASTE EXAMPLE EXPOSED PAD 25 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 7 12 1924 ADVANCE□INFORMATION DRV8426E, DRV8426P www.ti.com SLOSE56 –MAY 2020 Product Folder Links: DRV8426E DRV8426P Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

www.ti.com PACKAGE OUTLINE C 26X 0.65 8.45 28X 0.30 0.19 6.6

6.2 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8

1.2 MAX

2X 0.82 MAX NOTE 5 2X 0.825 MAX NOTE 5 4.05 3.53 3.10 2.58 B 4.5 4.3 A 9.8 9.6 NOTE 3 0.75 0.50 (0.15) TYP PowerPAD TSSOP - 1.2 mm max heightPWP0028M SMALL OUTLINE PACKAGE 4224480/A 08/2018 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may diﬀer or may not be present. SEATING PLANE PowerPAD is a trademark of Texas Instruments. TYPICAL TM A 20 SCALE 2.000 DETAIL A THERMAL PAD 14 15 ADVANCE□INFORMATION DRV8426E, DRV8426P SLOSE56 –MAY 2020 www.ti.com Product Folder Links: DRV8426E DRV8426P Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

28X (1.5) 28X (0.45) 26X (0.65) (5.8) (R0.05) TYP (3.4) NOTE 9 (9.7) NOTE 9 (1.2) TYP (0.6) (1.2) TYP ( 0.2) TYP VIA (3.1) (4.05) PowerPAD TSSOP - 1.2 mm max heightPWP0028M SMALL OUTLINE PACKAGE 4224480/A 08/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be ﬁlled, plugged or tented. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 8X SYMM SYMM 14 15 METAL COVERED BY SOLDER MASK SOLDER MASK DEFINED PAD SEE DETAILS 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL NON-SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) SOLDER MASK DEFINED ADVANCE□INFORMATION DRV8426E, DRV8426P www.ti.com SLOSE56 –MAY 2020 Product Folder Links: DRV8426E DRV8426P Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

www.ti.com EXAMPLE STENCIL DESIGN 28X (1.5) 28X (0.45) 26X (0.65) (5.8) (R0.05) TYP (4.05) BASED ON

0.125 THICK

(3.1) BASED ON PowerPAD TSSOP - 1.2 mm max heightPWP0028M SMALL OUTLINE PACKAGE 4224480/A 08/2018 2.62 X 3.420.175 2.83 X 3.700.15 3.10 X 4.05 (SHOWN)0.125 3.47 X 4.530.1 SOLDER STENCIL OPENING STENCIL THICKNESS NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have diﬀerent recommendations for stencil design. TM SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 8X SYMM SYMM 14 15 METAL COVERED BY SOLDER MASK SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES ADVANCE□INFORMATION DRV8426E, DRV8426P SLOSE56 –MAY 2020 www.ti.com Product Folder Links: DRV8426E DRV8426P Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

www.ti.com 16-Jun-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRV8426EPWPR PREVIEW HTSSOP PWP 28 2000 TBD Call TI Call TI -40 to 125 DRV8426ERGER PREVIEW VQFN RGE 24 3000 TBD Call TI Call TI -40 to 125 DRV8426PPWPR PREVIEW HTSSOP PWP 28 2000 TBD Call TI Call TI -40 to 125 DRV8426PRGER PREVIEW VQFN RGE 24 3000 TBD Call TI Call TI -40 to 125 PDRV8426EPWPR ACTIVE HTSSOP PWP 28 1 TBD Call TI Call TI -40 to 125 PDRV8426ERGER ACTIVE VQFN RGE 24 1 TBD Call TI Call TI -40 to 125 PDRV8426PPWPR ACTIVE HTSSOP PWP 28 1 TBD Call TI Call TI -40 to 125 PDRV8426PRGER ACTIVE VQFN RGE 24 1 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

www.ti.com 16-Jun-2020 Addendum-Page 2 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGE 24 VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4204104/H

www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. TSSOP - 1.2 mm max height TM PowerPADPWP 28 SMALL OUTLINE PACKAGE4.4 x 9.7, 0.65 mm pitch 4224765/A

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated

Product Information

PDRV8426EPWPR specifications and overview.

Summary

DRV8426E/P Dual H-Bridge Motor Drivers With Integrated Current Sense and Smart Tune Technology

Description

DRV8426E/P Dual H-Bridge Motor Drivers With Integrated Current Sense and Smart Tune Technology

Source title PDRV8426EPWPR Datasheet(PDF) - Texas Instruments

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