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PRODUCT□PREVIEW DRV8305-Q1 PWM 4.4 to 45 V MCU N-Channel MOSFETs Gate Drive Sense Automotive 3-Phase Brushless Gate Driver SPI nFAULT Shunt Amps M EN_GATE Protection Shunt Amps LDO 50-mA LDO Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice. DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 DRV8305-Q1Three-PhaseAutomotiveGateDriverWithThreeIntegratedCurrentShunt AmplifiersandVoltageRegulator

1 Features

1• AEC-Q100 Qualified for Automotive Applications

Ambient Operating Temperature Ranges: – Temperature Grade 0 (E): –40°C to 150°C – Temperature Grade 1 (Q): –40°C to 125°C
4.4-V to 45-V Operating Voltage
1.25-A and 1-A Peak Gate Drive Currents
Programmable High- and Low-Side Slew-Rate Control
Charge-Pump Gate Driver for 100% Duty Cycle
Three Integrated Current-Shunt Amplifiers
Integrated 50-mA LDO (3.3-V and 5-V Option)
3-PWM or 6-PWM Input Control up to 200 kHz
Single PWM-Mode Commutation Capability
Supports Both 3.3-V and 5-V Digital Interface
Serial Peripheral Interface (SPI) for Device Settings and Fault Reporting
Thermally-Enhanced 48-Pin HTQFP
Protection Features: – Fault Diagnostics and MCU Watchdog – Programmable Dead-Time Control – MOSFET Shoot-Through Prevention – MOSFET VDS Overcurrent Monitors – Gate-Driver Fault Detection – Reverse Battery-Protection Support – Limp Home-Mode Support – Overtemperature Warning and Shutdown

2 Applications

Three-Phase BLDC and PMSM Motors
Automotive Fuel and Water Pumps
Automotive Fans and Blowers

3 Description

The DRV8305-Q1 device is a gate driver IC for three- phase motor-drive applications. The device provides three high-accuracy and temperature compensated half-bridge drivers, each capable of driving a high- side and low-side N-channel MOSFET. A charge pump driver supports 100% duty cycle and low- voltage operation for cold crank situations. The device can tolerate load dump voltages up to 45-V. The DRV8305-Q1 device includes three bidirectional current-shunt amplifiers for accurate low-side current measurements that support variable gain settings and an adjustable offset reference. The DRV8305-Q1 device has an integrated voltage regulator to support an MCU or other system power requirements. The voltage regulator can be interfaced directly with a LIN physical interface to allow low system standby and sleep currents. The gate driver uses automatic handshaking when switching to prevent current shoot through. The VDS of both the high-side and low-side MOSFETs is accuractely sensed to protect the external MOSFETs from overcurrent conditions. The SPI provides detailed fault reporting, diagnostics, and device configurations such as gain options for the current shunt amplifier, individual MOSFET overcurrent detection, and gate-drive slew-rate control. Device Options:

DRV8305NQ: Grade 1 with voltage refernece
DRV83053Q: Grade 1 with 3.3-V, 50-mA LDO
DRV83055Q: Grade 1 with 5-V, 50-mA LDO
DRV8305NE: Grade 0 with voltage reference Device Information (1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV8305-Q1 HTQFP (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

PRODUCT□PREVIEW DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Table of Contents

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2015) to Revision A Page

PRODUCT□PREVIEW PowerPAD (GND) EN_GATE INHA INLA INHB INLB INHC INLC nFAULT nSCS SDI SDO SCLK PWRGD GND AVDD SO1 SO2 SO3 SN3 SP3 SN2 SP2 SN1 SP1 GHA SHA SLA GLA GLB SLB SHB GHB GHC SHC SLC GLC VREG WAKE DVDD GND VDRAIN CP1H CP1L PVDD CP2L CP2H VCPH VCP_LSD DRV8305-Q1 www.ti.com SLVSD12A –MAY 2015–REVISED MARCH 2016 Product Folder Links: DRV8305-Q1 Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

NAME NO. EN_GATE 1 I Enable gate Enables the gate driver and current shunt amplifiers; internal pulldown INHA 2 I Bridge PWM input PWM input signal for bridge A high side INLA 3 I Bridge PWM input PWM input signal for bridge A low side INHB 4 I Bridge PWM input PWM input signal for bridge B high side INLB 5 I Bridge PWM input PWM input signal for bridge B low side INHC 6 I Bridge PWM input PWM input signal for bridge C high side INLC 7 I Bridge PWM input PWM input signal for bridge C low side nFAULT 8 OD Fault indicator When low indicates a fault has occurred; open drain; external pullup to MCU power supply needed (1 kΩ to 10 kΩ) nSCS 9 I SPI chip select Select/enable for SPI; active low SDI 10 I SPI input SPI input signal SDO 11 O SPI output SPI output signal SCLK 12 I SPI clock SPI clock signal PWRGD 13 OD Power good VREG and MCU watchdog fault indication; open drain; external pullup to MCU power supply needed (1 kΩ to 10 kΩ) GND 14, 45 P Device ground Must be connected to ground AVDD 15 P Analog regulator 5-V internal analog supply regulator; bypass to GND with a 6.3-V, 1-µF ceramic capacitor SO1 16 O Current amplifier output Output of current sense amplifier 1 SO2 17 O Current amplifier output Output of current sense amplifier 2 SO3 18 O Current amplifier output Output of current sense amplifier 3

internal amplifier reference voltage and SDO pullup. Table 1. External Components

Table 1. External Components (continued) Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. is expected. Contact TI for lifetime impact if the use case requires TJ = 150°C to 175°C greater than 10 hours.

6 Specifications

6.1 Absolute Maximum Ratings

PRODUCT□PREVIEW DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) ±2000 V Charged-device model (CDM), per AEC Q100-011 ±500

6.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted) MIN MAX UNIT PVDD Power supply voltage range 4.4 45 V PVDD Power supply voltage range for voltage regulator operation 4.3 45 V VCPH Charge pump external load current 0 30 mA VCP_LSD Low-side regulator external load current 0 30 mA IGATE Total average gate drive current (HS + LS) 0 30 mA fgate Operating switching frequency of gate driver 0 200 kHz VREG Voltage regulator external load current (regulator enabled device options) 0 50 mA CO_OPA Maximum external capacitive load on shunt amplifier output (without external resistor) 0 60 pF InFAULT nFAULT sink current (nFAULT = 0.3 V) 0 7 mA TA Operating ambient temperature, DRV8305xQPHPQ1 –40 125 °C Operating ambient temperature, DRV8305xEPHPQ1 –40 150 °C TJ Operating junction temperature, DRV8305xQPHPQ1 –40 150 °C Operating junction temperature, DRV8305xEPHPQ1 –40 175 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC (1) DRV8305-Q1 UNITPHP (HTQFP)

48 PINS

RθJA Junction-to-ambient thermal resistance 26.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 12.9 °C/W RθJB Junction-to-board thermal resistance 7.6 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 7.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 0.6 °C/W

6.5 Electrical Characteristics

PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (PVDD, DVDD, AVDD) VPVDD PVDD operating voltage 4.4 45 V Voltage regulator (VREG) operational 4.3 45 IPVDD_Operating PVDD operating supply current EN_GATE = HIGH; VREG no load; outputs HI-Z 20 mA IPVDD_Standby PVDD standby supply current EN_GATE = LOW; VREG no load 5 mA IPVDD_Sleep PVDD sleep supply current EN_GATE = LOW; Sleep Mode; TJ = –40 to 150 °C 60 200 μA EN_GATE = LOW; Sleep Mode; TJ = 150 to 175 °C 250 uA VAVDD Internal regulator voltage PVDD = 5.3 to 45 V 4.85 5 5.15 V PVDD = 4.4 to 5.3 V PVDD – 0.4 PVDD VDVDD Internal regulator voltage 3.3 V VOLTAGE REGULATOR (3.3-V or 5-V VREG) VVREG VREG DC output voltage PVDD = 5.4 to 45 V VREG ×

0.97 VREG VREG ×

1.03 VPVDD = 4.4 to 5.3 V; 5-V regulator PVDD – 0.4 PVDD PVDD = 4.4 to 5.3 V; 3.3-V regulator VREG × 1.03 VLineReg Line regulation ΔVOUT/ΔVIN 5.3 V ≤ VIN ≤ 12 V; IO = 1 mA 10 30 mV VLoadReg Load regulation ΔVOUT/ΔIOUT 100 μA ≤ IOUT ≤ 50 mA 30 mV Vdo Dropout voltage IOUT = 100 μA; 3.3 V 0.05 0.1 V IOUT = 50 mA; 3.3 V 0.2 0.4 LOGIC-LEVEL INPUTS (INHx, INLx, EN_GATE, SCLK, nSCS) VIL Input logic low voltage 0 0.8 V VIH Input logic high voltage 2 5 V RPD Internal pulldown resistor To GND 100 kΩ CONTROL OUTPUTS (nFAULT, SDO, PWRGD) VOL Output logic low voltage nFAULT; SDO; PWRGD; IO = 5 mA 0.5 V VOH Output logic high voltage SDO; IO = 5 mA VREG - 0.9 V IOH Output logic high leakage VO = 3.3 V –1 1 μA HIGH VOLTAGE TOLERANT LOGIC INPUT (WAKE) VIL_WAKE Output logic high voltage 1.1 1.41 V VIH_WAKE Output logic high leakage 1.42 1.75 V GATE DRIVE OUTPUT (GHx, GLx) VGHS High side gate driver Vgs voltage VPVDD = 8 to 45 V; IGATE < 30 mA 9 10 10.5 VVPVDD = 5.5 to 8 V; IGATE < 10 mA 7 10.5 VPVDD = 4.4 to 5.5 V; IGATE < 5 mA 5 9 VGLS Low-side gate driver Vgs voltage VPVDD = 8 to 45 V; IGATE < 30 mA 9 10 10.5 VVPVDD = 5.5 to 8 V; IGATE < 10 mA 9 10.5 VPVDD = 4.4 to 5.5 V; IGATE < 5 mA 8 10.5 PEAK CURRENT DRIVE TIMES (GHx, GLx) tDRIVE Peak sink or source current drive time TDRIVEP = 00; TDRIVEN = 00 220 ns TDRIVEP = 01; TDRIVEN = 01 440 TDRIVEP = 10; TDRIVEN = 10 880 TDRIVEP = 11; TDRIVEN = 11 1780

PRODUCT□PREVIEW DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HIGH-SIDE PEAK CURRENT GATE DRIVE (GHx) IDRIVEP_HS High side peak source current IDRIVEP_HS = 0000 0.01 A IDRIVEP_HS = 0001 0.02 IDRIVEP_HS = 0010 0.03 IDRIVEP_HS = 0011 0.04 IDRIVEP_HS = 0100 0.05 IDRIVEP_HS = 0101 0.06 IDRIVEP_HS = 0110 0.07 IDRIVEP_HS = 0111 0.125 IDRIVEP_HS = 1000 0.25 IDRIVEP_HS = 1001 0.5 IDRIVEP_HS = 1010 0.75 IDRIVEP_HS = 1011 1 IDRIVEP_HS = 1100, 1101, 1110, 1111 0.05 IDRIVEN_HS High side peak sink current IDRIVEN_HS = 0000 0.02 A IDRIVEN_HS = 0001 0.03 IDRIVEN_HS = 0010 0.04 IDRIVEN_HS = 0011 0.05 IDRIVEN_HS = 0100 0.06 IDRIVEN_HS = 0101 0.07 IDRIVEN_HS = 0110 0.08 IDRIVEN_HS = 0111 0.25 IDRIVEN_HS = 1000 0.5 IDRIVEN_HS = 1001 0.75 IDRIVEN_HS = 1010 1 IDRIVEN_HS = 1011 1.25 IDRIVEN_HS = 1100, 1101, 1110, 1111 0.06 LOW SIDE PEAK CURRENT GATE DRIVE (GLx) IDRIVEP_LS Low-side peak source current IDRIVEP_LS = 0000 0.01 A IDRIVEP_LS = 0001 0.02 IDRIVEP_LS = 0010 0.03 IDRIVEP_LS = 0011 0.04 IDRIVEP_LS = 0100 0.05 IDRIVEP_LS = 0101 0.06 IDRIVEP_LS = 0110 0.07 IDRIVEP_LS = 0111 0.125 IDRIVEP_LS = 1000 0.25 IDRIVEP_LS = 1001 0.5 IDRIVEP_LS = 1010 0.75 IDRIVEP_LS = 1011 1 IDRIVEP_LS = 1100, 1101, 1110, 1111 0.05

PRODUCT□PREVIEW DRV8305-Q1 www.ti.com SLVSD12A –MAY 2015–REVISED MARCH 2016 Product Folder Links: DRV8305-Q1 Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDRIVEN_LS Low-side peak sink current IDRIVEN_LS = 0000 0.02 A IDRIVEN_LS = 0001 0.03 IDRIVEN_LS = 0010 0.04 IDRIVEN_LS = 0011 0.05 IDRIVEN_LS = 0100 0.06 IDRIVEN_LS = 0101 0.07 IDRIVEN_LS = 0110 0.08 IDRIVEN_LS = 0111 0.25 IDRIVEN_LS = 1000 0.5 IDRIVEN_LS = 1001 0.75 IDRIVEN_LS = 1010 1 IDRIVEN_LS = 1011 1.25 IDRIVEN_LS = 1100, 1101, 1110, 1111 0.06 PASSIVE GATE PULL DOWN (GHx, GLx) RSLEEP_PD Gate pull down resistance, sleep mode EN_GATE = LOW; GHx to GND; 1000 Ω EN_GATE = LOW; GLx to GND; 500 Ω RSTANDBY_PD Gate pull down resistance, standby mode EN_GATE = LOW; GHx to GND; 1000 Ω EN_GATE = LOW; GLx to GND; 500 Ω ACTIVE GATE PULL DOWN (GHx, GLx) IHOLD Gate pull down current, holding EN_GATE = HIGH; GHx to SHx; GLx to SLx 50 mA ISTRONG Gate pull down current, strong EN_GATE = HIGH; GHx to SHx; GLx to SLx 1.25 A GATE TIMING tpd_lf-O Positive input falling to GHS_x falling PVDD = 12 V; CL = 1 nF; 50% to 50% 150 ns tpd_lr-O Positive input rising to GHS_x rising PVDD = 12 V; CL = 1 nF; 50% to 50% 150 ns td_min Minimum dead time after hand shaking 280 ns tdtp Dead time in addition to td_min DEAD_TIME = 000 35 ns DEAD_TIME = 001 52 DEAD_TIME = 010 88 DEAD_TIME = 011 440 DEAD_TIME = 100 880 DEAD_TIME = 101 1760 DEAD_TIME = 110 3520 DEAD_TIME = 111 5280 tPD_MATCH Propagation delay matching between high-side and low- side 50 ns tDT_MATCH Dead time matching 50 ns

PRODUCT□PREVIEW DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT SHUNT AMPLIFIER GCSA Current sense amplifier gain GAIN_CSx = 00 10 V/V GAIN_CSx = 01 19.9 GAIN_CSx = 10 39.8 GAIN_CSx = 11 79.5 GERR Current sense amplifier gain error Input differential > 0.025 V; TJ = –40 to 150 °C –3% 3% Input differential > 0.025 V; TJ = 150 to 175 °C –4% 4% tSETTLING Current sense amplifier settling time Settling time to 1%; no blanking; GCSA = 10; Vstep = 0.46 V 300 ns Settling time to 1%; no blanking; GCSA = 20; Vstep = 0.46 V 600 Settling time to 1%; no blanking; GCSA = 40; Vstep = 0.46 V 1.2 µs Settling time to 1%; no blanking; GCSA = 80; Vstep = 0.46 V 2.4 VIOS DC input offset GCSA = 10; input shorted; RTI –4 4 mV VVREF_ERR Reference buffer error (DC) Internal or external VREF; TJ = –40 to 150 °C –2% 2% Internal or external VREF; TJ = 150 to 175 °C –3% 3% VDRIFTOS Input offset error drift GCSA = 10; input shorted; RTI 10 µV/C IBIAS Input bias current VIN_COM = 0; SOx open 100 µA IOFFSET Input bias current offset IBIAS (SNx-SPx); VIN_COM = 0; SOx open 1 µA VIN_COM Common input mode range –0.15 0.15 V VIN_DIFF Differential input range -0.48 0.48 V CMRR Common mode rejection ration External input resistance matched; DC; GCSA = 10 60 80 dB External input resistance matched; 20 kHz; GCSA = 10 60 80 PSRR Power supply rejection ratio DC (<120 Hz); GCSA = 10 150 dB 20 kHz; GCSA = 10 90 VSWING Output voltage swing PVDD > 5.3 V 0.3 4.7 V VSLEW Output slew rate GCSA = 10; RL = 0 Ω; CL = 60 pF 5.2 10 V/µs IVO Output short circuit current SOx shorted to ground 20 mA UGB Unity gain bandwidth product GCSA = 10 2 MHz VOLTAGE PROTECTION VAVDD_UVLO AVDD under voltage Fault Relative to GND 3.3 3.5 V VVREG_UV VREG under voltage Fault VREG_UV_LEVEL = 00 VREG x 0.9 V VREG_UV_LEVEL = 01 VREG x 0.8 VREG_UV_LEVEL = 10 VREG x 0.7 VREG_UV_LEVEL = 11 VREG x 0.7 VVREG_UV_DGL VREG under voltage monitor deglitch time 1.5 2 µs VPVDD_UVFL Under voltage protection warning, PVDD PVDD falling 7.7 8.1 V PVDD rising 7.9 8.3

PRODUCT□PREVIEW DRV8305-Q1 www.ti.com SLVSD12A –MAY 2015–REVISED MARCH 2016 Product Folder Links: DRV8305-Q1 Submit Documentation FeedbackCopyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT (1) Specified by design (2) Overtemperature shutdown (OTSD) is disabled by default for DRV8305xEPHPQ1 and may only be re-enabled through control register. VPVDD_UVLO1 Under voltage protection lock out, PVDD PVDD falling 4.1 V PVDD rising 4.3 VPVDD_UVLO2 Under voltage protection fault, PVDD PVDD falling 4.2 4.4 V PVDD rising 4.4 4.6 VPVDD_OVFL Overvoltage protection warning, PVDD PVDD falling 33.5 36 V PVDD rising 32.5 35 VVCPH_UVFL Charge pump under voltage protection warning, VCPH Relative to PVDD 8 V VVCPH_UVLO2 Charge pump under voltage protection fault, VCPH Relative to PVDD, SET_VCPH_UV = 0 4.5 4.9 V Relative to PVDD, SET_VCPH_UV = 1 4.2 4.6 VVCP_LSD_UVLO2 Low-side regulator under voltage fault, VCP_LSD Relative to GND 6.4 7.5 V VVCPH_OVLO Charge pump over voltage protection fault, VCPH Relative to PVDD 14 18 V VVCPH_OVLO_ABS Charge pump over voltage protection fault, VCPH Relative to GND 60 V TEMPERATURE PROTECTION OTW_CLR Junction temperature to clear over temperature (OTW) warning(1) 100 130 150 °C OTW_SET Junction temperature for over temperature (OTW) warning(1) 135 160 185 °C OTSD_CLR Junction temperature to clear over temperature shutdown (OTSD)(1) 125 155 180 °C OTSD_SET (2) Junction temperature for over temperature shutdown (OTSD)(1) 160 185 210 °C TEMP_FLAG1 Junction temperature flag setting 1(1) 105 °C TEMP_FLAG2 Junction temperature flag setting 2(1) 125 °C TEMP_FLAG3 Junction temperature flag setting 3(1) 135 °C TEMP_FLAG4 Junction temperature flag setting 4(1) 185 °C PROTECTION CONTROL tpd,E-L Delay, error event to all gates low TBLANK = 00; TVDS = 00 1 µs tpd,E-SD Delay, error event to nFAULTx low TBLANK = 00; TVDS = 00 1 µs

PRODUCT□PREVIEW DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated Electrical Characteristics (continued) PVDD = 4.4 to 45 V, DRV8305xQ: TJ = –40°C to 150°C, DRV8305xE: TJ = –40°C to 175°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FET CURRENT PROTECTION (VDS SENSING) VDS_TRIP Drain-source voltage protection limit VDS_LEVEL = 00000 0.06 V VDS_LEVEL = 00001 0.068 VDS_LEVEL = 00010 0.076 VDS_LEVEL = 00011 0.086 VDS_LEVEL = 00100 0.097 VDS_LEVEL = 00101 0.109 VDS_LEVEL = 00110 0.123 VDS_LEVEL = 00111 0.138 VDS_LEVEL = 01000 0.155 VDS_LEVEL = 01001 0.175 VDS_LEVEL = 01010 0.197 VDS_LEVEL = 01011 0.222 VDS_LEVEL = 01100 0.25 VDS_LEVEL = 01101 0.282 VDS_LEVEL = 01110 0.317 VDS_LEVEL = 01111 0.358 VDS_LEVEL = 10000 0.403 VDS_LEVEL = 10001 0.454 VDS_LEVEL = 10010 0.511 VDS_LEVEL = 10011 0.576 VDS_LEVEL = 10100 0.648 VDS_LEVEL = 10101 0.73 VDS_LEVEL = 10110 0.822 VDS_LEVEL = 10111 0.926 VDS_LEVEL = 11000 1.043 VDS_LEVEL = 11001 1.175 VDS_LEVEL = 11010 1.324 VDS_LEVEL = 11011 1.491 VDS_LEVEL = 11100 1.679 VDS_LEVEL = 11101 1.892 VDS_LEVEL = 11110 2.131 VDS_LEVEL = 11111 2.131 tVDS VDS sense deglitch time TVDS = 00 0 µs TVDS = 01 1.75 TVDS = 10 3.5 TVDS = 11 7 tBLANK VDS sense blanking time TBLANK = 00 0 µs TBLANK = 01 1.75 TBLANK = 10 3.5 TBLANK = 11 7 tWARN_PULSE nFAULT pin warning pulse length 56 µs PHASE SHORT PROTECTION VSNSOCP_TRIP Phase short protection limit Fixed voltage 2 V

6.6 SPI Timing Requirements (Slave Mode Only)

Figure 1. SPI Slave Mode Timing Definition

6.7 Typical Characteristics

Figure 2. Standby Current Figure 3. Operating Current Figure 4. Sleep Current Figure 5. VCPH Voltage

7 Detailed Description

7.1 Overview

The DRV8305-Q1 is a 4.4-V to 45-V automotive gate driver IC for three-phase motor driver applications. This device reduces external component count in the system by integrating three half-bridge drivers, charge pump, three current shunt amplifiers, an uncommited 3.3-V or 5-V, 50-mA LDO, and a variety of protection circuits. The DRV8305-Q1 provides overcurrent, shoot-through, overtemperature, overvoltage, and undervoltage protection. Fault conditions are indicated by the nFAULT pin and specific fault information can be read back from the SPI registers. The protection circuits are highly configurable to allow adaptation to different applications and support limp home operation. The gate driver uses a tripler charge pump to generate the appropriate gate to source voltage bias for the external, high-side N-channel power MOSFETs during low supply conditions. A regulated 10-V LDO derived from the charge pump supplies the gate to source voltage bias for the low-side N-channel MOSFET. The high-side and low-side peak gate drive currents are adjustable through the SPI registers to finely tune the switching of the external MOSFETs without the need for external components. An internal handshaking scheme is used to prevent shoot-through and minimize the dead time when transitioning between MOSFETs in each half-bridge. Multiple input methods are provided to accommodate different control schemes including a 1-PWM mode which integrates a six-step block commutation table for BLDC motor control. VDS sensing of the external power MOSFETs allows for the DRV8305-Q1 to detect overcurrent conditions and respond appropriately. Integrated blanking and deglitch timers are provided to prevent false trips related to switching or transient noise. Individual MOSFET overcurrent conditions are reported through the SPI status registers and nFAULT pin. A dedicated VDRAIN pin is provided to accurately sense the drain voltage of the high- side MOSFET. The three internal current shunt amplifiers allow for the implementation of common motor control schemes that require sensing of the half-bridge currents through a low-side current shunt resistor. The amplifier gain, reference voltage, and blanking are adjustable through the SPI registers. A calibration method is providing to minimize inaccuracy related to offset voltage. Three versions of the DRV8305-Q1 are available with separate part numbers for the different devices options:

DRV8305NQ: VREG pin has the internal LDO disabled and is only used as a voltage reference input for the amplifiers and SDO pullup. Grade 1.
DRV83053Q: VREG is a 3.3-V, 50-mA LDO output pin. Grade 1.
DRV83055Q: VREG is a 5.0-V, 50-mA LDO output pin. Grade 1.
DRV8305NE: VREG pin has the internal LDO disabled and is only used as a voltage reference input for the amplifiers and SDO pullup. Grade 0.

PRODUCT□PREVIEW VREG LDO Digital Inputs and Outputs Core Logic SPI SCLK nSCS SDI SDO Voltage Monitoring Thermal Sensor EN_GATE INH_A INL_A nFAULT INH_B INL_B INH_C INL_C Current Sense Amplifier 1 Current Sense Amplifier 2 Current Sense Amplifier 3 SN1 SP1 SN2 SP2 SN3 SP3 Ref/k Ref/k Ref/k VCPH GH_A SH_A GL_A SL_A HS VCP_LSD LS VDS VDS VDRAIN Phase A Pre-Driver VCPH GH_B SH_B GL_B SL_B HS VCP_LSD LS VDS VDS VDRAIN Phase B Pre-Driver VCPH GH_C SH_C GL_C SL_C HS VCP_LSD LS VDS VDS VDRAIN Phase C Pre-Driver PVDD PVDD Control Configuration Timing Protection PVDD AVDD AVDD AVDD VREG VREG VREG High Side Gate Drive 2-Stage Charge Pump VDRAIN VDRAIN PVDD VCPH CP1LCP1HCP2LCP2H Low Side Gate Drive LDO VCP_LSD VCP_LSD DVDD LDO AVDD LDO AVDDDVDD AVDDDVDD SO1 SO2 SO3 WAKE VREG/VREF PWRGD GND PowerPADGND VCPH VREG VREG DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Integrated Three-Phase Gate Driver

allows for it to be used in a broad range of applications.

7.3.2 INHx/INLx: Gate Driver Input Modes

The DRV8305-Q1 can be operated in three different inputs modes to support various commutation schemes.

Table 2 shows the truth table for the 6-PWM input mode. This mode allows for each half-bridge to be placed in one of three states, either High, Low, or Hi-Z, based on the inputs.

Table 2. 6-PWM Truth Table Figure 6. 6-PWM Mode

Table 3 shows the truth table for the 3-PWM input mode. This mode allows for each half-bridge to be placed in one of two states, either High or Low, based on the inputs. The three high-side inputs (INHx) are used to control the state of the half-bridge with the complimentary low-side signals being generated internally. Deadtime can be adjusted through the internal setting (DEAD_TIME) in the SPI registers. In this mode all activity on INLx is ignored.

Table 3. 3-PWM Truth Table

1 X H L

0 X L H

1 PWM

Figure 7. 3-PWM Mode

Table 4 and Table 5 show the truth tables for the 1-PWM input mode. The 1-PWM mode uses an internally stored 6-step block commutation table to control the outputs of the three half-bridge drivers based on one PWM and three GPIO inputs. This mode allows the use of a lower cost microcontroller by requiring only one PWM resource. The PWM signal is applied on pin INHA (PWM_IN) to set the duty cycle of the half-bridge outputs along with the three GPIO signals on pins INLA (PHC_0), INHB (PHC_1), INLB (PHC_2) that serve to set the value of a three bit register for the commutation table. The PWM may be operated from 0-100% duty cycle. The three bit register is used to select the state for each half-bridge for a total of eight states including an align and stop state. An additional and optional GPIO, INHC (DWELL) can be used to facilitate the insertion of dwell states or phase current overlap states between the six commutation steps. This may be used to reduce acoustic noise and improve motion through the reduction of abrupt current direction changes when switching between states. INHC must be high when the state is changed and the dwell state will exist until INHC is taken low. If the dwell states are not being used, the INHC pin can be tied low. In 1-PWM mode all activity on INLC is ignored.

Figure 8. 1-PWM Mode

Table 4. 1-PWM Active Freewheeling Table 5. 1-PWM Diode Freewheeling

7.3.3 VCPH Charge Pump: High-Side Gate Supply

The DRV8305-Q1 uses a charge pump to generate the proper gate to source voltage bias for the high-side N- channel MOSFETs. Similar to the often used bootstrap architecture, the charge pump generates a floating supply voltage used to enable the MOSFET. When enabled, the gate of the external MOSFET is connected to VCPH through the internal gate drivers. The charge pump of the DRV8305-Q1 regulates the VCPH supply to PVDD + 10-V in order to support both standard and logic level MOSFETs. As opposed to a bootstrap architecture, the charge pump supports 0 to 100% duty cycle operation by eliminating the need to refresh the bootstrap capacitor. The charge pump also removes the need for bootstrap capacitors to be connected to the switch-node of the half- bridge. In order to support automotive cold crank transients on the battery which require the system to be operational to as low as 4.4 V, a regulated triple charge pump scheme is used to create sufficient VGS to drive standard and logic level MOSFETs during the low voltage transient. Between 4.4 to 18 V the charge pump regulates the voltage in a tripler mode. Beyond 18 V and until the max operating voltage, it switches over to a doubler mode in order to improve efficiency. The charge pump is disabled until EN_GATE is set high to reduce unneeded power consumption by the IC. After EN_GATE is set high, the device will go through a power up sequence to enable the gate drivers and gate drive supplies. 1 ms should be allocated after EN_GATE is set high to allow the charge pump to reach its regulation voltage. The charge pump is continuously monitored for undervoltage and overvoltage conditions to prevent underdriven or overdriven MOSFET scenarios. If an undervoltage or overvoltage condition is detected the appropriate actions is taken and reported through the SPI registers.

7.3.4 VCP_LSD LDO: Low-Side Gate Supply

The DRV8305-Q1 uses a linear regulator to generate the proper gate to source voltage vias for the low-side N- channel MOSFETs. The linear regulator generates a fixed 10-V supply voltage with respect to GND. When enabled, the gate of the external MOSFET is connected to VCPH_LSD through the internal gate drivers. In order to support automotive cold crank transients the input voltage for the VCP_LSD linear regulator is taken from the VCPH charge pump. This allows the DRV8305-Q1 to provide sufficient VGS to drive standard and logic level MOSFETs during the low voltage transient. The low-side regulator is disabled until EN_GATE is set high to reduce unneeded power consumption by the IC. After EN_GATE is set high, the device will go through a power up sequence for the gate drivers and gate drive supplies. 1 ms should be allocated after EN_GATE is set high to allow the low-side regulator to reach its regulation voltage. The VCP_LSD regulator is continuously monitored for undervoltage conditions to prevent underdriven MOSFET scenarios. If an undervoltage condition is detected the appropriate actions is taken and reported through the SPI registers.

7.3.5 GHx/GLx: Half-Bridge Gate Drivers

application benefits are outlined below as well as in application report, SLVA714. Figure 9. DRV8305-Q1 Gate Driver Architecture

7.3.5.1 IDRIVE: Gate Driver Output Current

different operating conditions through software alone.

(sink)/70 mA (source) current settings in order to maintain the accuracy required for precise slew rate control. switches are used to minimize the power losses associated with mirroring such large currents.

QGS = Gate-to-source charge
QGD = Gate-to-drain charge (Miller charge)

Figure 10. MOSFET Charge Example

7.3.5.2 TDRIVE: Gate Driver State Machine

drive system with minimal overhead. added externally through the MCU or SPI register will be inserted after the handshake process.

enabled or disabled and improve efficiency of the gate drive. will simply terminate if a PWM command is received while it is active. Figure 11. TDRIVE Gate Drive State Machine

7.3.5.3 CSAs: Current Shunt Amplifiers

control through the application MCU.

Each of the three current sense amplifiers can be programmed and calibrated independently.
Can provide output bias up to 2.5 V to support bidirectional current sensing.
May be used for either individual or total current shunt sensing.
Four programmable gain settings through SPI registers (10, 20, 40 and 80 V/V).
Reference voltage for output bias provided from voltage regulator VREG for DRV83053Q and DRV83055Q
Reference voltage for output bias provided from externally applied voltage on VREG pin for DRV8305NQ and DRV8305NE
Programmable output bias scaling. The scaling factor k can be programmed through SPI registers (1/2 or 1/4)
Programmable blanking time (delay) of the amplifier outputs. The blanking time is implemented from any rising or falling edge of gate drive outputs. The blanking time is applied to all three current sense amplifiers equally. In case the current sense amplifiers are already being blanked when another gate driver rising or falling edge is seen, the blanking interval will be restarted at the edge. Note that the blanking time options do

7.3.6 DVDD and AVDD: Internal Voltage Regulators

The DRV8305-Q1 has two internal regulators, DVDD and AVDD, that power internal circuitry. These regulators cannot be used to drive external loads and may not be supplied externally. DVDD is the voltage regulator for the internal logic circuits and is maintained at a value of 3.3 V through the entire operating range of the device. DVDD is derived from the PVDD power supply. DVDD should be bypassed externally with a 1-µF capacitor to GND. AVDD is the voltage regulator that provides the voltage rail for the internal analog circuit blocks including the current sense amplifiers and is maintained at a value 5.0 V. AVDD is derived from the PVDD voltage power supply. AVDD should be bypassed externally with a 1-µF capacitor to GND. Because the allowed PVDD operating range of the device permits operation below the nominal value of AVDD, this regulator operates in two regimes: namely a linear regulating regime and a dropout region. In the dropout region, the AVDD will simply track the PVDD voltage minus a voltage drop. If the device is expected to operate within the dropout region, take care while selecting current sense amplifier components and settings to accommodate the reduced voltage rail.

7.3.7 VREG: Voltage Regulator Output

The DRV8305-Q1 integrates a 50 mA, LDO voltage regulator (VREG) that is dedicated for driving external loads such as an MCU directly. The VREG regulator also supplies the reference for the SDO output of the SPI bus and the voltage reference for the amplifier output bias. The three different DRV8305-Q1 device versions provide different configurations for the VREG output. For the DRV83053Q, the VREG output is regulated at 3.3 V. For the DRV83055Q, the VREG output is regulated at 5.0 V. For the DRV8305NQ and DRV8305NE, the VREG voltage regulator is disabled (VREG pin used for reference voltage) and the reference voltage for SDO and the amplifier output bias must be supplied from an external supply to the VREG pin. The DRV8305-Q1 VREG voltage regulator also features a PWRGD pin to protect against brownouts on externally driven devices. The PWRGD pin is often tied to the reset pin of a microcontroller to ensure that the microcontroller is always reset when the VREG output voltage is outside of its recommended operation area. When the voltage output of the VREG regulator drops or exceeds the set threshold (programmable).

The PWRGD pin will go low for a period of 56 µs.
After the 56 µs period has expired, the VREG voltage will be checked and PWRGD will be held low until the VREG voltage has recovered. The voltage regulator also has undervoltage protection implemented for both the input voltage (PVDD) and output voltage (VREG).

7.3.8 Protection Features

7.3.8.1 Fault and Warning Classification

The DRV8305-Q1 integrates extensive error detection and monitoring features. These features allow the design of a robust system that can protect against a variety of system related failure modes. The DRV8305-Q1 classifies error events into two categories and takes different device actions dependent on the error classification. The first error class is a Warning. There are several types of conditions that are classified as warning only. Warning errors are report only and the DRV8305-Q1 will take no other action effecting the gate drivers or other blocks. When a warning condition occurs it will be reported in the corresponding SPI status register bit and on the nFAULT pin with a repeating 56 µs pulse low followed by a 56 µs pulse high. A warning error can be cleared by an SPI read to the corresponding status register bit. The same warning will not be reported through the nFAULT pin again unless that warning or condition passes and then reoccurs.

A warning error is reported on the nFAULT pin with a repeating 56 µs pulse low followed by a 56 µs pulse high
The warning is reported on the nFAULT pin until a SPI read to the corresponding status register
The SPI read will clear the nFAULT report, but the SPI register will remain asserted until the condition has passed
The nFAULT pin will report a new warning if the condition clears and then occurs again

PRODUCT□PREVIEW DRV8305-Q1 SLVSD12A –MAY 2015–REVISED MARCH 2016 www.ti.com Product Folder Links: DRV8305-Q1 Submit Documentation Feedback Copyright © 2015–2016, Texas Instruments Incorporated The second error class is a Fault. Fault errors will trigger a shutdown of the gate driver with its major blocks and are reported by holding nFAULT low with the corresponding status register asserted. Fault errors are latched until the appropriate recovery sequence is performed.

A fault error is reported by holding the nFAULT pin low and asserting the FAULT bit in register 0x1
The error type will also be asserted in the SPI registers
A fault error is a latched fault and must be cleared with the appropriate recovery sequence
If a fault occurs during a warning error, the fault error will take precendence, latch nFAULT low and shutdown the gate driver
The output MOSFETs will be placed into their high impedance state in a fault error event
To recover from a fault type error, the condition must be removed and the CLR_FLTs bit asserted in register 0x9, bit D1 or an EN_GATE reset pulse issued
The CLR_FLTS bit self clears to 0 after fault status reset and nFAULT pin is released There are two exceptions to the fault and warning error classes. The first exception is the temperature flag warnings (TEMP_FLAGX). A Temperature Flag warning will not trigger any action on the nFAULT pin and the corresponding status bit will be updated in real time. See the overtemperature section for additional information. The second exception is the MCU Watchdog and VREG Undervoltage (VREG_UV) faults. These are reported on the PWRGD pin to protect the system from lock out and brownout conditions. See their corresponding sections for additional information. Note that nFAULT is an open-drain signal and must be pulled up through an external resistor.

7.3.8.2 MOSFET Shoot-Through Protection (TDRIVE)

DRV8305-Q1 integrates analog handshaking and digital dead time to prevent shoot-through in the external MOSFETs.

An internal handshake through analog comparators is performed between each high-side and low-side MOSFET switching transaction (see TDRIVE: Gate Driver State Machine). The handshake monitors the voltage between the gate and source of the external MOSFET to ensure the device has reached its cutoff threshold before enabling the opposite MOSFET.
A minimum dead time (digital) of 40 ns is always inserted after each successful handshake. This digital dead time is programmable through the DEAD_TIME SPI setting in register 0x7, bits D6-D4 and is in addition to the time taken for the analog handshake.

7.3.8.3 MOSFET Overcurrent Protection (VDS_OCP)

To protect the system and external MOSFET from damage due to high current events, VDS overcurrent monitors are implemented in the DRV8305-Q1. The VDS sensing is implemented for both the high-side and low-side MOSFETs through the pins below:

High-side MOSFET: VDS measured between VDRAIN and SHx pins
Low-side MOSFET: VDS measured between SHx and SLx pins Based on the RDS(on) of the power MOSFETs and the maximum allowed IDS, a voltage threshold can be calculated, which when exceeded, triggers the VDS overcurrent protection feature. The voltage threshold level (VDS_LEVEL) is programmable through the SPI VDS_LEVEL setting in register 0xC, bits D7-D3 and may be changed during gate driver operation if needed. The VDS overcurrent monitors implement adjustable blanking and deglitch times to prevent false trips due to switching voltage transients. The VDS blanking time (tBLANK) is inserted digitally and programmable through the SPI TBLANK setting in register 0x7, bits D3-D2. The tBLANK time is inserted after each switch ON transistion (LOW to HIGH) of the output gate drivers is commanded. During the tBLANK time, the VDS comparators are not being monitored in order to prevent false trips when the MOSFET first turns ON. After the tBLANK time expires the overcurrent monitors will begin actively watching for an overcurrent event. The VDS deglitch time (tVDS) is inserted digitally and programmable through the SPI TVDS setting in register 0x7, bits D1-D0. The tVDS time is a delay inserted after the VDS sensing comparators have tripped to when the protection logic is informed that a VDS event has occurred. If the overcurrent event does not persist through tVDS delay then it will be ignored by the DRV8305-Q1. Note that the dead time and blanking time are overlapping timers as shown in Figure 13.

Figure 13. VDS Deglitch and Blank Diagram VDS_MODE setting in register 0xC, bits D2-D0.

VDS Latched Shutdown Mode: When a VDS overcurrent event occurs, the device will pull all gate drive outputs low in order to put all six external MOSFETs into high impedance mode. The fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers.
VDS Report Only Mode: In this mode, the device will take no action related to the gate drivers. When the overcurrent event is detected the fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was detected in reported through the SPI status registers. The gate drivers will continue to operate normally.
VDS Disabled Mode: The device ignores all the VDS overcurrent event detections and does not report them.

7.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)

gate driver switches back to a lower hold off pull down to improve efficiency.

7.3.8.3.2 MOSFET Gate Drive Protection (GDF)

voltage by a value that could be damaging to the external MOSFETs. the DIS_GDRV_FAULT setting in register 0x9, bit D8. encountered an abnormal condition.

7.3.8.4 Low-Side Source Monitors (SNS_OCP)

report a SNS_OCP fault error on the nFAULT pin and corresponding SPI status bit in register 0x2, bits D2-D0.

7.3.8.5 Fault and Warning Operating Modes

Table 6. Fault and Warning Operating Modes(1)

7.3.9 Undervoltage Warning (UVFL), Undervoltage Lockout (UVLO), and Overvoltage (OV) Protection

The DRV8305-Q1 implements undervoltage and overvoltage monitors on its system supplies to protect the system, prevent brownout conditons, and prevent unexpected device behavior. Undervoltage is monitored for on the PVDD, AVDD, VREF, VCPH, and VCP_LSD power supplies. Overvoltage is monitored for on the PVDD and VCPH power supplies. The values for the various undervoltage and overvoltage levels are provided in the electrical characteristics table under the voltage protection section. The monitors for the main power supply, PVDD, incorporates several additional features:

Undervoltage warning (PVDD_UVFL) level. Device operation is not impacted, report only indication.
PVDD_UVFL is warning type error indicated on the nFAULT pin and the PVDD_UVFL status bit in register 0x1, bit D7
Independent UVLO levels for the gate driver (PVDD_UVLO2) and VREG LDO regulator (PVDD_UVLO1). PVDD_UVLO2 will trigger a shutdown of the gate driver
PVDD_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register 0x3, bit D10
PVDD_UVLO2 may be disabled through the DIS_VPVDD_UVLO setting in register 0x9, bit D9. The fault will still be reported in the status bit in register 0x3, bit D10
Overvoltage detection to monitor for load dump or supply pumping conditions. Device operation is not impacted, report only indication
PVDD_OV is a warning type error indicated on the nFAULT pin and the PVDD_OV bit in register 0x1, bit D6 The monitors for the high-side charge pump supply, VCPH, and low-side supply (VCP_LSD) incorporate several additional features:
VCPH relative (VCPH_OVLO) and absolute overvoltage (VCPH_OVLO_ABS) detection. The DRV8305-Q1 monitors VCPH for overvoltage conditions with respect to PVDD and GND
VCPH_OVLO and VCPH_OVLO_ABS are fault type errors reported on nFAULT and the corresponding status bit in register 0x3, bits D1-D0
VCPH undervoltage (VCPH_UVLO2) is monitored to prevent underdriven MOSFET conditions. VCPH_UVLO2 will trigger a shutdown of the gate driver
VCPH_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register 0x3, bit D2
VCP_LSD undervoltage (VCP_LSD_UVLO2) is monitored to prevent underdriven MOSFET conditions. VCP_LSD_UVLO2 will trigger a shutdown of the gate driver
VCP_LSD_UVLO2 is a fault type error indicated on the nFAULT pin and corresponding status bit in register 0x3, bit D4
Undervoltage proteciton for VCPH and VCP_LSD may not be disabled in the operating state

7.3.9.1 Overtemperature Warning (OTW) and Shutdown (OTSD) Protection

A multi-level temperature detection circuit is implemented in the DRV8305-Q1.

Flag Level 1 (TEMP_FLAG1): Level 1 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D3.
Flag Level 2 (TEMP_FLAG2): Level 2 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D2.
Flag Level 3 (TEMP_FLAG3): Level 3 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D1.
Flag Level 4 (TEMP_FLAG4): Level 4 overtemperature flag. No warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D8.
Warning Level (OTW): Overtemperature warning only. Warning reported on nFAULT. Real-time flag indicated in SPI register 0x1, bit D0.
Fault Level (OTSD): Overtemperature fault and latched shut down of the device. Fault reported on nFAULT and in SPI register 0x3, bit D8. SPI operation is still available and register settings will be retained in the device during OTSD operation as long as PVDD is within operation range. An OTSD fault can be cleared when the device temperature has dropped below the fault level and a CLR_FLTS is issued.

7.3.9.2 Reverse Supply Protection

maximum external load on VCPH. resistor. The current limit resistor must be sized not to exceed the maximum current load on the VDRAIN pin. 100 Ω is recommended between VDRAIN and the drain of the external high-side MOSFET. Figure 14. Typical Scheme for Reverse Battery Protection Using VCPH

7.3.9.3 MCU Watchdog

The DRV8305-Q1 incorporates an MCU watchdog function to ensure that the external controller that is instructing the device is active and not in an unknown state. The MCU watchdog function may be enabled by writing a 1 to the WD_EN setting in the SPI register 0x9. bit D3. The default setting for the device is with the watchdog disabled. When the watchdog is enabled, an internal timer starts to countdown to the interval set by the WD_DLY setting in the SPI register 0x9, bits D6-D5. To restart the watchdog timer, the address 0x1 (status register) must be read by the controller within the interval set by the WD_DLY setting. If the watchdog timer is allowed to expire without the address 0x1 being read, a watchdog fault will be enabled. Response to a watchdog fault is as follows:

A latched fault occurs on the DRV8305-Q1 and the gate drivers are put into a safe state. An appropriate recovery sequence must then be performed.
The PWRGD pin is taken low for 56 µs and then back high in order to reset the controller or indicate the watchdog fault
The nFAULT pin is asserted low, the WD_EN bit is cleared, and the WD_FAULT set high in register 0x3, bit
It is recommended to read the status registers as part of the recovery or power-up routine in order to determine whether a WD_FAULT had previously occurred Note that the watchdog fault results in a clearing of the WD_EN setting and it will have to be set again to resume watchdog functionality.

7.3.9.4 VREG Undervoltage (VREG_UV)

The DRV8305-Q1 has an undervoltage monitor on the VREG output regulator to ensure the external controller does not experience a brownout condition. The undervoltage monitor will signal a fault if the VREG output drops below a set threshold from its set point. The VREG output set point is configured for two different levels, 3.3 V or 5 V, depending on the DRV8305-Q1 device options (DRV83053Q and DRV83055Q). The VREG undervoltage level can be set through the SPI setting VREG_UV_LEVEL in register 0xB, bits D1-D0. The VREG undervoltage monitor can be disabled through the SPI setting DIS_VREG_PWRGD in register 0xB, bit D2. Response to a VREG undervoltage fault is as follows:

A latched fault occurs on the DRV8305-Q1 and the gate drivers are put into a safe state. An appropriate recovery sequence must then be performed.
The PWRGD is taken low until the undervoltage condition is removed and for at least a minimum of 56 µs.
The nFAULT pin is asserted low and the VREG_UV bit set high in register 0x3, bit D6.
The fault can be cleared after the VREG undervoltage condition is removed with CLR_FLTS or an EN_GATE reset pulse Note that the VREG undervoltage monitor is disabled on the no regulator (VREF) device option (DRV8305NQ and DRV8305NE).

7.4 Device Functional Modes

7.4.1 Power Up Sequence

device. When PVDD power is applied the device will remain inactive until PVDD cross the digital logic threshold. point the device will enter its standby state. Figure 15. Power-Up Sequence

7.4.2 Standby State

device configurations through SPI in the standby state.

7.4.3 Operating State

occurs, the DRV8305-Q1 will immedietely re-enter the standby state.

7.4.4 Sleep State

values in the SPI control registers and it is not recommended to write through SPI in the sleep state.

7.4.5 Limp Home or Fail Code Operation

IDRIVE Gate Current Output (IDRIVEN_HS, IDRIVEP_HS, IDRIVEN_LS, IDRIVEP_LS): All four IDRIVEX settings may be adjusted during normal operation without issue. This features allows the software to change the slew rate, switching characteristics of the external MOSFETs on the fly if required without having to stop the motor rotation. The IDRIVEX settings are located in the SPI registers 0x5 (high-side) and 0x6 (low-side)
VDS Fault Mode (VDS_MODE): The VDS overcurrent monitors may be changed from latched shut down (VDS_MODE = b'000) or report only (VDS_MODE = b'001) modes to disabled (VDS_MODE = b'010) mode to allow operation of the external MOSFETs past normal operating conditions. This is the only VDS_MODE change allowed in the operating state. The VDS_MODE setting is located in the SPI register 0xC, bits D2-D0.
VDS Comparator Thresholds (VDS_LEVEL): The VDS overcurrent monitor threshold (VDS_LEVEL) may be changed at any time during operation to allow for higher that standard operating currents. The VDS_LEVEL setting is located in the SPI register 0xC.
VGS Fault Mode (DIS_GDRV_FAULT): The VGS fault detection monitors can be disabled through the SPI register 0x9, bit D8. Reporting in SPI will also be disabled as a result.
SNS_OCP Fault Mode (DIS_SNS_OCP): The sense amplifer overcurrent monitors can be disabled through the SPI register 0x9, bit D4. Reporting in SPI will also be disabled as a result.
PVDD Underoltage Lockout (DIS_VPVDD_UVLO2): The main power supply undervoltage lockout can be disabled through the SPI register 0x9, but D9. Reporting in SPI will also be disabled as a result.
OTSD Overtemperature Shutdown (FLIP_OTS): The overtemperature shutdown can be disabled through the SPI register 0x9, bit D10. Reporting in SPI will also be disabled as a result. The OTS overtemperature shutdown is disabled by default on the Grade 0, DRV8305xE device.

Figure 16. Operating States

7.5 Programming

7.5.1 SPI Communication

7.5.1.1 SPI

data with the first 5 bits (MSB) as don't cares.

CPOL (clock polarity) = 0 and CPHA (clock phase) = 1
SCLK must be low when nSCS transistions
Full 16 SCLK cycles
Data is always propogated on the rising edge of SCLK
Data is always captured on the falling edge of SCLK
MSB is shifted in and out first
When nSCS is high, SCLK and SDI are ignored and SDO is high impedance
nSCS should be taken high for at least 500 ns between frames
If the data sent to SDI is less than or greater than 16 bits it is considered a frame error and the data will be ignored.

7.5.1.2 SPI Format

Figure 17. SPI Slave Mode Timing Diagram

1 read or write bit W [15]
4 address bits A [14:11]
11 data bits D [10:0] The SPI output data (SDO) word response word is 11 bits long (first 5 bits are don't cares). It contains the content of the register being accessed. The MSB of the SDI word (W0) is the read/write bit. When W0 = 0, the input data is a write command. When W0 = 1, the input data is a read command. For a write command: The response word is the data currently in the register being written to. For a read command: The response word is the data currently in the register being read.

Table 7. SPI Input Data Control Word Format Table 8. SPI Output Data Response Word Format

7.6 Register Maps

Table 9. Register Map

7.6.1 Status Registers

out of the watchdog timer. Status registers are read only registers.

7.6.1.1 Warning and Watchdog Reset (Address = 0x1)

Table 10. Warning and Watchdog Reset Register Description

10 R FAULT 0x0 Fault indication

9 R RSVD 0x0 -

8 R TEMP_FLAG4 0x0 Temperature flag setting for approximately 175°C

7 R PVDD_UVFL 0x0 PVDD undervoltage flag warning

6 R PVDD_OVFL 0x0 PVDD overvoltage flag warning

5 R VDS_STATUS 0x0 Real time OR of all VDS overcurrent monitors

4 R VCHP_UVFL 0x0 Charge pump undervoltage flag warning

3 R TEMP_FLAG1 0x0 Temperature flag setting for approximately 105°C

2 R TEMP_FLAG2 0x0 Temperature flag setting for approximately 125°C

1 R TEMP_FLAG3 0x0 Temperature flag setting for approximately 135°C

0 R OTW 0x0 Overtemperature warning

7.6.1.2 OV/VDS Faults (Address = 0x2)

Table 11. OV/VDS Faults Register Description

10 R VDS_HA 0x0 VDS overcurrent fault for high-side MOSFET A

9 R VDS_LA 0x0 VDS overcurrent fault for low-side MOSFET A

8 R VDS_HB 0x0 VDS overcurrent fault for high-side MOSFET B

7 R VDS_LB 0x0 VDS overcurrent fault for low-side MOSFET B

6 R VDS_HC 0x0 VDS overcurrent fault for high-side MOSFET C

5 R VDS_LC 0x0 VDS overcurrent fault for low-side MOSFET C

2 R SNS_C_OCP 0x0 Sense C overcurrent fault

1 R SNS_B_OCP 0x0 Sense B overcurrent fault

0 R SNS_A_OCP 0x0 Sense A overcurrent fault

7.6.1.3 IC Faults (Address = 0x3)

Table 12. IC Faults Register Description

10 R PVDD_UVLO2 0x0 PVDD undervoltage 2 fault

9 R WD_FAULT 0x0 Watchdog fault

8 R OTSD 0x0 Overtemperature fault

7 R RSVD 0x0 -

6 R VREG_UV 0x0 VREG undervoltage fault

5 R AVDD_UVLO 0x0 AVDD undervoltage fault

4 R VCP_LSD_UVLO2 0x0 Low-side gate supply fault

3 R RSVD 0x0 -

2 R VCPH_UVLO2 0x0 High-side charge pump undervoltage 2 fault

1 R VCPH_OVLO 0x0 High-side charge pump overvoltage fault

0 R VCPH_OVLO_ABS 0x0 High-side charge pump overvoltage ABS fault

7.6.1.4 VGS Faults (Address = 0x4)

Table 13. Gate Driver VGS Faults Register Description

10 R VGS_HA 0x0 VGS gate drive fault for high-side MOSFET A

9 R VGS_LA 0x0 VGS gate drive fault for low-side MOSFET A

8 R VGS_HB 0x0 VGS gate drive fault for high-side MOSFET B

7 R VGS_LB 0x0 VGS gate drive fault for low-side MOSFET B

6 R VGS_HC 0x0 VGS gate drive fault for high-side MOSFET C

5 R VGS_LC 0x0 VGS gate drive fault for low-side MOSFET C

7.6.2 Control Registers

Control registers are used to set the device parameters for DRV8305-Q1. The default values are shown in bold.

Control registers are read/write registers
Do not clear on register read, CLR_FLTs, or EN_GATE resets
Cleared to default values on power up
Cleared to default values when the device enters SLEEP mode

7.6.2.1 HS Gate Drive Control (Address = 0x5)

Table 14. HS Gate Driver Control Register Description

10 R/W RSVD 0x0 -

7.6.2.2 LS Gate Drive Control (Address = 0x6)

Table 15. LS Gate Driver Control Register Description

7.6.2.3 Gate Drive Control (Address = 0x7)

Table 16. Gate Drive Control Register Description

10 R/W VCPH_FREQ 0x0 Reduce charge pump frequency center and spread

9 R/W COMM_OPTION 0x1 Rectification control (PWM_MODE = b'10 only)

(1) Overtemperature shutdown (OTSD) is disabled by default for DRV8305xEPHPQ1 and may only be re-enabled through this control bit.

7.6.2.4 IC Operation (Address = 0x9)

Table 17. IC Operation Register Description

10 R/W FLIP_OTSD 0x0 Enable OTSD(1)

9 R/W DIS_PVDD_UVLO2 0x0 Disable PVDD_UVLO2 fault and reporting

8 R/W DIS_GDRV_FAULT 0x0 Disable gate drive fault and reporting

7 R/W EN_SNS_CLAMP 0x0 Enable sense amplifier clamp

4 R/W DIS_SNS_OCP 0x0 Disable SNS overcurrent protection fault and reporting

3 R/W WD_EN 0x0 Watchdog enable

2 R/W SLEEP 0x0 Put device into sleep mode

1 R/W CLR_FLTS 0x0 Clear faults

0 R/W SET_VCPH_UV 0x0 Set charge pump undervoltage threshold level

7.6.2.5 Shunt Amplifier Control (Address = 0xA)

Table 18. Shunt Amplifier Control Register Description

10 R/W DC_CAL_CH3 0x0 DC calibration of CS amplifier 3

9 R/W DC_CAL_CH2 0x0 DC calibration of CS amplifier 2

8 R/W DC_CAL_CH1 0x0 DC calibration of CS amplifier 1

7.6.2.6 Voltage Regulator Control (Address = 0xB)

Table 19. Voltage Regulator Control Register Description

2 R/W DIS_VREG_PWRGD 0x0 Disable VREG undervoltage fault and reporting

7.6.2.7 VDS Sense Control (Address = 0xC)

Table 20. VDS Sense Control Register Description

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8305-Q1 is a gate driver IC designed to drive a 3-phase BLDC motor in combination with external power MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, three current shunt amplifiers, adjustable slew rate control, logic LDO, and a suite of protection features.

2 INHA

3 INLA

4 INHB

5 INLB

6 INHC

7 INLC

10 SDI

11 SDO

12 SCLK

14 GND

15 AVDD

16 SO1

17 SO2

18 SO3

19 SN3

20 SP3

21 SN2

22 SP2

23 SN1

24 SP1

8.2 Typical Application

The following design is a common application of the DRV8305-Q1. Figure 18. Typical Application Schematic

8.2.1 Design Requirements

Table 21. Design Parameters

8.2.2 Detailed Design Procedure

8.2.2.1 Gate Drive Average Current

approximate RMS load on the gate drive supply through the following equation. Note that this is only a first-order approximation.

8.2.2.2 MOSFET Slew Rates

but a rough first-order approximation can be calculated as shown in the following.

8.2.2.3 Overcurrent Protection

overcurrent conditions and are not for precise current regulation. exceeds the VDS_LEVEL value, the DRV8305-Q1 will take action according to the VDS_MODE register. The overcurrent trip level can be determined with the MOSFET RDS(on) and the VDS_LEVEL setting.

8.2.2.4 Current Sense Amplifiers

configure the current shunt amplifiers.

Determine the peak current that the motor will demand (IMAX). This demand depends on the motor

parameters and the application requirements. IMAX in this example is 14 A.

Determine the available voltage output range for the current shunt amplifiers. This will be the ± voltage

V. This gives an output range of ±1.65 V.

Determine the sense resistor value and amplifier gain settings. The sense resistor value and amplifier gain

(10 V/V). These values allow the current shunt amplifiers to measure ±33 A across the sense resistor.

8.2.3 Application Curves

Figure 19. Gate Drive 20% Duty Cycle Figure 20. Gate Drive 80% Duty Cycle Figure 21. Motor Spinning 1000 RPM Figure 22. Motor Spinning 2000 RPM

9 Power Supply Recommendations

9.1 Bulk Capacitance

beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.

Highest current required by the motor system
Power supply’s capacitance and ability to source or sink current
Amount of parasitic inductance between the power supply and motor system
Acceptable voltage ripple
Type of motor used (brushed DC, brushless DC, stepper)
Motor braking method The inductance between the power supply and motor drive system will limit the rate current can change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage remains stable and high current can be quickly supplied. The data sheet generally provides a recommended value, but system-level testing is required to determine the appropriate-sized bulk capacitor.

Figure 23. Example Setup of Motor Drive System With External Power Supply when the motor transfers energy to the supply.

10 Layout

10.1 Layout Guidelines

Use the following layout recommendations when designing a PCB for the DRV8305-Q1.

The DVDD and AVDD 1-μF bypass capacitors should connect directly to the adjacent GND pin to minimize loop impedance for the bypass capacitor.
The CP1 and CP2 0.047-μF flying capacitors should be placed directly next to the DRV8305-Q1 charge pump pins.
The VCPH 2.2-μF and VCP_LSD 1-μF bypass capacitors should be placed close to their corresponding pins with a direct path back to the DRV8305-Q1 GND net.
The PVDD 4.7-μF bypass capacitor should be placed as close as possible to the DRV8305-Q1 PVDD supply pin.
Use the proper footprint as shown in the mechanical drawing.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the DRV8305- Q1 GH_X to the power MOSFET and returns through SH_X. The low-side loop is from the DRV8305-Q1 GL_X to the power MOSFET and returns through SL_X.
The VDRAIN pin is used to sense the DRAIN voltage of the high-side MOSFETs for the VDS overcurrent monitors. It should route through the 100 Ω series resistor directly to the MOSFET DRAIN, ideally at the midpoint of the half-bridge connections in order to get the most accurate sense point.

10.2 Layout Example

Figure 24. Layout Recommendation

11 Device and Documentation Support

11.1 Documentation Support

See the following documents for additional information.

Understanding IDRIVE and TDRIVE in TI Motor Gate Drivers, SLVA714.
PowerPAD™ Thermally Enhanced Package, SLMA002
PowerPAD™ Made Easy, SLMA004
Sensored 3-Phase BLDC Motor Control Using MSP430, SLAA503

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 5-Feb-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DRV83053QPHPQ1 PREVIEW HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV83053Q DRV83053QPHPRQ1 PREVIEW HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV83053Q DRV83055QPHPQ1 PREVIEW HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV83055Q DRV83055QPHPRQ1 PREVIEW HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV83055Q DRV8305NEPHPQ1 PREVIEW HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 DRV8305NE DRV8305NEPHPRQ1 PREVIEW HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 150 DRV8305NE DRV8305NQPHPQ1 PREVIEW HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV8305NQ DRV8305NQPHPRQ1 PREVIEW HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV8305NQ PDRV83053QPHPRQ1 PREVIEW HTQFP PHP 48 1000 TBD Call TI Call TI -40 to 125 PDRV83055QPHPRQ1 PREVIEW HTQFP PHP 48 1000 TBD Call TI Call TI -40 to 125 PDRV8305NEPHPRQ1 PREVIEW HTQFP PHP 48 1000 TBD Call TI Call TI -40 to 125 PDRV8305NQPHPRQ1 PREVIEW HTQFP PHP 48 1000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

www.ti.com 5-Feb-2016 Addendum-Page 2 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DRV8305-Q1 :

Catalog: DRV8305 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

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Product Information

PDRV8305NEPHPRQ1 specifications and overview.

Summary

Three-Phase Automotive Gate Driver

Description

Three-Phase Automotive Gate Driver

Source title PDRV8305NEPHPRQ1 Datasheet(PDF) - Texas Instruments

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