PDRV8161DGSR

DRV8161_V01 TI | Alldatasheet

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Technical content

DRV816x 100V Half-Bridge Smart Gate Driver with Integrated Protection and Current Sense Amplifier

1 Features

• Drives two N-channel MOSFETs in half-bridge configuration – High-side MOSFET source/drain up to 102V (absolute max) – 8V (5V DRV8162L) to 20V gate drive power supply – Integrated bootstrap diode
• 16-level gate drive peak current – 16mA - 1000mA source current – 32mA - 2000mA sink current – Source-sink current ratio 1:1, 1:2, 1:3
• Adjustable PWM dead time insertion 20ns - 400ns
• Robust design for motor phase (SH) switching – Slew rate 20V/ns – Negative transient voltage -20V – 2-A strong gate pull down
• Split gate drive supply inputs for redundant shutdown (DRV8162, DRV8162L)
• Low-offset current sense amplifier (DRV8161) – Adjustable gain (5, 10, 20, 40 V/V)
• Flexible PWM control interface; 2-pin PWM, and independent PWM mode
• 13-level VDS over current threshold
• Independent shutdown pin (nDRVOFF)
• Gate driver soft shutdown sequence
• Integrated protection features – GVDD under voltage (GVDDUV) – Bootstrap under voltage (BST_UV) – MOSFET over current protection (VDS) – Shoot through protection – Thermal shutdown (OTSD) – Fault condition indicator (nFAULT)
• Supports 3.3V, and 5V Logic Inputs

2 Applications

• Industrial & collaborative robot
• Mobile robot (AGV/AMR)
• Linear motor transport systems
• Servo Drives
• Drones
• E-Bikes, E-Scooters, E-Mobility

3 Description

The DRV816x devices are half-bridge gate drivers capable of driving high-side and low-side N-channel MOSFETs. The gate drive voltages are generated from the GVDD supply pin and the integrated bootstrap circuit is used to drive the high-side FET up to 102V drain. The Smart Gate Drive architecture supports 16-level (48 combination) gate drive peak current up to 1A source and 2A sink, and a built-in timing control of gate drive current. The devices can be used to drive various types of loads including brushless/brushed DC motors, PMSM, stepper motors, SRM, and solenoids. Internal protection functions are provided for supply undervoltage, FET over-current, and die over temperature. The nFAULT pin indicates fault events detected by the protection features. The nDRVOFF pin initiates power stage shutdown independent from PWM control. The DRV8162 and DRV8162L devices offer split power supply architecture to assist safe torque off (STO) function. Many device parameters including gate drive current, dead time, PWM control interface, and over current detection are configurable with a few passive components connected to device pins. An integrated low-side current sense amplifier (DRV8161) provides current measurement information back to the controller. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) DRV8161 VSSOP (20) 5.1mm × 3.0mm DRV8162(2) VSSOP (20) 5.1mm × 3.0mm (1) For more information, see Section 12 (2) Includes DRV8162 (Product Preview) and DRV8162L (Advance Information) device variant. See the Device Comparison Table. M 5 to 90 V (102V Abs Max) DRV816x Single Half-Bridge Gate Driver Gate Drive Current Sense (DRV8161) N-Channel MOSFETsnDRVOFF/ nFAULT PWM (INH/L) Smart Gate Driver 5 or 8 to 20 V 1x CSA (DRV8161) Protections Controller x3 for 3-phase BLDC Current Sense Feedback DRV816x Simplified Schematic ADVANCE INFORMATION DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

10.3 Receiving Notification of Documentation Updates..37

12 Mechanical, Packaging, and Orderable

DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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4 Device Comparison Table

DRV8161 DRV8161(1) YES GVDD 8-V 2-pin, Independent FETDRV8162 DRV8162(2) No GVDD and GVDD_LS 8-V DRV8162L(1) 5-V (1) Advance Information. The products are in sampling and preproduction phase. (2) Product Preview. The product is in the formative or design phase. Contact TI for more information. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

5 Pin Configuration and Functions

Figure 5-1. DRV8161 (Advance Information) DGS Package 20-pin VSSOP Top View 8IDRIVE1 13 GVDD_LS 9NC 12 GND 10GVDD 11 IDRIVE2 1DT/MODE 20 VDRAIN 2INH/IN 19 BST 3INL/EN 18 SH 4NC 17 GH 5nDRVOFF 16 NC 6nFAULT 15 GL 7VDSLVL 14 SL Figure 5-2. DRV8162 (Product Preview) and DRV8162L (Advance Information) DGS Package 20- pin VSSOP Top View Table 5-1. Pin Functions—DRV816x Devices PIN TYPE DESCRIPTION NAME NO. DRV8161 20-pin DRV8162, DRV8162L 20-pin DT/MODE 1 1 I Selects input pin interface logic and gate drive dead time setting. Connect a resistor between DT and GND to adjust dead time between 20 ns to 1000 ns, and select a PWM mode. INLH/IN 2 2 I Gate driver control input. Gate driver control depends on DT/MODE pin setting. INL/EN 3 3 I Gate driver control input. Gate driver control depends on DT/MODE pin setting. NC — 4 N/A No Connect. Leave open. nDRVOFF — 5 I Gate driver shutdown control. Pulling nDRVOFF low turns off high-side and low-side external MOSFETs by putting the gate drivers into the pull-down state. nFAULT/ nDRVOFF 4 — I/OD Shared fault indicator pin and gate driver shutdown pin. Connect this pin to an external pull-up resistor to the controller supply or a controller output pin. This pin is pulled logic low during a fault condition. To active gate drive shutdown, pull the pin low by external logic. nFAULT — 6 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pull-up resistor to controller I/O supply, 3.3V to 5.0V. VDSLVL 5 7 I VDS monitor threshold setting. This pin is a multilevel input pin set by an external resistor. CSAREF 6 — PWR Current sense amplifier reference. Connect a capacitor between the CSAREF and GND pins. SO 7 — O Current sense amplifier output. CSAGAIN 8 — I Gain settings for current sense amplifier. This pin is a multilevel input pin set by an external resistor. IDRIVE1 9 8 I Gate drive source and sink current setting. This pin is a multilevel input pin set by an external resistor. NC 9, 16 No Connect. Leave open. GVDD 10 10 PWR Gate driver power supply input. Connect a capacitor between the GVDD and GND pins. IDRIVE2 11 11 I Gate drive source and sink current setting. This pin is a multilevel input pin set by an external resistor. DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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Table 5-1. Pin Functions—DRV816x Devices (continued) PIN TYPE DESCRIPTION NAME NO. DRV8161 20-pin DRV8162, DRV8162L 20-pin GND 12 12 PWR Device ground. GVDD_LS — 13 PWR Low-side gate driver power supply input (DRV8162 and DRV8162L only). Connect a capacitor between the GVDD_LS and GND pins. SN 13 — I Current sense amplifier input. Connect to the low-side of the current shunt resistor. SP 14 — I Current shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. SL 15 14 I Low-side source pin. Connect to the low-side power MOSFET source. This pin is an input for the VDS monitor and the output for the low-side gate driver sink. GL 16 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET. GH 17 17 O High-side gate driver output. Connect to the gate of the high-side power MOSFET. SH 18 18 I High-side source pin. Connect to the high-side power MOSFET source. This pin is an input for the VDS monitor and the output for the high-side gate driver sink. BST 19 19 O Bootstrap output pin. Connect a capacitor between BST and SH. VDRAIN 20 20 PWR High-side MOSFET drain sense input for VDS monitor and charge pump reference. Connect to the high-side MOSFET drain. THERMAL PAD PWR Leave open, or tied to GND PWR = power, I = input, O = output, NC = no connection, OD = open-drain output www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

6 Specification

6.1 Absolute Maximum Ratings

Over recommended operating conditions (unless otherwise noted)(1) MIN MAX UNIT Gate driver regulator pin voltage GVDD, GVDD_LS -0.3 20 V High-side drain pin voltage VDRAIN, TJ = 25℃ -0.3 102 V Bootstrap pin voltage BST, TJ = 25℃ -0.3 115 V Bootstrap pin voltage BST with respect to SH -0.3 20 V Logic pin voltage nFAULT -0.3 20 VINH(IN), INL(EN), nDRVOFF, VDSLVL -0.3 20 DT/MODE, IDRIVE1, IDRIVE2, CSAGAIN -0.3 6 High-side gate drive pin voltage GH, TJ = 25℃ GVDD >= 11V -5 115 V High-side gate drive pin voltage GH with respect to SH -0.3 20 V High-side source pin voltage SH, DC -5 105 V Transient high-side source pin negative voltage SH, 1 µs -20 V High-side source pin slew rate SH , VBST-SH >3.5V 20 V/ns Low-side gate drive pin voltage GL with respect to SL -0.3 20 V Low-side source sense pin voltage SL -5 VGVDD+0.3 V Transient low-side source sense pin negative voltage SL, 1 µs -16 V Current sense amplifier reference input pin voltage CSAREF -0.3 5.5 V Shunt amplifier input pin voltage SN, SP -1 1 V Transient 500-ns shunt amplifier input pin voltage SN, SP, 500ns -16 20 V Shunt amplifier output pin voltage SO -0.3 VCSAREF + 0.3 V Junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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6.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted) MIN NOM MAX UNIT VGVDD Power supply voltage GVDD, GVDD_LS 8 V Power supply voltage (DRV8162L only) GVDD, GVDD_LS, DRV8162L device variant 5 V VGVDD-SL Power supply voltage with respect to SL GVDD(DRV8161), GVDD_LS (DRV8162x) for low-side Pre-Driver PWM operation 3.5 V VVDRAIN High-side drain pin voltage VDRAIN, low-side gate drive, and high- side gate drive switching with bootstrap 0 90 V VBST-SH Bootstrap pin voltage with respect to SH BST (VBST - VSH), high-side gate drive switching and no BST_UV detection, VBST-SH min > VBST_UV max (rising), 6.1 V Bootstrap pin voltage with respect to SH (DRV8162Lonly) BST (VBST - VSH), DRV8162L device variant only, high-side gate drive switching and no BST_UV detection, VBST-SH min > VBST_UV max (rising) 4.6 V VBST Bootstrap pin voltage BST 0 105 V VSH High-side source pin voltage SH -2 95 V VI Digital / Pin detection input voltage INH, INL, IDRIVE1, IDRIVE2, GAIN, VDSLVL 0 5.5 V VOD Open drain pullup voltage nFAULT 5.5 V IOD Open drain output current nFAULT –5 mA VCSAREF Current sense amplifier reference voltage CSAREF 3.0 5.5 V TA Operating ambient temperature –40 125 °C TJ Operating junction temperature –40 150 °C

6.4 Thermal Information 1pkg

THERMAL METRIC(1) DRV8161/DRV8162 UNITDGS(VSSOP)

20 PINS

RθJA Junction-to-ambient thermal resistance TBD °C/W RθJC(top) Junction-to-case (top) thermal resistance TBD °C/W RθJB Junction-to-board thermal resistance TBD °C/W ΨJT Junction-to-top characterization parameter TBD °C/W ΨJB Junction-to-board characterization parameter TBD °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance TBD °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

6.5 Electrical Characteristics

VGVDD = 12 V, VVDRAIN = 48 V, CSAREF = 5V, TJ = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES (GVDD, BST) IVDRAIN_UNP WR VDRAIN leakage current under GVDD unpowered GVDD = 0V, VDRAIN = 48V, VBST-SH = 0V 3.5 5 µA IGVDD GVDD active mode current INH = INL = Switching @ 20kHz; VBST = VGVDD; No FETs connected, DT/MODE Pin open. VDS_LVL = 2V 2 mA tWAKE Turnon time GVDD = 0V to 12V VGVDD = VGVDD_UV to active mode (outputs ready : nFAULT = High) 0.4 ms ILBS_TCPON Bootstrap pin leakage current during high-side pull-up INH = high; TCP_ON 30 µA LOGIC-LEVEL INPUTS (INH, INL, nDRVOFF) VIL Input logic low voltage INL, INH, nDRVOFF 0.8 V VIH Input logic high voltage INL, INH, nDRVOFF 2.2 V RPU Input pullup resistance nDRVOFF to internal regulator, no external connection 250 kΩ RPD Input pulldown resistance INH, INL to GND 250 kΩ tnDRVOFF_DE G nDRVOFF input deglitch time nDRVOFF falling and rising 2.1 µs tnDRVOFF_DIA G nDRVOFF diagnostic pulse valid input time DRV8162 and DRV8162L only 0.5 µs OPEN-DRAIN OUTPUT (nFAULT) VOL Output logic low voltage IOD = 5 mA, GVDD > 4V 0.4 V BOOTSTRAP DIODE (BST) VBOOTD Bootstrap diode forward voltage IBOOT = 10 mA 0.8 V IBOOT = 100 mA 1.3 RBOOTD Bootstrap dynamic resistance (ΔVBOOTD/ΔIBOOT) IBOOT = 100 mA and 50 mA 4.8 Ω CHARGE PUMP (BST) VTCP Trickle charge pump output voltage VBST-SH , INH = High, VSH = VVDRAIN = 20V, VBST > VGVDD, External load ITRICKLE = 2uA, TJ = 25℃ 8.5 V VBST-SH , INH = High, VSH = VVDRAIN = 20V, VBST > VGVDD, External load ITRICKLE = 2uA, TJ = 150℃ 4.9 GATE DRIVERS (GH, GL, SH, SL) DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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VGVDD = 12 V, VVDRAIN = 48 V, CSAREF = 5V, TJ = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDRIVEP0 Peak source gate current VBST-VSH = VGVDD = 12V 16 mA IDRIVEP1 VBST-VSH = VGVDD = 12V 32 IDRIVEP2 VBST-VSH = VGVDD = 12V 64 IDRIVEP3 VBST-VSH = VGVDD = 12V 96 IDRIVEP4 VBST-VSH = VGVDD = 12V 128 IDRIVEP5 VBST-VSH = VGVDD = 12V 160 IDRIVEP6 VBST-VSH = VGVDD = 12V 192 IDRIVEP7 VBST-VSH = VGVDD = 12V 224 IDRIVEP8 VBST-VSH = VGVDD = 12V 256 IDRIVEP9 VBST-VSH = VGVDD = 12V 288 IDRIVEP10 VBST-VSH = VGVDD = 12V 320 IDRIVEP11 VBST-VSH = VGVDD = 12V 384 IDRIVEP12 VBST-VSH = VGVDD = 12V 448 IDRIVEP13 VBST-VSH = VGVDD = 12V 512 IDRIVEP14 VBST-VSH = VGVDD = 12V 768 IDRIVEP15 VBST-VSH = VGVDD = 12V 1024 IDRIVEN0 Peak sink gate current VBST-VSH = VGVDD = 12V 32 mA IDRIVEN1 VBST-VSH = VGVDD = 12V 64 IDRIVEN2 VBST-VSH = VGVDD = 12V 128 IDRIVEN3 VBST-VSH = VGVDD = 12V 192 IDRIVEN4 VBST-VSH = VGVDD = 12V 256 IDRIVEN5 VBST-VSH = VGVDD = 12V 320 IDRIVEN6 VBST-VSH = VGVDD = 12V 384 IDRIVEN7 VBST-VSH = VGVDD = 12V 448 IDRIVEN8 VBST-VSH = VGVDD = 12V 512 IDRIVEN9 VBST-VSH = VGVDD = 12V 576 IDRIVEN10 VBST-VSH = VGVDD = 12V 640 IDRIVEN11 VBST-VSH = VGVDD = 12V 768 IDRIVEN12 VBST-VSH = VGVDD = 12V 896 IDRIVEN13 VBST-VSH = VGVDD = 12V 1024 IDRIVEN14 VBST-VSH = VGVDD = 12V 1536 IDRIVEN15 VBST-VSH = VGVDD = 12V 2048 RPD_LS Low-side passive pull down GL to SL, VGL - VSL = 2V 85 kΩ RPDSA_HS High-side semi active pull down VGVDD < VGVDD_UV GH to SH, VGH - VSH = 2V 4 kΩ IPUHOLD_HS High-side pull-up hold current 512 mA IPDHOLD_HS High-side pull-down hold current 2048 mA IPDSTRONG_L S Low-side pull-down strong current 2048 mA IPDSTRONG_H S High-side pull-down strong current 2048 mA IDRVIVENSD_L S Low-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN13 (1024mA Typ) or smaller settings 32 mA IDRVIVENSD_L S Low-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN14 (1536mA Typ) or IDRIVEN15 (2048mA Typ) 64 mA IDRIVENSD_H S High-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN13 (1024mA Typ) or smaller settings 32 mA www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

VGVDD = 12 V, VVDRAIN = 48 V, CSAREF = 5V, TJ = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IDRIVENSD_H S High-side peak sink gate shutdown current IDRIVENx is set to IDRIVEN14 (1536mA Typ) or IDRIVEN15 (2048mA Typ) 64 mA GATE DRIVERS TIMINGS tPDR_LS Low-side rising propagation delay INL to GL rising, no load on GL 50 ns tPDF_LS Low-side falling propagation delay INL to GL falling, no load on GL 50 ns tPDR_HS High-side rising propagation delay INH to GH rising, no load on GH 50 ns tPDF_HS High-side falling propagation delay INH to GH falling, no load on GH 50 ns tPD_MATCH Matching propagation delay of low-side gate driver GL turning ON to GL turning OFF, From VGL-SL = 1V to VGL-SL = VGVDD - 1V;, no load on GL ±4 ns tPD_MATCH Matching propagation delay of high-side gate driver GH turning ON to GH turning OFF, From VGH-SH = 1V to VGH-SH = VBST-SH - 1V; no load on GH ±4 ns tPD_MATCH_P H Matching propagation delay per phase from GL off to GH on Deadtime disabled. GL turning OFF to GH turning ON, From VGL-SL = VGVDD - 1V to VGH-SH = 1V ±4 ns tPD_MATCH_P H Matching propagation delay per phase from GH off to GL on Deadtime disabled. GH turning OFF to GL turning ON, From VGH-SH = VBST-SH - 1V to VGL-SL = 1V ±4 ns tDEAD Gate drive dead time RDT = 470 Ω 2-pin PWM mode; IDRIVEN15 nsRDT = 1.3 KΩ 2-pin PWM mode; IDRIVEN15 100 RDT = 3.3 KΩ 2-pin PWM mode; IDRIVEN15 370 tMINDEAD_VG S Minimum gate drive dead time (shortest available) of VGS monitor mode VGS monitor dead time insertion; tDEAD_CFG < 130ns; HS falling to LS rising, LS falling to HS rising 280 ns CURRENT SHUNT AMPLIFIERS (SN, SO, SP, CSAREF) ACSA Sense amplifier gain CSAGAIN = Tied to GND (LEVEL0) 5 V/V CSAGAIN = 10kΩ typ tied to GND (LEVEL1) 10 V/V CSAGAIN = 30kΩ typ tied to GND (LEVEL2) 20 V/V CSAGAIN = open; (LEVEL3) 40 V/V tSET Settling time to ±1% VSTEP = 1.6 V, ACSA = 5 V/V, CSO = 500pF 0.6 µs VSTEP = 1.6 V, ACSA = 40 V/V, CSO = 500pF 0.8 µs BW Bandwidth ACSA = 5 V/V, CLOAD = 60-pF, small signal -3 dB 5 MHz VSWING Output voltage range VCSAREF = 3 to 5.5 V 0.25 VCSAREF - 0.25 V VCOM Common-mode input range -0.225 0.225 V VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, Gain ACSA = 10, 20, 40 V/V -1.3 1.3 mV VOFF Input offset voltage VSP = VSN = GND; TJ = 25℃, Gain ACSA = 5 V/V -2.6 2.6 mV VOFF_DRIFT Input drift offset voltage VSP = VSN = GND, ; –40℃ ≤ TJ ≤ 150℃ 8 µV/℃ IBIAS Input bias current VSP = VSN = GND, VCSAREF = 3V to 5.5V 100 µA IBIAS_OFF Input bias current offset ISP – ISN -1 1 µA DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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VGVDD = 12 V, VVDRAIN = 48 V, CSAREF = 5V, TJ = 25℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CMRR Common-mode rejection ratio DC 80 dB 20 kHz 60 dB ICSA_SUP Supply current for CSA CSAREF, VCSAREF = 3.V to 5.5V 1.5 mA TCMREC Common mode recovery time 2 us PROTECTION CIRCUITS VGVDD_UV GVDD undervoltage threshold VGVDD rising 7.4 V VGVDD falling 6.7 V VGVDD_UV GVDD undervoltage threshold VGVDD rising, DRV8162L 4.8 V VGVDD falling, DRV8162L 4.7 VBST_UV Bootstrap undervoltage threshold VBST - VSH; VBST rising, GVDD = 12V 7.43 V VBST - VSH; VBST falling, GVDD = 12V 7.25 VBST - VSH; VBST rising, GVDD = 5V, DRV8162L 4.08 VBST - VSH; VBST falling, GVDD = 5V, DRV8162L 3.94 VDS_LVL0-0 VDS overcurrent protection threshold level (DC) RVDSLVL = 0.1 KΩ max (LEVEL0) 0.1 V VDS_LVL1-1 RVDSLVL = 2 KΩ typ (LEVEL1); one pulse detected on VDSLVL pin 0.15 VDS_LVL1-0 RVDSLVL = 2 KΩ typ (LEVEL1); DC 0.2 VDS_LVL2-1 RVDSLVL = 5.6 KΩ typ (LEVEL2); one pulse detected on VDSLVL pin 0.3 VDS_LVL2-0 RVDSLVL = 5.6 KΩ typ (LEVEL2) 0.4 VDS_LVL3-1 RVDSLVL = 12 KΩ typ (LEVEL3); one pulse detected on VDSLVL pin 0.5 VDS_LVL3-0 RVDSLVL = 12 KΩ typ (LEVEL3) 0.6 VDS_LVL4-1 RVDSLVL = 26 KΩ typ (LEVEL4); one pulse detected on VDSLVL pin 0.7 VDS_LVL4-0 RVDSLVL = 26 KΩ typ (LEVEL4) 0.8 VDS_LVL5-1 RVDSLVL = 62 KΩ typ (LEVEL5); one pulse detected on VDSLVL pin 0.9 VDS_LVL5-0 RVDSLVL = 62 KΩ typ (LEVEL5) 1.0 VDS_LVL6-1 RVDSLVL = 130 KΩ typ (LEVEL6) ; one pulse detected on VDSLVL pin VDSLVL 1.5 VDS_LVL6-0 RVDSLVL = 130 KΩ typ (LEVEL6); 2.0 tDS_DG VDS protection deglitch time 3 µs tDS_BLK VDS overcurrent protection blanking time 1 µs tVDSLVLFIL VDSLVL pin digital input - one pulse filter time for LEVELx-1 4 µs VIHVDSLVL VDSLVL pin digital input - one pulse high-level detection voltage for LEVELx-1 1 V TOTSD Thermal shutdown temperature 170 °C www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

6.6 Timing Diagrams

VGL – SL 50% 50% VGVDD – 1V tPDR_LS tPDR_HS tPDF_LS tPDF_HS VGH - SH VBST-SH – 1V Figure 6-1. Gate Driver Propagation Delay Timing Diagram INL VGH - SH 50% 50% VGVDD – 1V tPDF_HS tPDF_LS 50% 50%INH VGL – SL tDEAD VBST-SH – 1V tDEAD Figure 6-2. Gate Driver Dead Timing Insertion (INH and INL monitor mode) INL VGH - SH INH VGL – SL tDEAD_VGS VGS_TH (typ 1V) VGS_TH (typ 1V) tDEAD_VGS Figure 6-3. Gate Driver Dead Timing Insertion (VGS monitor mode) DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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7 Detailed Description

7.1 Overview

The DRV816x devices are integrated 100-V gate drivers for various electromechanical loads including brushless DC (BLDC) motors, brushed DC motors, stepper motors, switched reluctance motors, and solenoids. These devices reduce system component count, cost, and complexity by integrating half-bridge gate drivers with a trickle charge pump, bootstrap diode, and FET VDS monitoring. The FET VDS monitors protect the external FETs against shorts to the supply, to ground, or across motor terminals. The DRV8161 integrates a bidirectional low-side current sense amplifier for current feedback to the controller ADC. The half-bridge architecture allows for the gate driver to be placed near the power stage FETs to simplify signal routing, reduce radiated EMI, and reduce overall PCB area. The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A source, 2-A sink peak currents. The integrated bootstrap diode, external bootstrap capacitor, and integrated trickle charge pump generate the high-side gate drive supply voltage from the GVDD pin. The GVDD pin directly supplies the low-side gate drive supply voltage. The DRV8162 and DRV8162L device variants offer separate GVDD and GVDD_LS pins to help the system design of safe torque off (STO). A smart gate-drive architecture provides the ability to adjust the output gate-drive current strength allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for the removal of external gate drive resistors and diodes reducing BOM component count, cost, and PCB area. The architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the half-bridge dead time, and protect against dV/dt parasitic turn on of the external power MOSFET. In addition to the high level of device integration, the DRV816x devices provide a wide range of integrated protection features. These features include power-supply under voltage lockout (UVLO), VDS over current monitoring (OCP), and over temperature shutdown (OTSD). The nFAULT pin indicates fault events detected by the protection features. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

7.2 Functional Block Diagram

• VDSLVL VDRAIN – SH LS VDS OCP - VDSLVL SH – SL To Load Output nFAULT/nDRVOFF VIO nDRVOFF IDRIVE1 IDRIVE2 CBST RnFAULT CCSAREF Fault logic OTSD VM VDRAIN CVDRAIN Figure 7-1. Block Diagram for DRV8161 DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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GVDD_LS HS LS GND Trickle CP OutputnFAULT VIO HS VDS OCP - VDSLVL VDRAIN – SH LS VDS OCP - VDSLVL DL – SL INH/IN INL/EN Control Inputs DT/MODE IDRIVE1 IDRIVE2 nDRVOFF GVDD_LS CGVDD_LS GVDD CGVDD CBST RnFAULT Fault logic OTSD VM VDRAIN CVDRAIN Switch Switch GVDD_LS To Load Figure 7-2. Block Diagram for DRV8162 and DRV8162L www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

7.3 Feature Description

7.3.1 Gate Drivers

The DRV816x family of devices integrates high-side and low-side FET gate drivers capable of driving N-channel power MOSFETs in half-bridge configuration. A bootstrap gate drive architecture generates the high-side gate driver voltage during PWM switching. The GVDD pin supplies both high-side and low-side gate drivers and sets the VGS voltage for the FETs. The DRV816x devices support half-bridge power stage architecture. In addition to the regular 2-pin PWM control interface, the device offers an independent PWM mode by disabling shoot through protection and allowing the high-side and low-side FETs to be controlled independently. Independent FET control is useful for driving solenoids and switched reluctance motors. The DRV8162 and DRV8162L have separate supply pins (GVDD and GVDD_LS) for high-side and low-side FET gate drive. This allows the system to support safe torque off (STO) function by adding external power switches to the gate drive supply pins.

7.3.1.1 PWM Control Modes

The DRV816x family of devices provides three different PWM control modes to support various commutation and control methods. The PWM control modes are 1-pin PWM, 2-pin PWM and independent PWM mode. The modes are configured by DT/MODE pin. DT/MODE pin is latched at power up, so in order to change the PWM control mode the device needs to be reset through power supply. Refer to Table 7-6 for the configuration of PWM control mode using the DT/MODE pin. 7.3.1.1.1 2-pin PWM Mode In 2-pin PWM mode, half-bridge driver supports three output states: low, high, or high-impedance (Hi-Z). The corresponding INH and INL signals control the output state as listed in Table 7-1. Table 7-1. 2-pin PWM Mode Truth Table INL INH GL GH SH 0 0 L L Hi-Z 0 1 L H H 1 0 H L L 1 1 L L Hi-Z DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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7.3.1.1.2 1-pin PWM Mode (preview only) WARNING The DRV8161 prototype samples do not support 1-pin PWM Mode. This function is preview only. Please contact TI for more detailed information. In 1-pin PWM mode, the IN pin controls half-bridge and supports two output states: low or high. The EN pin is used to put the half bridge in the Hi-Z state. If the Hi-Z state is not required, tie INL/EN pin to logic high. The corresponding INH/IN and INL/EN signals control the output state as listed in Table 7-2. Table 7-2. 1-pin PWM Mode Truth Table (preview only) INL/EN INH/IN GL GH SH

0 X L L Hi-Z

7.3.1.1.3 Independent PWM Mode

DRV816x supports independent PWM mode, the INH and INL pins control the outputs, GH and GL, respectively. This control mode lets the device drive separate high-side and low-side load. The independent PWM drive mode can be used for various type of loads including solenoids, Switched Reluctance Motor (SRM), unidirectional brushed DC motors, and low-side and high-side switches. In this mode, turning on both the high-side and low-side MOSFETs at the same time in a given half bridge gate driver is possible to use the device as a high-side or low-side driver. The shoot-through protection and dead time are bypassed in the mode. Table 7-3. Independent PWM Mode Truth Table INL INH GL GH 0 0 L L 0 1 L H 1 0 H L 1 1 H H Figure 7-3 shows how the device can be used to connect an inductive load where both the high-side and low-side MOSFETs can be turned on at the same time to drive the load without causing shoot-through. The external diodes for current recirculation are recommended. This configuration helps the design of solenoids or applications. The trickle charge pump is enabled all the time regardless of low-side PWM activity. Note The low-side VDS monitor of DRV816x is not available if independent PWM mode is configured. For DRV8161, the CSA output can be monitored by MCU to detect the over current condition. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

GVDD_LS VDRAIN DRV8162 VDS monitor INH INL Load power supply GVDD TCP Load Figure 7-3. Independent PWM mode for single load between high-side and low-side Figure 7-4shows how the device can be used to connect a high-side load and a low-side load at the same time with one half-bridge and drive the loads independently. DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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GVDD_LS VDRAIN DRV8162 VDS monitor INH INL Load power supply GVDD GND Load power supply TCP Load Load Figure 7-4. Independent PWM mode for high-side and low-side independent loads

7.3.1.2 Gate Drive Architecture

The gate driver device use a complimentary, push-pull topology for both the high-side and low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates. The low side gate driver is supplied directly from the GVDD regulator supply. For the high-side gate driver a bootstrap diode and capacitor are used to generate the floating high-side gate voltage supply. The bootstrap diode is integrated and an external bootstrap capacitor is used on the BST pin. The high-side gate driver has semi-active pull down and low side gate has passive pull down to help prevent the external MOSFET from turning ON when power supply is disconnected. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

RPD_LS RPDSA_HS Semi-active pull-down DBST GVDD GL GVDD CGVDD VM VDRAIN RSENSE SP SN GND Figure 7-5. DRV8161 Gate Driver Block Diagram DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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RPD_LS RPDSA_HS Semi-active pull-down DBST GL GVDD CGVDD GND VM GVDD_LS CGVDD_LS GND VDRAIN VGVDD_LS VGVDD_LS Figure 7-6. DRV8162 and DRV8162L Gate Driver Block Diagram

7.3.1.2.1 Tickle Charge Pump (TCP)

An internal trickle charge pump (TCP) is connected to BST node to reduce voltage drop due to the leakage currents of the driver and external components. The charge pump generates V TCP voltage with respect to VDRAIN pin. For the independent PWM mode, the charge pump is active all the time. For the 2-pin PWM and 1-pin PWM mode, if the INL stays low for 250us (typ), the charge pump is activated. WARNING Depending on the system use case or the device condition, the output capability of TCP charge pump is not always sufficient to maintain the voltage on C BST during 100% duty cycle. In particular at high temperature, the charge pump output voltage V TCP can be lower than the bootstrap undervoltage threshold V BST_UV, and hence the high-side gate driver output becomes shutdown. To avoid the shutdown, the length of 100% duty cycle time must be limited, or CBST must be charged by system periodically to maintain the voltage.

7.3.1.2.2 Deadtime and Cross-Conduction Prevention (Shoot through protection)

In the DRV816x, if the device is configured to 2-pin PWM mode, high- and low-side inputs operate independently, with an exception to prevent cross conduction when the high and low side of the same half-bridge are turned ON at same time. The device turns OFF high- and low- side output to prevent shoot through when high- and low-side inputs are logic high at same time. The DRV816x also provide dead time insertion to prevent both external MOSFETs of each half-bridge from switching on at the same time. The deadtime can be enabled and adjusted between 20 ns and 400 ns by www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

Figure 7-7. Cross Conduction Prevention and Dead time Insertion (2-pin PWM, dead time insertion enabled) DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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7.3.2 Pin Diagrams

7.3.2.1 Four Level Input Pin (CSAGAIN)

Figure 7-8 shows the structure of the four level input pin, CSAGAIN, for hardware interface configuration. The input can be set with an external resistor. The C CSAGAIN is optional to help reduce the impact of GND noise. The CSA GAIN information is not latched at the device power up and may be updated during the device operation.

40 V/V

20 V/V

10 V/V

5 V/V

Figure 7-8. Four Level Input Pin Structure

7.3.2.2 Digital output nFAULT (DRV8162, DRV8162L)

Figure 7-9 shows the structure of the open-drain output pins, nFAULT. The open-drain output requires an external pullup resistor to function correctly. Refer to Table 7-7 for the device actions including nFAULT. RnFAULT VCCIO nFAULT MCU GPIO input DRV8160S Pull-up Low nFAULT No Fault Fault Status VCCIO 1 : No fault 0 : Fault Fault reporting Open Drain inactive : No Fault Open Drain active : Fault Figure 7-9. nFAULT Open Drain Output buffer

7.3.2.3 Digital InOut nFAULT/nDRVOFF (DRV8161)

Figure 7-10 shows the structure of the open-drain output and input pin. In the DRV8161 device variant, two functions nFAULT and nDRVOFF are achieved by sharing one device pin, nFAULT/nDRVOFF. The open-drain output requires an external pullup resistor to function correctly. If a fault condition is detected, the device activates Open Drain buffer, and nFAULT/nDRVOFF pin is driven low. The nFAULT/nDRVOFF pins is internally connected to Gate Drive Shutdown logic, and the gate drive outputs are shutdown (pull-down) if the nFAULT/ nDRVOFF pin low. Refer to Table 7-7 for the device actions including nFAULT. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

1: Gate Drive active 0: Shutdown Open Drain inactive : No Fault Open Drain active : Fault Output HiZ : No action Output Low : Gate Drive shutdown1 : No fault 0 : Fault Figure 7-10. nFAULT/nDRVOFF Open Drain Output and Input buffer

7.3.2.4 Multi-level inputs (IDRIVE1 and IDRIVE2)

The DRV816x have IDRIVE1 and IDRIVE2 device pins for gate drive current configuration. Each pin can set 8 levels, LEVEL0 to LEVEL7, with an external resistor connected between the device pin and GND. The gate drive current IDRIVEN and I DRIVEP can be determined by Table 7-4. The (G) in the table indicates that VGS monitor dead time insertion is enabled. The IDRIVE1 and IDRIVE2 information are latched at the device power up. DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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Figure 7-11. Multi-level digital inputs of IDRIVE1 and IDRIVE2 www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

Table 7-4. IDRIVE1/IDRIVE2 Truth Table for Gate Drive Current configuration IDRIVE2 LEVEL0 LEVEL1 LEVEL2 LEVEL3 LEVEL4 LEVEL5 LEVEL6 LEVEL7 Source:Sink = 1:2 Source:Sink = 1:2 Source:Sink = 1:1.5 Source:Sink = 1:1.5 Source:Sink = 1:1 Source:Sink = 1:3 VGS dead time insertion enabled IDRIVE2 open IDRIVE P[mA] IDRIVE N[mA] IDRIVE P[mA] IDRIVE N[mA] IDRIVE P[mA] IDRIVE N[mA] IDRIVE P[mA] IDRIVE N[mA] IDRIVE P[mA] IDRIVE N[mA] IDRIVE P[mA] IDRIVE N[mA] IDRIVE P[mA] IDRIVE N[mA] IDRIVE P[mA] IDRIVE N[mA] IDRIVE1 LEVE 256 512 16 32 256 384 16 32 128 128 64 192 32 (G) 64 (G) 16 (G) 32 (G) LEVE 288 576 32 64 288 448 32 32 192 192 128 384 96 (G) 192 (G) 64 (G) 128 (G) LEVE 320 640 64 128 320 448 64 64 256 256 192 576 128 (G) 256 (G) 128 256 LEVE 384 768 96 192 384 576 96 128 320 320 256 768 160 (G) 320 (G) 192 384 LEVE 448 896 128 256 448 640 128 192 384 384 288 896 192 (G) 384 (G) 256 512 LEVE 512 1024 160 320 512 768 160 256 448 448 384 1024 224 (G) 448 (G) 320 640 LEVE 768 1536 192 384 768 1024 192 256 512 512 512 1536 512 (G) 1024 (G) 512 1024 LEVE 1024 2048 224 448 1024 1536 224 384 1024 1024 768 2048 1024 (G) 2048 (G) 1024 2048

7.3.2.5 Multi-level digital input (VDSLVL)

The VDS monitor threshold level of DRV816x is configurable using VDSLVL pin. The pin can set 8 levels, LEVEL0 to LEVEL7, with an external resistor connected between VDSLVL and GND. The 7 threshold levels are determined by Table 7-5. As shown in Figure 7-13, if one digital pulse is applied to VDSLVL pin, additional 6 threshold levels are available. If VDSLVL pin is open, VDS monitor function is disabled. The VDS monitor threshold infomration is latched at the device power up. RVDSLVL GND CVDSLVL VDSLVL Filter Rising edge detect VIHVDSLVLPLS tVDSLVLPLS > tVDSLVLFIL max nFAULT VDSLVL LEVELx-0 (no pulse detected) LEVELx-1 (one pulse detected) x = 0,…,7 VDSLVLMCU Optional if LEVELx-1 is used. tVDSLVLFIL Figure 7-12. VDSLVL input pulse timing diagram DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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(device pin) VIHVDSLVL tVDLLVLFIL VDSLVL (LEVELx-0) latch VDSLVL (threshold level) tVDLLVLFIL VDSLVL (LEVELx-1)Not defined tVDLLVLPLS_WAIT Figure 7-13. Multilevel digital input of VDSLVL Table 7-5. VDS threshold level selection table VDSLVL input pin (RVDSLVL) VDS monitor threshold LEVELx-0 (no pulse detected) LEVELx-1 (one pulse detected) LEVEL7 (OPEN) Disabled Disabled LEVEL6 (130KΩ typ) 2-V 1.5-V LEVEL5 (62KΩ typ) 1-V 0.9-V LEVEL4 (27KΩ typ) 0.8-V 0.7-V LEVEL3 (12KΩ typ) 0.6-V 0.5-V LEVEL2 (5.6KΩ typ) 0.4-V 0.3-V LEVEL1 (2KΩ typ) 0.2-V 0.15-V LEVEL0 (Short to GND) 0.1-V Not available

7.3.2.6 Multi-level digital input DT/MODE

Figure 7-14 shows the structure of mutlelevel input pin DT/MODE for hardware interface configuration. The input can be set with an external resistor R DTMODE connected to GND. The C DTMODE is optional to help reduce the impact of GND noise. The shoot through function, dead time insertion, and PWM control mode are configured as shown in Table 7-6. The information of LEVEL0, 1, 2, 3, and LEVEL5 are latched at the device power up. RDTMODE GND CDTMODE DT/MODE DT/MODE Table tDEAD 1-pin/2-pin PWM Independent FET mode selection Figure 7-14. DT/MODE Pin Structure Table 7-6. DT/MODE Table DT/MODE (RDTMODE) Shoot Through protection Dead Time Insertion (tDEAD) PWM Control mode LEVEL5 (pin floating) enabled disabled 2-pin PWM LEVEL4 - Linear (10 KΩ - 1 MΩ) Reserved. LEVEL3 (3.3 KΩ) enabled enabled (370-ns) 2-pin PWM www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

Table 7-6. DT/MODE Table (continued) DT/MODE (RDTMODE) Shoot Through protection Dead Time Insertion (tDEAD) PWM Control mode LEVEL2 (1.3 KΩ) enabled enabled (100-ns) 2-pin PWM LEVEL1 (470 Ω) enabled enabled (20-ns) 2-pin PWM LEVEL0 (short to GND) disabled disabled Independent PWM

7.3.3 Low-Side Current Sense Amplifiers

The DRV8161 integrates high-performance low-side current sense amplifier for current measurements using low-side shunt resistor. Low-side current measurements are commonly used to implement overcurrent protection, external torque control, or brushless DC commutation with the external controller. Current sense amplifier can be used to sense the sum of the half-bridge current. The current sense amplifier includes features such as configurable gain, and a voltage reference pin (CSAREF). DRV8161 generates internally a common voltage of VCSAREF/2. The gain setting is adjustable between four different levels (5 V/V, 10 V/V, 20 V/V, and 40 V/V). Gain settings can be configured through CSAGAIN pin. DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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7.3.3.1 Bidirectional Current Sense Operation

DRV8161 internally generates common mode voltage to enable bidirectional for current measurement. The current sense amplifier operates as bidirectional mode and the SO pin outputs an analog voltage equal to the voltage across the SP and SN pins multiplied by the gain setting (GCSA) plus the output bias voltage VVREF / 2 . Use Equation 1 to calculate the current through the shunt resistor (CSAREF / 2 case) . I GCSA RSENSE VVREFVSOx (1) SO (V) SP – SN (V) VVREF VVREF / 2 VLINEAR Figure 7-15. Bidirectional Current Sense Output

0 VVVREF / 2

VSO(off)max VSO(off)min VVREF VVREF – V 0.25 V 0 V I × R -I × R SO SP – SN SO VOFF, VDRIFT VSO(range+) VSO(range-) SP SN R I AV Figure 7-16. Bidirectional Current Sense Regions www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

7.3.4 Gate Driver Shutdown Sequence (nDRVOFF)

When nDRVOFF is driven low, the gate driver goes into shutdown, overriding signals on inputs pins INH/IN and INL/EN. nDRVOFF bypasses the digital control logic inside the device, and is connected directly to the gate driver output. This pin provides a mechanism for externally monitored faults to disable gate driver by directly bypassing an external controller or the internal control logic. When DRV816x detect the nDRVOFF pin is driven low, the device disables the gate driver and puts it into pulldown mode. The gate driver shutdown sequence proceeds as shown in Figure 7-17 . When the gate driver initiates the shutdown sequence, the active driver pulldown is applied at IDRVN_SD current for the tDRVN_SD time. INH / INL GH / GL IDRVN_SD IDRVPIPDSTRONG GH / GL active pullup/down IPDHOLD nDRVOFF (low active) or VDS fault (internal status) tDRVN_SD nDRVOFF = High No VDS Fault nDRVOFF = Low or VDS Fault is detected Figure 7-17. Gate Driver Shutdown Sequence 7.3.4.1 nDRVOFF Diagnostic Figure 7-18 proposes a diagnostic of nDRVOFF of DRV8162 and DRV8162L. If a low active pulse t nDRVOFF_DIAG (typ 0.5us) is applied to nDRVOFF pin, the device responds by driving nFAULT low without shutdown of the gate driver outputs. This device function is intended for a diagnostic of nDRVOFF function while continuing PWM operation. If nDRVOFF is driven low longer than tnDRVOFF_DEG, the device initiates the shutdown. nDRVOFF nFAULT tnDRVOFF_DIAG(TYP) GH / GL No Shutdown tnDRVOFF_DEG(TYP) or longer tPDR + tnDRVOFF_DEG(TYP) tnDRVOFF_DIAG(TYP) tnDRVOFF_DIAG(TYP) Diagnostic of nDRVOFF Gate Driver Shutdown Figure 7-18. nDRVOFF Diagnostic DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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7.3.5 Gate Driver Protective Circuits

The DRV816x are protected against GVDD undervoltage and overvoltage, bootstrap undervoltage, MOSFET VDS and Overtemperature (OTSD) events. Table 7-7. Fault Action and Response FAULT CONDITION CONFIGURATION REPORT GATE DRIVER GH GATE DRIVER GL RECOVERY GVDD undervoltage (GVDD_UV) VGVDD < VGVDD_UV - nFAULT S-PD(1) P-PD(2) VGVDD > VGVDD_UV VDS overcurrent (VDS_OCP) VDS > VDSLVL VDSLVL pin with R (LEVEL0 - LEVEL6) nFAULT S-PD (1) P-PD(2) Latched: INH(IN) = Low & INL(EN) = Low for > tCLKFLT VDSLVL pin open (LEVEL7) None Active(3) Active(3) No action Thermal shutdown (OTSD) TJ > TOTSD - nFAULT S-PD (1) P-PD(2) TJ < TOTSD Bootstrap undervoltage VBST-SH < VBST_UV - None S-PD(1) Active(3) VBST-SH > VBST_UV (1) S-PD : Semi-active Pull Down (2) P-PD : Passive Pull Down (3) Active : Gate Drivers are active for PWM

7.3.5.1 GVDD Undervoltage Lockout (GVDD_UV)

If at any time the voltage on the GVDD pin falls lower than the V GVDD_UV threshold voltage for longer than the tGVDD_UV_DG deglitch time, the device detects a GVDD undervoltage event. After detecting the GVDD_UV undervoltage event, all of the gate driver outputs are driven low to disable the external MOSFETs, the charge pump is disabled, and the nFAULT pin pulls low. After the GVDD_UV condition is cleared, the nFAULT goes high.

7.3.5.2 MOSFET VDS Overcurrent Protection (VDS_OCP)

The DRV816x devices have adjustable V DS voltage monitors to detect overcurrent or short-circuit conditions on the external power MOSFETs. A MOSFET overcurrent event is sensed by monitoring the V DS voltage drop across the external MOSFET R DS(on). The high-side VDS monitors measure between the VDRAIN and SH pins. The low-side VDS monitors measure between the SH and SL pins. If the voltage across external MOSFET exceeds the V VDSLVL threshold for longer than the t DS_DG deglitch time, a VDS_OCP event is recognized. After detecting the VDS overcurrent event, all of the gate driver outputs are driven low to disable the external MOSFETs and nFAULT pin is driven low. The VDS threshold can be set between 0.1 V to 2.0 V by VDSLVL pin. The VDS deglitch time is fixed at tVDSDEG. The VDS OCP can be disabled by leaving VDSLVL pin open. After the over current condition is cleared, the fault state remains latched and can be cleared when INH(IN) and INL(EN) stay low for tCLRFLT time. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

+VDS +VDS +VDS +VDS VVDSLVL VVDSLVL– GND SP SN GND RSENSE DRV8161 only DRV816x Figure 7-19. DRV816x MOSFET VDS Overcurrent protection

7.3.5.3 Thermal Shutdown (OTSD)

If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), an OTSD event is recognized. After detecting the OTSD overtemperature event, all of the gate driver outputs are driven low to disable the external MOSFETs, and nFAULT pin is driven low. After OTSD condition is cleared, the device returns to normal operation and nFAULT goes high. DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV816x family of devices is primarily used in applications for three-phase brushless DC motor control. The design procedures in the Section 8.2 section highlight how to use and configure the DRV816x family of devices.

8.2 Typical Application

8.2.1 Typical Application with DRV8161

Figure shows a typical application diagram of DRV8161. RVDSLVL CVDSLVL RnFAULT VCCIO MCU / Digital Controller PWM timer GPIO GPIO (Tristate) Optional CBST CBST CVDRAIN CVM VM Load RIDRIVE2 CIDRIVE2 RDTMODE CDTMODE CSAGAIN SN IDRIVE1 GND GVDD IDRIVE2 DT/MODE VDRAIN INH/IN BST INL/EN SH nFAULT /nDRVOFF GH VDSLVL GL CSAREF SL SO SP RSENSE RSP RSN CSPSN CSN CSP CGVDD RIDRIVE CIDRIVE VGVDD VCSAREF CCSAGAIN RCSAGAIN ADC CSO RSO Figure 8-1. Typical application diagram of DRV8161

8.2.2 Typical Application with DRV8162 and DRV8162L

Figure shows a typical application diagram of DRV8162 and DRV8162L. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

IDRIVE1 GVDD_LS NC GND GVDD IDRIVE2 DTMODE VDRAIN INH/IN BST INL/EN SH NC nDRVOFF GH nFAULT GL VDSLVL SL CGVDD RIDRIVE1 CIDRIVE2 RVDSLVL CVDSLVL RnFAULT VCCIO MCU / Digital Controller PWM timer GPIO VGVDD GPIO Optional CBST CBST CVDRAIN CVM VM Load GVDD_LS RIDRIVE2 CIDRIVE2 GVDD RDTMODE CDTMODE CGVDD_LS GVDD GVDD_LS SWGVDD SWGVDD2 Optional (GVDD and GVDD_LS can be tied together for gate drive operation GVDD and GVDD_LS NC Figure 8-2. Typical application diagram of DRV8162 and DRV8162L

8.2.3 External Components

The table lists the recommended values of the external components for the gate driver. Table 8-1. DRV816x External Components COMPONENTS PIN 1 PIN 2 RECOMMENDED CBST BST SH 1.0-μF, VBST-SH-rated capacitor between BST and SH depending on the total gate charge of external MOSFET Qg. CBST > 20 X Qg / (VGH-VSH). The maximum CBST is 2.2-μF, CGVDD GVDD GND 10-μF, VGVDD-rated capacitor. This capacitor can be shared with the other two DRV816x devices in 3-phase power stage design if the capacitor is placed sufficiently close to all the three devices. The voltage drop due to bootstrap operation at power up and during PWM switching must be reviewed by users. CGVDD_LS GVDD_LS GND 1-μF, VGVDD-rated capacitor CVDRAIN VDRAIN GND 0.1-μF, VVDRAIN-rated capacitor RnFAULT VCCIO nFAULT Pullup resistor 10K-Ω RIDRIVE1 IDRIVE1 GND Hardware interface resistor See Section 7.3.2.4 CIDRIVE1 IDRIVE1 GND OPTIONAL: 0.1-nF, 5-V -rated capacitor RIDRIVE2 IDRIVE2 GND Hardware interface resistor See Section 7.3.2.4 CIDRIVE2 IDRIVE2 GND OPTIONAL: 0.1-nF, 5-V -rated capacitor RVDSLVL VDSLVL GND Hardware interface resistor See Section 7.3.2.5 CVDSLVL VDSLVL GND OPTIONAL: 0.1-nF, 5-V -rated capacitor DVDSLVL VDSLVL MCU OPTIONAL: Diode between VDSLVL pin and MCU GPIO. RDTMODE DT/MODE GND Hardware interface resistor See Section 7.3.2.6 DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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Table 8-1. DRV816x External Components (continued) COMPONENTS PIN 1 PIN 2 RECOMMENDED CDTMODE DT/MODE GND OPTIONAL: 0.1-nF, 5-V -rated capacitor RCSAGAIN CSAGAIN GND Hardware interface resistor See Section 7.3.2.1 CCSAGAIN CSAGAIN GND OPTIONAL: 0.1-nF, 5-V -rated capacitor CCSAREF CSAREF GND 0.1-μF, VCSAREF-rated capacitor RSENSE SP SN Sense shunt resistor RSP, RSN SP/SN RSENSE OPTIONAL: 10-Ω for current sense amplifier input filter. CSPSN SP SN OPTIONAL: 1-nF ceramic capacitor for current sense amplifier input filter. CSP, CSN SP/SN GND OPTIONAL: 1-nF ceramic capacitor for current sense amplifier input filter. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

9 Layout

9.1 Layout Guidelines

• Minimize length and impedance of GH, SH, GL, and SL traces. Use as few vias as possible to minimize parasitic inductance. It is also recommended to increase these trace widths shortly after routing away from the device pin to minimize parasitic resistance.
• Keep bootstrap capacitor CBST close to their respective pins
• Keep GVDD capacitors close to GVDD pin
• Keep VDRAIN capacitor close to VDRAIN pin to supply steady switching current for the charge pump.
• Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk capacitance should be placed such that it minimizes the length of any high current paths through the external MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB layers. These practices minimize inductance and let the bulk capacitor deliver high current.
• Connect SL pin to MOSFET source, not directly to GND, for accurate VDS detection.
• DRV8161 only: Route SN/SP pins in parallel from the sense resistor to the device. Place filtering components close to the device pins to minimize post-filter noise coupling. Ensure that SN/SP stay separated from GND plane to achieve best CSA accuracy.
• The hardware interface resistors RIDRIVE1, RIDRIVE2, RVDSLVL, RDTMODE, and RCSAGAIN should be placed as close as possible to the device pins.
• Minimize parallel routing to reduce noise coupling from potential noise source into any noise-sensitive device signals. The noise-sensitive signals include the multilevel hardware interface pins IDRIVE1, IDRIVE2, VDSLVL, DTMODE and CSAGAIN as well as the current sense amplifier output SO. DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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10 Device and Documentation Support

10.1 Device Support

10.2 Documentation Support

10.2.1 Related Documentation

• Texas Instruments,Understanding Smart Gate Drive (Rev. D) application report
• Texas Instruments, Brushless-DC Motor Driver Considerations and Selection Guide (Rev. A) application report
• Texas Instruments, Best Practices for Board Layout of Motor Drivers (Rev. B) application note
• Texas Instruments, Hardware Design Considerations for an Electric Bicycle Using a BLDC Motor application report
• Texas Instruments,Sensored 3-Phase BLDC Motor Control Using MSP430 application report

10.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.4 Community Resources

10.5 Trademarks

All trademarks are the property of their respective owners. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (May 2024) to Revision A (July 2024) Page

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

www.ti.com PACKAGE OUTLINE C 18X 0.5 2X 4.5 20X 0.275 0.165 5.1

4.7 TYP

0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -15 ) 4X (7 -15 )

1.1 MAX

B 3.1 2.9 A 5.2 5.0 NOTE 3 0.7 0.4 (0.15) TYP VSSOP - 1.1 mm max heightDGS0020A SMALL OUTLINE PACKAGE 4226367/A 10/2020 10 11

0.1 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. No JEDEC registration as of September 2020. 5. Features may differ or may not be present. SEATING PLANE PowerPAD is a trademark of Texas Instruments. TYPICAL A 20 DETAIL A DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

20X (1.45) 20X (0.3) 18X (0.5) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGS0020A SMALL OUTLINE PACKAGE 4226367/A 10/2020 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. LAND PATTERN EXAMPLE SCALE: 16X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL NON-SOLDER MASK SOLDER MASK DETAILS DEFINED (PREFERRED) SOLDER MASK DEFINED www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN (18X 0.5) 20X (1.45) 20X (0.3) (4.4) (R0.05) TYP VSSOP - 1.1 mm max heightDGS0020A SMALL OUTLINE PACKAGE 4226367/A 10/2020 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 16X SYMM SYMM 10 11 DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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12.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant www.ti.com DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: DRV8161 DRV8162 ADVANCE INFORMATION

TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PDRV8161DGSR VSSOP DGS 20 3000 367.0 367.0 35.0 DRV8161, DRV8162 SLVSGZ1A – MAY 2024 – REVISED JULY 2024 www.ti.com

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www.ti.com 17-Jul-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PDRV8161DGSR ACTIVE VSSOP DGS 20 3000 TBD Call TI Call TI -40 to 125 Samples PDRV8162LDGSR ACTIVE VSSOP DGS 20 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 17-Jul-2024 Addendum-Page 2

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