PDRV5056A2EDBZTQ1

DRV5056-Q1 TI1 | Alldatasheet

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ADVANCE□INFORMATION B south OUT 0 mT VCC VL (MAX) 0.6 V OUT DRV5056-Q1 VCC Controller VCC GND ADC Copyright © 2017, Texas Instruments Incorporated Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. DRV5056-Q1 SBAS643 –JANUARY 2018 DRV5056-Q1AutomotiveUnipolarRatiometricLinearHallEffectSensor

1 Features

1• Unipolar Linear Hall Effect Magnetic Sensor

• Operates From 3.3-V and 5-V Power Supplies
• Analog Output With 0.6-V Quiescent Offset: – Maximizes Voltage Swing for High Accuracy
• Magnetic Sensitivity Options (At VCC = 5 V): – A1: 200 mV/mT, ±20-mT Range – A2: 100 mV/mT, ±39-mT Range – A3: 50 mV/mT, ±79-mT Range – A4: 25 mV/mT, ±158-mT Range
• Fast 20-kHz Sensing Bandwidth
• Low-Noise Output With ±1-mA Drive
• Compensation For Magnet Temperature Drift
• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 0: –40°C to 150°C Ambient Operating Temperature Range – Device HBM ESD Classification Level 2 – Device CDM ESD Classification Level C4B
• Standard Industry Packages: – Surface-Mount SOT-23 – Through-Hole TO-92

2 Applications

• Automotive Position Sensing
• Brake, Acceleration, Clutch Pedals
• Torque Sensors, Gear Shifters
• Throttle Position, Height Leveling
• Powertrain and Transmission Components
• Current Sensing

3 Description

The DRV5056-Q1 device is a linear Hall effect sensor that responds proportionally to magnetic flux density. The device can be used for accurate position sensing in a wide range of applications. Featuring a unipolar magnetic response, the analog output drives 0.6 V when no magnetic field is present, and increases when a south magnetic pole is applied. This response maximizes the output dynamic range in applications that sense one magnetic pole. Four sensitivity options further maximize the output swing based on the required sensing range. The device operates from 3.3-V or 5-V power supplies. Magnetic flux perpendicular to the top of the package is sensed, and the two package options provide different sensing directions. The device uses a ratiometric architecture that can minimize error from VCC tolerance when the external analog-to-digital converter (ADC) uses the same VCC for its reference. Additionally, the device features magnet temperature compensation to counteract how magnets drift for linear performance across a wide –40°C to +150°C temperature range. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DRV5056-Q1 SOT-23 (3) 2.92 mm × 1.30 mm TO-92 (3) 4.00 mm × 3.15 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Schematic Magnetic Response

ADVANCE□INFORMATION DRV5056-Q1 SBAS643 – JANUARY 2018 www.ti.com Product Folder Links: DRV5056-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Table of Contents

11.1 Receiving Notification of Documentation Updates 15

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES January 2018 * Initial release.

ADVANCE□INFORMATION GND OUTVCC 1 2 3 GND VCC OUT DRV5056-Q1 www.ti.com SBAS643 – JANUARY 2018 Product Folder Links: DRV5056-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

5 Pin Configuration and Functions

VCC 1 1 — Power supply. TI recommends connecting this pin to a ceramic capacitor to ground with a value of at least 0.01 µF. OUT 2 3 O Analog output GND 3 2 — Ground reference (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply voltage VCC –0.3 7 V Output voltage OUT –0.3 VCC + 0.3 V Magnetic flux density, BMAX Unlimited T Operating junction temperature, TJ –40 170 °C Storage temperature, Tstg –65 150 °C

ADVANCE□INFORMATION DRV5056-Q1 SBAS643 – JANUARY 2018 www.ti.com Product Folder Links: DRV5056-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±3000 V Charged device model (CDM), per AEC Q100-011 ±750 (1) There are two isolated operating VCC ranges. For more information see the Operating VCC Ranges section. (2) Power dissipation and thermal limits must be observed.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Power supply voltage(1) 3 3.63 V 4.5 5.5 IO Output continuous current –1 1 mA TA Operating ambient temperature(2) –40 150 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) DRV5056-Q1 UNITSOT-23 (DBZ) TO-92 (LPG)

3 PINS 3 PINS

RθJA Junction-to-ambient thermal resistance 170 121 °C/W RθJC(top) Junction-to-case (top) thermal resistance 66 67 °C/W RθJB Junction-to-board thermal resistance 49 97 °C/W YJT Junction-to-top characterization parameter 1.7 7.6 °C/W YJB Junction-to-board characterization parameter 48 97 °C/W (1) B is the applied magnetic flux density. (2) VN describes voltage noise on the device output. If the full device bandwidth is not needed, noise can be reduced with an RC filter.

6.5 Electrical Characteristics

for VCC = 3 V to 3.63 V and 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT ICC Operating supply current 6 10 mA tON Power-on time (see Figure 4) B = 0 mT, no load on OUT 150 300 µs fBW Sensing bandwidth 20 kHz td Propagation delay time From change in B to change in OUT 10 µs BND Input-referred RMS noise density VCC = 5 V 130 nT/√Hz VCC = 3.3 V 215 BN Input-referred noise BND × 6.6 × √20 kHz VCC = 5 V 0.12 mTPP VCC = 3.3 V 0.2 VN Output-referred noise(2) BN × S DRV5056A1 24 mVPP DRV5056A2 12 DRV5056A3 6 DRV5056A4 3

ADVANCE□INFORMATION DRV5056-Q1 www.ti.com SBAS643 – JANUARY 2018 Product Folder Links: DRV5056-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated (1) B is the applied magnetic flux density. (2) BL describes the minimum linear sensing range at 25°C taking into account the maximum VQ and Sensitivity tolerances. (3) See the Sensitivity Linearity section. (4) STC describes the rate the device increases Sensitivity with temperature. For more information, see the Sensitivity Temperature Compensation For Magnets section. (5) See the Ratiometric Architecture section.

6.6 Magnetic Characteristics

for VCC = 3 V to 3.63 V and 4.5 V to 5.5 V, over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT VQ Quiescent voltage B = 0 mT, TA = 25°C DRV5056A1 0.535 0.6 0.665 VDRV5056A2 0.54 0.6 0.66 DRV5056A3, DRV5056A4 0.55 0.6 0.65 VQΔT Quiescent voltage temperature drift B = 0 mT, TA = –40°C to 150°C versus 25°C VCC = 5 V 0.08 V VCC = 3.3 V 0.04 S Sensitivity VCC = 5 V, TA = 25°C DRV5056A1 190 200 210 mV/mT DRV5056A2 95 100 105 DRV5056A3 47.5 50 52.5 DRV5056A4 23.8 25 26.2 VCC = 3.3 V, TA = 25°C DRV5056A1 114 120 126 DRV5056A2 57 60 63 DRV5056A3 28.5 30 31.5 DRV5056A4 14.3 15 15.8 BL Linear magnetic sensing range(2) VCC = 5 V, TA = 25°C DRV5056A1 ±20 mT DRV5056A2 ±39 DRV5056A3 ±79 DRV5056A4 ±158 VCC = 3.3 V, TA = 25°C DRV5056A1 ±19 DRV5056A2 ±39 DRV5056A3 ±78 DRV5056A4 ±155 VL Linear range of output voltage(3) VQ VCC – 0.2 V STC Sensitivity temperature compensation for magnets(4) 0.12 %/°C SLE Sensitivity linearity error(3) VOUT is within VL ±1% SRE Sensitivity ratiometry error(5) TA = 25°C, with respect to VCC = 3.3 V or 5 V -2.5% 2.5%

7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Magnetic Flux Direction

Figure 1. Direction of Sensitivity

travels from the top to the bottom of the package results in negative millitesla values. Figure 2. The Flux Direction for Positive B

7.3.2 Magnetic Response

• VQ is typically 600 mV
• B is the applied magnetic flux density
• Sensitivity(25°C) depends on the device option and VCC
• STC is typically 0.12%/°C
• TA is the ambient temperature
• VOUT is within the VL range (1) As an example, consider the DRV5056A3 with VCC = 3.3 V, a temperature of 50°C, and 67 mT applied. Excluding tolerances, VOUT = 600 mV + 67 mT × (30 mV/mT × [1 + 0.0012/°C × (50°C – 25°C)]) = 2670 mV.

7.3.3 Sensitivity Linearity

range, sensitivity is reduced and nonlinear. Figure 3 graphs the magnetic response. Figure 3. Magnetic Response quiescent voltage and sensitivity tolerances. any two negative B values, while the output is within the VL range.

7.3.4 Ratiometric Architecture

when the ADC uses VCC as its reference.

• S(VCC) is the sensitivity at the current VCC voltage
• S(5V) or S(3.3V) is the sensitivity when VCC = 5 V or 3.3 V
• VCC is the current VCC voltage (3)

7.3.5 Operating VCC Ranges

because there is a crossover threshold near 4 V that adjusts device characteristics.

7.3.6 Sensitivity Temperature Compensation For Magnets

12% higher than at TA = 25°C.

7.3.7 Power-On Time

and no load attached to OUT. Figure 4 shows this timing diagram. Figure 4. tON Definition

7.3.8 Hall Element Location

Figure 5 shows the location of the sensing element inside each package option. Figure 5. Hall Element Location

7.4 Device Functional Modes

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Selecting the Sensitivity Option

so that the output voltage swing is maximized.

8.1.2 Temperature Compensation for Magnets

reduced, temperature drift errors are also reduced.

8.1.3 Adding a Low-Pass Filter

a resistor in between because doing so can make the output unstable.

8.1.4 Designing for Wire Break Detection

exists. Figure 6 shows the circuit, and Table 1 describes fault scenarios. Figure 6. Wire Fault Detection Circuit

Table 1. Fault Scenarios and the Resulting VOUT

8.2 Typical Application

Figure 7. Unipolar Sensing Application

8.2.1 Design Requirements

Use the parameters listed in Table 2 for this design example. Table 2. Design Parameters

8.2.2 Detailed Design Procedure

such as iron, nickel, and cobalt because these materials change the magnetic flux lines.

magnetic sensing range) that is larger than the maximum magnetic flux density in the application. distance centered with the magnet. Figure 8 shows diagrams for Equation 4 and Equation 5. Figure 8. Rectangular Block and Cylinder Magnets

• W is width
• L is length
• T is thickness (the direction of magnetization)
• D is distance
• C is diameter (5) An online tool that uses these formulas is located at http://www.ti.com/product/drv5013. When different magnet orientations are used, TI recommends using simulation software and testing to determine the magnetic flux density throughout a distance.

9 Power Supply Recommendations

recommends using a ceramic capacitor with a value of at least 0.01 µF.

10 Layout

10.1 Layout Guidelines

effect sensors within plastic or aluminum enclosures and sensing magnets on the outside is common practice.

10.2 Layout Examples

Figure 9. Layout Examples

ADVANCE□INFORMATION DRV5056-Q1 www.ti.com SBAS643 – JANUARY 2018 Product Folder Links: DRV5056-Q1 Submit Documentation FeedbackCopyright © 2018, Texas Instruments Incorporated

11 Device and Documentation Support

11.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 17-Jan-2018 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PDRV5056A1EDBZTQ1 ACTIVE SOT-23 DBZ 3 250 TBD Call TI Call TI -40 to 150 PDRV5056A2EDBZTQ1 ACTIVE SOT-23 DBZ 3 250 TBD Call TI Call TI -40 to 150 PDRV5056A3EDBZTQ1 ACTIVE SOT-23 DBZ 3 250 TBD Call TI Call TI -40 to 150 PDRV5056A4EDBZTQ1 ACTIVE SOT-23 DBZ 3 250 TBD Call TI Call TI -40 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 17-Jan-2018 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C TYP0.20 0.08 0.25 2.64 2.10

1.12 MAX

TYP0.10 0.01 3X 0.5 0.3 TYP0.6 0.2 1.9 0.95 TYP -80 A 3.04 2.80 B1.4 1.2 (0.95) SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration TO-236, except minimum foot length.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

3X (1.3) 3X (0.6) (2.1) 2X (0.95) (R0.05) TYP 4214838/C 04/2017 SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE SCALE:15X PKG SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN (2.1) 2X(0.95) 3X (1.3) 3X (0.6) (R0.05) TYP SOT-23 - 1.12 mm max heightDBZ0003A SMALL OUTLINE TRANSISTOR 4214838/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:15X SYMM PKG

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