PDI1394P11 PHILIPS | Alldatasheet
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/C0109 /C0110 /C0114 PDI1394P11 3-port physical layer interface Product specification Supersedes data of 1998 Sep 24
1999 Apr 09
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
21999 Apr 09 853–2150 21222
1.0 FEATURES
- 3 cable interface ports
- Supports 100Mb/s and 200Mb/s transfers
- Interfaces to any 1394 standard Link Layer Controller
- 5V tolerant I/Os with Bus Holders
- Single 3.3V supply voltage
- Arbitrated (short) Bus Reset (1394a feature)
2.0 DESCRIPTION
The Philips Semiconductors PDI1394P11 is an IEEE1394-1995 compliant Physical Layer interface. The PDI1394P11 provides the analog physical layer functions needed to implement a three port node in a cable-based IEEE 1394–1995 network. Additionally, the device manages bus initialization and arbitration cycles, as well as transmission and reception of data bits. The Link Layer Controller interface is compatible with both 3V and 5V Link Controllers. While providing a maximum transmission data rate of 200 Mb/s, the PDI1394P11 is compatible with current 100 Mb/s Physical Layer ICs. The PDI1394P11 is available in the LQFP64 package.
3.0 ORDERING INFORMATION
PACKAGE TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 64-pin plastic LQFP 0°C to +70°C PDI1394P11 BD PDI1394P11 BD SOT314-2
4.0 PIN CONFIGURATION
TPA1– TPB1+ TPB1– AGND TPA2+ TPA2– TPB2+ TPB2– TPA3+ TPA3– TPB3+ TPB3– DGND DGND ISO– AGND PLLVDD XO XI FILTER PLLGND PLLGND AGND AGND RESET– LPS PD DGND SYSCLK DGND CTL0 CTL1 DGND DGND DVDD TESTM2 TESTM1 CPS AGND C/LKON PC2 PC1 PC0 CNA AGND PDI1394P11 DVDD DVDD DVDD LREQ DVDD AVDD AVDD AVDD AVDD
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 3
5.0 PIN DESCRIPTION
PIN NUMBER PIN SYMBOL I/O NAME AND FUNCTION
1 RESET– I* Power up reset, active LOW
2 LPS I* Link Layer Controller (LLC) power status
3 LREQ I* Link request from controller
4 DVDD I* Should be connected to the LLC VDD supply when a 5V LLC is connected to the
Phy, and should be connected to the Phy DVDD when a 3V LLC is used. 5, 6, 19, 20 DVDD D I Digital circuit power
7 PD I* Device power down input
8, 10, 17, 18, 63, 64 DGND – Digital circuit ground 9 SYSCLK O* 49.152 MHz clock to link controller 11, 12 CTL[0:1] I/O* Link interface bi-directional control signals 13, 14, 15, 16 D[0:3] I/O* Link interface bi-directional data signals 22, 21 TESTM[1:2] I* Test/Mode Control pins 11 =1394–1995 mode 10 = 1394a mode 00/01 = Reserved
23 CPS I Cable power status
24, 25, 51, 55 AVDD – Analog circuit power 26, 32, 41, 49, 50, 61AGND – Analog circuit ground
27 C/LKON I/O* Bus/Isochronous Resource Manager capable input, or LINK-ON signal output
30, 29, 28 PC[0:2] I* Power class bits 0 through 2 inputs
31 CNA O* Cable Not Active output
36, 40, 45 TPA[1:3]+ I/O Port n cable pair A, positive signal 35, 39, 44 TPA[1:3]– I/O Port n cable pair A, negative signal 34, 38, 43 TPB[1:3]+ I/O Port n cable pair B, positive signal 33, 37, 42 TPB[1:3]– I/O Port n cable pair B, negative signal 46, 47, 48 TPBIAS[1:3] O Cable termination voltage supplies 52, 53 PLLGND – PLL circuit ground
54 FILTER I/O PLL external filter capacitor
56 XI I Crystal oscillator connection
57 XO O Crystal oscillator connection
58 PLLVDD – PLL circuit power
59, 60 R[0:1] – External current setting resistor
62 ISO– I* Link interface isolation status input
NOTE: * Indicates 5V tolerant structure.
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 4
6.0 BLOCK DIAGRAM
& TRANSMIT CLOCK GENERATOR TRANSMIT DATA ENCODER TESTM1 TESTM2 C/LKON PC0 PC1 PC2 CTL0 CTL1 LREQ SYSCLK CNA ISO– LPS CPS RESET– PD TPBIAS1 TPBIAS2 TPBIAS3 TPA1+ TPA1– TPB1+ TPB1– TPA2+ TPA2– TPB2+ TPB2– TPA3+ TPA3– TPB3+ TPB3– XI XO FILTER SV00228
7.0 FUNCTIONAL SPECIFICATION
The PDI1394P11 is an IEEE1394–1995 High Performance Serial Bus Specification compliant physical layer interface device. It provides an interface between an attached link layer controller and three 1394 cable interface ports. In addition to the interface function, the PDI1394P11 performs bus initialization and arbitration functions as well as monitoring line conditions and connection status.
7.1 Clocking
The PDI1394P11 utilizes a stable internal reference clock of 196.608 MHz. The reference clock is generated using an external 24.576 MHz crystal and an internal Phase Locked Loop (PLL). The PLL clock is divided down to 49.152 MHz and 98.304 MHz clock signals. The 49.152 MHz clock is used for internal logic and provided as an output to clock a link layer controller. The 196.608 MHz and 98.304 MHz clocks are used for synchronization of the transmitted strobe and data information.
7.2 Port Interfaces
The PDI1394P11 provides the transceiver functions needed to implement a three port node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. In addition to transmission and reception of packet data, the line transceivers monitor conditions on the cable to determine connection status, data speed, and bus arbitration states. The PDI1394P11 receives data to be transmitted over the bus from two or four parallel data paths to the Link Controller, D[0:3]. These data paths are latched and synchronized with the 49.152 MHz clock. The parallel bit paths are combined serially, encoded and transmitted at either 98.304 Mb/s or 196.608 Mb/s, depending whether the transaction is a 100 Mb/s or 200 Mb/s transfer, respectively. The transmitted data is encoded as data-strobe information, with the data information being transmitted on the TPB cable pairs and the strobe information transmitted on the TPA cable pairs. During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair and the strobe information is received on the TPB cable pair. The combination of the data and strobe signals is decoded to recover the receive clock signal and the serial data stream. The serial data stream is converted to two or four parallel bit streams, resynchronized to the internal 49.152 MHz clock and sent to the
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 5
associated link controller. The received data is also transmitted out the other active cable ports. The cable status, bus initialization and arbitration states are monitored through the cable interface using differential comparators. The outputs of these comparators are used by internal logic to determine cable and arbitration status. The TPA channel monitors the incoming cable common-mode voltage value during arbitration to determine the speed of the next packet transmission. The TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage, indicating the cable connection status. The PDI1394P11 provides a nominal 1.85 V for driver load termination. This bias voltage, when seen through a cable by a remote receiver, is used to sense the presence of an active connection. The value of this bias voltage has been chosen to allow inter-operability between transceiver chips operating from either 5 V nominal supplies, or 3.3 V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor.
8.0 RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITION LIMITS UNITSYMBOL PARAMETER CONDITION MIN TYP MAX UNIT VDD DC supply voltage Source/non-source power node 3.0 3.3 3.6 V VIH High level input voltage CMOS inputs 2.0 5.5 V VIL Low level input voltage CMOS inputs 0.8 V VID–100 Differential input voltageCable inputs, 100Mbit operation 142 260 mV VID–200 Differential input voltageCable inputs, 200Mbit operation 132 260 mV VID–ARB Differential input voltageCable inputs, during arbitration 171 262 mV V C Common mode voltage TPB cable inputs, 100Mbit or speed signaling OFF, source power node 1.165 2.515 VVIC–100 Common mode voltage TPB cable inputs, 100Mbit or speed signaling OFF, non–source power node 1.165 2.015 V V CS Common mode voltage TPB cable inputs, 200Mbit or speed signaling, source power node 0.935 2.515 VVIC–200SP Common mode voltage TPB cable inputs, 200Mbit or speed signaling, non–source power node 0.935 2.015 V Receive input jitter TPA, TPB cable inputs, 100Mbit operation ±1.08 ns Receive input jitter TPA, TPB cable inputs, 200Mbit operation ±0.5 ns Receive input skew Between TPA and TPB cable inputs, 100Mbit operation ±0.8 ns Receive input skew Between TPA and TPB cable inputs, 200Mbit operation ±0.55 ns IO /IO Output current IO /IO SYSCLK –16 16 mAIOL /IOH O utput current, IOL /IOH Control, Data, CNA, C/LKON –12 12 mA IO Output current TPBIAS outputs –3 1.3 mA fXTAL Crystal frequency Parallel resonant fundamental mode crystal 24.5735 24.576 24.5785 MHz Tamb Operating ambient temperature range in free air 0 +70 °C
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 6
9.0 ABSOLUTE MAXIMUM RATINGS 1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL PARAMETER CONDITION LIMITS UNITSYMBOL PARAMETER CONDITION MIN MAX UNIT VDD DC supply voltage –0.3 4.6 V VI DC input voltage3 Inputs CPS, TPAn, TPBn, FILTER, XI –0.5 VDD +0.5 V VI,5t DC input voltage 5V tolerant digital inputs RESET–, LPS, LREQ, PD, CTL[0:1], D[0:3], TESTM[2:1], C/LKON, PC[0:2], ISO––0.5 5.5 V VO DC output voltage3 –0.5 VDD +0.5 V IIK DC input diode current VI < 0 – –50 mA IOK DC output diode current VO < 0 or VO > VDD – ±50 mA Tstg Storage temperature range –65 +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed.
10.0 CABLE DRIVER
SYMBOL PARAMETER TEST CONDITION LIMITS UNITSYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT VOD Differential output voltage 56 load 172 265 mV IO(diff) Difference current, TPA+, TPA–, TPB+, TPB– Driver enabled, speed signaling OFF–1.051 1.051 mA ISP Common mode speed signaling current, TPB+, TPB–200Mbit speed signaling enabled +2.532 +4.842 mA VOFF OFF state common mode voltage Drivers disabled 20 mV NOTES: 1. Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents. 2. Limits defined as one half of the algebraic sum of currents flowing into TPB+ and TPB–.
11.0 CABLE RECEIVER
SYMBOL PARAMETER TEST CONDITION LIMITS UNITSYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT IIC Common mode input current Driver disabled –20 20 µA Z Differential input impedance Driver disabled 15 kΩ ZID Differential input impedance Driver disabled 6 pF Z C Common mode input impedance Driver disabled 20 kΩ ZIC Common mode input impedance Driver disabled 24 pF VTH Receiver input threshold voltage –60 60 mV VTH Cable bias detect threshold, TPBn cable inputsDriver disabled 0.6 1.0 V
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 7
12.0 OTHER DEVICE I/O
SYMBOL PARAMETER TEST CONDITION LIMITS UNITSYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT IDD Supply current VDD = 3.3 V One port transmitting One port receiving One port not connected 60 mA IDD Su ly current VDD = 3.6 V 175 mA VDD = 3.6 VPower-down mode 1.5 2 5 mA VP Cable Power Threshold Voltage R L = 400 kΩ to CPS pin 4.7 7.5 V VOH High-level output voltage IOH = Max., VDD = Min. VDD – 0.55 V VOL Low-level output voltage IOL = Min., VDD = Max. 0.5 V II Input current, LREQ, LPS, PD, TESTM[1:2] VI = 5.5 V or 0 V, ISO– = 0 ±1.0 µA IOZ OFF-state output current, CTLn, Dn, C/LKON I/Os, PC[0:2] inputs VO = 5.5 V or 0 V, ISO– = 0 ±5.0 µA I Pullup current RESET input VI = 1.5 V –20 –40 –80 µA IPU Pullup current, RESET – input VI = 0 V –22 –45 –90 µA I Pulldown current RESET input VI = VDD 100 260 450 µAIPD Pulldow n current, RESET – input PD = high 100 260 450 µA Power-up reset time, RESET– input C = 0.1 µf 2 ms VTH + Positive arbitration comparator threshold voltage 89 168 mV VTH – Negative arbitration comparator threshold voltage –168 –89 mV VTH–SP Speed signal input threshold voltage 49 131 mV VIT+ Positive going input threshold voltage, LREQ, CTLn, Dn inputs VDD /2 + 0.12 VDD /2 + 0.66 V VIT– Negative going input threshold voltage, LREQ, CTLn, Dn inputs VDD /2 – 0.66 VDD /2 – 0.12 V VO TPBIASn output voltage 1.665 1.85 2.015 V Ib Absolute value of bus holding current LREQ, PD, CTLn, Dn inputs, LPS ISO– = high, VI = 0.5 VDD 190 µA
13.0 THERMAL CHARACTERISTICS
SYMBOL PARAMETER TEST CONDITION LIMITS UNITSYMBOL PARAMETER TEST CONDITION MIN TYP MAX UNIT R Θ jA Junction-to-free-air thermal resistanceBoard mounted, no air flow 92.5 °C/W R Θ jC Junction-to-case thermal resistance 10.4 °C/W
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14.0 AC SWITCHING CHARACTERISTICS
15.0 SWITCHING WAVEFORMS
Figure 1. Dn, CTLn, LREQ input setup and hold times Figure 2. Dn, CTLn, output delay relative to SYSCLK
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 9
16.0 INTERNAL REGISTER CONFIGURATION
The accessible internal registers of this device are listed in the following tables: ADDRESS 0 1 2 3 4 5 6 7
0000 Physical ID R CPS
0001 RHB IBR GC
0010 SPD Reserved NP
0011 AStat1 BSTAT1 Ch1 Con1 Reserved
0100 AStat2 BSTAT2 Ch2 Con2 Reserved
0101 AStat3 BSTAT3 Ch3 Con3 Reserved
0110 Loopint CPSint CPS IR Reserved C
0111 Reserved PC2 PC1 PC0 C
1000 Reserved
1001 Reserved ISBR
The keys are listed as follows: FIELD SIZE TYPE DESCRIPTION Physical ID 6 Rd The address of the local node determined during the Self-ID. R 1 Rd Indicates that the local node is the root. CPS 1 Rd Cable power Status (CPS input). RHB 1 Rd/Wr Root hold-OFF bit. Instructs the local node to try to become the root during the next bus reset. IBR 1 Rd/Wr Initiate Bus Reset. Instructs the PDI1394P11 to initiate Bus Reset at the next opportunity. GC 6 Rd/Wr Gap count. Used to optimize the gap times based on the size of the network. See 1394 standard for details. SPD 2 Rd Indicates the top signaling speed of the local ports. NP 4 Rd The number of ports on this device, set to 0011. AStat(n) 2 Rd The line state of TPA of port n: 11 = Z 01 = 1 10 = 0 00 = invalid data state. Power up reset initializes to this line state. Also this line state is output during transmit and receive operations. The line state outputs are generally valid during arbitration and idle conditions on the bus. BStat(n) 2 Rd The line state of TPB of port n. The encoding is the same as AStat(n). Ch(n) 1 Rd If = 1, then port n is a child, otherwise it is a parent. Con(n) 2 Rd If = 1, then port n is connected, otherwise it is disconnected. Loopint 1 Rd/Wr Indicates that the PDI1394P11 times out in tree ID, waiting for child signal from two or more ports. The Loopint can be cleared by writing a ‘‘0’’ to this bit, but if the loop configuration has not been corrected, it will promptly return to a ‘‘1’’. CPSint 1 Rd/Wr Indicates that the cable power has dropped too low for guaranteed reliable operation. It can be cleared by writing a ‘‘0’’ to the bit, but it will immediately return if CPS is still LOW. CPS 1 Rd/Wr Cable Power Status is also included in this register to expedite handling the CPSint. IR 1 Rd/Wr Indicates that the last bus reset was initiated in the PDI1394P11. This bit is also included in the self ID packet. C 1 Rd If set, this node is a contender for the role of bus or Isochronous Resource Manager. PC2 1 Rd The least significant power class bit PC1 1 Rd The middle power class bit PC0 1 Rd The most significant power class bit ISBR 1 Rd/Wr Initiate Short Bus Reset. Instructs the PDI1394P11 to initiate an arbitrated short bus reset. See Section 17.1.
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17.0 APPLICATION INFORMATION
Figure 3. External Component Connections Figure 4. Twisted pair cable interface connections
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17.1 Arbitrated (short) Bus Reset
To enable Arbitrated (short) Bus Reset mode, set TESTM2 low. Reset) bit (bit 7) of Phy register 9 initiates an arbitrated bus reset. when initiated by another node.
17.2 Setting the CPS Trip Point
is adjustable on the PDI1394P11. values are shown in Table 1. Table 1. Typical threshold voltage values
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 12
18.0 EXTERNAL COMPONENTS AND CONNECTIONS
18.1 Logic Reset input (RESET–, pin 1)
Forcing this pin low causes a Bus Reset condition on the active cable ports, and resets the internal logic to the Reset Start state. SYSCLK remains active. An internal pull-up resistor is provided that is connected to V DD , so only an external delay capacitor is required. This input is a standard logic buffer and may also be driven by an open drain logic output buffer. The RESET pin also has a n-channel pull-down transistor activated by the PD (Power Down) pin.
18.2 Link Power Status input (LPS, pin 2)
In a non-isolated implementation a 10kΩ resistor is connected to the VDD supplying the link layer controller to monitor the link’s power status. In an isolated implementation a square wave with a minimum frequency of 500 kHz can be applied to the LPS pin to indicate the pin is powered. If the link is not powered on the Control I/O’s (pins 11,12), Data I/O’s (pins 13 – 16) and SYSCLK output (pin 9) are disabled, and the PDI1394P11 will perform only the basic repeater functions required for network initialization and operation.
18.3 Link Request input (LREQ, pin 3)
LREQ is a signal from the link layer controller used to request the PDI1394P11 to perform some service. This pin supports an optional isolation barrier.
18.4 Power Down input (PD, pin 7)
This input powers down all device functions with the exception of the CNA circuit to conserve power in portable or battery powered applications. It must be held high for at least 3.5ms to assure a successful reset after power down. This pin supports an optional isolation barrier.
18.5 System Clock output (SYSCLK, pin 9)
Provides a 49.152 MHz clock signal, synchronized with the data transfers, to the link layer controller. This pin supports an optional isolation barrier.
18.6 Control I/Os (CTL[0:1], pins[11,12])
These are bi-directional signals used in the communication between the PDI1394P11 and the link layer controller that control passage of information between the two devices. These pins support an optional isolation barrier.
18.7 Data I/Os (D[0:3], pins [13,14,15,16])
These are bi-directional information signals used in the communication between the PDI1394P11 and the link layer controller. These pins support an optional isolation barrier.
18.8 Test Mode control and ISBR mode inputs
(TESTM[1:2], pins[22,21]) These two logic signals are used in manufacturing to enable production line testing of the PDI1394P11. For normal use these should be tied to V DD . To enable ISBR (Arbitrated (short) bus reset) mode, set TESTM1 high and TESTM2 low. See section 17.1 for more information on ISBR mode.
18.9 Cable Power Status input (CPS, pin 23)
This is normally connected to the cable power through an external resistor. The circuit drives an internal comparator which is used to detect the presence of cable power. This information is maintained in an internal register and is available to the link layer controller through a register read. See section 17.2 for information on setting the CPS trip point.
18.10 Bus or Isochronous Resource Manager
Capable input or Link-On output (C/LKON, pin 27) This is a bi-directional pin that is used as an input to specify, in the Self-ID packet, that the node is Bus or Isochronous Resource Manager Capable. As an output it signals the reception of a Link-On message by supplying a 6.114 MHz signal. The bit value programming is done by tying the pin through a 10kΩ resistor to a high (V DD ) or low (GND). The use of the series resistor allows the Link-On to override the input value when necessary.
18.11 Power Class bits 0 through 2 inputs
Used as inputs to set the bit values of the three Power Class bits in the self-ID packet (bits 21, 22 and 23). These bits can be programmed by tying the pins high to VDD or low to GND.
18.12 Cable Not Active output (CNA, pin 31)
This pin outputs the cable connection status. If all ports are disconnected this pin outputs a high. If any port has a cable connected then this pin outputs a low.
18.13 Twisted Pair I/O’s (TPA[1:3]+,
TPB[1:3]+, pins [43,38,34], TPB[1:3]–, pins [42, 37, 33]) These pins send and receive differential data over the twisted pair cables. Two series connected external 56 Ω cable termination resistors are required at each twisted pair. Each unused TPB pin must be tied through a 5kΩ resistor to ground. The TPA pins can be left floating.
18.14 Twisted Pair Bias outputs (TPBIAS[1:3],
pins [46, 47, 48]) These outputs provide the 1.86 V nominal bias voltage needed for proper operation of the twisted pair cable drivers, and for signaling to the remote nodes that there is a valid cable connection. Three TPBIAS outputs are provided for separate connection to each of the three TPA twisted pairs to provide electrical isolation. A 1µF capacitor to ground must be connected to each TPBIAS pin whether it is used or not.
18.15 PLL Filter (FILTER, pin 54)
This pin is connected to an external filter capacitor used in a lag-lead filter for a PLL frequency multiplier running off of the crystal oscillator.
18.16 Oscillator crystal (Xl, pin 56 & XO, pin 57)
These pins connect to a 24.576 MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used, the suggested values of 12 pF are appropriate for one specified for 15 pF loads.
18.17 Current setting resistor (R[0:1],
pins [59,60]) An internal reference voltage is applied across the resistor connected between these two pins to set the internal operating and the cable driver output currents. A low TCR (<150ppm/°C temperature coefficient) with a value of 6.34 kΩ ±1% should be used to meet the 1394 standard output voltage limits.
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 13
18.18 Isolation Barrier disable (ISO–, pin 62)
When ISO– is high, busholder circuits are enabled on the LREQ, PD, and LPS input pins and on the CTL, and Data bidirectional pins. This mode also allows isolation using a single 1nF capacitor per signal line. When ISO– is low, busholder circuits are disabled and isolation can be realized by using the scheme explained in Annex J of the 1394–1995 spec.
18.19 Supply filters (AVDD, pins [24, 25, 51, 55],
DVDD, pins [5,6,19,20], and PLLVDD, pin 58) A combination of decoupling capacitors is suggested for each supply group, such as paralleled 10 µF and 0.1 µF. The high frequency 0.1 µF capacitors should be mounted as close as possible to the PDI1394P11 device supply leads. These supply lines are separated on the IC to provide noise isolation. They should be tied together at a low impedance point on the circuit board. Individual filter networks are desirable. Details of a phy-link Interface supporting an optional isolation barrier are provided in Annex J of the 1394 standard.
19.0 PRINCIPLES OF OPERATION
The PDI1394P11 is designed to operate with a link layer controller. These devices use an interface such as described in Annex J of the 1394 standard. The following describes the operation of the phy-link interface.
19.1 Data Transfer and Clock rates
The PDI1394P11 supports 100/200 Mbit/s data transfer, and has four bi-directional data lines D[0:3] crossing the interface. In 100 Mbit/s operation only D[0:1] pins are used, in 200 Mbit/s operations all D[0:3] pins are used for data transfer. The unused D[n] pins are driven low. In addition there are two bi-directional control lines CTL[0:1], the 50 MHz SYSCLK line from the phy to the link, and the link request line LREQ from the link to the phy. The PDI1394P11 has control of all the bi-directional pins. The link is allowed to drive these pins only after it has been given permission by the phy. The dedicated LREQ request pin is used by the link for any activity which it wishes to initiate. When the phy has control of the bus the CTL[0:1] lines are encoded as follows: CTL [0:1] NAME DESCRIPTION OF ACTIVITY
00 Idle No activity is occurring (this is the default
mode).
01 Status Status information is being sent from the
phy to the link.
10 Receive An incoming packet is being sent from the
phy to the link.
11 Grant The link has been given control of the bus
to send an outgoing packet. When the link has control of the bus (phy permission) the CTL[0:1] lines are encoded as follows: CTL [0:1] NAME DESCRIPTION OF ACTIVITY
00 Idle The link releases the bus (transmission
has been completed).
01 Hold The link is holding the bus while data is
being prepared for transmission or sending another packet without arbitrating.
10 Transmit An outgoing packet is being sent from the
link to the phy.
11 NA None
19.2 Request
When the link layer controller wishes to request the bus, or access a register that is located in the PDI1394P11, a serial stream of information is sent across the LREQ line. The length of the stream will vary depending on whether the transfer is a bus request, a read command, or a write command. Regardless of the type of transfer, a start bit of 1 is required at the beginning of the stream, and a stop bit of 0 is required at the end of the stream. Bit 0 is the most significant, and is transmitted first. The LREQ line will be required to idle low (logic level 0).
19.2.1 Link Layer Controller Bus Request
For a Bus Request, the length of the LREQ data stream is 7 bits as follows: BIT(S) NAME DESCRIPTION
0 Start Bit Indicates the beginning of the transfer
(always 1) 1–3 Request Type Indicates the type of bus request (see the table below for the encoding of this field) 4–5 Request Speed This should be 00 for PDI1394P11’s
100 Mbit/s speed and 01 for
200 Mbit/s speed.
6 Stop Bit Indicates the end of the transfer
(always 0)
19.2.2 Link Layer Controller Requests Read Register Access
For a Read Register Request, the length of the LREQ data stream is 9 bits as follows: BIT(S) NAME DESCRIPTION (always 1) 1–3 Request Type Always a 100 indicating that this is a read register request 4–7 Address The address of the phy register to be read
8 Stop Bit Indicates the end of the transfer (always 0)
19.2.3 Link Layer Controller Requests Write Register Access
For a Write Register Request, the length of the LREQ data stream is 17 bits. The details of bits are as shown below: BIT(S) NAME DESCRIPTION (always 1) 1–3 Request Type Always a 101 indicating that this is a write register request 4–7 Address The address of the phy register to be written to 8–15 Data The data that is to be written to the specified register address
16 Stop Bit Indicates the end of the transfer (always 0)
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19.2.4 Other Requests and LREQ
001 IsoReq Isochronous request: Arbitrate for the bus, no gaps
010 PriReq Priority request: Arbitrate after a subaction gap, ignore fair protocol
011 FairReq Fair request: Arbitrate after a subaction gap, follow fair protocol
100 RdReg Return the specified register contents through a status transfer
101 WrReg Write to the specified register
19.3 Operation of LREQ
Figure 6. LREQ Input Sequence (each cell represents one SYSCLK sample time) one clock after the next interface idle. when the isochronous transfer has been completed.
19.4 Read/Write Requests
attempt to transfer the contents of the register until it is successful.
19.5 Status
consecutive status transfers. The phy normally sends just the first four bits of status to the link. which contains the new node address. The definition of the bits in the status transfer are shown below.
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20.0 STATUS REQUEST, LENGTH OF STREAM: 16 BITS
defined in the P1394 standard). This bit is used by the link in its busy/retry state machine. in the P1394 standard). This bit is used by the link to detect the completion of an isochronous cycle. 2 Bus Reset Indicates that the phy has entered the bus reset state.
3 State Time out or
in the cable topology, or that the cable power has dropped below the threshold for reliable operation. 4–7 Address These bits hold the address of the phy register whose contents will be transferred to the link. 8–15 Data The data that is to be sent to the link.
21.0 STATUS TRANSFER TIMING
00 S[0,1] S[2,3]PHY
Figure 7. Status Transfer Timing
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22.0 TRANSMIT
SYSCLK cycle, followed by idle for one clock cycle. of the bus if it needs some time to prepare the data for transmission. ‘hold’ if it is ready to transmit as soon as bus ownership is granted. releases control of the interface. CTL pins, the phy will assert its own ‘Idle’ state on the CTL lines.
22.1 TRANSMIT TIMING WAVEFORMS
Figure 8. Transmit Timing Waveforms
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23.0 RECEIVE
been completely transferred, the phy will assert ‘Idle’ on the CTL pins which will complete the receive operation. NOTE : The speed is a phy-link protocol and not included in the CRC.
23.1 RECEIVE TIMING WAVEFORMS
Figure 9. Receive Timing Waveforms X transmitted as 0, ignored on receive.
24.0 POWER CLASS BITS IN SELF–ID PACKET
The settings of the PC[0:2] pins appear in the pwr field of the self–ID packet. Bit 21 is transmitted first, followed by bit 22 and then bit 23. 000 Node does not need power and does not repeat power. 001 Node is self powered, and provides a minimum of 15 W to the bus. 010 Node is self powered, and provides a minimum of 30 W to the bus. 011 Node is self powered, and provides a minimum of 45 W to the bus. 100 Node may be powered from the bus, and is using up to 1 W. 101 Node may be powered from the bus, and is using up to 1 W. An additional 2 W is needed to enable the LLC and higher layers. 110 Node may be powered from the bus, and is using up to 1 W. An additional 5 W is needed to enable the LLC and higher layers. 111 Node may be powered from the bus, and is using up to 1 W. An additional 9 W is needed to enable the LLC and higher layers.
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 18
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 19
Philips Semiconductors Product specification PDI1394P113-port physical layer interface
1999 Apr 09 20
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors
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P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Copyright Philips Electronics North America Corporation 1999 All rights reserved. Printed in U.S.A. Date of release: 04-99 Document order number: 9397 750 05511 /C0109 /C0110 /C0114 Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Production Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Data sheet status [1] Please consult the most recently issued datasheet before initiating or completing a design.