Interface

PDAC39RFS10ACL

Texas Instruments

DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface REVISED FEBRUARY 2026

Manufacturer: Texas Instruments

Document: 232 Pages / 14Mb

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DAC39RF10-SP_V01 TI | Alldatasheet

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Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
PDF pages: 232

Technical content

DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface

1 Features

Radiation hardness assured DAC39RFx10-SP: – Single event upset (SEU) immune registers – Single-event latch up (SEL): 120MeV-cm2/mg – RLAT Total ionizing dose (TID): 300krad (Si)
Radiation tolerant DAC39RFx10-SEP: – Single event upset (SEU) immune registers – Single-event latch up (SEL): 43MeV-cm2/mg – RLAT Total ionizing dose (TID): 30krad (Si)
16-bit, 10.4 or 20.8GSPS, multi-Nyquist DAC Cores
Maximum input data rate: – 8-bit, Single channel, DES mode: 20.8GSPS – 12-bit, Single channel, DES mode: 15.5GSPS – 16-bit, Single channel: 10.4GSPS – 8-bit, Dual channel, 10.4GSPS – 12-bit, Dual channel: 7.75GSPS/ch – 16-bit, Dual channel: 6.2GSPS/ch
Output bandwidth (-3dB): 12GHz
Performance at fOUT = 2.997GHz, DES2XL mode, DEM/Dither off – Noise floor (small signal): –155dBFS/Hz – SFDR (-0.1dBFS) : 60dBc – IMD3 (-7dBFS each tone) : –62dBc – Additive phase noise, 10kHz offset: -138dBc/Hz
Four Integrated digital up-converters (DUC) – Interpolation: 1x, 2x, 3x, 4x, 6x, 8x, 12x ... 256x – Complex baseband DUC for I/Q output – Complex to real up conversion for dual channel direct RF sampling – 64-bit frequency resolution NCOs
JESD204C Interface – Up to 16 Lanes at up to 12.8Gbps – Class C-S, subclass-1 Compatible – Internal AC coupling capacitors
SYSREF Windowing for automatic SYSREF timing calibration
Space screening and assurance: – Meets ASTM E595 outgassing specification – One fabrication, assembly, and test site – Wafer lot traceability – Extended product life cycle – Radiation lot acceptance test (RLAT) – Production burn-in (DAC39RFx10-SP only)
This device contains non-encapsulated chip-caps with tin (Sn) finish of >97% purity. See reliability report for more information

2 Applications

Satellite communications (SATCOM)
Wideband and highspeed data transmission
RF synthesis for clocking or local oscillator (LO)
Phased array antenna systems
Synthetic aperture radar (SAR) exciter
Spectroscopy

3 Description

The DAC39RF10-Sx and 'RFS10-Sx are a family of dual and single channel digital-to-analog converters (DAC) with 16-bit resolution. The devices can be used as non-interpolating or interpolating DACs for either direct RF sampling or complex baseband signal generation. The maximum input data rate is 20.8GSPS for a single channel or 10.4 GSPS for two channels. The devices can generate signals of up to 10, 7.5, and 5GHz signal bandwidth (8, 12, and 16- bit input resolution) at carrier frequencies exceeding 10GHz enabling direct sampling in X-band. The high sampling rate, output frequency range, 64- bit NCO frequency resolution and any frequency hopping with phase coherence also makes the DAC39RF10-Sx and 'RFS10-Sx capable of arbitrary waveform generation (AWG) and direct digital synthesis (DDS). A JESD204B and JESD204C compatible serial interface has 16 receiver pairs capable of up to 12.8Gbps. The interface is JESD204B and JESD204C subclass-1 compliant for deterministic latency and multi-device synchronization through the use of SYSREF.

Package Information

PART NUMBER(1) GRADE(2) PACKAGE SIZE(3) DAC39RF10ACLNSP Space Enhanced Product (-SEP) 30krad(Si) ACL, 17mm × 17mm, 1mm pitch DAC39RFS10ACLNSP DAC39RF10ACL-MLS Flight grade Space- MLS (-SP) 300krad(Si)DAC39RFS10ACL-MLS (1) For more information, see Section 12. (2) For additional information about part grade, see the TI Part Ratings. (3) The package size (length × width) is a nominal value and includes pins, where applicable. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

CLK– SYSREF+ SYSREF– SYSREF Window JESD204B/ 204C Block 0SRX+ 0SRX– DACOUTB+ DACOUTB– SYNC Mul -Nyquist DAC 7SRX+ 7SRX– 15SRX+ 15SRX– 8SRX+ 8SRX– Lane MUX DACOUTA+ DACOUTA– Mul -Nyquist DAC FRDI0 FRDI1 FRDI2 FRDI3 RF Bonder or IQ DAC MUX DUC0 L DUC1 L DUC2 L DUC3 L DESDAC DESDAC FRCLK FRCS Fast Recon gura on controller TXENABLE0 SDO SCS SCLK SDI RESET ALARM Control Interface & GPIOs TXENABLE1 Block Diagram (Dual Channel Devices) DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.11 Typical Characteristics: Bandwidth and DC

6.15 Typical Characteristics: Power Dissipation and

6.18 Typical Characteristics: Phase and Amplitude

10.1 Receiving Notification of Documentation Updates225

12 Mechanical, Packaging, and Orderable

www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

4 Device Comparison

Device # Channels Maximum Sample Rate (Single, Dual Edge) Radiation Tolerance JESD Interface SEL/SEFI TID DAC39RF10 2 10.24, 20.48GSPS N/A N/A Yes DAC39RFS10 1 10.24, 20.48GSPS N/A N/A Yes DAC39RF12 2 12, 24GSPS N/A N/A Yes DAC39RFS12 1 12, 24GSPS N/A N/A Yes DAC39RF10-EP 2 10.4, 20.8GSPS N/A N/A Yes DAC39RFS10-EP 1 10.4, 20.8GSPS N/A N/A Yes DAC39RF10-SP 2 10.4, 20.8GSPS 120MeV 300krad Yes DAC39RFS10-SP 1 10.4, 20.8GSPS 120MeV 300krad Yes DAC39RF10-SEP 2 10.4, 20.8GSPS 43MeV 30krad Yes DAC39RFS10-SEP 1 10.4, 20.8GSPS 43MeV 30krad Yes DDS39RF12 2 12, 24GSPS N/A N/A 2 lanes only DDS39RFS12 1 12, 24GSPS N/A N/A 2 lanes only DAC39RF10EF 2 10.24, 20.48GSPS N/A N/A Input rate limited DAC39RFS10EF 1 10.24, 20.48GSPS N/A N/A Input rate limited DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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5 Pin Configuration and Functions

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E F G H J K L M N P R T Not to scale DGND DGND DGND 2SRX- 2SRX+ DGND 0SRX- 0SRX+ DGND AGND AGND DACOUTA+ DACOUTA- AGND VSSCLK VSSCLK DGND DGND DGND 3SRX- 3SRX+ DGND 1SRX- 1SRX+ DGND AGND AGND AGND AGND AGND VSSCLK VSSCLK 4SRX+ 5SRX+ VDDT VDDT VDDT DGND VDDT VDDT DGND AGND VEEAM18 VEEAM18 VEEAM18 AGND VSSCLK VSSCLK 4SRX- 5SRX- VDDT TXEN1 TXEN0 RESET SDO SDI VDDIO AGND VEEAM18 VEEAM18 VEEAM18 AGND VSSCLK CLK+ DGND DGND DGND FRDI0 FRDI1 SCANEN SCS SCLK VDDIO VSSCLK VSSCLK VDDCLK10 VSSCLK VSSCLK VSSCLK CLK- 6SRX+ 7SRX+ VDDT FRCLK FRDI2 DGND VDDDIG VDDEA VDDEA VDDLA VDDCLK10 VSSCLK VSSCLK VSSCLK VSSCLK VSSCLK 6SRX- 7SRX- VDDT FRCS FRDI3 VDDT DGND VDDDIG DGND VSSCLK VSSCLK VSSCLK AGND VDDA18A AGND AGND DGND DGND DGND ALARM VDDT DGND VDDDIG DGND DGND VDDLA VDDCLK10 VDDCLK18 VDDCLK18 VDDA18A AGND RBIAS- DGND DGND DGND SYNC VDDT DGND VDDDIG DGND DGND VDDLB VDDCLK10 VDDSYS18 VDDSYS18 VDDA18B EXTREF RBIAS+ 14SRX+ 15SRX+ VDDT VDDR18 DGND VDDT DGND VDDDIG DGND VSSCLK VSSCLK VSSCLK AGND VDDA18B AGND AGND 14SRX- 15SRX- VDDT VDDR18 DGND DGND VDDDIG VDDEB VDDEB VDDLB VDDCLK10 VSSCLK VSSCLK VSSCLK VSSCLK VSSCLK DGND DGND DGND VDDR18 RTEST VDDT DGND VDDDIG DGND VSSCLK VSSCLK VDDCLK10 VSSCLK VSSCLK VSSCLK SYSREF+ 12SRX+ 13SRX+ VDDT VDDR18 DGND ATEST VDDDIG DGND VQPS AGND VEEBM18 VEEBM18 VEEBM18 AGND VSSCLK SYSREF- 12SRX- 13SRX- VDDT VDDT VDDT DGND VDDT VDDT VQPS AGND VEEBM18 VEEBM18 VEEBM18 AGND VSSCLK VSSCLK DGND DGND DGND 11SRX+ 11SRX- DGND 9SRX+ 9SRX- DGND AGND AGND AGND AGND AGND VSSCLK VSSCLK DGND DGND DGND 10SRX+ 10SRX- DGND 8SRX+ 8SRX- DGND AGND AGND DACOUTB+ DACOUTB- AGND VSSCLK VSSCLK Figure 5-1. FCBGA Package, 256-Ball Flip Chip BGA with 1mm pitch (Top View) www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. DAC OUTPUTS DACOUTA- A13 O DAC channel A analog output negative terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance. DACOUTA+ A12 O DAC channel A analog output positive terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance. DACOUTB- T13 O DAC channel B analog output negative terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance. Not available in single channel devices. DACOUTB+ T12 O DAC channel B analog output positive terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance. Not available in single channel devices. DIFFERENTIAL CLOCK AND SYSREF INPUTS CLK- E16 I Device clock input negative terminal. There is an internal 100Ω differential termination between CLK+ and CLK–. This input is self-biased and must be AC coupled to the clock source. CLK+ D16 I Device clock input positive terminal. There is an internal 100Ω differential termination between CLK+ and CLK–. This input is self-biased and must be AC coupled to the clock source. SYSREF- N16 I Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω differential termination between SYSREF+ and SYSREF–. SYSREF+ M16 I Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω differential termination between SYSREF+ and SYSREF–. SerDes INTERFACE 0SRX- A7 I Serdes Lane 0 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 0SRX+. 0SRX+ A8 I Serdes Lane 0 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 0SRX-. 10SRX- T5 I Serdes Lane 10 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 10SRX+. 10SRX+ T4 I Serdes Lane 10 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 10SRX-. 11SRX- R5 I Serdes Lane 11 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 11SRX+. 11SRX+ R4 I Serdes Lane 11 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 11SRX-. 12SRX- P1 I Serdes Lane 12 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 12SRX+. 12SRX+ N1 I Serdes Lane 12 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 12SRX-. 13SRX- P2 I Serdes Lane 13 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 13SRX+. 13SRX+ N2 I Serdes Lane 13 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 13SRX-. 14SRX- L1 I Serdes Lane 14 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 14SRX+. 14SRX+ K1 I Serdes Lane 14 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 14SRX-. 15SRX- L2 I Serdes Lane 15 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 15SRX+. 15SRX+ K2 I Serdes Lane 15 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 15SRX-. 1SRX- B7 I Serdes Lane 1 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 1SRX+. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. 1SRX+ B8 I Serdes Lane 1 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 1SRX-. 2SRX- A4 I Serdes Lane 2 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 2SRX+. 2SRX+ A5 I Serdes Lane 2 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 2SRX-. 3SRX- B4 I Serdes Lane 3 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 3SRX+. 3SRX+ B5 I Serdes Lane 3 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 3SRX-. 4SRX- D1 I Serdes Lane 4 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 4SRX+. 4SRX+ C1 I Serdes Lane 4 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 4SRX-. 5SRX- D2 I Serdes Lane 5 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 5SRX+. 5SRX+ C2 I Serdes Lane 5 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 5SRX-. 6SRX- G1 I Serdes Lane 6 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 6SRX+. 6SRX+ F1 I Serdes Lane 6 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 6SRX-. 7SRX- G2 I Serdes Lane 7 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 7SRX+. 7SRX+ F2 I Serdes Lane 7 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 7SRX-. 8SRX- T8 I Serdes Lane 8 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 8SRX+. 8SRX+ T7 I Serdes Lane 8 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 8SRX-. 9SRX- R8 I Serdes Lane 9 negative input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 9SRX+. 9SRX+ R7 I Serdes Lane 9 positive input. Includes in package AC-coupling series capacitor and 100Ω internal termination to 9SRX-. GPIO FUNCTIONS ALARM H4 O ALARM pin is asserted when an internal unmasked alarm is detected. Alarm mask is set by ALM_MASK register. FRCLK F4 I Fast reconfiguration interface clock. FRCS G4 I Fast reconfiguration interface chip select. Internal pullup. FRDI0 E4 I Fast reconfiguration interface data bit 0. FRDI1 E5 I Fast reconfiguration interface data bit 1. FRDI2 F5 I Fast reconfiguration interface data bit 2. FRDI3 G5 I Fast reconfiguration interface data bit 3. RESET D6 I Device reset input, active low. Must be toggled after power up. Internal pullup. SCANEN E6 I TI use only, can be left unconnected. Internal pulldown. SCLK E8 I Serial programming interface (SPI) clock input. SCS E7 I Serial programming interface (SPI) device select input, active low. Internal pullup. SDI D8 I Serial programming interface (SPI) data input. SDO D7 O Serial programming interface (SPI) data output. High impedance when not reading out SPI data. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. SYNC J4 O JESD204C SYNC output, active low. TXEN0 D5 I Transmit enable for channel A active high input. This pin must be enabled using register USE_TX_EN0. The DAC output is forced to midcode (0x0000 in 2's complement) when transmission is disabled. Internal pullup. TXEN1 D4 I Transmit enable for channel B active high input. This pin must be enabled using register USE_TX_EN1. The DAC output is forced to midcode (0x0000 in 2's complement) when transmission is disabled. Internal pullup. ANALOG FUNCTIONS ATEST N6 O Analog test pin for TI use. Must be left disconnected. EXTREF J15 I/O Reference voltage output or input, determined by the EXTREF_EN register field. If the internal reference is used, the ball must be tied through 0.1uF to AGND. RBIAS- H16 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS+. RBIAS+ J16 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS-. RTEST M5 O TI use only. Tie to AGND. POWER SUPPLIES VDDA18A G14 H14 I 1.8V supply voltage for DAC channel A. Can be combined with VDDA18B, but can degrade channel-to-channel crosstalk (XTALK). VDDA18B J14 K14 I 1.8V supply voltage for DAC channel B. Can be combined with VDDA18A, but can degrade channel-to-channel crosstalk (XTALK). VDDCLK10 F11 H11 J11 L11 E12 M12 I 1V supply voltage for internal sampling clock distribution path. Noise or spurs on this supply can degrade phase noise performance. Recommended to separate from VDDDIG and VDDA for best performance. VDDCLK18 H12 H13 I 1.8V supply voltage for clock (CLK+/–) input buffer. Noise or spurs on this supply can degrade phase noise performance. VDDDIG F7 H7 J7 L7 N7 G8 K8 M8 I 1V supply voltage for digital block. Recommended to separate from VDDA and VDDCLK for best performance. VDDEA F8 F9 I 1V supply voltage for channel A DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEB. VDDEB L8 L9 I 1V supply voltage for channel B DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEA. VDDIO D9 E9 I 1.8V supply for CMOS input and output terminals. VDDLA F10 H10 I 1V supply for DAC analog latch for channel A. Separate from VDDLB for best channel-to- channel crosstalk (XTALK). Must be separated from VDDDIG for best performance. VDDLB J10 L10 I 1V supply for DAC analog latch for channel B. Separate from VDDLA for best channel-to- channel crosstalk (XTALK). Must be separated from VDDDIG for best performance. VDDR18 K4 L4 M4 N4 I 1.8V Supply voltage for SerDes receivers. VDDSYS18 J12 J13 I 1.8V supply voltage for SYSREF (SYSREF+/–) input buffer. Can be combined with VDDCLK18 when SYSREF is disabled during normal operation. This supply must be separate from VDDCLK18 when SYSREF is run continuously during operation to avoid noise and spur coupling and reduced phase noise performance. VDDT C3 D3 F3 G3 K3 L3 N3 P3 C4 P4 C5 H5 J5 P5 G6 K6 M6 C7 P7 C8 I 1V Supply voltage for SerDes termination. VEEAM18 C11 D11 C12 D12 C13 D13 I –1.8V supply voltage for DAC current source bias for channel A. Can be combined with VEEBM18, but can degrade channel-to-channel crosstalk (XTALK). VEEBM18 N11 P11 N12 P12 N13 P13 I –1.8V supply voltage for DAC current source bias for channel B. Can be combined with VEEAM18, but can degrade channel-to-channel crosstalk (XTALK). VQPS N9 P9 I TI use only. Can be tied to DGND during normal operation. GROUNDS DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. AGND A10 B10 C10 D10 N10 P10 R10 T10 A11 B11 R11 T11 B12 R12 B13 G13 K13 R13 A14 B14 C14 D14 N14 P14 R14 T14 G15 H15 K15 G16 K16 - Analog ground. DGND A1 B1 E1 H1 J1 M1 R1 T1 A2 B2 E2 H2 J2 M2 R2 T2 A3 B3 E3 H3 J3 M3 R3 T3 K5 L5 N5 A6 B6 C6 F6 H6 J6 L6 P6 R6 T6 G7 K7 M7 H8 J8 N8 A9 B9 C9 G9 H9 J9 K9 M9 R9 T9 - Digital ground. VSSCLK E10 G10 K10 M10 E11 G11 K11 M11 F12 G12 K12 L12 E13 F13 L13 M13 E14 F14 L14 M14 A15 B15 C15 D15 E15 F15 L15 M15 N15 P15 R15 T15 A16 B16 C16 F16 L16 P16 R16 T16 - Clock ground. (1) I = input, O = output, I/O = bidirectional www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS MIN MAX UNIT Supply voltage range Supply voltage range, VDDA18A, VDDA18B(2) -0.3 2.45 V Supply voltage range, VEEAM18, VEEBM18(2) -2.0 0.3 V Supply voltage range, VDDCLK18, VDDSYS18(3) -0.3 2.45 V Supply voltage range, VDDLB, VDDLA, VDDCLK10(3) -0.3 1.3 V Supply voltage range, VDDIO, VQPS, VDDR18(4) -0.3 2.45 V Supply voltage range, VDDDIG, VDDEB, VDDEA, VDDT(4) -0.3 1.3 V Voltage between any combination of AGND, DGND and VSSCLK Voltage between any combination of AGND, DGND and VSSCLK -0.1 0.1 V Voltage applied to input pins CLK+, CLK–, SYSREF+, SYSREF-(3) -0.3 VDDCLK18+0.3 V [0:15]SRX-/+ AC Voltage 1.6 [0:15]SRX-/+ DC Voltage to GND -5 5 SCLK, SCS, SDI, RESET, SYNC, SCANEN, TXEN[0:1], FRDI[0:3], FRCLK, FRCS, SYNC (4) -0.3 VDDIO+0.3 EXTREF(2) -0.3 VDDA18A + 0.3 Voltage at output pins DACOUTA+, DACOUTA-(2) -0.3 VDDA18A + 0.5 V DACOUTB+, DACOUTB-(2) -0.3 VDDA18B + 0.5 ATEST, RBIAS-/+(2) -0.5 VDDA18B + 0.3 SDI, SDO, ALARM(4) -0.5 VDDIO + 0.3 Peak input current (any input) -20 20 mA Peak total input current (sum of absolute value of all currents forced in or out, not including power supply current and DACOUTA+, DACOUTA–, DACOUTB+ and DACOUTB–) 30 mA Junction temperature, TJ 150 °C Storage temperature, Tstg -65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) Measured to AGND. (3) Measured to VSSCLK. (4) Measured to DGND.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ ESDA/JEDEC JS-001, all pins(1) 1000 V Charged device model (CDM), per ANSI/ ESDA/JEDEC JS-002, all pins(2) 250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Supply voltage range VDDA18A, VDDA18B(1) 1.71 1.8 1.89 V VEEAM18, VEEBM18(1) -1.89 -1.8 -1.71 V VDDCLK18, VDDSYS18, VDDR18(2) 1.71 1.8 1.89 V VDDLB, VDDLA, VDDCLK10(2) 0.95 1 1.05 V VDDIO(3) 1.71 1.8 1.89 V VQPS(3) 0 0 1.89 V VDDDIG, VDDEB, VDDEA, VDDT(3) 0.95 1 1.05 V VCMI Input common mode voltage CLK+, CLK–(2) (4) 0.4 V VCMI Input common mode voltage SYSREF+, SYSREF–(2) (4) 0 0.4 1.0 V VID Input differential peak-to-peak voltage SYSREF+ to SYSREF– 800 1000 2000 mVPP-DIFF CLK+ to CLK–, fCLK < 5GHz 800 1000 1400 mVPP-DIFF CLK+ to CLK–, 5GHz < fCLK < 7.5GHz 800 1000 1800 mVPP-DIFF CLK+ to CLK–, fCLK > 7.5GHz 800 1000 2000 mVPP-DIFF DCMIN CLK+/– duty cycle minimum 45 % DCMAX CLK+/– duty cycle maximum 55 % TA Operating free-air temperature -55 125 °C TJ Operating Junction Temperature 150(5) °C (1) Measured to AGND. (2) Measured to VSSCLK. (3) Measured to DGND. (4) SYSREF+/- termination has two options. In option 1 the inputs are weakly self-biased to the optimal common mode voltage, which is appropriate for AC coupling. In option 2, each input terminal is connected through 50Ohms to ground, which is appropriate to level shift from a higher common mode voltage. (5) Die is designed for Tj = 150 °C operation and for device and die metallization degradation up to 150,000 POH continuous operation at Tj = 122 °C. Prolonged use above a junction temperature of Tj =105 °C may, however, increase the package failure-in-time (FIT) rate.

6.4 Thermal Information

THERMAL METRIC(1) 17mm × 17mm FC-BGA UNIT

256 PINS

RθJA Junction-to-ambient thermal resistance 15.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 0.9 °C/W RθJB Junction-to-board thermal resistance 4.2 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 4.2 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.5 Electrical Characteristics - DC Specifications

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, 2 channels, FINPUT = 2.56 3GSPS, JMODE 1 , 8b/10b encoding, Interpolation, FCLK = 10.24 2GHz, FOUT = 2997MHz, NRZ mode, IFSSWITCH = 20.5mA, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC ACCURACY BITS DAC core resolution 16 bits DNL Differential nonlinearity ±2.2 LSB INL Integral nonlinearity ±9 LSB DAC ANALOG OUTPUT (DACOUTA+, DACOUTA–, DACOUTB+, DACOUTB–) IFS_SWITCH Switched full scale output current 3.6kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B= 0xF and FINE_CUR_A / FINE_CUR_B = default, CUR_2X_EN = 1 mA 3.6kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B= 0xF and FINE_CUR_A / FINE_CUR_B = default 20.5 3.6kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0x0 and FINE_CUR_A / FINE_CUR_B = default, CUR_2X_EN = 1 3.6kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0x0 and FINE_CUR_A / FINE_CUR_B = default 5.5 ISTATIC Static output current per pin 3.6kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0xF and FINE_CUR_A / FINE_CUR_B = default 4.8 mA IFSDRIFT Full scale output current temperature drift 3.6kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0xF and FINE_CUR_A / FINE_CUR_B = default -8.6 uA/℃ -0.3 PPM/℃ IFSERROR Full scale current error 3.6kΩ resistor from RBIAS+ to RBIAS-, COARSE_CUR_A / COARSE_CUR_B = 0xF and FINE_CUR_A / FINE_CUR_B = default ±0.1 % IMIDOFFERR Mid Code Offset Error Mid Code offset ±0.02 %FSR VCOMP Output compliance voltage range Measured from DACOUTA+, DACOUTA–, DACOUTB+ or DACOUTB– to AGND VDDA18 A/B - 0.5 VDDA18 A/B + 0.5 V COUT Output capacitance Single-ended capacitance to ground 0.25 pF RTERM Output differential termination resistance 102 Ω RTERMDRIFT Output differential termination resistance temperature coeff –9.6 mΩ/℃ –42 PPM/℃ CLOCK AND SYSREF INPUTS (CLK+, CLK-, SYSREF+, SYSREF-) RT Internal differential termination resistance 100 Ω CIN Internal differential input capacitance 0.5 pF DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.5 Electrical Characteristics - DC Specifications (continued)

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, 2 channels, FINPUT = 2.56 3GSPS, JMODE 1 , 8b/10b encoding, Interpolation, FCLK = 10.24 2GHz, FOUT = 2997MHz, NRZ mode, IFSSWITCH = 20.5mA, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE VOLTAGE VREF Reference output voltage 0.9 V IREF Maximum reference output current sourcing capability for EXTREF ball with internal reference 100 nA JESD204C SERDES INTERFACE ([15:0]SRX+/- ) VSRDIFF SerDes Receiver Input Amplitude 50 1200 mVppdiff VSRCOM SerDes Input Common Mode Internal AC coupled ZSRdiff SerDes Internal Differential Termination 100 Ω CMOS INTERFACE (ALARM, SCLK, SCS, SDI, SDO, RESET, FRDI[0:3], FRCLK, FRCS, SYNC, TXENABLE[0:1]) IIH High level input current (with pulldowns) SCANEN(1) 200 uA IIH High level input current (without pulldowns) SCS, RESET, FRCS, TXEN[0:1], FRDI[0:3], FRCLK, SDI, SCLK(1) 2 uA IIL Low level input current (with pullups) SCS, RESET, FRCS, TXEN0:1 –200 uA IIL Low level input current (without pullups) SCANEN, FRDI[0:3], FRCLK, SDI, SCLK(1) –3 uA CI Input capacitance Input capacitance 3 pF VIH High level input voltage SCLK, SCS, SDI, RESET, FRDI[0:3], FRCLK, FRCS, SCANEN, TXEN[0:1] 0.7 x VDDIO1 V VIL Low level input voltage 0.3 x VDDIO1 V VOH High level output voltage ALARM, SDO, SYNC, ILOAD = –400 uA 1.55 V VOL Low level output voltage ALARM, SDO, SYNC, ILOAD = 400 uA 0.2 V TEMPERATURE SENSOR Res Resolution 1 ℃/LSB Range Digital Range -50 150 ℃ TERROR Temperature Error TA = 25℃, device powered down except for temperature sensor and SPI ±5 ℃ (1) With no IO supply voltage offset in connecting device. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.6 Electrical Characteristics - AC Specifications

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6.6 Electrical Characteristics - AC Specifications (continued)

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10.24GSPS, DUAL or SINGLE CHANNEL MODE, JMODE 1, 2x Int, NRZ MODE POUT Output power into 100Ω load, IFS_SWITCH = 20.5mA(2) fOUT = 97MHz 1.1 dBm fOUT = 997MHz 0.7 dBm fOUT = 1997MHz –0.4 dBm fOUT = 2997MHz –0.8 dBm fOUT = 3997MHz –1.8 dBm Output power into 100Ω load, IFS_SWITCH = 41mA(2) fOUT = 97MHz 7.0 dBm fOUT = 997MHz 6.8 dBm fOUT = 1997MHz 5.5 dBm fOUT = 2997MHz 5.1 dBm fOUT = 3997MHz 3.1 dBm SFDR Spurious free dynamic range (SFDR) across 0 - FDAC/2, IFS_SWITCH = 20.5mA fOUT = 97MHz 85 dBc fOUT = 997MHz 67 dBc fOUT = 1997MHz 62 dBc fOUT = 2997MHz 61 dBc fOUT = 3997MHz 62 dBc Spurious free dynamic range (SFDR) across 0 - FDAC/2, IFS_SWITCH = 41mA fOUT = 97MHz 76 dBc fOUT = 997MHz 52 dBc fOUT = 1997MHz 49 dBc fOUT = 2997MHz 50 dBc fOUT = 3997MHz 51 dBc HD2 Second harmonic (HD2), 0 - FDAC/ 2, IFS_SWITCH = 20.5mA fOUT = 97MHz –85 dBc fOUT = 997MHz –79 dBc fOUT = 1997MHz –66 dBc fOUT = 2997MHz –63 dBc fOUT = 3997MHz –62 dBc Second harmonic (HD2), 0 - FDAC/ 2, IFS_SWITCH = 41mA fOUT = 97MHz –76 dBc fOUT = 997MHz –74 dBc fOUT = 1997MHz –62 dBc fOUT = 2997MHz –65 dBc fOUT = 3997MHz –59 dBc HD3 Third harmonic (HD3), 0 - FDAC/ 2, IFS_SWITCH = 20.5mA fOUT = 97MHz –94 dBc fOUT = 997MHz –68 dBc fOUT = 1997MHz –64 dBc fOUT = 2997MHz –63 dBc fOUT = 3997MHz –75 dBc Third harmonic (HD3), 0 - FDAC/ 2, IFS_SWITCH = 41mA fOUT = 97MHz –76 dBc fOUT = 997MHz –56 dBc fOUT = 1997MHz –54 dBc fOUT = 2997MHz –48 dBc fOUT = 3997MHz –51 dBc www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SFDRNONHD23 non-HD2/3 SFDR, IFS_SWITCH = 20.5mA fOUT = 97MHz 88 dBc fOUT = 997MHz 84 dBc fOUT = 1997MHz 86 dBc fOUT = 2997MHz 85 dBc fOUT = 3997MHz 83 dBc non-HD2/3 SFDR, IFS_SWITCH = 41mA fOUT = 97MHz 90 dBc fOUT = 997MHz 73 dBc fOUT = 1997MHz 78 dBc fOUT = 2997MHz 78 dBc fOUT = 3997MHz 65 dBc IMD3 Third-order two tone intermodulation distortion, IFS_SWITCH = 20.5mA fOUT = 97 +/- 10MHz, -7dBFS/tone –91 dBc fOUT = 997 +/- 10MHz, -7dBFS/tone –77 dBc fOUT = 1997 +/- 10MHz, -7dBFS/tone –75 dBc fOUT = 2997 +/- 10MHz, -7dBFS/tone –64 dBc fOUT = 3997 +/- 10MHz, -7dBFS/tone –64 dBc Third-order two tone intermodulation distortion, IFS_SWITCH = 41mA fOUT = 97 +/- 10MHz, -7dBFS/tone –86 dBc fOUT = 997 +/- 10MHz, -7dBFS/tone –62 dBc fOUT = 1997 +/- 10MHz, -7dBFS/tone –59 dBc fOUT = 1997 +/- 10MHz, -6dBFS/tone, JMODE 3, 8x Int –55 dBc fOUT = 2997 +/- 10MHz, -7dBFS/tone –53 dBc fOUT = 3997 +/- 10MHz, -7dBFS/tone –54 dBc NSD Noise spectral density, large signal, sinusoidal output, IFS_SWITCH = 20.5mA(3) fOUT = 97MHz, 70MHz offset from fOUT –158 dBc/Hz fOUT = 997MHz, 70MHz offset from fOUT –158 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT –154 dBc/Hz fOUT = 2997MHz, 70MHz offset from fOUT –150 dBc/Hz fOUT = 3997MHz, 70MHz offset from fOUT –148 dBc/Hz NSD Noise spectral density, large signal, sinusoidal output, IFS_SWITCH = 41mA(3) fOUT = 97MHz, 70MHz offset from fOUT –159 dBc/Hz fOUT = 997MHz, 70MHz offset from fOUT –158 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT –154 dBc/Hz fOUT = 2997MHz, 70MHz offset from fOUT –151 dBc/Hz fOUT = 3997MHz, 70MHz offset from fOUT –149 dBc/Hz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSD Noise spectral density, small signal, sinusoidal output, IFS_SWITCH = 20.5mA(3) AOUT = -20dBFS, fOUT = 97MHz, 70MHz offset from fOUT –160 dBFS/Hz AOUT = -20dBFS, fOUT = 997MHz, 70MHz offset from fOUT –158 dBFS/Hz AOUT = -20dBFS, fOUT = 1997MHz, 70MHz offset from fOUT –155 dBFS/Hz AOUT = -20dBFS, fOUT = 2997MHz, 70MHz offset from fOUT –152 dBFS/Hz AOUT = -20dBFS, fOUT = 3997MHz, 70MHz offset from fOUT –152 dBFS/Hz NSD Noise spectral density, small signal, sinusoidal output, IFS_SWITCH = 41mA(3) AOUT = -20dBFS, fOUT = 97MHz, 70MHz offset from fOUT –161 dBFS/Hz AOUT = -20dBFS, fOUT = 997MHz, 70MHz offset from fOUT –159 dBFS/Hz AOUT = -20dBFS, fOUT = 1997MHz, 70MHz offset from fOUT –158 dBFS/Hz AOUT = -20dBFS, fOUT = 2997MHz, 70MHz offset from fOUT –154 dBFS/Hz AOUT = -20dBFS, fOUT = 3997MHz, 70MHz offset from fOUT –152 dBFS/Hz NPR Noise Power Ratio, peak Signal spanning 80% of Nyquist zone, notch at center of Nyquist zone of 5% of Nyquist zone, 12dB PAR, IFS_SWITCH = 20.5mA 47.4 dBc Signal spanning 80% of Nyquist zone, notch at center of Nyquist zone of 5% of Nyquist zone, IFS_SWITCH = 41mA 48 dBc ENOB Effective number of bits Calculated from peak NPR, IFS_SWITCH = 20.5mA 9.6 bits Calculated from peak NPR, IFS_SWITCH = 41mA 9.7 bits PN Additive DAC phase noise, external clock contribution subtracted out, NRZ mode, DEM and Dither off fCLK = 10.24GHz, fOUT = 997MHz, 100Hz offset –122 dBc/Hz fCLK = 10.24GHz, fOUT = 997MHz, 1KHz offset –132 dBc/Hz fCLK = 10.24GHz, fOUT = 997MHz, 10kHz offset –143 dBc/Hz fCLK = 10.24GHz, fOUT = 997MHz, 100kHz offset –153 dBc/Hz fCLK = 10.24GHz, fOUT = 997MHz, 1MHz offset –161 dBc/Hz fCLK = 10.24GHz, fOUT = 997MHz, 10MHz offset –166 dBc/Hz fCLK = 10.24GHz, fOUT = 997MHz, 100MHz offset –168 dBc/Hz www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10.24GSPS, DUAL or SINGLE CHANNEL MODE, JMODE 1, 2x Int, RTZ MODE POUT Output power with 2:1 balun and 50Ω load fOUT = 97MHz –4.5 dBm fOUT = 997MHz –4.9 dBm fOUT = 1997MHz –5.7 dBm fOUT = 1997MHz, IFS_SWITCH = 41mA 0.3 dBm fOUT = 2997MHz –5.5 dBm fOUT = 3997MHz –6.7 dBm fOUT = 5997MHz –7.1 dBm fOUT = 6997MHz –5.6 dBm fOUT = 7997MHz –9.1 dBm fOUT = 8997MHz –11.0 dBm SFDR Spurious free dynamic range (SFDR) across 0 - FDAC/2 fOUT = 97MHz 60 dBc fOUT = 997MHz 61 dBc fOUT = 1997MHz 62 dBc fOUT = 1997MHz, IFS_SWITCH = 41mA 50 dBc fOUT = 2997MHz 61 dBc fOUT = 3997MHz 61 dBc Spurious free dynamic range (SFDR) across FDAC/2 - FDAC fOUT = 5997MHz 64 dBc fOUT = 6997MHz 59 dBc fOUT = 7997MHz 53 dBc fOUT = 8997MHz 53 dBc HD2 2nd Harmonic Distortion in 0 - FDAC/2 fOUT = 97MHz –60 dBc fOUT = 997MHz –61 dBc fOUT = 1997MHz –62 dBc fOUT = 1997MHz, IFS_SWITCH = 41mA –62 dBc fOUT = 2997MHz –61 dBc fOUT = 3997MHz –61 dBc 2nd Harmonic Distortion in FDAC/2 - FDAC fOUT = 5997MHz –67 dBc fOUT = 6997MHz –59 dBc fOUT = 7997MHz –53 dBc fOUT = 8997MHz –53 dBc HD3 3rd Harmonic Distortion in 0 - FDAC/2 fOUT = 97MHz –80 dBc fOUT = 997MHz –73 dBc fOUT = 1997MHz –66 dBc fOUT = 1997MHz, IFS_SWITCH = 41mA –50 dBc fOUT = 2997MHz –63 dBc fOUT = 3997MHz –66 dBc 3rd Harmonic Distortion in FDAC/2 - FDAC fOUT = 5997MHz –64 dBc fOUT = 6997MHz –68 dBc fOUT = 7997MHz –63 dBc fOUT = 8997MHz –57 dBc www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SFDRNONHD23 non-HD2/3 SFDR 0 - FDAC/2 fOUT = 97MHz 85 dBc fOUT = 997MHz 80 dBc fOUT = 1997MHz 81 dBc fOUT = 1997MHz, IFS_SWITCH = 41mA 74 dBc fOUT = 2997MHz 80 dBc fOUT = 3997MHz 78 dBc non-HD2/3 SFDR FDAC/2 - FDAC fOUT = 5997MHz 77 dBc fOUT = 6997MHz 78 dBc fOUT = 7997MHz 75 dBc fOUT = 8997MHz 73 dBc IMD3 Third-order two tone intermodulation distortion fOUT = 97 +/- 10MHz, -7dBFS/tone –85 dBc fOUT = 997 +/- 10MHz, -7dBFS/tone –77 dBc fOUT = 1997 +/- 10MHz, -7dBFS/tone –71 dBc fOUT = 2997 +/- 10MHz, -7dBFS/tone –67 dBc fOUT = 3997 +/- 10MHz, -7dBFS/tone –66 dBc fOUT = 5997 +/- 10MHz, -7dBFS/tone –61 dBc fOUT = 6997 +/- 10MHz, -7dBFS/tone –58 dBc fOUT = 7997 +/- 10MHz, -7dBFS/tone –61 dBc fOUT = 8997 +/- 10MHz, -7dBFS/tone –69 dBc NSD Noise spectral density, large signal, sinusoidal output(3) fOUT = 97MHz, 70MHz offset from fOUT –160 dBc/Hz fOUT = 997MHz, 70MHz offset from fOUT –148 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT –147 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT, IFS_SWITCH = 41mA –148 dBc/Hz fOUT = 2997MHz, 70MHz offset from fOUT –145 dBc/Hz fOUT = 3997MHz, 70MHz offset from fOUT –145 dBc/Hz fOUT = 5997MHz, 70MHz offset from fOUT –142 dBc/Hz fOUT = 6997MHz, 70MHz offset from fOUT –143 dBc/Hz fOUT = 7997MHz, 70MHz offset from fOUT –142 dBc/Hz fOUT = 8997MHz, 70MHz offset from fOUT –140 dBc/Hz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 10.24GSPS, DUAL or SINGLE CHANNEL MODE, JMODE 1, 2x Int, RF MODE POUT Output power with 2:1 balun and 50Ω load fOUT = 5997MHz –3.3 dBm fOUT = 6997MHz –0.9 dBm fOUT = 7997MHz, IFS_SWITCH = 41mA 1.6 dBm fOUT = 7997MHz –3.9 dBm fOUT = 8997MHz –5.1 dBm SFDR Spurious free dynamic range (SFDR) across FDAC/2 - FDAC fOUT = 5997MHz 56 dBc fOUT = 6997MHz 51 dBc fOUT = 7997MHz, IFS_SWITCH = 41mA 41 dBc fOUT = 7997MHz 56 dBc fOUT = 8997MHz 56 dBc HD2 2nd Harmonic Distortion in FDAC/2 - FDAC fOUT = 5997MHz –56 dBc fOUT = 6997MHz –51 dBc fOUT = 7997MHz, IFS_SWITCH = 41mA –57 dBc fOUT = 7997MHz –57 dBc fOUT = 8997MHz –61 dBc HD3 3rd Harmonic Distortion in FDAC/2 - FDAC fOUT = 5997MHz –59 dBc fOUT = 6997MHz –60 dBc fOUT = 7997MHz, IFS_SWITCH = 41mA –42 dBc fOUT = 7997MHz –64 dBc fOUT = 8997MHz –57 dBc SFDRNONHD23 non-HD2/3 SFDR across FDAC/2 - FDAC fOUT = 5997MHz 78 dBc fOUT = 6997MHz 76 dBc fOUT = 7997MHz, IFS_SWITCH = 41mA 70 dBc fOUT = 7997MHz 81 dBc fOUT = 8997MHz 69 dBc IMD3 Third-order two tone intermodulation distortion fOUT = 5997 +/- 10MHz, -7dBFS/tone –59 dBc fOUT = 6997 +/- 10MHz, -7dBFS/tone –56 dBc fOUT = 7997 +/- 10MHz, -7dBFS/ tone, IFS_SWITCH = 41mA –44 dBc fOUT = 7997 +/- 10MHz, -7dBFS/tone –63 dBc fOUT = 8997 +/- 10MHz, -7dBFS/tone –64 dBc NSD Noise spectral density, large signal, sinusoidal output(3) fOUT = 5997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 6997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 7997MHz, 70MHz offset from fOUT, IFS_SWITCH = 41mA –146 dBc/Hz fOUT = 7997MHz, 70MHz offset from fOUT –145 dBc/Hz fOUT = 8997MHz, 70MHz offset from fOUT –144 dBc/Hz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 20.48GSPS, SINGLE CHANNEL MODE, 10.24GSPS INPUT, JMODE 0, 2x DES INTERPOLATION MODE POUT Output power with 2:1 balun and 50Ω load, IFS_SWITCH = 20.5mA fOUT = 97MHz 1.0 dBm fOUT = 997MHz 0.8 dBm fOUT = 1997MHz 0.6 dBm fOUT = 2997MHz 0.2 dBm fOUT = 3997MHz –1.9 dBm fOUT = 5997MHz -1.1 dBm fOUT = 6997MHz 0.2 dBm fOUT = 7997MHz –2.8 dBm fOUT = 8997MHz –5 dBm POUT Output power with 2:1 balun and 50Ω load, IFS_SWITCH = 41mA fOUT = 97MHz 7.0 dBm fOUT = 997MHz 6.8 dBm fOUT = 1997MHz 6.5 dBm fOUT = 2997MHz 6.0 dBm fOUT = 3997MHz 4.0 dBm fOUT = 5997MHz 4.7 dBm fOUT = 6997MHz 5.7 dBm fOUT = 7997MHz 2.6 dBm fOUT = 8997MHz 0.4 dBm SFDR Spurious free dynamic range (SFDR) across 0 - FDAC/4, IFS_SWITCH = 20.5mA fOUT = 97MHz 84 dBc fOUT = 997MHz 67 dBc fOUT = 1997MHz 71 dBc fOUT = 2997MHz(4) 55 77 dBc fOUT = 3997MHz 77 dBc Spurious free dynamic range (SFDR) across FDAC/4 - FDAC/2, IFS_SWITCH = 20.5mA fOUT = 5997MHz 55 dBc fOUT = 6997MHz 48 dBc fOUT = 7997MHz 65 dBc fOUT = 8997MHz 55 dBc Spurious free dynamic range (SFDR) across 0 - FDAC/4, IFS_SWITCH = 41mA fOUT = 97MHz 76 dBc fOUT = 997MHz 52 dBc fOUT = 1997MHz 66 dBc fOUT = 2997MHz 75 dBc fOUT = 3997MHz 70 dBc Spurious free dynamic range (SFDR) across FDAC/4 - FDAC/2, IFS_SWITCH = 41mA fOUT = 5997MHz 60 dBc fOUT = 6997MHz 50 dBc fOUT = 7997MHz 65 dBc fOUT = 8997MHz 40 dBc DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IMGDES FDAC/2 - FOUT DES Image, IFS_SWITCH = 20.5mA fOUT = 97MHz –75 dBc fOUT = 997MHz –66 dBc fOUT = 1997MHz –57 dBc fOUT = 2997MHz –55 dBc fOUT = 3997MHz –45 dBc fOUT = 5997MHz –33 dBc fOUT = 6997MHz –44 dBc fOUT = 7997MHz –38 dBc fOUT = 8997MHz –33 dBc FDAC/2 - FOUT DES Image, IFS_SWITCH = 41mA fOUT = 97MHz –92 dBc fOUT = 997MHz –72 dBc fOUT = 1997MHz –65 dBc fOUT = 2997MHz –59 dBc fOUT = 3997MHz –49 dBc fOUT = 5997MHz –34 dBc fOUT = 6997MHz –46 dBc fOUT = 7997MHz –38 dBc fOUT = 8997MHz –32 dBc HD2 HD2 across 0 - FDAC/4, IFS_SWITCH = 20.5mA fOUT = 97MHz –84 dBc fOUT = 997MHz –75 dBc fOUT = 1997MHz –73 dBc fOUT = 2997MHz –82 –55 dBc fOUT = 3997MHz –77 dBc HD2 across FDAC/4 - FDAC/2, IFS_SWITCH = 20.5mA fOUT = 5997MHz –55 dBc fOUT = 6997MHz –48 dBc fOUT = 7997MHz –70 dBc fOUT = 8997MHz –70 dBc HD2 across 0 - FDAC/4, IFS_SWITCH = 41mA fOUT = 97MHz –78 dBc fOUT = 997MHz –72 dBc fOUT = 1997MHz –66 dBc fOUT = 2997MHz –84 dBc fOUT = 3997MHz –80 dBc HD2 across FDAC/4 - FDAC/2, IFS_SWITCH = 41mA fOUT = 5997MHz –60 dBc fOUT = 6997MHz –50 dBc fOUT = 7997MHz –65 dBc fOUT = 8997MHz –65 dBc www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HD3 HD3 across 0 - FDAC/4, IFS_SWITCH = 20.5mA fOUT = 97MHz –93 dBc fOUT = 997MHz –67 dBc fOUT = 1997MHz –77 dBc fOUT = 2997MHz –82 –70 dBc fOUT = 3997MHz –81 dBc HD3 across FDAC/4 - FDAC/2, IFS_SWITCH = 20.5mA fOUT = 5997MHz –76 dBc fOUT = 6997MHz –75 dBc fOUT = 7997MHz –65 dBc fOUT = 8997MHz –55 dBc HD3 across 0 - FDAC/4, IFS_SWITCH = 41mA fOUT = 97MHz –76 dBc fOUT = 997MHz –52 dBc fOUT = 1997MHz –72 dBc fOUT = 2997MHz –80 dBc fOUT = 3997MHz –75 dBc HD3 across FDAC/4 - FDAC/2, IFS_SWITCH = 41mA fOUT = 5997MHz –65 dBc fOUT = 6997MHz –74 dBc fOUT = 7997MHz –72 dBc fOUT = 8997MHz –40 dBc SFDRNONHD23 non-HD2/3 SFDR in 0 - FDAC/4, IFS_SWITCH = 20.5mA fOUT = 97MHz 89 dBc fOUT = 997MHz 84 dBc fOUT = 1997MHz 83 dBc fOUT = 2997MHz 78 dBc fOUT = 3997MHz 80 dBc non-HD2/3 SFDR in FDAC/4 - FDAC/2, IFS_SWITCH = 20.5mA fOUT = 5997MHz 82 dBc fOUT = 6997MHz 80 dBc fOUT = 7997MHz 82 dBc fOUT = 8997MHz 70 dBc non-HD2/3 SFDR in 0 - FDAC/4, IFS_SWITCH = 41mA fOUT = 97MHz 89 dBc fOUT = 997MHz 74 dBc fOUT = 1997MHz 80 dBc fOUT = 2997MHz 77 dBc fOUT = 3997MHz 70 dBc non-HD2/3 SFDR in FDAC/4 - FDAC/2, IFS_SWITCH = 41mA fOUT = 5997MHz 75 dBc fOUT = 6997MHz 65 dBc fOUT = 7997MHz 76 dBc fOUT = 8997MHz 73 dBc DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IMD3 Third-order two tone intermodulation distortion, IFS_SWITCH = 20.5mA fOUT = 97 +/- 10MHz, -7dBFS/tone –91 dBc fOUT = 997 +/- 10MHz, -7dBFS/tone –76 dBc fOUT = 1997 +/- 10MHz, -7dBFS/tone –75 dBc fOUT = 2997 +/- 10MHz, -7dBFS/tone –69 dBc fOUT = 3997 +/- 10MHz, -7dBFS/tone –70 dBc fOUT = 5997 +/- 10MHz, -7dBFS/tone –63 dBc fOUT = 6997 +/- 10MHz, -7dBFS/tone –56 dBc fOUT = 7997 +/- 10MHz, -7dBFS/tone –62 dBc fOUT = 8997 +/- 10MHz, -7dBFS/tone –60 dBc Third-order two tone intermodulation distortion, IFS_SWITCH = 41mA fOUT = 97 +/- 10MHz, -7dBFS/tone –85 dBc fOUT = 997 +/- 10MHz, -7dBFS/tone –63 dBc fOUT = 1997 +/- 10MHz, -7dBFS/tone –53 dBc fOUT = 2997 +/- 10MHz, -7dBFS/tone –52 dBc fOUT = 3997 +/- 10MHz, -7dBFS/tone –57 dBc fOUT = 5997 +/- 10MHz, -7dBFS/tone –51 dBc fOUT = 6997 +/- 10MHz, -7dBFS/tone –38 dBc fOUT = 7997 +/- 10MHz, -7dBFS/tone –42 dBc fOUT = 8997 +/- 10MHz, -7dBFS/tone –46 dBc NSD Noise spectral density, large signal, sinusoidal output, IFS_SWITCH = 20.5mA(3) fOUT = 97MHz, 70MHz offset from fOUT –158 dBc/Hz fOUT = 997MHz, 70MHz offset from fOUT –155 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT –152 dBc/Hz fOUT = 2997MHz, 70MHz offset from fOUT –150 dBc/Hz fOUT = 3997MHz, 70MHz offset from fOUT –149 dBc/Hz fOUT = 5997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 6997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 7997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 8997MHz, 70MHz offset from fOUT –144 dBc/Hz www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSD Noise spectral density, large signal, sinusoidal output, IFS_SWITCH = 4 1mA(3) fOUT = 97MHz, 70MHz offset from fOUT –158 dBc/Hz fOUT = 997MHz, 70MHz offset from fOUT –156 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT –154 dBc/Hz fOUT = 2997MHz, 70MHz offset from fOUT –151 dBc/Hz fOUT = 3997MHz, 70MHz offset from fOUT –150 dBc/Hz fOUT = 5997MHz, 70MHz offset from fOUT –147 dBc/Hz fOUT = 6997MHz, 70MHz offset from fOUT –147 dBc/Hz fOUT = 7997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 8997MHz, 70MHz offset from fOUT –144 dBc/Hz NSD Noise spectral density, small signal, sinusoidal output, IFS_SWITCH = 20.5mA(3) AOUT = -20dBFS, fOUT = 97MHz, 70MHz offset from fOUT –160 dBFS/Hz AOUT = -20dBFS, fOUT = 997MHz, 70MHz offset from fOUT –156 dBFS/Hz AOUT = -20dBFS, fOUT = 1997MHz, 70MHz offset from fOUT –154 dBFS/Hz AOUT = -20dBFS, fOUT = 2997MHz, 70MHz offset from fOUT –152 dBFS/Hz AOUT = -20dBFS, fOUT = 3997MHz, 70MHz offset from fOUT –152 dBFS/Hz AOUT = -20dBFS, fOUT = 5997MHz, 70MHz offset from fOUT –149 dBFS/Hz AOUT = -20dBFS, fOUT = 6997MHz, 70MHz offset from fOUT –149 dBFS/Hz AOUT = -20dBFS, fOUT = 7997MHz, 70MHz offset from fOUT –148 dBFS/Hz AOUT = -20dBFS, fOUT = 8997MHz, 70MHz offset from fOUT –149 dBFS/Hz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NSD Noise spectral density, small signal, sinusoidal output, IFS_SWITCH = 41mA(3) AOUT = -20dBFS, fOUT = 97MHz, 70MHz offset from fOUT –161 dBFS/Hz AOUT = -20dBFS, fOUT = 997MHz, 70MHz offset from fOUT –158 dBFS/Hz AOUT = -20dBFS, fOUT = 1997MHz, 70MHz offset from fOUT –156 dBFS/Hz AOUT = -20dBFS, fOUT = 2997MHz, 70MHz offset from fOUT –154 dBFS/Hz AOUT = -20dBFS, fOUT = 3997MHz, 70MHz offset from fOUT –153 dBFS/Hz AOUT = -20dBFS, fOUT = 5997MHz, 70MHz offset from fOUT –151 dBFS/Hz AOUT = -20dBFS, fOUT = 6997MHz, 70MHz offset from fOUT –152 dBFS/Hz AOUT = -20dBFS, fOUT = 7997MHz, 70MHz offset from fOUT –152 dBFS/Hz AOUT = -20dBFS, fOUT = 8997MHz, 70MHz offset from fOUT –151 dBFS/Hz NPR Noise power ratio, peak Signal spanning 80% of 2nd Nyquist zone, notch at center of Nyquist zone of 5% of Nyquist zone, 12dB PAR, IFS_SWITCH = 20.5mA, DES2XL (1st Nyquist) 47 dBc Signal spanning 80% of 2nd Nyquist zone, notch at center of Nyquist zone of 5% of Nyquist zone, 12dB PAR, IFS_SWITCH = 41mA, DES2XL (1st Nyquist) 49 dBc Signal spanning 80% of 2nd Nyquist zone, notch at center of Nyquist zone of 5% of Nyquist zone, 12dB PAR, IFS_SWITCH = 20.5mA, DES2XH (2nd Nyquist) 43 dBc Signal spanning 80% of 2nd Nyquist zone, notch at center of Nyquist zone of 5% of Nyquist zone, 12dB PAR, IFS_SWITCH = 41mA, DES2XH (2nd Nyquist) 45 dBc ENOB Effective number of bits Calculated from peak NPR, IFS_SWITCH = 20.5mA, DES2XL (1st Nyquist) 9.6 bits Calculated from peak NPR, IFS_SWITCH = 41mA, DES2XL (1st Nyquist) 9.8 bits Calculated from peak NPR, IFS_SWITCH = 20.5mA, DES2XH (2nd Nyquist) 8.9 bits Calculated from peak NPR, IFS_SWITCH = 41mA, DES2XH (2nd Nyquist) 9.2 bits www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 15.6GSPS, SINGLE CHANNEL MODE, 12-bit, JMODE 8, 66b/64b, DES MODE POUT Output power with 2:1 balun and 50Ω load fOUT = 97MHz 1 dBm fOUT = 997MHz 0.8 dBm fOUT = 1997MHz 0.5 dBm fOUT = 2997MHz 0 dBm fOUT = 3997MHz –2.4 dBm fOUT = 5997MHz –2.1 dBm fOUT = 6997MHz –1.3 dBm SFDR Spurious free dynamic range (SFDR) across 0 - FDAC/4 fOUT = 97MHz 83 dBc fOUT = 997MHz 69 dBc fOUT = 1997MHz 80 dBc fOUT = 2997MHz 78 dBc Spurious free dynamic range (SFDR) across FDAC/4 - FDAC/2 fOUT = 3997MHz 60 dBc fOUT = 5997MHz 80 dBc fOUT = 6997MHz 55 dBc IMGDES FDAC/2 - FOUT DES Image fOUT = 97MHz –63 dBc fOUT = 997MHz –55 dBc fOUT = 1997MHz –52 dBc fOUT = 2997MHz –48 dBc fOUT = 3997MHz –42 dBc fOUT = 5997MHz –38 dBc fOUT = 6997MHz –37 dBc HD2 2nd Harmonic Distortion in 0 - FDAC/2 fOUT = 97MHz –83 dBc fOUT = 997MHz –76 dBc fOUT = 1997MHz –70 dBc fOUT = 2997MHz –62 dBc fOUT = 3997MHz –62 dBc fOUT = 5997MHz –50 dBc fOUT = 6997MHz –48 dBc SFDRNONHD23 non-HD2/3 SFDR, excluding DES spur fOUT = 97MHz 87 dBc fOUT = 997MHz 76 dBc fOUT = 1997MHz 80 dBc fOUT = 2997MHz 78 dBc fOUT = 3997MHz 73 dBc fOUT = 5997MHz 80 dBc fOUT = 6997MHz 71 dBc www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HD3 3rd Harmonic Distortion in 0 - FDAC/2 fOUT = 97MHz –94 dBc fOUT = 997MHz –70 dBc fOUT = 1997MHz –63 dBc fOUT = 2997MHz –79 dBc fOUT = 3997MHz –65 dBc fOUT = 5997MHz –65 dBc fOUT = 6997MHz –55 dBc IMD3 Third-order two tone intermodulation distortion fOUT = 97 +/- 10MHz, -7dBFS/tone –91 dBc fOUT = 997 +/- 10MHz, -7dBFS/tone –81 dBc fOUT = 1997 +/- 10MHz, -7dBFS/tone –72 dBc fOUT = 2997 +/- 10MHz, -7dBFS/tone –66 dBc fOUT = 3997 +/- 10MHz, -7dBFS/tone –69 dBc fOUT = 5997 +/- 10MHz, -7dBFS/tone –70 dBc fOUT = 6997 +/- 10MHz, -7dBFS/tone –56 dBc NSD Noise spectral density, large signal, sinusoidal output(3) fOUT = 97MHz, 70MHz offset from fOUT –157 dBc/Hz fOUT = 997MHz, 70MHz offset from fOUT –155 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT –152 dBc/Hz fOUT = 2997MHz, 70MHz offset from fOUT –150 dBc/Hz fOUT = 3997MHz, 70MHz offset from fOUT –149 dBc/Hz fOUT = 5997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 6997MHz, 70MHz offset from fOUT –145 dBc/Hz NSD Noise spectral density, small signal, sinusoidal output(3) AOUT = -20dBFS, fOUT = 97MHz, 70MHz offset from fOUT –158 dBFS/Hz AOUT = -20dBFS, fOUT = 997MHz, 70MHz offset from fOUT –156 dBFS/Hz AOUT = -20dBFS, fOUT = 1997MHz, 70MHz offset from fOUT –153 dBFS/Hz AOUT = -20dBFS, fOUT = 2997MHz, 70MHz offset from fOUT –151 dBFS/Hz AOUT = -20dBFS, fOUT = 3997MHz, 70MHz offset from fOUT –150 dBFS/Hz AOUT = -20dBFS, fOUT = 5997MHz, 70MHz offset from fOUT –148 dBFS/Hz AOUT = -20dBFS, fOUT = 6997MHz, 70MHz offset from fOUT –149 dBFS/Hz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, FCLK = 10.24GHz, 8b/10b encoding, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, SE DEM and Dither (DEM_ADJ = 1 below 750MHz and DEM_ADJ = 0 above 750MHz), 8b/10b encoding, unless otherwise noted. FDAC = FCLK in NRZ, RTZ and RF modes and FDAC = 2×FCLK in DES1X and DES2XL/H modes. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HD3 3rd Harmonic Distortion in 0 - FDAC/2 fOUT = 97MHz –73 dBc fOUT = 997MHz –72 dBc fOUT = 1997MHz –63 dBc fOUT = 2997MHz –61 dBc fOUT = 3997MHz –60 dBc fOUT = 5997MHz –63 dBc fOUT = 6997MHz –57 dBc fOUT = 7997MHz –55 dBc fOUT = 8997MHz –53 dBc IMD3 Third-order two tone intermodulation distortion fOUT = 97 +/- 10MHz, -7dBFS/tone –90 dBc fOUT = 997 +/- 10MHz, -7dBFS/tone –77 dBc fOUT = 1997 +/- 10MHz, -7dBFS/tone –75 dBc fOUT = 2997 +/- 10MHz, -7dBFS/tone –69 dBc fOUT = 3997 +/- 10MHz, -7dBFS/tone –71 dBc fOUT = 5997 +/- 10MHz, -7dBFS/tone –63 dBc fOUT = 6997 +/- 10MHz, -7dBFS/tone –56 dBc fOUT = 7997 +/- 10MHz, -7dBFS/tone –62 dBc fOUT = 8997 +/- 10MHz, -7dBFS/tone –60 dBc NSD Noise spectral density, large signal, sinusoidal output(3) fOUT = 97MHz, 70MHz offset from fOUT –156 dBc/Hz fOUT = 997MHz, 70MHz offset from fOUT –154 dBc/Hz fOUT = 1997MHz, 70MHz offset from fOUT –152 dBc/Hz fOUT = 2997MHz, 70MHz offset from fOUT –150 dBc/Hz fOUT = 3997MHz, 70MHz offset from fOUT –149 dBc/Hz fOUT = 5997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 6997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 7997MHz, 70MHz offset from fOUT –146 dBc/Hz fOUT = 8997MHz, 70MHz offset from fOUT –143 dBc/Hz www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

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6.7 Electrical Characteristics - Power Consumption

10.24 GSPS, FOUT = 2997 MHz, NRZ

mode (dual channel version only) mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 168 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 326 IVDDCLK 1.0-V supply current for VDDCLK10 496 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2263 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123 PDIS Total power dissipation 3747 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 2: Dual DACs, 1 IQ input stream per DAC, FINPUT = 2.56 GSPS, JMODE 2, 4x Interpolation, FDAC = mode (dual channel version only) mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 168 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 326 IVDDCLK 1.0-V supply current for VDDCLK10 497 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 3256 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123 PDIS Total power dissipation 4742 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 3: Dual DACs, 2 IQ input streams per DAC, FINPUT = 640 MSPS, JMODE 3, 16x Interpolation, FDAC = 10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 3997 MHz, NRZ mode (dual channel version only) mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 133 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 327 IVDDCLK 1.0-V supply current for VDDCLK10 497 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 3191 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123 PDIS Total power dissipation 4612 mW www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, 2 channels, FINPUT = 2.56 GSPS, JMODE 1, 8b/10b encoding, 4x Interpolation, FCLK = 10.24 GHz, FOUT = 2997 MHz, NRZ mode, IFSSWITCH = 20.5 mA, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 4: Dual DACs, 2 IQ input streams per DAC, FINPUT = 160 MSPS, JMODE 6, 64x Interpolation, FDAC = 10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 3997 MHz, NRZ mode (dual channel version only) mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 106 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 327 IVDDCLK 1.0-V supply current for VDDCLK10 497 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2216 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123 PDIS Total power dissipation 3590 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 5: Dual DACs, 2 IQ input streams per DAC, FINPUT = 160MSPS, JMODE 5, 64x Interpolation, FDAC =10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 3997 MHz, NRZ mode (dual channel version only) mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 97 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 327 IVDDCLK 1.0-V supply current for VDDCLK10 497 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2260 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123 PDIS Total power dissipation 3618 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 6: Dual DACs, 2 IQ input streams per DAC, FINPUT = 853.33MSPS, JMODE 3, 12x Interpolation, FDAC =10.24 GSPS, FOUT1 = 2997 MHz, FOUT2 = 3997 MHz, NRZ mode (dual channel version only) mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 144 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 327 IVDDCLK 1.0-V supply current for VDDCLK10 497 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 3647 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 123 PDIS Total power dissipation 5090 5950 mW DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, 2 channels, FINPUT = 2.56 GSPS, JMODE 1, 8b/10b encoding, 4x Interpolation, FCLK = 10.24 GHz, FOUT = 2997 MHz, NRZ mode, IFSSWITCH = 20.5 mA, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 7: Dual DACs, 1 IQ input stream sent to both DACs after the NCO, FINPUT = 5.12GSPS, JMODE 1, 2x Interpolation, FDAC = 10.24 GSPS, FOUT = 2997 MHz, NRZ mode (dual channel version only) mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 153 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 330 IVDDCLK 1.0-V supply current for VDDCLK10 498 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2706 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 122 PDIS Total power dissipation 4186 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 8: Dual channel devices programmed as single DAC, FINPUT = 10.24GSPS, JMODE 0, 2x DES Interpolation, FDAC = 20.48 GSPS, FOUT = 7997 MHz, DES mode mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 153 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 311 IVDDCLK 1.0-V supply current for VDDCLK10 498 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2193 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70 PDIS Total power dissipation 3510 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 9: Dual channel devices programmed as single DAC, FINPUT = 20.48 GSPS, JMODE 14 (8-bit resolution), FDAC = 20.48 GSPS, FOUT = 7997 MHz, DES mode mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 153 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 311 IVDDCLK 1.0-V supply current for VDDCLK10 497 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 2035 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70 PDIS Total power dissipation 3351 mW www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

15.6 GSPS, FOUT = 7997 MHz, DES

IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 158 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 250 IVDDCLK 1.0-V supply current for VDDCLK10 392 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 1939 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70 PDIS Total power dissipation 3098 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 11: Single channel devices (DAC39RFSxx), FINPUT =

10.24 GSPS, JMODE 0, 2x DES

Interpolation, FDAC = 20.48 GSPS, FOUT = 7997 MHz, DES mode mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 154 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 162 IVDDCLK 1.0-V supply current for VDDCLK10 310 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 1867 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70 PDIS Total power dissipation 2848 mW IVDDA18 1.8-V combined supply current for VDDA18A and VDDA18B Power Mode 12: Single channel devices (DAC39RFSxx), FINPUT =

20.48 GSPS, JMODE 14 (8-bit

resolution), FDAC = 20.48 GSPS, FOUT = 7997 MHz, DES mode mA IVDDIO 1.8-V supply current for VDDIO 1 IVDDCSR 1.8-V combined supply current for VDDCLK18, VDDSYS18 and VDDR18 154 IVDDL 1.0-V combined supply current for VDDLB, VDDLA 162 IVDDCLK 1.0-V supply current for VDDCLK10 309 IDVDD 1.0-V supply current for VDDDIG, VDDT, VDDEB and VDDEA 1709 IVEE –1.8-V combined supply current for VEEAM18 and VEEBM18 70 PDIS Total power dissipation 2689 mW DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.8 Timing Requirements

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24 GHz, IFS_SWITCH = 20.5 mA, single tone amplitude = 0 dBFS, Dither and DEM enabled, unless otherwise noted. MIN NOM MAX UNIT INPUT CLOCK (CLK+, CLK-) fCLK Input clock frequency 800 10400 MHz SYSREF (SYSREF+, SYSREF-) tSYSREF_LOW SYSREF Low Timing 5*tCLK + 1 ns tSYSREF_HIGH SYSREF High Timing 5*tCLK + 1 ns tINV(SYSREF) Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register(1) 13 ps tINV(TEMP) Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register –0.05 ps/°C tINV(VA11) Drift of invalid SYSREF capture region over VDDSYS18 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register 0.19 ps/mV tSTEP(SP) Delay of SYSREF_POS LSB SYSREF_ZOOM = 0 20 ps SYSREF_ZOOM = 1 9 DC(SYSREF) SYSREF duty cycle (asserted) when using a periodic SYSREF signal SYSREF duty cycle (asserted) when using a periodic SYSREF signal 50% 55% t(PH_SYS) Minimum SYSREF± assertion duration after SYSREF± rising edge event 8 ns RESET tRESET Minimum RESET pulse width 100 ns TXENABLE tTXENABLE_LOW TXENABLE Low Time 102 clock cycles (1) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector section for more information on SYSREF windowing. The invalid region, specified by tINV(SYSREF), indicates the portion of the CLK± period(tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.9 Switching Characteristics

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.242GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT JESD204C SERDES INTERFACE [15:0]SRX-/+ fSERDES SERDES bit rate(4) .78125 12.8 Gbps UI Unit Interval 78.125 1280 ps LATENCY TDAC DAC clock period 1 / fCLK s tPD(RX) Serdes RX analog propagation delay Serdes RX analog propagation delay 215 ps tPDI Input clock rising edge cross-over to output sample cross-over Input clock rising edge cross-over to output sample cross-over 500 ps tDACLAT Digital path latency from SYSREF rising edge to DAC output See XLS Calculator tRELEASE Latency from SYSREF rising edge to elastic buffer release See XLS Calculator tRXIN Latency from SERDES Input to elastic buffer release See XLS Calculator tTXEN_OUTPUT TXENABLE rising edge to data output of DAC FAST_TX_EN = 0 varies(1) CLK Cycles FAST_TX_EN=1 and QUIET_TX_DISABLE=0 93 FAST_TX_EN=1 and QUIET_TX_DISABLE=1 133 tTXEN_MUTE TXENABLE falling edge to DAC output muted QUIET_TX_DISABLE=0 93 QUIET_TX_DISABLE=1 133 tTXEN_PW Required TXENABLE pulse width FAST_TX_EN = 0(2) 102 FAST_TX_EN = 1(3) 20 SERIAL PROGRAMMING INTERFACE Fs_c serial clock frequency 15.625 MHz Fs_cts serial clock frequency temp sensor TS_TEMP register read 1 MHz tP serial clock period 64 ns tPH serial clock pulse width high 32 ns tPL serial clock pulse width low 32 ns tSU SDI setup time 30 ns tH SDI hold time 3 ns tIZ SDI TRI-STATE 3 ns tODZ SDO driven to TRI-STATE 200fF load 5 ns tOZD SDO TRI-STATE to driven 200fF load 3 ns tOD SDO output delay 200fF load 3 ns tCSS SCS setup 30 ns tCSH SCS hold 3 ns tRS RESET setup to serial clock RESET high 30 ns tRH RESET hold to serial clock RESET high 30 ns tIAG Inter-access gap 30 ns FAST RECONFIGURATION (FR) INTERFACE FFRCLK FRCLK frequency 200 MHz tFRCLK_P FRCLK period 5 ns tFRCLK_PH FRCLK pulse width high 2 ns www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.9 Switching Characteristics (continued)

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6.10 SPI and FRI Timing Diagrams

Figure 6-1. SPI Clock Timing Diagram SCLK tSU SDI tH Figure 6-2. SPI Data Input Timing Diagram SCS tODZ SCLK SCLK SDO SDO tOZD SDO tOD Figure 6-3. SPI Data Output Timing Diagram SCLK tCSH tCSS SCS SCS tIAG Figure 6-4. SPI Chip Select Timing Diagram SCLK or SCS tRS RESET SCLK or SCS tRH RESET Figure 6-5. RESET Timing Diagram www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

tFRDI_SU FRDI tFRDI_H tFRCLK_PL tFRCLK_PH Figure 6-6. FRDI Timing Diagram tFRCS_SU tFRCS_H FRCLK FRCS Figure 6-7. FRCS Timing Diagram DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.11 Typical Characteristics: Bandwidth and DC Linearity

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. F r e q u e n c y ( G H z ) Output Response(dB) 0 5 1 0 1 5 2 0 2 5 - 1 5 - 1 0 - 5 1 0 1 x C u r r e n t 2 x C u r r e n t Not including Sin(x)/x response, PCB and cable loss removed. Figure 6-8. Output Response vs Frequency Includes PCB loss. External balun and cable loss removed. Figure 6-9. Output Power vs Frequency (NRZ/RF modes) O u t p u t F r e q u e n c y ( G H z ) Fullscale Output Power (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 1 0 D E S 2 X L D E S 2 X H 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A Includes PCB loss. External balun and cable loss removed. Figure 6-10. Output Power vs Frequency (DES2X modes) D A C C o d e DNL (Codes) 0 1 0 0 0 0 2 0 0 0 0 3 0 0 0 0 4 0 0 0 0 5 0 0 0 0 6 0 0 0 0 - 1 5 - 1 0 - 5 1 0 1 5 D E M O f f / D i t h e r O f f S E D E M / S E D i t h e r IFS_SWITCH = 20.5mA Figure 6-11. DNL vs DAC Code: 20.5mA D A C C o d e DNL (Codes) 0 1 0 0 0 0 2 0 0 0 0 3 0 0 0 0 4 0 0 0 0 5 0 0 0 0 6 0 0 0 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 2 0 3 0 4 0 D E M O f f / D i t h e r O f f S E D E M / S E D i t h e r IFS_SWITCH = 5mA Figure 6-12. DNL vs DAC Code: 5mA D A C C o d e INL (Codes) 0 1 0 0 0 0 2 0 0 0 0 3 0 0 0 0 4 0 0 0 0 5 0 0 0 0 6 0 0 0 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 1 0 1 5 2 0 2 5 D E M O f f / D i t h e r O f f S E D E M / S E D i t h e r IFS_SWITCH = 20.5mA Figure 6-13. INL vs DAC Code: 20.5mA www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.11 Typical Characteristics: Bandwidth and DC Linearity (continued)

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. D A C C o d e INL (Codes) 0 1 0 0 0 0 2 0 0 0 0 3 0 0 0 0 4 0 0 0 0 5 0 0 0 0 6 0 0 0 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 2 0 4 0 6 0 8 0 1 0 0 D E M O f f / D i t h e r O f f S E D E M / S E D i t h e r IFS_SWITCH = 5mA Figure 6-14. INL vs DAC Code: 5mA C u r r e n t G a i n C o d e IFSSWITCH(mA) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 C U R _ 2 X _ E N = 0 C U R _ 2 X _ E N = 1 Gain Code = 64*COARSE_CUR_x + FINE_CUR_x Figure 6-15. IFS_SWITCH vs Gain Code C u r r e n t G a i n C o d e IFSSWITCHError (mA) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 - 0 . 1 - 0 . 0 8 - 0 . 0 6 - 0 . 0 4 - 0 . 0 2 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 C U R _ 2 X _ E N = 0 C U R _ 2 X _ E N = 1 Gain Code = 64*COARSE_CUR_x + FINE_CUR_x, error relative to linear end point fit Figure 6-16. IFS_SWITCH Error vs Gain Code C u r r e n t G a i n C o d e IFSSWITCHError (Gain Code LSBs) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 - 5 - 4 - 3 - 2 - 1 C U R _ 2 X _ E N = 0 C U R _ 2 X _ E N = 1 Gain Code = 64*COARSE_CUR_x + FINE_CUR_x, error relative to linear end point fit Figure 6-17. IFS_SWITCH Error vs Gain Code DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. C u r r e n t G a i n C o d e IFSSWITCHDNL (Gain Code LSBs) 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 C U R _ 2 X _ E N = 0 C U R _ 2 X _ E N = 1 Gain Code = 64*COARSE_CUR_x + FINE_CUR_x, error relative to linear end point fit Figure 6-18. IFS_SWITCH Error Differential Non-Linearity vs Gain Code www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.12 Typical Characteristics: Single Tone Spectra

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10 GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-19. fOUT = 97MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-20. fOUT = 97MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-21. fOUT = 97MHz, -12dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-22. fOUT = 997MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-23. fOUT = 997MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-24. fOUT = 997MHz, -12dBFS DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.12 Typical Characteristics: Single Tone Spectra (continued)

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10 GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. includes PCB, cable and balun loss Figure 6-25. fOUT = 2097MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-26. fOUT = 2097MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e includes PCB, cable and balun loss Figure 6-27. fOUT = 2097MHz, -12dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z D E S 2 X L includes PCB, cable and balun loss Figure 6-28. fOUT = 3497MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z D E S 2 X L includes PCB, cable and balun loss Figure 6-29. fOUT = 3497MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z D E S 2 X L includes PCB, cable and balun loss Figure 6-30. fOUT = 3497MHz, -12dBFS www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10 GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. includes PCB, cable and balun loss Figure 6-31. fOUT = 6097MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e includes PCB, cable and balun loss Figure 6-32. fOUT = 6097MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e includes PCB, cable and balun loss Figure 6-33. fOUT = 6097MHz, -12dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e includes PCB, cable and balun loss Figure 6-34. fOUT = 8097MHz, 0dBFS DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.13 Typical Characteristics: Dual Tone Spectra

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6.13 Typical Characteristics: Dual Tone Spectra (continued)

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10 GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 10MHz tone spacing, includes PCB, cable and balun loss Figure 6-41. Dual Tone, fOUT = 97MHz, -12dBFS (0 - fCLK) F r e q u e n c y ( G H z ) Amplitude (dBm) - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 10MHz tone spacing, includes PCB, cable and balun loss Figure 6-42. Dual Tone, fOUT = 97MHz, -6dBFS (0 - 1GHz) F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 50MHz tone spacing, includes PCB, cable and balun loss Figure 6-43. Dual Tone, fOUT = 997MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 50MHz tone spacing, includes PCB, cable and balun loss Figure 6-44. Dual Tone, fOUT = 997MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 50MHz tone spacing, includes PCB, cable and balun loss Figure 6-45. Dual Tone, fOUT = 997MHz, -12dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 100MHz tone spacing, includes PCB, cable and balun loss Figure 6-46. Dual Tone, fOUT = 2097MHz, 0dBFS www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10 GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 100MHz tone spacing, includes PCB, cable and balun loss Figure 6-47. Dual Tone, fOUT = 2097MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 100MHz tone spacing, includes PCB, cable and balun loss Figure 6-48. Dual Tone, fOUT = 2097MHz, -12dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 200MHz tone spacing, includes PCB, cable and balun loss Figure 6-49. Dual Tone, fOUT = 3497MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 200MHz tone spacing, includes PCB, cable and balun loss Figure 6-50. Dual Tone, fOUT = 3497MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z M o d e D E S 2 X L M o d e 200MHz tone spacing, includes PCB, cable and balun loss Figure 6-51. Dual Tone, fOUT = 3497MHz, -12dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e 400MHz tone spacing, includes PCB, cable and balun loss Figure 6-52. Dual Tone, fOUT = 6097MHz, 0dBFS DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10 GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted. F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e 400MHz tone spacing, includes PCB, cable and balun loss Figure 6-53. Dual Tone, fOUT = 6097MHz, -6dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e 400MHz tone spacing, includes PCB, cable and balun loss Figure 6-54. Dual Tone, fOUT = 6097MHz, -12dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e 400MHz tone spacing, includes PCB, cable and balun loss Figure 6-55. Dual Tone, fOUT = 8097MHz, 0dBFS F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 R F M o d e D E S 2 X H M o d e 400MHz tone spacing, includes PCB, cable and balun loss Figure 6-56. Dual Tone, fOUT = 8097MHz, -6dBFS www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

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6.14 Typical Characteristics: Noise Spectral Density

NSD at 70MHz offset from tone, typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, DEM_ADJ = 1 below 750MHz and 0 above 750MHz, unless otherwise noted. O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 N R Z R F D E M / D i t h e r O n , D E M _ A D J = 0 D E M / D i t h e r O n , D E M _ A D J = 1 D E M / D i t h e r O f f IFS_SWITCH = 41mA, NRZ and RF Modes Figure 6-58. NSD vs Output Frequency and DEM/Dither Mode O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 D E S 2 X L D E S 2 X H D E M / D i t h e r O n , D E M _ A D J = 0 D E M / D i t h e r O n , D E M _ A D J = 1 D E M / D i t h e r O f f IFS_SWITCH = 41mA, DES2XL and DES2XH Modes Figure 6-59. NSD vs Output Frequency and DEM/Dither Mode A m p l i t u d e ( d B F S ) NSD (dBc/Hz) - 6 - 5 - 4 - 3 - 2 - 1 0 - 1 7 6 - 1 7 5 - 1 7 4 - 1 7 3 - 1 7 2 - 1 7 1 - 1 7 0 - 1 6 9 - 1 6 8 4 9 . 7 M H z 9 7 M H z IFS_SWITCH = 41mA, DES2XL, DEM/Dither off Figure 6-60. NSD vs Digital Amplitude at Low Frequency O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM and Dither Off, NRZ and RF Modes Figure 6-61. NSD vs Output Frequency and Output Current www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.14 Typical Characteristics: Noise Spectral Density (continued)

O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM and Dither On, NRZ and RF Modes Figure 6-62. NSD vs Output Frequency and Output Current O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM and Dither Off, DES2XL and DES2XH Modes Figure 6-63. NSD vs Output Frequency and Output Current O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM and Dither On, DES2XL and DES2XH Modes Figure 6-64. NSD vs Output Frequency and Output Current O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, NRZ and RF Modes Figure 6-65. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM and Dither Off, NRZ and RF Modes Figure 6-66. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither On, DEM_ADJ = 0, NRZ and RF Modes Figure 6-67. NSD vs Output Frequency and Digital Amplitude DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither On, DEM_ADJ = 1, NRZ and RF Modes Figure 6-68. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM and Dither On, DEM_ADJ = 0, NRZ and RF Modes Figure 6-69. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM and Dither On, DEM_ADJ = 1, NRZ Mode Figure 6-70. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, DES2XL and DES2XH Modes Figure 6-71. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM and Dither Off, DES2XL and DES2XH Modes Figure 6-72. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither On, DEM_ADJ = 0, DES2XL and DES2XH Modes Figure 6-73. NSD vs Output Frequency and Digital Amplitude www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM and Dither On, DEM_ADJ = 0, DES2XL and DES2XH Modes Figure 6-74. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither On, DEM_ADJ = 1, DES2XL Mode Figure 6-75. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 - 1 3 5 - 1 3 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM and Dither On, DEM_ADJ = 1, DES2XL Mode Figure 6-76. NSD vs Output Frequency and Digital Amplitude O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0

4 G S P S , - 1 2 d B F S

6 G S P S , - 1 2 d B F S

8 G S P S , - 1 2 d B F S

1 0 G S P S , - 1 2 d B F S

4 G S P S , 0 d B F S

6 G S P S , 0 d B F S

8 G S P S , 0 d B F S

1 0 G S P S , 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, NRZ and RF Modes Figure 6-77. NSD vs Output Frequency and Sample Rate O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither On, NRZ and RF Modes Figure 6-78. NSD vs Output Frequency and Sample Rate O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, DES2XL and DES2XH Modes Figure 6-79. NSD vs Output Frequency and Sample Rate DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) NSD (dBFS/Hz) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 - 1 4 5 - 1 4 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither On, DES2XL and DES2XH Modes Figure 6-80. NSD vs Output Frequency and Sample Rate T e m p e r a t u r e (  C ) NSD (dBFS/Hz) - 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 9 7 M H z , 0 d B F S 9 7 M H z , - 2 0 d B F S 2 9 9 7 M H z , 0 d B F S 2 9 9 7 M H z , - 2 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, NRZ Mode Figure 6-81. NSD vs Temperature T e m p e r a t u r e (  C ) NSD (dBFS/Hz) - 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 1 6 0 - 1 5 8 - 1 5 6 - 1 5 4 - 1 5 2 - 1 5 0 - 1 4 8 - 1 4 6 - 1 4 4 - 1 4 2 - 1 4 0 0 d B F S - 2 0 d B F S FOUT = 7242MHz, IFS_SWITCH = 20.5mA, DEM and Dither Off, RF Mode Figure 6-82. NSD vs Temperature T e m p e r a t u r e (  C ) NSD (dBFS/Hz) - 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 9 7 M H z , 0 d B F S 9 7 M H z , - 2 0 d B F S 2 9 9 7 M H z , 0 d B F S 2 9 9 7 M H z , - 2 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off,, DES2XL Mode Figure 6-83. NSD vs Temperature T e m p e r a t u r e (  C ) NSD (dBFS/Hz) - 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 1 6 0 - 1 5 8 - 1 5 6 - 1 5 4 - 1 5 2 - 1 5 0 - 1 4 8 - 1 4 6 - 1 4 4 - 1 4 2 - 1 4 0 0 d B F S - 2 0 d B F S FOUT = 7242MHz, IFS_SWITCH = 20.5mA, DEM and Dither Off, DES2XH Mode Figure 6-84. NSD vs Temperature V o l t a g e ( % ) NSD (dBFS/Hz) - 1 0 - 5 0 5 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 9 7 M H z , 0 d B F S 9 7 M H z , - 2 0 d B F S 2 9 9 7 M H z , 0 d B F S 2 9 9 7 M H z , - 2 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, NRZ Mode Figure 6-85. NSD vs Supply Voltage www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

V o l t a g e ( % ) NSD (dBFS/Hz) - 1 0 - 8 - 6 - 4 - 2 0 2 4 6 8 1 0 - 1 6 0 - 1 5 8 - 1 5 6 - 1 5 4 - 1 5 2 - 1 5 0 - 1 4 8 - 1 4 6 - 1 4 4 - 1 4 2 - 1 4 0 0 d B F S - 2 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, RF Mode Figure 6-86. NSD vs Supply Voltage V o l t a g e ( % ) NSD (dBFS/Hz) - 1 0 - 5 0 5 1 0 - 1 8 0 - 1 7 5 - 1 7 0 - 1 6 5 - 1 6 0 - 1 5 5 - 1 5 0 9 7 M H z , 0 d B F S 9 7 M H z , - 2 0 d B F S 2 9 9 7 M H z , 0 d B F S 2 9 9 7 M H z , - 2 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, DES2XL Mode Figure 6-87. NSD vs Supply Voltage V o l t a g e ( % ) NSD (dBFS/Hz) - 1 0 - 8 - 6 - 4 - 2 0 2 4 6 8 1 0 - 1 6 0 - 1 5 8 - 1 5 6 - 1 5 4 - 1 5 2 - 1 5 0 - 1 4 8 - 1 4 6 - 1 4 4 - 1 4 2 - 1 4 0 0 d B F S - 2 0 d B F S IFS_SWITCH = 20.5mA, DEM and Dither Off, DES2XH Mode Figure 6-88. NSD vs Supply Voltage DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.15 Typical Characteristics: Power Dissipation and Supply Currents

Typical values at TA = +25°C and nominal supply voltages, IFS_SWITCH = 20.5mA, 1 DAC device = DAC39RFS10-SP, 2 DAC device = DAC39RF10-SP except where noted. C l o c k F r e q u e n c y ( G H z ) Power Dissipation (mW) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 J M O D E 0 , 1 x I n t , 1 r e a l J M O D E 1 , 2 x I n t , 2 r e a l J M O D E 1 , 3 x I n t , 2 r e a l J M O D E 3 , 1 6 x I n t , 4 I Q J M O D E 7 , 2 5 6 x I n t , 4 I Q IFS_SWITCH = 20.5mA Figure 6-89. Power Dissipation vs Clock Frequency and Digital Mode C l o c k F r e q u e n c y ( G H z ) Power Dissipation (mW) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 J M O D E 0 , 1 x I n t , 1 r e a l J M O D E 1 , 2 x I n t , 2 r e a l J M O D E 1 , 3 x I n t , 2 r e a l J M O D E 3 , 1 6 x I n t , 4 I Q J M O D E 7 , 2 5 6 x I n t , 4 I Q IFS_SWITCH = 41mA Figure 6-90. Power Dissipation vs Clock Frequency and Digital Mode C l o c k F r e q u e n c y ( G H z ) Power Dissipation (mW) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 D E S 2 X L / H M o d e s N R Z / R F M o d e s JMODE 0, single DAC Device Figure 6-91. Power Dissipation vs Clock Frequency and DAC Mode C l o c k F r e q u e n c y ( G H z ) Power Dissipation (mW) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 D E S 2 X L / H M o d e s N R Z / R F M o d e s JMODE 1, 2x interpolation, dual DACs Figure 6-92. Power Dissipation vs Clock Frequency and DAC Mode C l o c k F r e q u e n c y ( G H z ) Power Dissipation (mW) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0

1 D A C , 1 x C u r r e n t

1 D A C , 2 x C u r r e n t

2 D A C s , 1 x C u r r e n t

2 D A C s , 2 x C u r r e n t

JMODE 0, 1x interpolation, single DAC device vs dual DAC device Figure 6-93. Power Dissipation vs Clock Frequency and DAC Mode C l o c k F r e q u e n c y ( G H z ) IVDDA18(mA) 0 1 2 3 4 5 6 7 8 9 1 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 6 0 Independent of JMODE and interpolation, single DAC device vs dual DAC device Figure 6-94. VDDA18 Current vs Clock Frequency and DAC Mode www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.15 Typical Characteristics: Power Dissipation and Supply Currents (continued)

Typical values at TA = +25°C and nominal supply voltages, IFS_SWITCH = 20.5mA, 1 DAC device = DAC39RFS10-SP, 2 DAC device = DAC39RF10-SP except where noted. C l o c k F r e q u e n c y ( G H z ) IVDDCLK18(mA) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 1 2 1 4 1 6 1 8 2 0 Independent of JMODE, interpolation, and single/dual DAC device Figure 6-95. VDDCLK18 Current vs Clock Frequency C l o c k F r e q u e n c y ( G H z ) IVEEM18(mA) 3 4 5 6 7 8 9 1 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 Independent of JMODE, interpolation, single DAC device vs dual DAC device Figure 6-96. VEEM18 Current vs Clock Frequency and DAC Mode C l o c k F r e q u e n c y ( G H z ) IVDDL2(mA) 0 1 2 3 4 5 6 7 8 9 1 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0

1 D A C

2 D A C s

Independent of JMODE, Interpolation, single DAC device vs dual DAC device Figure 6-97. VDDLx Current vs Clock Frequency Independent of JMODE, Interpolation, single DAC device vs dual DAC device Figure 6-98. VDDCLK Current vs Clock Frequency C l o c k F r e q u e n c y ( G H z ) IVDDE(mA) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 Independent of JMODE, Interpolation, single DAC device vs dual DAC device Figure 6-99. VDDE Current vs Clock Frequency C l o c k F r e q u e n c y ( G H z ) IVDDR18(mA) 0 1 2 3 4 5 6 7 8 9 1 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 J M O D E 0 , 1 x I n t , 1 r e a l J M O D E 1 , 2 x I n t , 2 r e a l J M O D E 1 , 3 x I n t , 2 r e a l J M O D E 3 , 1 6 x I n t , 4 I Q J M O D E 7 , 2 5 6 x I n t , 4 I Q Dependent on # of Serdes and baud rate Figure 6-100. VDDR18 Current vs Clock Frequency and Mode DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Typical values at TA = +25°C and nominal supply voltages, IFS_SWITCH = 20.5mA, 1 DAC device = DAC39RFS10-SP, 2 DAC device = DAC39RF10-SP except where noted. C l o c k F r e q u e n c y ( G H z ) IVDDT(mA) 0 1 2 3 4 5 6 7 8 9 1 0 2 5 0 5 0 0 7 5 0 1 0 0 0 1 2 5 0 1 5 0 0 J M O D E 0 , 1 x I n t , 1 r e a l J M O D E 1 , 2 x I n t , 2 r e a l J M O D E 1 , 3 x I n t , 2 r e a l J M O D E 3 , 1 6 x I n t , 4 I Q J M O D E 7 , 2 5 6 x I n t , 4 I Q Dependent on # of Serdes and baud rate Figure 6-101. VDDT Current vs Clock Frequency and Mode C l o c k F r e q u e n c y ( G H z ) IVDDDIG(mA) 0 1 2 3 4 5 6 7 8 9 1 0 5 0 0 1 0 0 0 1 5 0 0 2 0 0 0 2 5 0 0 J M O D E 0 , 1 x I n t , 1 r e a l J M O D E 1 , 2 x I n t , 2 r e a l J M O D E 1 , 3 x I n t , 2 r e a l J M O D E 3 , 1 6 x I n t , 4 I Q J M O D E 7 , 2 5 6 x I n t , 4 I Q Dual DAC Device Figure 6-102. VDDDIG Current vs Clock Frequency and Digital Mode C l o c k F r e q u e n c y ( G H z ) IVDDDIG(mA) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 single DAC device, JMODE 0, bypass mode Figure 6-103. VDDDIG Current vs Clock Frequency www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 67 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.16 Typical Characteristics: Linearity Sweeps

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24 GHz, IFS_SWITCH = 20.5mA, single tone amplitude = 0dBFS, Dither and DEM enabled, DEM_ADJ = 1 below 750MHz and 0 above 750MHz, unless otherwise noted. SFDR/harmonics measured between 0 and fCLK/2 when fOUT < fCLK/2 and fCLK/2 and fCLK when fOUT > fCLK/2. O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 N R Z D E S 2 X L R F D E S 2 X H D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 20.5mA Figure 6-104. SFDR vs Frequency and Mode O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 41mA Figure 6-105. SFDR vs Frequency and Mode O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 20.5mA Figure 6-106. IMD3 vs Frequency and Mode O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 41mA Figure 6-107. IMD3 vs Frequency and Mode DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.16 Typical Characteristics: Linearity Sweeps (continued)

O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 20.5mA Figure 6-108. HD2 vs Frequency and Mode O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 41mA Figure 6-109. HD2 vs Frequency and Mode O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 20.5mA Figure 6-110. HD3 vs Frequency and Mode O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 D E S 2 X , D E M / D i t h e r O n N R Z / R F , D E M / D i t h e r O n D E S 2 X , D E M / D i t h e r O f f N R Z / R F , D E M / D i t h e r O f f IFS_SWITCH = 41mA Figure 6-111. HD3 vs Frequency and Mode O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-112. SFDR vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-113. SFDR vs Frequency and Output Current in NRZ/RF Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-114. SFDR vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-115. SFDR vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-116. SFDR vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-117. SFDR vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-118. SFDR vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-119. SFDR vs Frequency and Digital Amplitude in NRZ/RF Modes DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-120. SFDR vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-121. SFDR vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-122. SFDR vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-123. SFDR vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-124. SFDR vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-125. SFDR vs Frequency and Sample Rate in NRZ/RF Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-126. SFDR vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) SFDR (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-127. SFDR vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-128. IMD3 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-129. IMD3 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-130. IMD3 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-131. IMD3 vs Frequency and Output Current in DES2X Modes DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-132. IMD3 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-133. IMD3 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-134. IMD3 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-135. IMD3 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-136. IMD3 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-137. IMD3 vs Frequency and Digital Amplitude in DES2X Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 73 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-138. IMD3 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-139. IMD3 vs Frequency and Digital Amplitude in DES2X Modes T o n e S p a c i n g ( M H z ) IMD3 (dBc) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 1 2 0 . 5 m A , D E M / D i t h e r o f f 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 0 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 1 4 1 m A , D E M / D i t h e r o f f FCENTER = 1997MHz Figure 6-140. IMD3 vs Tone Spacing in NRZ Mode T o n e S p a c i n g ( M H z ) IMD3 (dBc) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 1 2 0 . 5 m A , D E M / D i t h e r o f f 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 0 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 1 4 1 m A , D E M / D i t h e r o f f FCENTER = 1997MHz Figure 6-141. IMD3 vs Tone Spacing in DES2XL Mode T o n e S p a c i n g ( M H z ) IMD3 (dBc) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 1 2 0 . 5 m A , D E M / D i t h e r o f f 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 0 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 1 4 1 m A , D E M / D i t h e r o f f FCENTER = 7997MHz Figure 6-142. IMD3 vs Tone Spacing in RF Mode T o n e S p a c i n g ( M H z ) IMD3 (dBc) 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 0 2 0 . 5 m A , D E M / D i t h e r o n , D E M _ A D J = 1 2 0 . 5 m A , D E M / D i t h e r o f f 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 0 4 1 m A , D E M / D i t h e r o n , D E M _ A D J = 1 4 1 m A , D E M / D i t h e r o f f FCENTER = 7997MHz Figure 6-143. IMD3 vs Tone Spacing in DES2XH Mode DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-144. IMD3 vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-145. IMD3 vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-146. IMD3 vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) IMD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-147. IMD3 vs Frequency and Sample Rate in DES2X Modes T e m p e r a t u r e (  C ) IMD3 (dBc) - 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 9 7 M H z , D E M / D i t h o n 9 7 M H z , D E M / D i t h o f f 2 9 9 7 M H z , D E M / D i t h o n 2 9 9 7 M H z , D E M / D i t h o f f Figure 6-148. IMD3 vs Temperature in NRZ Mode T e m p e r a t u r e (  C ) IMD3 (dBc) - 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 9 7 M H z , D E M / D i t h o n 9 7 M H z , D E M / D i t h o f f 2 9 9 7 M H z , D E M / D i t h o n 2 9 9 7 M H z , D E M / D i t h o f f Figure 6-149. IMD3 vs Temperature in DES2XL Mode www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 6-150. IMD3 vs Temperature in RF Mode at 7247MHz T e m p e r a t u r e (  C ) IMD3 (dBc) - 6 0 - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 D E M / D i t h o n D E M / D i t h o f f Figure 6-151. IMD3 vs Temperature in DES2XH Mode at 7247MHz V o l t a g e ( % v s n o m i n a l ) IMD3 (dBc) - 1 0 - 5 0 5 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 D E M / D i t h o n D E M / D i t h o f f 2 9 9 7 M H z , D E M / D i t h o n 2 9 9 7 M H z , D E M / D i t h o f f Figure 6-152. IMD3 vs Voltage in NRZ Mode Figure 6-153. IMD3 vs Voltage in DES2XL Mode V o l t a g e ( % v s n o m i n a l ) IMD3 (dBc) - 1 0 - 5 0 5 1 0 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 D E M / D i t h o n D E M / D i t h o f f Figure 6-154. IMD3 vs Voltage in RF Mode at 7247MHz V o l t a g e ( % v s n o m i n a l ) IMD3 (dBc) - 1 0 - 5 0 5 1 0 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 D E M / D i t h o n D E M / D i t h o f f Figure 6-155. IMD3 vs Voltage in DES2XH Mode at 7247MHz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-156. HD2 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-157. HD2 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-158. HD2 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-159. HD2 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-160. HD2 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-161. HD2 vs Frequency and Digital Amplitude in NRZ/RF Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-162. HD2 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-163. HD2 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-164. HD2 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-165. HD2 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-166. HD2 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-167. HD2 vs Frequency and Digital Amplitude in DES2X Modes DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-168. HD2 vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-169. HD2 vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-170. HD2 vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD2 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-171. HD2 vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-172. HD3 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-173. HD3 vs Frequency and Output Current in NRZ/RF Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 79 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-174. HD3 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-175. HD3 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-176. HD3 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-177. HD3 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-178. HD3 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-179. HD3 vs Frequency and Digital Amplitude in NRZ/RF Modes DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-180. HD3 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-181. HD3 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-182. HD3 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-183. HD3 vs Frequency and Digital Amplitude in DES2X Modes DEM/Dither on Figure 6-184. HD3 vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-185. HD3 vs Frequency and Sample Rate in NRZ/RF Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-186. HD3 vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD3 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-187. HD3 vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD4 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-188. HD4 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD4 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-189. HD4 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD4 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-190. HD4 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD4 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-191. HD4 vs Frequency and Output Current in DES2X Modes DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-192. HD5 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-193. HD5 vs Frequency and Output Current in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither off Figure 6-194. HD5 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DEM/Dither on Figure 6-195. HD5 vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-196. HD5 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-197. HD5 vs Frequency and Digital Amplitude in NRZ/RF Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-198. HD5 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-199. HD5 vs Frequency and Digital Amplitude in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither off Figure 6-200. HD5 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 20.5mA, DEM/Dither on Figure 6-201. HD5 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither off Figure 6-202. HD5 vs Frequency and Digital Amplitude in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 - 1 7 d B F S - 1 2 d B F S - 7 d B F S 0 d B F S IFS_SWITCH = 41mA, DEM/Dither on Figure 6-203. HD5 vs Frequency and Digital Amplitude in DES2X Modes DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-204. HD5 vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-205. HD5 vs Frequency and Sample Rate in NRZ/RF Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither on Figure 6-206. HD5 vs Frequency and Sample Rate in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) HD5 (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 G S P S , - 1 2 d B F S 1 0 G S P S , 0 d B F S DEM/Dither off Figure 6-207. HD5 vs Frequency and Sample Rate in DES2X Modes www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

O u t p u t F r e q u e n c y ( G H z ) DES Image (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 5 m A 1 0 m A 2 0 . 5 m A 4 1 m A DES Image = FCLK - FOUT Figure 6-208. DES Image vs Frequency and Output Current in DES2X Modes O u t p u t F r e q u e n c y ( G H z ) DES Image (FCLK- FOUT) (dBc) 0 1 2 3 4 5 6 7 8 9 1 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 F C L K = 4 G H z F C L K = 6 G H z F C L K = 8 G H z F C L K = 1 0 G H z DES Image = FCLK - FOUT. DES Image relative to power of the tone at the same frequency as the image using the inverse DES2X mode. This removes the bandwidth difference across frequency. Figure 6-209. DES Image vs Frequency and Sample Rate in DES2X Modes DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.17 Typical Characteristics: Modulated Waveforms

NSD at 70MHz offset from tone, typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24GHz, DEM_ADJ = 0 when DEM enabled, NPR waveform 80% of Nyquist with 5% gap for measurement and 12dB PAR, unless otherwise noted. D i g i t a l B a c k o f f ( d B ) NPR (dBc) - 2 0 - 1 8 - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 0 2 5 3 0 3 5 4 0 4 5 5 0 4 1 m A , D E X 2 X L 4 1 m A , N R Z 2 0 . 5 m A , D E X 2 X L 2 0 . 5 m A , N R Z DEM/Dither Off Figure 6-210. Noise Power Ratio vs Digital Backoff: 1st Nyquist Zone D i g i t a l B a c k o f f ( d B ) NPR (dBc) - 2 0 - 1 8 - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 0 2 5 3 0 3 5 4 0 4 5 5 0 4 1 m A , D E X 2 X L 4 1 m A , N R Z 2 0 . 5 m A , D E X 2 X L 2 0 . 5 m A , N R Z DEM/Dither On Figure 6-211. Noise Power Ratio vs Digital Backoff: 1st Nyquist Zone D i g i t a l B a c k o f f ( d B ) NPR (dBc) - 2 0 - 1 8 - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 0 2 5 3 0 3 5 4 0 4 5 5 0 2 0 . 5 m A , D E X 2 X L 2 0 . 5 m A , N R Z DEM/Dither Off Figure 6-212. Noise Power Ratio vs Digital Backoff: 2nd Nyquist Zone D i g i t a l B a c k o f f ( d B ) NPR (dBc) - 2 0 - 1 8 - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 0 2 5 3 0 3 5 4 0 4 5 5 0 2 0 . 5 m A , D E X 2 X L 2 0 . 5 m A , N R Z DEM/Dither On Figure 6-213. Noise Power Ratio vs Digital Backoff: 2nd Nyquist Zone I F S _ S W I T C H ( m A ) NPR (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 3 6 3 8 4 0 4 2 4 4 4 6 4 8 5 0 D E X 2 X L , D E M / D i t h e r O n D E X 2 X L , D E M / D i t h e r O f f N R Z , D E M / D i t h e r O n N R Z , D E M / D i t h e r O f f Figure 6-214. Noise Power Ratio vs Output Current: 1st Nyquist Zone I F S _ S W I T C H ( m A ) NPR (dBc) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 3 6 3 8 4 0 4 2 4 4 4 6 4 8 5 0 D E X 2 X L , D E M / D i t h e r O n D E X 2 X L , D E M / D i t h e r O f f N R Z , D E M / D i t h e r O n N R Z , D E M / D i t h e r O f f Figure 6-215. Noise Power Ratio vs Output Current: 2nd Nyquist Zone www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

6.18 Typical Characteristics: Phase and Amplitude Noise

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24GHz, single tone amplitude = 0dBFS, fOUT = 1GHz, unless otherwise noted. Input clock contribution removed by phase noise analyzer. O f f s e t F r e q u e n c y ( H z ) SSB Phase Noise (dBc/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 - 1 8 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 N R Z D E M / D i t h e r o f f N R Z D E M / D i t h e r o n D E S 2 X L D E M / D i t h e r o f f D E S 2 X L D E M / D i t h e r o n fCLK = 8GHz Figure 6-216. Phase Noise vs Offset Frequency at 1GHz O f f s e t F r e q u e n c y ( H z ) SSB Phase Noise (dBc/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 - 1 8 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 N R Z D E M / D i t h e r o f f N R Z D E M / D i t h e r o n D E S 2 X L D E M / D i t h e r o f f D E S 2 X L D E M / D i t h e r o n fCLK = 10.24GHz Figure 6-217. Phase Noise vs Offset Frequency at 1GHz O f f s e t F r e q u e n c y ( H z ) SSB Phase Noise (dBc/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 - 1 8 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 F O U T = 1 G H z F O U T = 2 G H z F O U T = 4 G H z F O U T = 6 G H z F O U T = 8 G H z F O U T = 1 0 G H z DES2XL and DES2XH modes, DEM/Dither off Figure 6-218. Phase Noise vs Offset Frequency and Output Frequency O f f s e t F r e q u e n c y ( H z ) SSB Phase Noise (dBc/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 - 1 8 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 D E M / D i t h e r o f f , 2 5  C D E M / D i t h e r o n , 2 5  C D E M / D i t h e r o f f , 9 0  C D E M / D i t h e r o n , 9 0  C NRZ mode Figure 6-219. Phase Noise vs Offset Frequency at 1GHz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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6.18 Typical Characteristics: Phase and Amplitude Noise (continued)

Typical values at TA = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, fCLK = 10.24GHz, single tone amplitude = 0dBFS, fOUT = 1GHz, unless otherwise noted. Input clock contribution removed by phase noise analyzer. O f f s e t F r e q u e n c y ( H z ) SSB Phase Noise (dBc/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 - 1 8 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 D E M / D i t h e r o f f , 2 5  C D E M / D i t h e r o n , 2 5  C D E M / D i t h e r o f f , 9 0  C D E M / D i t h e r o n , 9 0  C DES2XL mode Figure 6-220. Phase Noise vs Offset Frequency at 1GHz I n p u t C l o c k ( G H z ) Jitter (fs) 8 8 . 5 9 9 . 5 1 0 1 0 1 2 1 4 1 6 1 8 2 0 D E S 2 X L , 9 0  C N R Z , 9 0  C D E S 2 X L , 2 5  C N R Z , 2 5  C Integrated from 100Hz to 30MHz, DEM/Dither off Figure 6-221. Jitter vs Input Clock I n p u t C l o c k ( G H z ) Jitter (fs) 8 8 . 5 9 9 . 5 1 0 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 D E S 2 X L , 9 0  C N R Z , 9 0  C D E S 2 X L , 2 5  C N R Z , 2 5  C Integrated from 100Hz to 30MHz, DEM/Dither on Figure 6-222. Jitter vs Input Clock O f f s e t F r e q u e n c y ( H z ) Amplitude Noise (dBc/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 - 1 8 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 N R Z D E M / D i t h e r o f f N R Z D E M / D i t h e r o n D E S 2 X L D E M / D i t h e r o f f D E S 2 X L D E M / D i t h e r o n Figure 6-223. Amplitude Noise vs Offset Frequency at 1GHz www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 89 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

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7 Detailed Description

7.1 Overview

DAC39RF10-Sx and 'RFS10-Sx are a family of single and dual channel digital-to-analog converters (DAC) with 16-bit resolution. The device can be used as single channel or dual channel non-interpolation DACs. The device can also be used as interpolating DACs in either direct RF sampling mode or baseband mode, supporting up to four complex (IQ) input streams that can be combined at different RF frequencies. The maximum input data rate is 20.8 GSPS in single channel mode or 10.4GSPS in dual channel mode or baseband mode. The device can generate signals of up to 5, 7, 8, 10GHz signal bandwidth (8, 12, 16-bit input resolution) at carrier frequencies exceeding 8GHz enabling direct sampling through C-band and into X-band. The 64-bit NCO frequency resolution and infinite frequency hopping with phase coherence, continuity and reset options makes the device ideally suited for arbitrary waveform generation (AWG) and direct digital synthesis (DDS). A JESD204C compatible serial interface with 8b/10b and 64b/66b encoding options has 16 receiver pairs capable of up to 12.8Gbps. The interface is JESD204C subclass-1 compliant for deterministic latency and multi-device synchronization through the use of SYSREF. The SYSREF Windowing feature allows for automatic SYSREF timing calibration.

7.2 Functional Block Diagrams

CLK– SYSREF+ SYSREF– SYSREF Window JESD204B/ 204C Block 0SRX+ 0SRX– DACOUTB+ DACOUTB– SYNC Mul -Nyquist DAC 7SRX+ 7SRX– 15SRX+ 15SRX– 8SRX+ 8SRX– Lane MUX DACOUTA+ DACOUTA– Mul -Nyquist DAC FRDI0 FRDI1 FRDI2 FRDI3 RF Bonder or IQ DAC MUX DUC0 L DUC1 L DUC2 L DUC3 L DESDAC DESDAC FRCLK FRCS Fast Recon gura on controller TXENABLE0 SDO SCS SCLK SDI RESET ALARM Control Interface & GPIOs TXENABLE1 Figure 7-1. Dual Channel Device www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 91 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

CLK– SYSREF+ SYSREF– SYSREF Window JESD204B/ 204C Block 0SRX+ 0SRX– SYNC 7SRX+ 7SRX– 15SRX+ 15SRX– 8SRX+ 8SRX– Lane MUX DACOUTA+ DACOUTA– FRDI0 FRDI1 FRDI2 FRDI3 RF Bonder or IQ DAC MUX DUC0 L DUC1 L DUC2 L DUC3 L DESDAC FRCLK FRCS Fast Recon gura on controller TXENABLE0 SDO SCS SCLK SDI RESET ALARM Control Interface & GPIOs TXENABLE1 Mul -Nyquist DAC Figure 7-2. Single Channel Device DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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7.3 Feature Description

This section describes the analog and digital features of the device.

7.3.1 DAC Output Modes

The DAC39RF10-Sx and 'RFS10-Sx consists of a multi-Nyquist DAC core capable of direct transmission through the third Nyquist zone. The high output frequency capabilities are enabled by specific output switching waveforms that alter the output waveform, changing the frequency response of the DAC to enhance the DAC images in alternate Nyquist zones. The desired switching waveforms can be selected through the serial interface. A list of modes along with their properties and uses are provided in Table 7-1. The responses shown in this section do not consider the effect of the DAC analog bandwidth or external passive or active signal chain components. Table 7-1. Summary of Multi-Nyquist Output Modes and Uses DAC OUTPUT MODE PASSES DC Optimal Frequency Range PEAK OUTPUT POWER(1) Other Non-return-to-zero (NRZ) Yes 0 - FCLK/2 0 dBFS Return-to-zero (RTZ) Yes 0 - FCLK –6 dBFS Radio Frequency (RF) No FCLK/2 - FCLK –2.8 dBFS Dual Edge Sampling (DES) Yes 0 - FCLK 0 dBFS Duty cycle image at FCLK - FOUT (1) Peak power here does not include the effect of analog output bandwidth due to parasitic passive components or external components www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 93 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

7.3.1.1 NRZ Mode

Non-return-to-zero (NRZ) mode is the standard zero-order hold mode. The timing diagram for NRZ mode is given in Figure 7-3. The sample is output from the DAC on the CLK rising edge and held until the rising edge. This output waveform can be thought of as a rectangular filter in time domain resulting in a sinc response in the frequency domain. The result is a frequency response that has significant power loss in the 2 nd and 3rd Nyquist zones and a null at the sampling rate and is meant for 1 st Nyquist zone operation only. A plot of the frequency response of NRZ mode is shown in Figure 7-4. CLK+ CLK– DAC Output (Sine Wave) +IFS -IFS tpd TSample = 1/FCLK Figure 7-3. NRZ Mode Timing Diagram F O U T / F C L K Normalized Response (dB) 0 0 . 5 1 1 . 5 2 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 Figure 7-4. NRZ Mode Output Frequency Response

7.3.1.2 RTZ Mode

Return-to-zero (RTZ) mode is similar to the standard zero-order hold mode used by DACs; however, the response adds a return-to-zero pulse for the second half of the sample period. The timing diagram for RTZ mode is given in Figure 7-5. This output waveform can be thought of as a rectangular filter in time domain that is half the length of that which is used in NRZ mode, resulting in a sinc response that is expanded by two times in the frequency domain. The result is a frequency response with less power loss in the 2 nd Nyquist zone and a null at twice the sampling rate. It can be used for 1 st and 2 nd Nyquist zone applications. The return-to-zero pulse provides flatter response through the first Nyquist zone at a tradeoff of 6dB lower peak power. A plot of the frequency response of RTZ mode is shown in Figure 7-6. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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CLK– DAC Output (Sine Wave) +IFS -IFS tpd TS = 1/FCLK TMIDSCALE = 1/(2*FCLK) Figure 7-5. RTZ Mode Timing Diagram F O U T / F C L K Normalized Response (dB) 0 0 . 5 1 1 . 5 2 2 . 5 3 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 Figure 7-6. RTZ Mode Output Frequency Response

7.3.1.3 RF Mode

RF mode adds a mixing function to the DAC output by inverting the sample halfway through the sample period. The result is a sinc response that peaks and provides maximum flatness in the 2 nd Nyquist zone. The timing diagram for RF mode is given in Figure 7-7. A plot of the frequency response of RF mode is shown in Figure 7-8. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 95 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

CLK– DAC Output (Sine Wave) +VFS -VFS TS = 1/FCLK tpd TS /2 Figure 7-7. RF Mode Timing Diagram F O U T / F C L K Normalized Response (dB) 0 0 . 5 1 1 . 5 2 2 . 5 3 - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 Figure 7-8. RF Mode Output Frequency Response

7.3.1.4 DES Mode

Dual edge sampling (DES) mode outputs unique samples on both the rising and falling edge of CLK, doubling the sample rate for the same clock frequency. An extra digital interpolate by 2 stage is included in the device to enable a double sample rate. An non-50% CLK duty cycle results in an image of the signal at F CLK - F OUT. Compared to NRZ mode with the same clock frequency, DES mode provides significant reduction in the image amplitude, reducing filter requirements. There are three DES modes: DES1X, DES2XL and DES2XH. DES1X mode also allows 15.52 or 20.8GSPS of unique data in 12-bit and 8-bit single channel mode, supporting 7.68GHz or 10.4GHz of signal bandwidth. DES2XL uses an low pass 2x interpolation filter to increase from the single edge sample rate to dual edge sample rate, and supports output frequencies between 0 - 0.4*F CLK with up to 4.16GHz of signal BW) . DES2XH uses a high pass interpolation filter, supporting output frequencies between 0.6 - 1.0*F CLK with the same signal BW as DES2XL. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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CLK– DAC Output (Sine Wave) +VFS -VFS TS = 1/(2*FCLK) tpd tpd_f Figure 7-9. DES Mode Timing Diagram F O U T / F C L K Normalized Response (dB) 0 0 . 5 1 1 . 5 2 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 Figure 7-10. DES1X Output Frequency Response

7.3.2 DAC Core

The device has two 16-bit DAC cores.

7.3.2.1 DAC Output Structure

The DAC core analog output structure is shown in Figure 7-11 for one DAC channel. There is a differential termination resistance between the two current output pins, DACOUTx±. The current steering switch array connects to the output pins and steers current between the output pins based on the digital code. A constant DC current bias, IBIAS, draws current from both outputs regardless of the digital code. The IBIAS current is: 3mA x 2 CUR_2X_EN (COARSE_CUR_x + 5)/20 (1) With a 3.6kΩ resistor from RBIAS+ to RBIAS-. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 97 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 7-11. Analog Output Structure Examples of conversions from digital codes to currents on the IOUTx± outputs are given in Table 7-2. The currents shown in Table 7-2 include both the current steered portion and the bias currents on each leg. Table 7-2. Example Digital Code to Analog Current Conversions DIGITAL CODE 2'S COMPLEMENT OFFSET BINARY IDACOUTx+ IDACOUTx– IDACOUTx+ – IDACOUTx– 32767 0111 1111 1111 1111 1111 1111 1111 1111 0.9999847 × IFS + IBIAS 0.0000153 × IFS + IBIAS 0.9999694 × IFS 16384 0100 0000 0000 0000 1100 0000 0000 0000 ¾ × IFS + IBIAS ¼ × IFS + IBIAS ½ × IFS 0 0000 0000 0000 0000 0000 0000 0000 0000 ½ × IFS + IBIAS ½ × IFS + IBIAS 0 –16384 1100 0000 0000 0000 0100 0000 0000 0000 ¼ × IFS + IBIAS ¾ × IFS + IBIAS –½ × IFS –32768 1000 0000 0000 0000 0000 0000 0000 0000 IBIAS IFS + IBIAS –IFS

7.3.2.2 Full-Scale Current Adjustment

The total DAC output current is set through the external RBIAS resistor and the COARSE_CUR_A or COARSE_CUR_B and the FINE_CUR_A or FINE_CUR_B registers. There is a switched fullscale current and a static fullscale current. The switched current is divided between DACOUTA/B+ and DACOUTA/B- in proportion to the digital signal value at the DAC. The static current is fixed at the output of each ball DACOUTA/B+ and DACOUTA/B-. The equation for the DAC switched output current is I F SSW I TC H = 3.6 k Ω R BI AS × 5 m A + 1 m A * C O ARSE + 0.0156 m A * F I N E × 2 CU R _ 2 X _ EN (2) where

Rbias is the external bias resistor
COARSE is the value of the register COARSE_CUR_A or COARSE_CUR_B (0 to 15)
FINE is the value of register FINE_CUR_A or FINE_CUR_B (0 to 63)
CUR_2X_EN is the value of register CUR_2X_EN (0 or 1) The static current is a fixed fraction of the switched current IFSSTATIC = 0.235 x IFSSWITCH (3) With a 3.6kΩ bias resistor, COARSE_CUR_A or COARSE_CUR_B = 15 and FINE_CUR_A or FINE_CUR_B = 31, IFSSWITCHED is ~ 20.5mA and I FSSTATIC ~ 4.82mA (on each ball + and -). Enabling CUR_2X_EN doubles the currents. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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7.3.3 DEM and Dither

The device contains two optional features to improve non-linearity due to current segment and switch timing mismatch: Dynamic element Mixing (DEM) and dither. The DAC core consists of 1. Thermometer encoded current sources/switches representing the upper MSBs 2. Thermometer encoded current sources/switches representing the middle bits (called ULSBs) 3. Binary weighted current sources/switches representing the lower LSBs. 4. Additional current sources/switches for dithering DEM randomizes which MSB and ULSB current sources/switches are used to generate the output, which whitens the non-linearity due to mismatches between the current sources and switch timing. The DEM_DACA/B and DEM_ADJ registers control the frequency and amplitude of the shift in current sources/segments. Dither add or subtracts 8 different digital code values to the digital data which are then canceled by switching additional current sources with the same amplitude. The digital data path is expanded so the full 16-bit range is maintained. The DITH_DACA/B registers control the frequency of the dither. Using DEM generally improves low order harmonics near fullscale. Dither generally improves higher order harmonics near fullscale and all harmonics at lower digital amplitudes. Both DEM and dither increase the noise floor (both amplitude and phase) of the output due to the whitening of the non-linearity and the additional switching activity. This is reduced by DEM and dither settings with lower switching activity, that is. data dependent or reduced activity DEM. However, data dependent or reduced activity DEM is less effective at higher output frequencies. For data sheet specification testing in Electrical Characteristics - AC Specifications , data dependent DEM (DEM_ADJ = 1) is used below 750MHz and normal activity DEM (DEM_ADJ = 0) above 750MHz, but different settings (including disabling DEM and/or dither) can be tested and the best chosen based on the specific use case.

7.3.4 Offset Adjustment

The device allows an offset adjustment to the signal at the DAC output. The offset adjustment does NOT take away from the full 16-bit digital range of the DAC data. The offset is set by the DAC_OFS[0] or DAC_OFS[1] register values for DACA and DACB, respectively. If dithering is enabled (see register DEM_DITH), the value is saturated to the range of ±128. If dithering is disabled, the value is saturated to the range ±3968. This makes sure that the primary DAC range will never be exceeded.

7.3.5 Clocking Subsystem

The device requires a clock running at a frequency equal to the DAC core sampling rate in NRZ, RTZ and RF modes, or at half of the DAC core sampling rate in DES mode. The clocking subsystem is shown in Figure 7-12. CLK+ CLKt SYSREF+ SYSREFt SYSREF Window To DAC cores, digital logic, SerDes, ... Figure 7-12. Device Clocking Subsystem

7.3.5.1 SYSREF Frequency Requirements

The SYSREF input period must be an integer multiple of all clocks in the part, including the LMFC/LEMC. The following table depicts the requirements for the SYSREF period: www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 99 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-3. Requirements for SYSREF period Requirements on SYSREF Period Reason SYSREF period must be a multiple of 16 CLK cycles. DAC Encoder/DEM always operates with a FDAC/16 clock that is aligned to SYSREF. SYSREF period must be a multiple of LT CLK cycles This constraint does not apply to DDS mode (DDS_EN=1). Makes sure the SYSREF period is a multiple of the input sample period. SYSREF period must be a multiple of 4*LT*S/F CLK cycles. This constraint does not apply to DDS mode (DDS_EN=1). Makes sure the SYSREF period is a multiple of the effective link layer clock period. SYSREF period must be a multiple of LT*S*K CLK cycles. This constraint does not apply to Subclass 0 mode (SUBCLASS=0) or DDS mode (DDS_EN=1) Makes sure that SYSREF period is a multiple of the LMFC/LEMC period. Note that K=256*E/F in 64b/66b mode.

7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)

The SYSREF Windowing block is used to first detect the position of SYSREF relative to the input clock CLK± rising edge. Based on the window information, an optimum SYSREF sampling time is selected to maximize setup and hold timing margins relative to the input clock. In many cases, a single SYSREF sampling position SYSREF_SEL is sufficient to meet timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However, this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system. This section describes proper usage of the SYSREF Windowing block ( SYSREF_RECV_SLEEP must be programmed to 0). First, apply the device clock and SYSREF to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the SYSREF_POS field. Each bit of SYSREF_POS represents a potential SYSREF sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL to the value corresponding to that SYSREF_POS position. In general, the middle sampling position between two setup and hold instances is chosen. The determination of SYSREF_SEL is performed at the nominal operating conditions of the system (temperature and supply voltage) to provide maximum margin for operating condition variations. This process can be performed at final test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this characterization can be used to track the optimal SYSREF sampling position as system operating conditions change. In general, a single value can be found that meets timing over all conditions for well-matched systems, such as those where CLK± and SYSREF± come from a single clocking device. The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are finer. See the electrical specifications table for delay step sizes when SYSREF_ZOOM is enabled and disabled. In general, SYSREF_ZOOM is recommended to always be used ( SYSREF_ZOOM = 1) unless a transition region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates. Bits 0 and 19 of SYSREF_POS are always 1 because there is insufficient information to determine if these settings are close to a timing violation, although the actual valid window can extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location in SYSREF_POS. Table 7-4 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings. Although 20 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POSbits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage, however in the fourth example a value of 14 provides additional margin and can be selected instead. If SYSREF_PS_EN is set to 0, only the last SYSREF edge is used for the SYSREF_POS values. Setting SYSREF_PS_EN to 1 enables an "infinite persistence" mode, where if any SYSREF edge since DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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SYSREF_PS_EN is enabled has a 1 in a position, the SYSREF_POS value is set to one. This provides worst case values for SYSREF_POS to select the optimum SYSREF_SEL setting. Table 7-4. Examples of SYSREF_POS Readings and SYSREF_SEL Selections SYSREF_POS[19:0] OPTIMAL SYSREF_SEL SETTING0x092[3:0] (positions 19-16) 0x0917:0(positions 15-8) 0x0907:0 (positions 7-0) b1000 b01100000 b00011001 8 or 9 b1000 b00000000 b00110001 12 b1000 b01100000 b00000001 6 or 7 b1000 b00000011 b00000001 4 or 14 b1100 b01100011 b00011001 6 (1) Underlined 0 indicates the bits that are selected, as given in the last column of this table. To use SYSREF Windowing: 1. Apply SYSREF and CLK 2. Set SYSREF_RECV_SLEEP = 0 and SYSREF_ZOOM = 1 3. If persistence is desired, set SYSREF_PS_EN = 1 and allow many SYSREF transitions for SYSREF_POS to build. 4. Read SYSREF_POS and determine a proper setting for SYSREF_SEL, as shown above. If a proper sampling point cannot be determined, set SYSREF_ZOOM = 0 and retry. 5. Once a proper value for SYSREF_SEL is applied, program SYSREF_PROC_EN = 1 and SYSREF_ALIGN_EN = 1. 6. SYSREF is now being properly processed by the device and the user can proceed to use the JESD204C interface (or other functionality) that relies on SYSREF. 7. SYSREF may need to be adjusted over large temperature or supply voltage swings, depending on the input clock frequency. The SYSREF invalid window dependence on temperature (tINV(TEMP)) and VA11 supply voltage (tINV(VA11)) is given in Section 6.8. To adjust SYSREF_SEL to track shifts in SYSREF relative to the input clock, the following steps can be looped (that is, in background during operation of the JESD204C link): a. If persistence is desired, clear and then set SYSREF_PS_EN, and allow many SYSREF transitions for the SYSREF_POS data to build. b. Read SYSREF_POS and determine a new value for SYSREF_SEL (but do not program it yet). The procedure to incrementally adjust SYSREF_SEL should prefer values that are closer to the previousSYSREF_SEL value rather than selecting the smallest valid SYSREF_SEL value. This helps make sure that the original valid window is selected and tracked rather than selecting a different window which would cause clock realignment to occur. c. Program SYSREF_PROC_EN = 0. Write the new SYSREF_SEL value, and then set SYSREF_PROC_EN = 1. The new SYSREF_SEL value is now used by the device. d. Wait for some period of time, then return to step 7a above.

7.3.6 Digital Signal Processing Blocks

The digital signal processing blocks are shown in Figure 7-13 . The device includes four digital up-converter (DUC) blocks supporting four complex (IQ) input streams that can be combined at different RF frequencies. The four DUCs can be flexibly assigned and summed together for either DAC output in the channel bonder. The final signal processing block is a extra interpolate by 2 filter for use with DES2XL/H mode. Table 7-5 and Table 7-6 list the available modes for single channel and dual channel outputs, respectively. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 101 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

L DUC1 L DUC2 L DUC3 L DESDAC DESDAC Input 0 Input 1 Input 2 Input 3 DAC A DAC B Figure 7-13. DUC Block with real output Table 7-5. DSP Modes with Single Output Signal Input Steams LT (Interpolati on) NCO_EN DUC_FORMAT DAC_SRC0 value MXMODE0/

1 Description

1 1 0 Real 0x1 NRZ, RTZ, RF, DES2x Single channel mode (no up-conversion). 1 1 0 Real 0x1 DES1x Single channel mode with dual-edge samples w/o interpolation (DES1X). The JESD204C interface provides all samples (no interpolation). 2, 4, 6 or 8 2-256x 1 Real 0x1, 0x3, 0x7, 0xF NRZ, RTZ, RF, DES2x 1-4 DUC channels with single real output DAC_SRC0 settings are for 1, 2, 3, or 4 DUC channels respectively. These modes only produce one output signal, so only one DAC is required. The table shows the programming to use DACA (MXMODE1 should be set to disabled). The user may elect to use DACB instead by programming DAC_SRC1 and MXMODE1 (and setting MXMODE0 to disabled). The user may also program DAC_SRC1=DAC_SRC0 and MXMODE1=MXMODE0 and then tie the DAC outputs together to get more output power. Table 7-6. DSP Modes with Dual Output Signal Input Steams LT (Interpola tion) NCO_EN DUC_FO RMAT DAC_SRC0 value DAC_SRC1 value MXMODE 0/1 Description 2 1 0 N/A 0x1 0x2 NRZ, RTZ, RF, DES2x Dual channel mode (no up-conversion) 2, 4, 6 or 8 2-256x 1 Real any bits set any bits set NRZ, RTZ, RF, DES2x 1-4 DUC channels with two real outputs 2 2-256x 1 or 0 Complex 0x1 0x4 NRZ, RTZ, RF, DES2x

1 DUC channel with complex output:

DACB outputs imaginary samples 4 2-256x 1 or 0 Complex 0x3 0xC NRZ, RTZ, RF, DES2x

2 DUC channels with complex output

These modes produce two output signals (and uses both DACs). The user may elect to swap the values programmed into DAC_SRC0 and DAC_SRC1 to swap the output signals. Typically MXMODE0 and MXMODE1 are set to the same setting, however this is not required. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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7.3.6.1 Digital Upconverter (DUC)

Each DUC interpolates the I and Q signals by factors ranging from LT = 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192 and 256. The resulting up-converted baseband I/Q signal is then multiplied by a complex sinusoid generated by the numerically controlled oscillator (NCO) to mix the signal to the desired carrier frequency for output from the DAC. The interpolation factors supported vs the number of DUCs enabled is listed in Table 7-7. Table 7-7. Supported Interpolation Factors vs Number of DUCs Enabled Number of Streams (JESD_M) Interpolation Factors Supported (LT) DUCs Enabled 2 2-256x DUC0 4 4-256x DUC0, DUC1 6 8-256x DUC0, DUC1, DUC2 8 8-256x DUC0, DUC1, DUC2, DUC3 The NCOs and mixer can be bypassed, essentially setting the frequency and phase to 0, in which case the I input passes to the I output and the Q input passes to the Q output.

7.3.6.1.1 Interpolation Filters

The first operation of the DUC is to interpolate the input signal to a higher data rate. The available interpolation options are summarized in Table 7-8. The sampling rate of the input signal is multiplied by the specified interpolation amount to determine the DAC output rate, subject to the maximum sample rate for the DAC39RF10-Sx and 'RFS10-Sx . These rates do not include the optional 2x interpolation for DES mode. For interpolations rates 6x and below, a reduced number of DUC channels are available. Table 7-8. Summary of Interpolation Options INTERPOLATION Maximum Number of DUC channels 2x 1 3x 1 4x 2 6x 2 8x 4 12x 4 16x 4 24x 4 32x 4 48x 4 64x 4 96x 4 128x 4 192x 4 256x 4 Each DUC contains multiple 2x or 3x interpolating filters. The filter coefficients for each filter are listed in Table 7-9 and the filters used for each interpolation factor are shown in Table 7-10. The interpolation filter composite responses are given in Figure 7-14 to Figure 7-42. The filters are designed to provide a passband bandwidth of 80% on the input bandwidth and passband ripple less than 0.01 dB. The stopband attenuation is greater than 90 dB for any signal within the passband. Table 7-9. Interpolation Filter Coefficients Filter Coefficients (Center Tap in Bold) fir1 [6 0 -19 0 47 0 -100 0 192 0 -342 0 572 0 -914 0 1409 0 -2119 0 3152 0 -4729 0 7420 0 -13334 0 41527 65536 41527 0 -13334 0 7420 0 -4729 0 3152 0 -2119 0 1409 0 -914 0 572 0 -342 0 192 0 -100 0 47 0 -19 0 6 ]*2-16 www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 103 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-9. Interpolation Filter Coefficients (continued) Filter Coefficients (Center Tap in Bold) fir2 [-12 0 84 0 -336 0 1006 0 -2691 0 10141 16384 10141 0 -2691 0 1006 0 -336 0 84 0 -12 ]*2-14 fir3 [29 0 -214 0 1209 2048 1209 0 -214 0 29 ]*2-11 fir4 [3 0 -25 0 150 256 150 0 -25 0 3 ]*2-8 fir5 [-1 0 9 16 9 0 -1 ]*2-4 fir_3x -38 -38 0 83 117 0 -214 -281 0 464 584 0 -900 -1102 0 1612 1929 0 -2713 -3190 0 4346 5040 0 -6699 -7684 0 10023 11408 0 -14701 -16661 0 21389 24260 0 -31417 -35960 0 48101 56540 0 -82781 -105224 0 215190 432780 524288 432780 215190 0 -105224 -82781 0 56540 48101 0 -35960 -31417 0 24260 21389 0 -16661 -14701 0 11408 10023 0 -7684 -6699 0 5040 4346 0 -3190 -2713 0 1929 1612 0 -1102 -900 0 584 464 0 -281 -214 0 117 83 0 -38 -38 ]*2-19 Table 7-10. Filters Used vs. DUC Interpolation Factor DUC Interpolation Factor (LDUC) Filters Used in DUC 1st Filter 2nd Filter 3rd Filter 4th Filter 5th Filter 6th Filter 7th Filter 8th Filter 2x fir1 3x fir_3x 4x fir1 fir2 6x fir_3x fir2 8x fir1 fir2 fir3 12x fir_3x fir2 fir3 16x fir1 fir2 fir3 fir4 24x fir_3x fir2 fir3 fir4 32x fir1 fir2 fir3 fir4 fir5 48x fir_3x fir2 fir3 fir4 fir5 64x fir1 fir2 fir3 fir4 fir5 fir5 96x fir_3x fir2 fir3 fir4 fir5 fir5 128x fir1 fir2 fir3 fir4 fir4 fir5 fir5 192x fir_3x fir2 fir3 fir4 fir4 fir5 fir5 256x fir1 fir2 fir3 fir4 fir4 fir4 fir5 fir5 N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-14. 2x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-15. 2x Interpolation Filter Passband Response DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-22. 8x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-23. 8x Interpolation Filter Passband Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-24. 12x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-25. 12x Interpolation Filter Passband Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-26. 16x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-27. 16x Interpolation Filter Passband Response DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-34. 64x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-35. 64x Interpolation Filter Passband Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-36. 96x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) 0 0 . 0 0 1 0 . 0 0 2 0 . 0 0 3 0 . 0 0 4 - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-37. 96x Interpolation Filter Passband Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-38. 128x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-39. 128x Interpolation Filter Passband Response DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-40. 192x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-41. 192x Interpolation Filter Passband Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 Figure 7-42. 256x Interpolation Filter Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Magnitude Response (dB) 0 0 . 0 0 0 4 0 . 0 0 0 8 0 . 0 0 1 2 0 . 0 0 1 5 6 2 5 - 0 . 0 0 1 - 0 . 0 0 0 8 - 0 . 0 0 0 6 - 0 . 0 0 0 4 - 0 . 0 0 0 2 0 . 0 0 0 2 0 . 0 0 0 4 0 . 0 0 0 6 0 . 0 0 0 8 0 . 0 0 1 Figure 7-43. 256x Interpolation Filter Passband Response

7.3.6.1.2 Numerically Controlled Oscillator (NCO)

Each DUC has an NCO block that is capable of phase continuous frequency hopping and phase coherent frequency hopping through a NCO with 64-bit frequency and 16-bit phase words. The NCO provides the complex sinusoid that is used for the complex mixing operation. The NCOs can also be used with DDS mode to generate a tone without using the DUC filter path. The NCO updates modes are either Phase-continuous (see Phase-continuous NCO Update Mode ), Phase- coherent (see Phase-coherent NCO Update Mode or Phase-sync (see Phase-sync NCO Update Mode). The NCO frequency is written to the NCO frequency word register setting through either the standard SPI interface or through the Fast Reconfiguration (FR) interface, which allows for faster frequency updates. The frequency update occurs either as soon as the new frequency word is written or once triggered by the chosen trigger source. Available trigger sources are a SPI register, the SYSREF signal or by replacing the LSB of the I input signal with a sync signal (determined by the NCO_SYNC_SRC register). In phase-continuous NCO update mode, the phase frequency is updated without reset of the phase accumulator, which maintains the current sinusoid phase when changing frequency to reduce discontinuities in the output response. Phase Continuous NCO Mode operation is demonstrated in Figure 7-44 and selected by programming NCO_CONT = 1 and NCO_AR = 0. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 109 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 7-44. Example Phase Continuous NCO Mode Operation The phase-coherent NCO update mode, the frequency word is updated and is multiplied by a counter to update the accumulator. This allows the phase for a particular frequency to be "coherent" with the previous usage of the frequency as if the NCO had never been tuned away from that frequency. Since the phase information is maintained by the counter, any frequency can be phase coherent. Phase Coherent NCO Mode operation is demonstrated in Figure 7-45 and selected by programming NCO_CONT = 0 and NCO_AR = 0. If alignment between multiple devices is required, then NCO_AR must be programmed to 1 during the initial NCO synchronization to align the master accumulator for all devices. Frequency 1 Frequency 2 NCO Output Frequency changed to frequency 2 Frequency changed to frequency 1 Figure 7-45. Example Phase Coherent NCO Mode Operation In Phase-sync NCO update mode, the frequency word is updated (if it changed) and the accumulator is reset. This mode can be used to align the NCOs across multiple devices by providing a synchronization signal simultaneously across all devices. This mode is selected by programming NCO_AR = 1. Many systems required synchronization between DAC channels including the phase of the internal NCOs when using digital up-conversion features. Further, frequency hopping systems may have additional requirements for synchronized frequency hopping to maintain NCO synchronization during changes in NCO frequency. The device has a number of ways to update NCO changes. These include:

Synchronization through the LSB of the "I" input of DUC0 in the JESD204C input data stream
Synchronization through SYSREF
Update through SPI_SYNC register bit
Update on the rising edge of FRCS of the FRI interface if the FRS bit is set. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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The method used for NCO synchronization is controlled through the register setting. The JESD204C LSB approach allows the synchronization information to be embedded in the input data and can therefore be easily controlled by the data source (that is, FPGA). By controlling the timing of the synchronization bit across multiple devices, multi-device synchronization can be achieved. Synchronization by issuing a SYSREF pulse requires a DC coupled SYSREF interface and the ability to issue a single SYSREF pulse unless the NCO frequency is an integer multiple of the SYSREF frequency. Many systems will use AC coupled SYSREF signals which eliminates the ability to reliably issue a single SYSREF pulse. Careful timing of the SPI interface, especially for very slow SYSREF signals (< 10 MHz), may make masking and unmasking of SYSREF at multiple devices possible, however it is not characterized since the SPI path is asynchronous. With SPI_SYNC synchronization, all NCOs within the device can be updated simultaneously. The NCO blocks can be synchronized using the LSB of the "I" input of the DUC0 channel on the JESD204C interface in complex input JMODES. Control bits that replace the LSB of the data samples are used to reset the NCO phase or an NCO frequency change. Table 7-11 show how the SYNC bit replaces the I sample LSB when using LSB replacement. The LSB replacement mode is enabled when the SPI_SYNC register bit is high while NCO_SYNC_SRC is set to 3. To trigger the event, the LSB must be low for 4 or more consecutive samples, and then high for 4 consecutive samples. The sync coincides with the 4 th high sample arriving at the DUC0 input. When using the SPI to update the NCO frequency word, the user must set SPI_SYNC back to 0 to change back to the LSB representing I sample data. When using the FR interface to update the NCO, the LSB changes back to representing the I sample data after the synchronization event is triggered. Table 7-11. Bit Assignment using LSB Replacement BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I Sample I[15:1] Sync Q Sample Q[15:0] Table 7-13 and Table 7-12 show the register programming for the different NCO modes. Each NCO[ n] can have separate mode selection. Table 7-12. NCO Programming: SPI Usage (FR_EN = 0) NCO_AR[n] NCO_CONT[n] Mode

0 Phase Coherent

1 Phase Continuous

Table 7-13. NCO Programming: FRI Usage (FR_EN = 1) FR_NCO_AR[n] NCO_CONT[n] Mode

7.3.6.1.3 Mixer Scaling

The DUC mixer support complex to complex or complex to real mixing of the complex interpolated input signal with the NCO frequency. The scaling in the mixer is exactly 1:1, so a fullscale 16-bit (absolute amplitude = 32767) complex tone results in a fullscale real or complex tone at the output. If the input absolute value of the www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 111 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

complex amplitude exceeds 32767 the mixer saturates, resulting in a corrupted waveform. This is illustrated in Figure 7-46, which shows the valid circular region in white and invalid corners in grey. I Q +32767 +32767-32767 -32767 32767 Grey = mixer satura on region white = no mixer satura on region Figure 7-46. Mixer Saturation Region for the 16-bit Complex Input

7.3.6.2 Channel Bonder

The channel bonder sits after the DUC blocks and is used to combine the outputs of the DUCs. A block diagram for one DAC channel is shown in Figure 7-47 . The DUC outputs can be scaled by 1 (0 dB), 0.5 (-6 dB) or 0.25 (-12 dB) as set by the DUC_GAIN registers to prevent saturation when summing the signals. The signals are summed at full precision as determined by the settings of the DAC_SRC registers, and then saturation and rounding occurs on the combined signal. When the DUC outputs are real, up to four DUCs are available to be combined for each DAC. When the DUC outputs are complex, only two DUCs are available per DAC. The channel bonder can combine any combination of the real or complex DUC outputs for each DAC. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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DUC_GAIN0DUC0 sum saturate round DUC_GAIN1DUC1 DUC_GAIN2 DUC_GAIN3 DESDAC DAC DUC2(I) or DUC0(Q) DUC3(I) or DUC1(Q) DAC_SRCx[1] DAC_SRCx[0] DAC_SRCx[2] DAC_SRCx[3] Figure 7-47. Channel Bonder Block Diagram

7.3.6.3 DES Interpolator

The output of the summation block or the non-interpolated input signal can optionally be interpolated by 2x by the DES interpolator to double the sample rate for DES2XL and DES2XH output modes. The DES interpolator has a passband bandwidth of 80%, stopband attenuation of 54dB and ripple less than ±0.02dB. The DES interpolator can operate as high pass (DES2XH) or low pass (DES2XL) with an inverted spectrum. The DES2X filter coefficients are listed in Table 7-14 and the responses are shown in Figure 7-48, with the passband ripple for DES2XL shown in Figure 7-49.The sample rate after interpolation is 2*f CLK due to having samples on both the rising and falling edges, so the x-axis in Figure 7-48 covers the Nyquist zone. Table 7-14. DES2X Filter Coefficients Filter Coefficients (center tap is in bold) DES2X [-9 0 19 0 -39 0 70 0 -122 0 211 0 -403 0 1293 2048 1293 0 -403 0 211 0 -122 0 70 0 -39 0 19 0 -9 ]*2-11 www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 113 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

N o r m a l i z e d F r e q u e n c y ( / F C L K ) Amplitude (dB) - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 1 0 2 0 D E S 2 X L D E S 2 X H Figure 7-48. DES Interpolator Frequency Response N o r m a l i z e d F r e q u e n c y ( / F C L K ) Amplitude (dB) - 0 . 1 - 0 . 0 8 - 0 . 0 6 - 0 . 0 4 - 0 . 0 2 0 . 0 2 0 . 0 4 0 . 0 6 0 . 0 8 0 . 1 Figure 7-49. DES Interpolator Frequency Response (Passband)

7.3.7 JESD204C Interface

The devices uses a JESD204C high-speed serial interface to transfer data from the logic device to the receiving DAC. The device serial lanes are capable of operating with both 8b/10b encoding and 64b/66b encoding. The JESD204C formats using 8b/10b encoding are backwards compatible with existing JESD204B receivers. A maximum of 16 lanes can be used to lower lane rates for interfacing with speed limited logic devices. There are a few differences between 8b/10b and 64b/66b encoding, which is highlighted throughout this section. Figure 7-50 shows a simplified block diagram of the 8b/10b encoded JESD204C interface and Figure 7-51 shows a simplified block diagram of the 64b/66b encoded JESD204C interface. DAC TRANSPORT LAYER SCRAMBLER (Optional) SERDES TX PHY 8b/10b LINK LAYER APPLICATION LAYER TRANSPORT LAYER DESCRAMBLE (Optional) SERDES RX PHY 8b/10b LINK LAYER Logic Device JESD204B or JESD204C Block DAC Device JESD204C Block ANALOG CHANNEL Figure 7-50. Simplified JESD204C Interface Diagram with 8b/10b Encoding DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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(Required) SERDES TX PHY 64b/66b LINK LAYER APPLICATION LAYER TRANSPORT LAYER DESCRAMBLER (Required) SERDES RX PHY 64b/66b LINK LAYER Logic Device JESD204C Block DAC Device JESD204C Block ANALOG CHANNEL Figure 7-51. Simplified JESD204C Interface Diagram with 64b/66b Encoding Not all optional features of JESD204C are supported by the device. The list of features that are supported and the features that are not supported is provided in Table 7-15 Table 7-15. Declaration of Supported JESD204C Features LETTER IDENTIFIER FEATURE SUPPORTED BY DEVICE? a 8b/10b link layer Yes b 64b/66b link layer Yes c 64b/80b link layer No d The command channel when using 64b/66b or 64b/80b link layer No e Forward error correction (FEC) when using the 64b/66b or 64b/80b link layer No f CRC3 when using the 64b/66b or 64b/80b link layer No g A physical SYNC pin when using the 8b/10b link layer Yes h Subclass 0 Yes i Subclass 1 Yes j Subclass 2 No k Lane alignment within a single link Yes l Subclass 1 with support for lane alignment on a multipoint link by means of the MULTIREF signal No m SYNC interface timing compatible with JESD204A Yes n SYNC interface timing compatible with JESD204B Yes The various signals used in the JESD204C interface and the associated device pin names are summarized briefly in Table 7-16 for reference. Table 7-16. Summary of JESD204C Signals SIGNAL NAME DEVICE PIN NAMES DESCRIPTION Data [15:0]SRX± High-speed serialized data after 8b/10b or 64b/66b encoding that is received by the SerDes receivers. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 115 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-16. Summary of JESD204C Signals (continued) SIGNAL NAME DEVICE PIN NAMES DESCRIPTION SYNC SYNC Link initialization signal (handshake), toggles low to start code group synchronization (CGS) process. Not used for 64B/66B encoding modes. Device clock CLK+, CLK– DAC sampling clock, also used for clocking digital logic and SerDes receivers. SYSREF SYSREF+, SYSREF– System timing reference used to deterministically reset the internal local multiframe clock (LMFC) or local extended multiblock clock (LEMC) counters in each JESD204C device

7.3.7.1 Deviation from JESD204C Standard

JESD204C section 4.3.4 requires subclass 1 devices to be able to measure the amount of device clock cycles by which the detected active edge of the SYSREF signal deviates from its expected position and not to re-align the LMFC/LEMC if the deviation from the expected position is less than a programmable number of device clock cycles. This design does not contain this feature, but is compliant with JESD204B in this regard. The LMFC and other supporting clocks are aligned to the detected SYSREF if the JESD204C subsystem and SYSREF processor are enabled (and SYSREF_ALIGN_EN=1).

7.3.7.2 Transport Layer

In the transmitter (logic device) the transport layer takes samples from the application layer and maps the samples into octets inside of frames. The frames are then mapped onto the available SerDes lanes. In the receiver (DAC) the transport layer performs the inverse operation to extract samples from the serialized data. The mapping of octets into frames and frames onto lanes is defined by the transport layer settings such as L, M, F, S, N and N'. An octet is 8 bits (before 8b/10b or 64b/66b encoding), a frame consists of F octets and the frames are mapped onto L lanes. Samples are N bits, but sent as N' bits across the link. The samples come from M converters and there are S samples per converter per frame cycle. There are a number of predefined transport layer modes in the device that are defined in JESD204C Interface Modes. The various configuration parameters for JESD204C block are defined in JESD204C Interface Parameter Definitions. The link layer further maps the frames into multiframes.

7.3.7.3 Scrambler and Descrambler

A data descrambler is available in the DAC device to descramble the data after reception. Scrambling is used to remove the possibility of spectral peaks in the transmitted data due to repetitive data streams. The scrambler is optional for 8b/10b encoded mode, however it is mandatory for 64b/66b encoded mode to have sufficient spectral content for clock recovery and adaptive equalization. The scrambler operates on the data before encoding, such that the 8b/10b scrambler scrambles the 8-bit octets before 10-bit encoding and the 64b/66b scrambler scrambles the 64-bit block before the sync header insertion (66-bit encoding). The JESD204C receiver automatically synchronizes its descrambler to the incoming scrambled data stream. For 8b/10b encoding, the initial lane alignment sequence (ILAS) is never scrambled. The descrambler can be enabled by setting SCR for 8b/10b encoding mode, but it is automatically enabled in 64b/66b mode. The scrambling polynomial is different for 8b/10b encoding and 64b/66b encoding schemes as defined by the JESD204C standard.

7.3.7.4 Link Layer

The link layer serves multiple purposes in JESD204C for both 8b/10b and 64b/66b encoding modes, however there are some differences in implementation for each encoding scheme. In general, the link layer responsibilities include scrambling of the data (see Scrambler and Descrambler), establishing the code (8b/10b) DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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or block (64b/66b) boundaries and the multiframe (8b/10b) or multiblock (64b/66b) boundaries to deskew the Serdes lanes, initializing the link, encoding the data, and monitoring the health of the link.

7.3.7.5 Physical Layer

The devices JESD204C physical layer contains 16 SerDes receivers. Each SerDes lane has a Continuous Time Linear Equalizer (CTLE) for channel loss equalization.

7.3.7.6 Serdes PLL Control

The Serdes receivers work over a wide frequency range if various parameters are altered. Before setting JESD_EN, the user must program various parameters for the Serdes receivers to work. The parameters are adjusted to maintain all these constraints: 1. The VCO clock frequency (FVCO) must be between 1.5625GHz and 3.2GHz. 2. When the VCO clock frequency (FVCO) is below 2.17GHz, VRANGE must be set. 3. The REFDIV, MPY and RATE settings are all associated with a frequency change. The product of all the frequency changes must match the R value for the selected JMODE. 4. Settings with a higher PLL reference clock (and smaller MPY multiplier) are preferred. Reference Divider (REFDIV) PLL (mul plier) (MPY) Receiver (RATE) DAC Clock (FCLK) Reference Clock (FREF) VCO Clock (FVCO) Serial bit rate (per lane) (FBIT) Figure 7-52. Serdes Clock Frequency Generation www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 117 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-17. PLL Configuration Table for 8b/10b Encoding Modes R decimal (fraction) CLK Range (FCLK) (GHz) Register Values to Program Actual Frequency Multipliers Lane Bit Rate (Gbps)REFDIV MPY RATE VRANGE REFDIV MPY RATE 0.3125 (40/128) 0.3125 (40/128) 0.3125 (40/128) 10.0-12.8 0x20 0x14 0x1 1 1/32 5 2 3.125 – 4.0 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 7-18. PLL Configuration Table for 64b/66b Encoding Modes R decimal (fraction) CLK Range (FCLK) (GHz) Register Values to Program Actual Frequency Multipliers Lane Bit Rate (FBIT) (Gbps)REFDIV MPY RATE VRANGE REFDIV MPY RATE

7.3.7.7 Serdes Crossbar

The device includes a crossbar immediately after coming out of the PHY that allows mapping of signals between lanes to simplify PCB routing between the Tx and Rx which could save PCB complexity or shorten the traces (reduce loss). See LANE_SEL n . The physical layer lanes ( 0SRX± to 15SRX± ) must be routed to the appropriate JESD204C lanes (JESD0 to JESD15) based on the lanes defined in the bit packing diagrams shown in JESD204C Format Diagrams. Crossbar 0SRX+ 0SRX– 15SRX+ 15SRX– JESD204C 0SRX 15SRX JESD0 JESD15 Figure 7-53. Crossbar Block Diagram

7.3.7.8 Multi-Device Synchronization and Deterministic Latency

JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices achieve the same deterministic latency then the devices are considered synchronized. This latency must be achieved from system startup to startup to be deterministic. There are two key requirements to achieve deterministic latency. The first is proper capture of SYSREF. SYSREF resets the LMFC counter in each device to act as a known timing reference. The second requirement is to choose a proper elastic buffer release point in the receiver. The converter device is the receiver (RX) in the JESD204C link and the logic device is the transmitter (TX). The elastic buffer is the key block for achieving deterministic latency and does so by absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release point is one that provides sufficient margin against delay variations. Choosing a proper release point requires knowing the average arrival time of data at the elastic buffer, referenced to an LMFC edge, and the total expected delay variation for all devices. With this information the region of invalid release points within the LMFC period can be defined, which www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 119 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

stretches from the minimum to maximum delay for all lanes. Essentially, the designer must make sure that the data for all lanes arrives at all devices after the previous release point occurs and before the next release point occurs. The invalid region can also be found experimentally - see Programming RBD. Figure 7-54 provides a simplified timing diagram that demonstrates this requirement. In this figure, the data for two transmitters (ADC or logic device) is shown. The second transmitter (TX 2) has a longer routing distance (tPCB) and results in a longer link delay than the first transmitter (TX 1). First, the invalid region of the LMFC period is marked off as determined by the data arrival times for all devices. Then, the release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate number of quad-octet steps from the LMFC edge so that the release point occurs within the valid region of the LMFC cycle. In the case of Figure 7-54, the LMFC edge (RBD = 0) is a good choice for the release point because there is sufficient margin on each side of the valid region. TX LMFC/LEMC RX LMFC/LEMC TX 1 Data Propagation tTX tPCB tRX-DESER Time TX 2 Data Propagation tTX tPCB Invalid Region of LMFC/LEMC Valid Region of LMFC/LEMC Nominal Link Delay (Arrival at Elastic Buffer) Link Delay Variation Choose LMFC/LEMC edge as release point (RBD = 0) Release point margin tRX-DESER Figure 7-54. LMFC Valid Region Definition for Elastic Buffer Release Point Selection The TX and RX LMFC do not necessarily need to be phase aligned, but knowledge of their phase is important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within every LMFC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay can exceed a single LMFC period; see JESD204B multi-device synchronization: Breaking down the requirements for more information.

7.3.7.8.1 Programming RBD

The range of values for RBD depends on the phase delta between the Rx and Tx LMFC/LEMC, as well as link latencies in the Tx, channel, and Rx. Therefore, do not provide a pre-determined RBD value that is appropriate for all systems. The LANE_ARR registers are provided to help the user measure lane arrival times and select an appropriate RBD value for the system. For deterministic latency, the RBD value can be selected during system prototyping and stored in system firmware. Calculating RBD each time the system is turned on can result in non-deterministic latency. The arrival times are reported in units of quad-bytes and are measured with respect to a modulo-64 reference counter that increments for each quad-byte received (per lane). The reference counter is aligned (reset) by SYSREF. Since the lane arrival times are modulo-values, it is important to use arithmetic that accounts for the modulus (the latest arriving lane might actually have a smaller LANE_ARR value than the earliest arriving lane). Figure 7-55 and Figure 7-56 depict the RBD calculation graphically to emphasize this. The lane arrival times are mapped onto a circle with a circumference of 64 quad-bytes which corresponds to the modulo-64 counter used to measure lane arrival times. The earliest usable RBD value is equal to the latest LANE_ARR value plus 1 (modulo 64). The latest usable RBD value is equal to the earliest LANE_ARR value plus the buffer depth (modulo 64) (the buffer depth is 16 quad-octets, except when K x F = 32, then the buffer depth is reduced to 8 quad-octets). Note that the latest, DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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usable RBD value causes the earliest arriving lane to overwrite buffer data on the same clock cycle that the data is being read out (this is acceptable and does not cause overflow). Choosing an RBD value in the middle of the usable range maximizes the skew tolerance; however, the user can choose a value closer to the latest arriving lane if lower latency is desired. Figure 7-55. RBD Example (lane arrivals do not straddle zero) Figure 7-56. RBD Example (lane arrivals straddle zero)

7.3.7.9 Operation in Subclass 0 Systems

The device can operate with subclass 0 compatibility provided that multi-DAC synchronization and deterministic latency are not required. With these limitations, the device can operate without the application of SYSREF. The internal LMFC is automatically self-generated with unknown starting phase. RBD does not need to be programmed as the elastic buffer is released automatically just after the latest arriving lane begins to write to the elastic buffer. SYNC is used as normal to initiate the CGS and ILAS.

7.3.7.10 Link Reset

The entire link layer for all lanes is reset any time:

There is a gearbox FIFO underflow/overflow detected (LANE_ERR[0]) on a lane used by the JESD link
There is an elastic buffer overflow detected (EB_ERR) on a lane used by the JESD link
The JESD link goes down (JESD_LINK_DOWN_ALM)
SYSREF causes clock divider or LMFC/LEMC realignment (REALIGNED)
The JTimer expires (JTIMER_EXPIRED_ALM)

7.3.8 Alarm Generation

The alarm pin is useful for notifying the host controller of events that may require intervention. Any active alarms in the SYS_ALM register asserts the alarm output if they are not masked in the ALM_MASK register.

7.4 Device Functional Modes

This section describes the functional modes of the device. Some of the features in this section have been discussed in further detail in Feature Description. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

7.4.1 DUC and DDS Modes

The device contains a DUC mode and a direct digital synthesis (DDS) mode. The data path mode uses complex (I and Q) data from the JESD interface, interpolates and upconverts it in the DUCs, sums the DUC outputs and generates the analog signal in the DAC. In DDS mode, the DUC NCOs are used directly to generate tones without requiring input data. The list below summarized how DDS mode differs from DUC mode: 1. Interpolation filters are not enabled 2. JESD204C interface is not enabled 3. NCOs use less power (no complex mixing) 4. AMP register supplies unique amplitudes for each DUC (DDS) channel, allowing DDS channels to generate tones to cancel harmonic tones in the DAC output. For example, DDS channel 0 could produce a fundamental tone, channel 1 could produce a tone to cancel HD2, and channel 2 could produce a tone to cancel HD3. 5. The JMODE and DUC_L registers are ignored and the SYSREF period constraints imposed by the JESD204C system and interpolation filters are removed. See Table 7-3. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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7.4.2 JESD204C Interface Modes

Each operational mode has a limited set of available interface formats (number of lanes, resolution).

7.4.2.1 JESD204C Interface Modes

The device JESD204C modes are configured with the parameters defined in Table 7-19, Table 7-20 and Table 7-21. Table 7-19. JESD204C Interface Parameter Definitions Parameter Description JMODE JESD204C mode number. The user configures this parameter to choose a supported mode. Most other parameters are derived from this setting. See Table 7-22. LS Lanes per sample stream. This is derived from JMODE. See Table 7-22. LT Ratio of clock to input sample rate. LT = FCLK / FINPUT. A value of 0.5 indicates that the DES1X mode is enabled, and the input sampling rate is twice the DAC clock frequency (the JESD204C system provides two samples per CLK cycle). If DES1X mode is not enabled, LT equals the interpolation factor, the ratio of output to input sample rate. Not that DES2X mode does not affect the value of LT. Interpolation factor 1-256x is programmed in the DUC_L register. Lx Maximum number of lanes used for a given JMODE. The link scales down the number of active lanes (L) depending on how many channels are enabled. See JESD_M register. Mx Maximum number of streams for a given JMODE. Mx is computed automatically according to Table 7-22. The user can specify the actual number of streams (M) using the JESD_M register. R Number of bits transmitted per lane per CLK cycle. Derived from JMODE and LT (see Table 7-22). Based on R, the user must program REFDIV, MPY, and RATE registers. Additionally, the maximum CLK frequency is a function of R. SI Sample Interleaving/Increment Factor. A value of 1 indicates that the standard transport layer mapping from the JESD204C standard is used (samples are mapped linearly from 0 to S-1). A value greater than 1 indicates that an alternate mapping is used as follows: Map samples starting with sample 0, incrementing the index by SI. Repeat this as many times as necessary to map all S samples, starting each repetition at an index that is one larger than the previous repetition. See JESD Format Diagrams JESD Format Diagrams. KR For 8b/10b operation, KR defines the legal values of K (frames per multiframe). The legal values are restricted to facilitate upset immunity of the elastic buffer. The multiframe length is restricted to a multiple of the elastic buffer depth of 64 characters (buffer depth is reduced to 32 characters if K=32 and F=1). For 8b/10b modes, K is programmed via the KM1 register. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 123 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-20. JESD204C Link Parameters Parameter Description ILAS Field Name Value for this device(1) ADJCNT DAC LMFC adjustment ADJCNT[3:0] n/a ADJDIR DAC LMFC adjustment direction ADJDIR[0] n/a BID Bank ID BID[3:0] n/a CF Number of control words per frame CF[4:0] 0 CS Number. of control bits per sample CS[1:0] 0 DID Device identification number DID[7:0] n/a F Number of octets per frame (per lane) F[7:0] See Table 7-22 HD High Density Format HD[0] See Table 7-22 JESDV JESD204 Version JESDV[2:0] n/a K Number of frames per multiframe K[7:0] Set by KM1register L Number of lanes per link L[4:0] ceiling(M/Mx*Lx) LID Lane identification no. LID[4:0] n/a M Number of sample streams per link (see (1)) M[7:0] Set by JESD_M register N Bits per sample (before adding control or tail bits) for JESD204C interface. N[4:0] See Table 7-22 N' Total number of bits per sample (including control and tail bits) for JESD204C interface. N’[4:0] See Table 7-22 PHADJ Phase adjustment request to DAC PHADJ[0] n/a S Number of samples per stream per frame S[4:0] See Table 7-22 SCR Scrambling enabled SCR[0] Set by SCR register SUBCLASSV Device Subclass Version SUBCLASSV[2:0] n/a RES1 Reserved field 1 RES1[7:0] n/a RES2 Reserved field 2 RES2[7:0] n/a CHKSUM Checksum (sum of all above fields, modulo 256) FCHK[7:0] n/a (1) In 8b/10b modes, the transmitter may send link configuration octets during the ILAS. The values sent by the transmitter are not checked by this receiver, and they do not need to match the operational values of the receiver. Table 7-21. Link Parameters (applicable in 64b/66b encoding only) Parameter Description Value for this device(1) E Number of multi-blocks per extended multi-block (64b/66b encoding only) 1 Each supported mode is assigned a mode number which can be programmed into the JMODE register with the parameters listed in Table 7-22. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 7-22. JESD Interface Modes JMODE Encoding Max Input Sample Rate per Stream (MSPS) MAX Serdes Baud Rate (Gbps) R = FBIT/ FCLK N Mx = Max Streams Ls = Lanes/ Stream Lx = Max # Lanes LT = Interpolation JESD Format KR MIN MAX F S HD SI 0 8b/10b 10240 12.8 1.25 16 1 16 16 1 1 2 16 0 1 32, 64, 12864b/66b 10400 10.725 1.03125 1 8b/10b 5120 12.8 2.5/LT 16 2 8 16 1 8 2 8 0 1 32, 64, 12864b/66b 6206.1 12.8 2.0625/LT 2 8b/10b 2560 12.8 5/LT 16 4 4 16 1 16 2 4 0 1 32, 64, 12864b/66b 3103.0 12.8 4.125/LT 3 8b/10b 1280 12.8 10/LT 16 8 2 16 2 32 2 2 0 1 32, 64, 12864b/66b 1551.5 12.8 8.25/LT 4 8b/10b 640 12.8 20/LT 16 8 1 8 4 64 2 1 0 1 32, 64, 12864b/66b 775.8 12.8 16.5/LT 5 8b/10b 320 12.8 40/LT 16 8 ½ 4 8 128 4 1 0 1 16,32,64 64b/66b 387.9 12.8 33/LT 6 8b/10b 160 12.8 80/LT 16 8 ¼ 2 16 256 8 1 0 1 8,16,32 64b/66b 193.9 12.8 66/LT 7 8b/10b 80 12.8 160/LT 16 8 ⅛ 1 32 256 16 1 0 1 4,8,16 64b/66b 97.0 12.8 132/LT 8 8b/10b 12800 12.8 1/LT 12 1 16 16 0.5 1 8 80 0 16 8,16,32 64b/66b 15515.2 12.8 0.825/LT 9 8b/10b 9600 12.8 1.25 12 1 12 12 1 1 2 16 1 1 32,64, 12864b/66b 10400 10.725 1.03125 10 8b/10b 6400 12.8 2 12 2 8 16 1 1 8 40 0 8 8,16,32 64b/66b 7757.6 12.8 1.65 11 8b/10b 4800 12.8 2.5 12 2 6 12 1 1 2 8 1 1 32,64, 12864b/66b 6206.1 12.8 2.0625 12 8b/10b 3200 12.8 4 12 2 4 8 1 1 8 20 0 4 8,16,32 64b/66b 3878.8 12.8 3.3 13 8b/10b 2400 12.8 5 12 2 3 6 1 1 2 4 1 1 32,64, 12864b/66b 3103.0 12.8 4.125 14 8b/10b 20480 12.8 0.625/LT 8 1 16 16 0.5 1 1 16 0 1 32,64, 128,25664b/66b 20800 10.725 0.515625/LT 15 8b/10b 10240 12.8 1.25 8 2 8 16 1 1 1 8 0 1 32,64, 128,25664b/66b 10400 10.725 1.03125 16 8b/10b 5120 12.8 2.5 8 2 4 8 1 1 1 4 0 1 32,64, 128,25664b/66b 6206.1 12.8 2.0625 1. At minimum interpolation rate

7.4.2.2 JESD204C Format Diagrams

The following sub-sections depict each output format, showing how samples and tail bits are mapped to the lanes. Any lanes that are not shown in the output format tables are unused. Each table depicts exactly one frame. Tail bits are discarded and ignored by the transport layer. All diagrams are with respect to the logical lane numbers which can be arbitrarily mapped to the external physical lanes using LANE_SELn. Table 7-23. Format Notation Description Notation Description T Tail bits (used for some 12-bit modes) CH0_I[n] In-Phase samples for channel 0. Can also be considered as “channel A” when the input isn’t considered to be complex data. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 125 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-23. Format Notation Description (continued) Notation Description CH0_Q[n] Quadrature samples for channel 0. Can also be considered as “channel B” when the input isn’t considered to be complex data. CH1_I[n] In-Phase samples for channel 1. CH1_Q[n] Quadrature samples for channel 1. CH2_I[n] In-Phase samples for channel 2. CH2_Q[n] Quadrature samples for channel 2. CH3_I[n] In-Phase samples for channel 3. CH3_Q[n] Quadrature samples for channel 3. In all of the above notations, n indicates the sample number. Some JESD204C modes have S=1 (one sample per stream per frame). In those cases, “[n]” is omitted in the descriptions. 7.4.2.2.1 16-bit Formats Table 7-24. JMODE 0 (16-bit, 16 lanes per stream, 1 stream) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I[0] Lane 1 CH0_I[1] Lane 2 CH0_I[2] Lane 3 CH0_I[3] Lane 4 CH0_I[4] Lane 5 CH0_I[5] Lane 6 CH0_I[6] Lane 7 CH0_I[7] Lane 8 CH0_I[8] Lane 9 CH0_I[9] Lane 10 CH0_I[10] Lane 11 CH0_I[11] Lane 12 CH0_I[12] Lane 13 CH0_I[13] Lane 14 CH0_I[14] Lane 15 CH0_I[15] Table 7-25. JMODE 1 (16-bit, 8 lanes per stream, 2 streams maximum) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I[0] Lane 1 CH0_I[1] Lane 2 CH0_I[2] Lane 3 CH0_I[3] Lane 4 CH0_I[4] Lane 5 CH0_I[5] Lane 6 CH0_I[6] Lane 7 CH0_I[7] Lane 8 CH0_Q[0] Lane 9 CH0_Q[1] Lane 10 CH0_Q[2] DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 7-25. JMODE 1 (16-bit, 8 lanes per stream, 2 streams maximum) (continued) Octet 0 1 Nibble 0 1 2 3 Lane 11 CH0_Q[3] Lane 12 CH0_Q[4] Lane 13 CH0_Q[5] Lane 14 CH0_Q[6] Lane 15 CH0_Q[7] Table 7-26. JMODE 2 (16-bit, 4 lanes per stream, 4 streams maximum) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I[0] Lane 1 CH0_I[1] Lane 2 CH0_I[2] Lane 3 CH0_I[3] Lane 4 CH0_Q[0] Lane 5 CH0_Q[1] Lane 6 CH0_Q[2] Lane 7 CH0_Q[3] Lane 8 CH1_I[0] Lane 9 CH1_I[1] Lane 10 CH1_I[2] Lane 11 CH1_I[3] Lane 12 CH1_Q[0] Lane 13 CH1_Q[1] Lane 14 CH1_Q[2] Lane 15 CH1_Q[3] Table 7-27. JMODE 3 (16-bit, 2 lanes per stream, 8 streams maximum) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I[0] Lane 1 CH0_I[1] Lane 2 CH0_Q[0] Lane 3 CH0_Q[1] Lane 4 CH1_I[0] Lane 5 CH1_I[1] Lane 6 CH1_Q[0] Lane 7 CH1_Q[1] Lane 8 CH2_I[0] Lane 9 CH2_I[1] Lane 10 CH2_Q[0] Lane 11 CH2_Q[1] Lane 12 CH3_I[0] Lane 13 CH3_I[1] Lane 14 CH3_Q[0] www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 127 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-27. JMODE 3 (16-bit, 2 lanes per stream, 8 streams maximum) (continued) Octet 0 1 Nibble 0 1 2 3 Lane 15 CH3_Q[1] Table 7-28. JMODE 4 (16-bit, 1 lane per stream, 8 streams maximum) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I Lane 1 CH0_Q Lane 2 CH1_I Lane 3 CH1_Q Lane 4 CH2_I Lane 5 CH2_Q Lane 6 CH3_I Lane 7 CH3_Q Table 7-29. JMODE 5 (16-bit, 1/2 lane per stream, 8 streams maximum) Octet 0 1 2 3 Nibble 0 1 2 3 4 5 6 7 Lane 0 CH0_I CH0_Q Lane 1 CH1_I CH1_Q Lane 2 CH2_I CH2_Q Lane 3 CH3_I CH3_Q Table 7-30. JMODE 6 (16-bit, 1/4 lane per stream, 8 streams maximum) Octet 0 1 2 3 4 5 6 7 Nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 0 CH0_I CH0_Q CH1_I CH1_Q Lane 1 CH2_I CH2_Q CH3_I CH3_Q Table 7-31. JMODE 7 (16-bit, 1/8 lane per stream, 8 streams maximum) Octet 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Lane 0 CH0_I CH0_Q CH1_I CH1_Q CH2_I CH2_Q CH3_I CH3_Q 7.4.2.2.2 12-bit Formats Table 7-32. JMODE 8 (12-bit, 16 lanes per stream, 1 stream) Octet 0 1 2 3 4 5 6 7 Nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 0 CH0_I[0] CH0_I[16] CH0_I[32] CH0_I[48] CH0_I[64] T Lane 1 CH0_I[1] CH0_I[17] CH0_I[33] CH0_I[49] CH0_I[65] T Lane 2 CH0_I[2] CH0_I[18] CH0_I[34] CH0_I[50] CH0_I[66] T Lane 3 CH0_I[3] CH0_I[19] CH0_I[35] CH0_I[51] CH0_I[67] T Lane 4 CH0_I[4] CH0_I[20] CH0_I[36] CH0_I[52] CH0_I[68] T Lane 5 CH0_I[5] CH0_I[21] CH0_I[37] CH0_I[53] CH0_I[69] T Lane 6 CH0_I[6] CH0_I[22] CH0_I[38] CH0_I[54] CH0_I[70] T Lane 7 CH0_I[7] CH0_I[23] CH0_I[39] CH0_I[55] CH0_I[71] T Lane 8 CH0_I[8] CH0_I[24] CH0_I[40] CH0_I[56] CH0_I[72] T DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 7-32. JMODE 8 (12-bit, 16 lanes per stream, 1 stream) (continued) Octet 0 1 2 3 4 5 6 7 Nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 9 CH0_I[9] CH0_I[25] CH0_I[41] CH0_I[57] CH0_I[73] T Lane 10 CH0_I[10] CH0_I[26] CH0_I[42] CH0_I[58] CH0_I[74] T Lane 11 CH0_I[11] CH0_I[27] CH0_I[43] CH0_I[59] CH0_I[75] T Lane 12 CH0_I[12] CH0_I[28] CH0_I[44] CH0_I[60] CH0_I[76] T Lane 13 CH0_I[13] CH0_I[29] CH0_I[45] CH0_I[61] CH0_I[77] T Lane 14 CH0_I[14] CH0_I[30] CH0_I[46] CH0_I[62] CH0_I[78] T Lane 15 CH0_I[15] CH0_I[31] CH0_I[47] CH0_I[63] CH0_I[79] T Table 7-33. JMODE 9 (12-bit, 12 lanes per stream, 1 stream) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I[0] CH0_I[1][11:8] Lane 1 CH0_I[1][7:0] CH0_I[2] [11:4] Lane 2 CH0_I[2] [3:0] CH0_I[3] Lane 3 CH0_I[4] CH0_I[5][11:8] Lane 4 CH0_I[5][7:0] CH0_I[6] [11:4] Lane 5 CH0_I[6] [3:0] CH0_I[7] Lane 6 CH0_I[8] CH0_I[9][11:8] Lane 7 CH0_I[9][7:0] CH0_I[10] [11:4] Lane 8 CH0_I[10] [3:0] CH0_I[11] Lane 9 CH0_I[12] CH0_I[13][11:8] Lane 10 CH0_I[13][7:0] CH0_I[14] [11:4] Lane 11 CH0_I[14] [3:0] CH0_I[15] Table 7-34. JMODE 10 (12-bit, 8 lanes per stream, 2 streams maximum) Octet 0 1 2 3 4 5 6 7 Nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 0 CH0_I[0] CH0_I[8] CH0_I[16] CH0_I[24] CH0_I[32] T Lane 1 CH0_I[1] CH0_I[9] CH0_I[17] CH0_I[25] CH0_I[33] T Lane 2 CH0_I[2] CH0_I[10] CH0_I[18] CH0_I[26] CH0_I[34] T Lane 3 CH0_I[3] CH0_I[11] CH0_I[19] CH0_I[27] CH0_I[35] T Lane 4 CH0_I[4] CH0_I[12] CH0_I[20] CH0_I[28] CH0_I[36] T Lane 5 CH0_I[5] CH0_I[13] CH0_I[21] CH0_I[29] CH0_I[37] T Lane 6 CH0_I[6] CH0_I[14] CH0_I[22] CH0_I[30] CH0_I[38] T Lane 7 CH0_I[7] CH0_I[15] CH0_I[23] CH0_I[31] CH0_I[39] T Lane 8 CH0_Q[0] CH0_Q[8] CH0_Q[16] CH0_Q[24] CH0_Q[32] T Lane 9 CH0_Q[1] CH0_Q[9] CH0_Q[17] CH0_Q[25] CH0_Q[33] T Lane 10 CH0_Q[2] CH0_Q[10] CH0_Q[18] CH0_Q[26] CH0_Q[34] T Lane 11 CH0_Q[3] CH0_Q[11] CH0_Q[19] CH0_Q[27] CH0_Q[35] T Lane 12 CH0_Q[4] CH0_Q[12] CH0_Q[20] CH0_Q[28] CH0_Q[36] T Lane 13 CH0_Q[5] CH0_Q[13] CH0_Q[21] CH0_Q[29] CH0_Q[37] T Lane 14 CH0_Q[6] CH0_Q[14] CH0_Q[22] CH0_Q[30] CH0_Q[38] T Lane 15 CH0_Q[7] CH0_Q[15] CH0_Q[23] CH0_Q[31] CH0_Q[39] T www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 129 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 7-35. JMODE 11 (12-bit, 6 lanes per stream, 2 streams maximum) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I[0] CH0_I[1][11:8] Lane 1 CH0_I[1][7:0] CH0_I[2] [11:4] Lane 2 CH0_I[2] [3:0] CH0_I[3] Lane 3 CH0_I[4] CH0_I[5][11:8] Lane 4 CH0_I[5][7:0] CH0_I[6] [11:4] Lane 5 CH0_I[6] [3:0] CH0_I[7] Lane 6 CH0_Q[0] CH0_Q[1][11:8] Lane 7 CH0_Q[1][7:0] CH0_Q[2] [11:4] Lane 8 CH0_Q[2] [3:0] CH0_Q[3] Lane 9 CH0_Q[4] CH0_Q[5][11:8] Lane 10 CH0_Q[5][7:0] CH0_Q[6] [11:4] Lane 11 CH0_Q[6] [3:0] CH0_Q[7] Table 7-36. JMODE 12 (12-bit, 4 lanes per stream, 2 streams maximum) Octet 0 1 2 3 4 5 6 7 Nibble 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 0 CH0_I[0] CH0_I[4] CH0_I[8] CH0_I[12] CH0_I[16] T Lane 1 CH0_I[1] CH0_I[5] CH0_I[9] CH0_I[13] CH0_I[17] T Lane 2 CH0_I[2] CH0_I[6] CH0_I[10] CH0_I[14] CH0_I[18] T Lane 3 CH0_I[3] CH0_I[7] CH0_I[11] CH0_I[15] CH0_I[19] T Lane 4 CH0_Q[0] CH0_Q[4] CH0_Q[8] CH0_Q[12] CH0_Q[16] T Lane 5 CH0_Q[1] CH0_Q[5] CH0_Q[9] CH0_Q[13] CH0_Q[17] T Lane 6 CH0_Q[2] CH0_Q[6] CH0_Q[10] CH0_Q[14] CH0_Q[18] T Lane 7 CH0_Q[3] CH0_Q[7] CH0_Q[11] CH0_Q[15] CH0_Q[19] T Table 7-37. JMODE 13 (12-bit, 3 lanes per stream, 2 streams maximum) Octet 0 1 Nibble 0 1 2 3 Lane 0 CH0_I[0] CH0_I[1][11:8] Lane 1 CH0_I[1][7:0] CH0_I[2] [11:4] Lane 2 CH0_I[2] [3:0] CH0_I[3] Lane 3 CH0_I[4] CH0_I[5][11:8] Lane 4 CH0_I[5][7:0] CH0_I[6] [11:4] Lane 5 CH0_I[6] [3:0] CH0_I[7] 7.4.2.2.3 8-bit Formats Table 7-38. JMODE 14 (8-bit, 16 lanes per stream, 1 stream) Octet 0 Nibble 0 1 Lane 0 CH0_I[0] Lane 1 CH0_I[1] Lane 2 CH0_I[2] Lane 3 CH0_I[3] Lane 4 CH0_I[4] Lane 5 CH0_I[5] DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 7-38. JMODE 14 (8-bit, 16 lanes per stream, 1 stream) (continued) Octet 0 Nibble 0 1 Lane 6 CH0_I[6] Lane 7 CH0_I[7] Lane 8 CH0_I[8] Lane 9 CH0_I[9] Lane 10 CH0_I[10] Lane 11 CH0_I[11] Lane 12 CH0_I[12] Lane 13 CH0_I[13] Lane 14 CH0_I[14] Lane 15 CH0_I[15] Table 7-39. JMODE 15 (8-bit, 8 lanes per stream, 2 streams maximum) Octet 0 Nibble 0 1 Lane 0 CH0_I[0] Lane 1 CH0_I[1] Lane 2 CH0_I[2] Lane 3 CH0_I[3] Lane 4 CH0_I[4] Lane 5 CH0_I[5] Lane 6 CH0_I[6] Lane 7 CH0_I[7] Lane 8 CH0_Q[0] Lane 9 CH0_Q[1] Lane 10 CH0_Q[2] Lane 11 CH0_Q[3] Lane 12 CH0_Q[4] Lane 13 CH0_Q[5] Lane 14 CH0_Q[6] Lane 15 CH0_Q[7] Table 7-40. JMODE 16 (8-bit, 4 lanes per stream, 2 streams maximum) Octet 0 Nibble 0 1 Lane 0 CH0_I[0] Lane 1 CH0_I[1] Lane 2 CH0_I[2] Lane 3 CH0_I[3] Lane 4 CH0_Q[0] Lane 5 CH0_Q[1] Lane 6 CH0_Q[2] Lane 7 CH0_Q[3] www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 131 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

7.4.3 NCO Synchronization Latency

There are two deterministic methods for synchronizing the NCO (frequency or phase change, accumulator reset): through an LSB of the JESD204C interface or via SYSREF. The latency parameters for each sychronization method are listed in Table 7-41. Using SYSREF as the Synchronization source, the latency parameter T SYSREF_NCO is the time between the moment SYSREF is sampled high by CLK and the arrival of the NCO change at the DAC output. The alignment to the data path samples can be calculated by the Excel spreadsheet latency calculator discussed in Section 7.4.4. When using the JESD204C interface LSB, the latency parameter T JSYNC_NCO is the difference in time of the NCO synchronization event relative to the corresponding data sample aligned with the LSB. T JSYNC_NCO is deterministic, but for some modes depends on the alignment of the LSB rising edge to the multiframe boundary (see Table 7-42). Table 7-41. NCO Synchronization Latency Parameters Latency Parameter Description Value TSYSREF_NCO Latency from SYSREF sampled high (by CLK) to DAC output reacting to an NCO synchronization event (that was triggered by SYSREF).

477.5 CLK cycles

TJSYNC_NCO The latency through the interpolation filter(s) to the NCO minus the latency of the LSB that synchronizes the NCO. Applies only when using the LSB of the input data to synchronize the NCO. To make input sample n be the first sample to be mixed with a new NCO frequency or phase, the LSB should be brought high on sample n’ = n+TJSYNC_NCO/LT. Note that n’ may not be an integer as the synchronization path is not always a whole number of input sample periods. See Table 7-42 Table 7-42. TJSYNC_NCO vs. LT Interpolation Factor (LT) TJSYNC_NCO CLK cycles 6 34, 40, 42, 46, 48, 52, 54, 60 8 86, 94 12 186, 194, 198, 206 16 290 24 458, 466 32 648 48 968 64 1396 96 2036 128 2932 192 4212 256 6004 (1) When multiple values are listed, it indicates that TJSYNC_NCO depends on when the LSB rises with respect to the multiframe boundary.

7.4.4 Data Path Latency

There are several difference latencies defined for the device as shown in Figure 7-57 and listed in Table 7-43. The latency within the device is dependent on the mode of operation, including JMODE, Interpolation factor, RBD setting, NCO usage and DES setting. An Excel spreadsheet calculator is provided by TI to calculate the device latency in different modes of operation. In JESD204C subclass 0 operation, the latency from Serdes input to DAC output is called T DAC_LAT0 and is not deteriministic and a minimum and maximum range is provided in the Excel spreadsheet calculator. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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In JESD204C subclass 1 operation, the latency T DAC_LAT from the SYSREF input to DAC output is deterministic and is provided in the Excel spreadsheet calculator. The JESD204C link latency is deterministic as long as SYSREF is sampled reliably and the RBD value is set properly. SYSREF Processor Delay Embed mul frame/ EMB ming info PHY Layer + Link Layer + RxFIFO setup me Scramble, Encode, Serialize RxFIFO (Hold data un l release) RBD Delay SYSREF Process Delay (TRxLMFC) App/ Transport Layer Tx RxLMFC Release FIFO Rx Inequalities must me met for deterministic link operation. Adjust RBD to make inequalities true. red_path(max) < blue_path + n*TMF red_path(min) > blue_path + (n-1)*TMF n is any integer (typically 0, 1, or 2) TMF is the period of the multiframe/EMBSYSREF JESD204C Link (Determinis c Latency) (determinis (determinis c) (determinis c) (non-determinis c) (non-determinis TRxIN (determinis DUC, DAC DAC Output TDAC_LAT TRELEASE PCB Traces Link-to- Trans bu er Transport Layer Transport & Applica on Layer (determinis JMODE, DUC_L, RBD DUC_L, NCO_EN, DES2X JMODE, DUC_L Delay Dependancies TDAC_LAT0 (subclass 0 only) Figure 7-57. Definition of Device Latencies Table 7-43. Latency Definitions Latency Parameter Definition TRELEASE Latency from the rising edge of CLK that follows the rising edge of SYSREF to release event for elastic buffer. (subclass 1 only). TDAC_LAT Latency from the rising edge of CLK that follows the rising edge of SYSREF to the time of the first sample at the DAC output of the multiframe/extended multiblock launched by SYSREF (subclass 1 only). TRxIN Latency from the receiver data inputs to the elastic buffer input, including the minimum setup time of the elastic buffer. This is non-deterministic, so a minimum and maximum limit are provided. TDAC_LAT0 Latency from receiver data inputs (multiframe/EMB boundary) to first sample of a multiframe launched on DAC output. This is non-deterministic, so a minimum and maximum limit are provided (subclass 0 only). www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 133 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

7.5 Programming

The device contains two programming interfaces: a SPI interface and a Fast Reconfiguration (FR) interface for fast programming of NCO frequency and phase.

7.5.1 Using the Standard SPI Interface

The standard SPI interface is accessed using the following four pins: serial clock (SCLK), serial data in (SDI), serial data out (SDO), and serial interface chip-select ( SCS). Register access is enabled through the SCS pin.

7.5.1.1 SCS

This signal must be asserted low to access a register through the serial interface. Setup and hold times with respect to the SCLK must be observed.

7.5.1.2 SCLK

Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.

7.5.1.3 SDI

Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write (R/W) bit, register address, and register value. The data are shifted in MSB first and multi-byte registers are always in little-endian format (least significant byte stored at the lowest address). Setup and hold times with respect to the SCLK must be observed (see the Switching Characteristics table).

7.5.1.4 SDO

The SDO signal provides the output data requested by a read command. This output is high impedance during write bus cycles and during the read bit and register address portion of read bus cycles.

7.5.1.5 Serial Interface Protocol

As shown in Figure 7-58, each register access consists of 24 bits. The first bit is high for a read and low for a write. The next 15 bits are the address of the register that is to be written to. During write operations, the last eight bits are the data written to the addressed register. During read operations, the last eight bits on SDI are ignored and, during this time, the SDO outputs the data from the addressed register. Figure 7-58 shows the serial protocol details. SCLK 1 24 Single Register Access SCS SDI Command Field Data Field SDO (read mode) Data Field High Z High Z 17168 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 R/W Figure 7-58. Serial Interface Protocol: Single Read and Write DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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7.5.1.6 Streaming Mode

The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction specifies the access type, register address, and data value as normal. Additional clock cycles of write or read data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The register address auto increments (default) or decrements for each subsequent 8-bit transfer of the streaming transaction. The ASCEND bit (register 000h, bit 5) controls whether the address value ascends (increments) or descends (decrements). Figure 7-59 shows the streaming mode transaction details. SCLK 1 24 Multiple Register Access SCS SDI Command Field Data Field (write mode) SDO (read mode) Data Field High Z 17168 32 Data Field High Z Data Field (write mode) A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 7-59. Serial Interface Protocol: Streaming Read and Write

7.5.2 Using the Fast Reconfiguration Interface

The FR interface provides fast write-only access to configure NCO frequencies and synchronization. The FR interface is similar to the SPI interface, but 4 bits are sent per clock cycle. The FR timing diagram is shown in Figure 7-60 . It uses a R/W bit (always Write for this device), a transaction sync bit (FRS), and 14-bits of address followed by some number of data bytes. The address is decremented after each data byte (consistent with little-endian). The interface is byte addressable and data is committed after each byte. The FR interface is takes 4-bits (one nibble) per clock. For multi-nibble fields, data is sent most-significant nibble first. When the transaction sync bit (FRS) is set, the synchronization event specified in the NCO_SYNC_SRC register field occurs at the rising edge of FRCS. Transactions ended before the completion of the first data byte may not trigger the sync event. FRCS FRCLK FRDI[3] RW A[11] A[7] A[3] D[7] D[3] Address A Address A-1 FRS A[10] A[6] A[2] D[6] D[2] FRDI[2] FRDI[1] FRDI[0] D[7] D[3] D[6] D[2] D[5] D[1] D[4] D[0] Figure 7-60. FR Interface Timing Diagram www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 135 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

The FR interface registers are listed in Table 7-44. There are two registers that can change the NCO frequency - FR_FREQL[3:0] is 64-bits for each NCO and changes the entire frequency word. FR_FREQS[3:0] is 32-bits for each NCO and changes only the upper 32-bits of the frequency word, providing for faster frequency changes. Table 7-44. FR Interface Registers Address Name Description 0x00FF FR_NCO_AR FR NCO Accumulator Reset (default: 0x0f) [7:4] RESERVED [3:0] FR_NCO_AR For each bit FR_NCO_AR[n], if set, the accumulator for NCOn is reset on every sync event specified by NCO_SYNC_SRC. Note: This register has no effect when FR_EN=0. 0x0100-0x011F FR_FREQL[3:0] FR 64-bit Frequency for NCO Accumulator (default for FR_FREQL[n]=0x00) The frequency setting for FR_FREQL[0] is at the lowest address. [63:0] FR_FREQL[n] This register is used instead of FREQ[n] when FR_EN=1. Changes to the upper 32-bits of this register also change FR_FREQS[n]. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register has no effect when FR_EN=0. 0x0120-0x0127 FR_PHASE[3:0] FR Phase for NCO Accumulator (default for FR_PHASE[n]=0x0000) The phase setting for FR_PHASE[0] is at the lowest address. [15:0] FR_PHASE[n] This register is used instead of PHASE[n] when FR_EN=1. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register has no effect when FR_EN=0. 0x0128-0x0137 FR_FREQS[3:0] FR 32-bit Frequency for NCO Accumulator (default for FR_FREQS[n]=0x00) The frequency setting for FR_FREQS[0] is at the lowest address. [31:0] FR_FREQS[n] This register is used instead of FREQ[n] when FR_EN=1. Changes to this register also change the upper 32-bits of FR_FREQL[n]. This register only controls the upper 32-bits of the frequency. The lower 32-bits of the frequency are always controlled by FR_FREQL[n]. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register has no effect when FR_EN=0. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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8 SPI Register Map

Table 8-1 lists the SPI registers. All register offset addresses not listed in Table 8-1 should be considered as reserved locations and the register contents should not be modified. Reserved register fields in addresses with non-reserved R/W fields always return the default/reset value during read, not the written value. Table 8-1. SPI Registers Offset Acronym Register Name Section 0x0000 CONFIG_A Configuration A Go 0x0002 DEVICE_CONFIG Device Configuration Go 0x0003 CHIP_TYPE Chip Type Go 0x0004 CHIP_ID Chip Identification Go 0x0006 CHIP_VERSION Chip Version Go 0x000C VENDOR_ID Vendor Identification Go 0x0010-0x007F RESERVED 0x0080 SYSREF_CTRL SYSREF Control Go 0x0081-0x008F RESERVED 0x0090-0x0092 SYSREF_POS SYSREF Capture Position Go 0x0093-0x009F RESERVED 0x00A0 SYSREF_ALIGN SYSREF Alignment Control Go 0x00A1 SYSREF_TERM SYSREF Termination Configuration Go 0x00A2-0x00FF RESERVED 0x0100 JESD_EN JESD204C Subsystem Enable Go 0x0101 JMODE JESD204C Mode Go 0x0102 JESD_M JESD204C Number of Streams Go 0x0103 JCTRL JESD204C Control Go 0x0104 SHMODE JESD204C Sync Word Mode Go 0x0105 KM1 JESD204C K Parameter Go x0106 RBD JESD204C Release Buffer Delay Go 0x0107 JESD_STATUS JESD204C System Status Register Go 0x0108 REFDIV JESD204C Reference Divider Go 0x0109 MPY JESD204C PLL Multiplier Go 0x010A RATE JESD204C Receive Rate Go 0x010B LB_VRANGE JESD204C VCO Range Go 0x010C-0x011F RESERVED 0x0120 JSYNC_N JESD204C Manual Sync Request Go 0x0121 JTEST JESD204C Test Control Go 0x0122-0x0123 RESERVED RESERVED 0x0124 JTIMER JESD204C Watchdog Timer Go 0x0125-0x0126 RESERVED 0x0127 SYNC_EPW JESD204C SYNC Error Report Pulse Width Go 0x0128 CRC_TH JESD204C CRC Error Thresholds Go 0x0129-0x012B RESERVED 0x012C LANE_ARSTAT Lane Arrival Status Go 0x012D RESERVED 0x012E-0x012F LANE_INV PHY Lane Inversion Go 0x0130-0x013F LANE_SEL[15:0] PHY Lane Select for Logical Lane n Go 0x0140-0x014F LANE_ARR[15:0] Lane n Arrival Time Go 0x0150-0x015F LANE_STATUS[15:0] Lane n Status Go www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 137 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-1. SPI Registers (continued) Offset Acronym Register Name Section 0x0160-0x016F LANE_ERR[15:0] Lane n Error Flags Go 0x0170-0x017F FIFO_STATUS[15:0] Gearbox FIFO Status for Logical Lane n Go 0x0180-0x0189 RESERVED 0x018A-0x019F RESERVED 0x01A0 BER_EN BER Measurement Control Go 0x01A1-0x01AF RESERVED 0x01B0-0x01BF BER_CNT[15:0] BER Error Count for Lane n Go 0x01C0 RESERVED 0x01C1 JPHY_CTRL SerDes PHY Control Go 0x01C2 EQ_CTRL SerDes Equalizer Control Go 0x01C3 EQZERO SerDes Equalizer Zero Go 0x01D0-0x01DF LANE_EQ[15:0] SerDes Equalizer Level for Lane n Go 0x01E0-0x01EF LANE_EQS[15:0] SerDes Equalizer Status for Lane n Go 0x1F0 ESRUN SerDes Eye-Scan Run Control Go 0x01F1 ES_CTRL SerDes Eye-Scan Control Go 0x01F2 ESPO SerDes Eye-Scan Phase Offset Go 0x01F3 ESVO SerDes Eye-Scan Voltage Offset Go 0x01F4 ES_BIT_SELECT SerDes Eye-Scan Bit Select Go 0x01F5 ESCOUNT_CLR SerDes Error Counter Clear Go 0x01F6-0x01F7 ESDONE SerDes Eye-Scan Process Done Go 0x01F8-0x01FF RESERVED 0x0200-0x020F ESVO_S[15:0] SerDes Eye-Scan Voltage Offset for Lane n Go 0x0210-0x022F ECOUNT[15:0] SerDes Error/Mismatch Count for Lane n Go 0x0230-0x0233 RESERVED 0x0234 LOS_TH SerDes Loss-of_Signal Threshold Go 0x0235 EQCNTSZ SerDes Equalizer Counter Size Go 0x0236-0x237 RESERVED 0x0238 CDRLOCK SerDes CDR Lock/Freeze Go 0x0239 CDRPHASE SerDes CDR Phase Status Go 0x023A-0x024F RESERVED 0x0250 PLL_STATUS SerDes PLL Status Go 0x0251-0x0252 RESERVED 0x0253 JESD_RST JESD Reset Go 0x0254-0x02AF RESERVED 0x02B0 EXTREF_EN Enable External Reference Go 0x02B1 CUR_2X_EN DAC Current Doubler Enable Go 0x02B2-0x02C1 RESERVED 0x02C2-0x02CE RESERVED 0x02CF DAC_OFS_CHG_BLK DAC Offset Adjustment Change Block Go 0x02D0-0x02DF RESERVED 0x02E0 DP_EN Datapath Enable Go 0x02E1 DUC_L DUC Interpolation Factor Go 0x02E2 DUC_GAIN DUC Gain Go 0x02E3 DUC_FORMAT DUC Output Format Go 0x02E4 DAC_SRC DAC Source Go DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-1. SPI Registers (continued) Offset Acronym Register Name Section 0x02E5-0x02E7 RESERVED 0x02E8 MXMODE DAC Output Mode Go 0x02E9 RESERVED 0x02EA TRUNC_HLSB Truncation Half LSB Offset Go 0x02EB-0x02F7 RESERVED 0x02F8 TX_EN_SEL Transmitter Enable Control Selection Go 0x02F9 TX_EN Transmitter Enable Configuration Go 0x02FA-0x02FF RESERVED 0x0300 NCO_CTRL NCO Control Go 0x0301 NCO_CONT NCO Phase Continuous Mode Go 0x0302 NCO_SYNC NCO Synchronization Configuration Go 0x0303 NCO_AR NCO Accumulator Reset Go 0x0304 SPI_SYNC SPI Sync Go 0x0305 NCO_SS NCO Continuous Self-Sync Mode Go 0x0306-0x0317 RESERVED 0x0318-0x031F AMP[3:0] DDS Amplitude Go 0x0320-0x0327 FREQ[0] Frequency for NCO0 Accumulator Go 0x0328-0x032F FREQ[1] Frequency for NCO1 Accumulator Go 0x0330-0x0337 FREQ[2] Frequency for NCO2 Accumulator Go 0x0338-0x033F FREQ[3] Frequency for NCO3 Accumulator Go 0x0340-0x0347 PHASE[3:0] Phase for NCOn Accumulator Go 0x0348-0x0377 RESERVED 0x0378-0x037F AMP_R[3:0] Readback for Amplitude Workd for NCOn Go 0x0380-0x039F FREQ_R[3:0] Readback for Frequency for NCOn Accumulator Go 0x03A0-0x03A7 PHASE_R[3:0] Readback for Phase Word for NCOn Accumulator Go 0x03A8-0x03DF RESERVED 0x03E0 FR_FRS_R Readback for FR Synchronization Go 0x03E1 FR_NCO_AR_R Readback for FR NCO Accumulator Reset Go 0x03E2-0x03FF RESERVED 0x0400 TS_TEMP Tempeature Reading in Celsius Go 0x0401 TS_SLEEP Temperature Sensor Sleep Go 0x0402-0x040F RESERVED 0x0410 SYNC_STATUS Synchronization Status Go 0x0411-0x042F RESERVED 0x0430 SYS_ALM System Alarm Status Go 0x0431 ALM_MASK Alarm Mask Go 0x0432 MUTE_MASK DAC Mute Mask Go 0x0433 MUTE_REC DAC Mute Recovery Go 0x0434-0x05FF RESERVED 0x0600 FUSE_STATUS Fuse Status Go 0x0601-0x0722 RESERVED 0x0723 FINE_CUR_A Fine Bias Current Control for DACA Go 0x0724 COARSE_CUR_A Coarse Bias Current Control for DACA Go 0x0725 FINE_CUR_B Fine Bias Current Control for DACB Go 0x0726 COARSE_CUR_B Coarse Bias Current Control for DACB Go www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 139 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-1. SPI Registers (continued) Offset Acronym Register Name Section 0x0727 DEM_ADJ DEM Adjust Go 0x0728 RESERVED 0x0729 DEM_DITH DEM and DITHER Control Go 0x72A-0x072D DAC_OFS DAC_Offset_Adjustment Go 0x72E - 0x7FF RESERVED

8.1 CONFIG_A Register (Offset = 0h) [reset = 30h]

CONFIG_A is shown in Figure 8-1 and described in Table 8-2. Return to the Register Summary Table. Configuration A (default: 0x30) Figure 8-1. CONFIG_A Register 7 6 5 4 3 2 1 0 SOFT_RESET RESERVED ASCEND RESERVED RESERVED R/W-0h R/W-0h R/W-1h R/W-1h R/W-0h Table 8-2. CONFIG_A Register Field Descriptions Bit Field Type Reset Description

7 SOFT_RESET R/W 0h Writing a 1 to this bit causes a full reset of the chip and all SPI

registers (including CONFIG_A). This bit is self-clearing and will always read zero. After writing this bit, the part may take up to 5 ns to reset. During this time, do not perform any SPI transactions.

6 RESERVED R/W 0h

5 ASCEND R/W 1h 0 : Address is decremented during streaming reads/writes

1 : Address is incremented during streaming reads/writes (default) 4 RESERVED R 1h Always read 1. 3-0 RESERVED R/W 0h

8.2 DEVICE_CONFIG Register (Offset = 2h) [reset = 00h]

DEVICE_CONFIG is shown in Figure 8-2 and described in Table 8-3. Return to the Register Summary Table. Device Configuration (default: 0x00) Figure 8-2. DEVICE_CONFIG Register 7 6 5 4 3 2 1 0 RESERVED MODE R/W-0h R/W-0h Table 8-3. DEVICE_CONFIG Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 0h DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-3. DEVICE_CONFIG Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 MODE R/W 0h 0 : Normal operation (default) 1 : Reserved 2 : Reserved 3 : Full power down. The user should follow the recommendations in Section 9.1.6 in this mode to avoid reliability concerns.

8.3 CHIP_TYPE Register (Offset = 3h) [reset = 04h]

CHIP_TYPE is shown in Figure 8-3 and described in Table 8-4. Return to the Register Summary Table. Chip Type (read-only: 0x04) Figure 8-3. CHIP_TYPE Register 7 6 5 4 3 2 1 0 RESERVED CHIP_TYPE R/W-0h R-4h Table 8-4. CHIP_TYPE Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 CHIP_TYPE R 4h Always returns 0x4, indicating that the part is a high speed DAC.

8.4 CHIP_ID Register (Offset = 4h) [reset = 003Bh]

CHIP_ID is shown in Figure 8-4 and described in Table 8-5. Return to the Register Summary Table. Chip Identification (read-only) Figure 8-4. CHIP_ID Register 15 14 13 12 11 10 9 8 CHIP_ID R-0h 7 6 5 4 3 2 1 0 CHIP_ID R-3Bh Table 8-5. CHIP_ID Register Field Descriptions Bit Field Type Reset Description 15-0 CHIP_ID R 003Bh Always returns 0x003B indicating it is the DAC39RF10 device family

8.5 CHIP_VERSION Register (Offset = 6h) [reset = 02h]

CHIP_VERSION is shown in Figure 8-5 and described in Table 8-6. Return to the Register Summary Table. Chip Version (read-only) www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 8-5. CHIP_VERSION Register 7 6 5 4 3 2 1 0 CHIP_VERSION R-2h Table 8-6. CHIP_VERSION Register Field Descriptions Bit Field Type Reset Description 7-0 CHIP_VERSION R 02h 1: PG1.0 2: PG2.0

8.6 VENDOR_ID Register (Offset = Ch) [reset = 0451h]

VENDOR_ID is shown in Figure 8-6 and described in Table 8-7. Return to the Register Summary Table. Vendor Identification (default: 0x0451) Figure 8-6. VENDOR_ID Register 15 14 13 12 11 10 9 8 VENDOR_ID R-04h 7 6 5 4 3 2 1 0 VENDOR_ID R-51h Table 8-7. VENDOR_ID Register Field Descriptions Bit Field Type Reset Description 15-0 VENDOR_ID R 451h TI vendor ID

8.7 SYSREF_CTRL Register (Offset = 0080h) [reset = 40h]

SYSREF_CTRL is shown in Figure 8-7 and described in Table 8-8. Return to the Register Summary Table. SYSREF Control Figure 8-7. SYSREF_CTRL Register 7 6 5 4 3 2 1 0 SYSREF_PRO C_EN SYSREF_REC V_SLEEP SYSREF_PS_E N SYSREF_ZOO M SYSREF_SEL R/W-0b R/W-1b R/W-0b R/W-0b R/W-0h Table 8-8. SYSREF_CTRL Register Field Descriptions Bit Field Type Reset Description 7 SYSREF_PROC_EN R/W 0h When set, this bit enables the SYSREF processor. When this is enabled, the system receives and processes each new SYSREF edge. User should always clear SYSREF_RECV_SLEEP before setting this bit. This bit is provided to allow the SYSREF receiver to stabilize before allowing the SYSREF to come to the digital. 6 SYSREF_RECV_SLEEP R/W 1b Clear this bit to enable the SYSREF receiver circuit. User should always clear SYSREF_PROC_EN before setting this bit. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-8. SYSREF_CTRL Register Field Descriptions (continued) Bit Field Type Reset Description

5 SYSREF_PS_EN R/W 0b When set, SYSREF_POS will contain 1’s for all positions that have

been detected as near the SYSREF edge since this bit was set. When cleared, SYSREF_POS will only contain 1’s for the last SYSREF edge that was detected.

4 SYSREF_ZOOM R/W 0b Set this bit to “zoom” in the SYSREF strobe status (impacts

SYSREF_POS and the step size of SYSREF_SEL). 3-0 SYSREF_SEL R/W 0b Set this field to select which SYSREF delay to use. Set this based on the results returned by SYSREF_POS.

8.8 SYSREF_POS Register (Offset = 90h) [reset = NA]

SYSREF_POS is shown in Figure 8-8 and described in Table 8-9. Return to the Register Summary Table. SYSREF Position Capture Figure 8-8. SYSREF_POS Register 23 22 21 20 19 18 17 16 RESERVED SYSREF_POS R R 15 14 13 12 11 10 9 8 SYSREF_POS R 7 6 5 4 3 2 1 0 SYSREF_POS R Table 8-9. SYSREF_POS Register Field Descriptions Bit Field Type Reset Description 23-20 Reserved R 0x0 Reserved 19-0 SYSREF_POS R NA Returns a 20-bit status value that indicates the position of the SYSREF edge with respect to CLK. Use this to determine the proper programming for SYSREF_SEL, and SYSREF_ZOOM.

8.9 SYSREF_ALIGN Register (Offset = 00A0h) [reset = 00h]

SYSREF_ALIGN is shown in Figure 8-9 and described in Table 8-10. Return to the Register Summary Table. SYSREF Alignment Control Figure 8-9. SYSREF_ALIGN Register 7 6 5 4 3 2 1 0 RESERVED SYSREF_ALIGN_EN R/W-00h R/W-0b Table 8-10. SYSREF_ALIGN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h Reserved www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 143 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-10. SYSREF_ALIGN Register Field Descriptions (continued) Bit Field Type Reset Description

0 SYSREF_ALIGN_EN R/W 0b When this bit is set, the chip realigns to each detected SYSREF

edge. This affects both the external clock divider and the JESD subsystem. SYSREF_TERM Register (Offset = 00A1h) [reset = 00h] SYSREF_TERM is shown in Figure 8-10 and described in Table 8-11. Return to the Register Summary Table. SYSREF Termination Configruation Figure 8-10. SYSREF_TERM Register 7 6 5 4 3 2 1 0 RESERVED SYSREF_RECV_LVPECL R/W-00h R/W-0b Table 8-11. SYSREF_TERM Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h Reserved 0 SYSREF_RECV_LVPECL R/W 0b 0: SYSREF termination is 100 Ohm differential with Vcm of 0.4V 1: SYSREF termination is singled ended 50 Ohm to GND (LVPECL mode)

8.10 JESD_EN Register (Offset = 0100h) [reset = 00h]

JESD_EN is shown in Figure 8-11 and described in Table 8-12. Return to the Register Summary Table. JESD204C Subsystem Enable Figure 8-11. JESD_EN Register 7 6 5 4 3 2 1 0 RESERVED JESD_EN R/W-00h R/W-0b Table 8-12. JESD_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h

0 JESD_EN R/W 0b 0 : Disable JESD204C interface

1 : Enable JESD204C interface When JESD_EN=0, the JESD204C subsystem is held in reset and the SERDES PHY is disabled. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC. Note: This register should only be changed when DP_EN=0.

8.11 JMODE Register (Offset = 0101h) [reset = 00h]

JMODE is shown in Figure 8-12 and described in Table 8-13. Return to the Register Summary Table. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Figure 8-12. JMODE Register 7 6 5 4 3 2 1 0 RESERVED JMODE R/W-00b R/W-000000b Table 8-13. JMODE Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00b 5-0 JMODE RW 000000b Specify the JESD204C interface mode. See Table 7-22. Note: This register should only be changed when JESD_EN=0.

8.12 JESD_M Register (Offset = 0102h) [reset = 01h]

JESD_M is shown in Figure 8-13 and described in Table 8-14. Return to the Register Summary Table. JESD204C Number of Streams Figure 8-13. JESD_M Register 7 6 5 4 3 2 1 0 JESD_M R/W-0h R/W-1h Table 8-14. JESD_M Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 JESD_M R/W 1h Specify the number of sample streams to enable (JESD204C M parameter). The supported settings for JESD_M depend on the DUC interpolation (DUC_L) and Mx. LDUC: Supported Settings for JESD_M 1x: 1 or 2 (but never larger than Mx) 2x or 3x: 2 (but never larger than Mx) 4x or 6x: 2 or 4 (but never larger than Mx) 8x or higher:2, 4, 6 or 8 (but never larger than Mx) See Table 7-22 for the Mx value associated with each JMODE. The number of lanes enabled (L) is computed as: L=ceiling(M/Mx*Lx). An I/Q pair counts as two streams. For example, when inputting 4 IQ streams, program JESD_M=8. Note: This register should only be changed when JESD_EN=0 and DP_EN=0.

8.13 JCTRL Register (Offset = 0103h) [reset = 03h]

JCTRL is shown in Figure 8-14 and described in Table 8-15. Return to the Register Summary Table. JESD204C Control. This register should only be changed when JESD_EN = 0. Figure 8-14. JCTRL Register 7 6 5 4 3 2 1 0 www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 145 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 8-14. JCTRL Register (continued) RESERVED TI_MODE SUBCLASS JENC RESERVED SFORMAT SCR R/W-0b R/W-0b R/W-0b R/W-0b R/W-00b R/W-1b R/W-1b Table 8-15. JCTRL Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R/W 0b

6 TI_MODE R/W 0b 0 : JESD204C standard mode (default)

1 : TI Mode - set this when using TI FPGA transmitter IP

5 SUBCLASS R/W 0b Specify how the elastic buffer is released:

0 : Subclass 0 operation (default). Release the elastic buffer immediately once all lanes have starting writing to the buffer. 1 : Subclass 1 operation. Release the elastic buffer on a release opportunity defined by the LMFC/LEMC and RBD.

4 JENC R/W 0b 0 : Use 8b/10b link layer

1 : Use 64b/66b link layer 3-2 RESERVED R/W 0b

1 SFORMAT R/W 1b Input sample format for JESD204C samples

0 : Offset binary 1 : Signed 2’s complement (default)

0 SCR R/W 1b 0 : 8b/10b Scrambler disabled

1 : 8b/10b Scrambler enabled (default) The 8b/10b scrambler is recommended to improve spurious noise and make sure that certain sample payloads cannot prevent the JESD204C receiver from detecting incorrect code-group or lane alignment. This register has no effect on 64b/66b modes (which are always scrambled).

8.14 SHMODE Register (Offset = 0104h) [reset = 00h]

SHMODE is shown in Figure 8-15 and described in Table 8-16. Return to the Register Summary Table. JESD204C Sync Word Mode Figure 8-15. SHMODE Register 7 6 5 4 3 2 1 0 RESERVED SHMODE R/W-0b R/W-00b Table 8-16. SHMODE Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 00h DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-16. SHMODE Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 SHMODE R/W 00b Select the mode for the 64b/66b sync word (32 bits of data per multi-block). This only applies when JENC=1 (64b/66b mode). 0 : Enable CRC-12 checking (JESD204C Table 41) (default setting) 1 : RESERVED 2 : RESERVED 3 : RESERVED Note: This device does not support any JESD204C command features. All command fields are ignored by the receiver. Note: This register should only be changed when JESD_EN=0.

8.15 KM1 Register (Offset = 0105h) [reset = 1Fh]

KM1 is shown in Figure 8-16 and described in Table 8-17. Return to the Register Summary Table. JESD204C K Parameter (minus 1) Figure 8-16. KM1 Register 7 6 5 4 3 2 1 0 KM1 R/W-1Fh Table 8-17. KM1 Register Field Descriptions Bit Field Type Reset Description 7-0 KM1 R/W 1Fh K is the number of frames per multiframe, and K-1 shall be programmed here when using the 8b/10b link layer (see JENC). Depending on the JMODE setting, there are constraints on the legal values of K (see Table 7-22 and KR). Programming an illegal value for K will cause the link to malfunction. The default value is KM1=31, which corresponds to K=32. Note: For modes using the 64b/66b link layer, the KM1 register is ignored. The effective value of K is 256*E/F. Note: This register should only be changed when JESD_EN=0.

8.16 RBD Register (Offset = 106h) [reset = 00h]

RBD is shown in Figure 8-17 and described in Table 8-18. Return to the Register Summary Table. JESD204C Release Buffer Delay Figure 8-17. RBD Register 7 6 5 4 3 2 1 0 RESERVED RBD R/W-0b R/W-000000b Table 8-18. RBD Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00b www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 147 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-18. RBD Register Field Descriptions (continued) Bit Field Type Reset Description 5-0 RBD R/W 000000b This register shifts the elastic buffer release opportunities. Increasing RBD by 1 delays the release opportunities by 4 bytes (octets). The legal RBD range is 0 to K*F/4-1. For 64b/66b modes, the legal RBD range is 0 to 63. See Programming RBD. Note: This register should only be changed when JESD_EN=0.

8.17 JESD_STATUS Register (Offset = 0107h) [reset = NA]

JESD_STATUS is shown in Figure 8-18 and described in Table 8-19. Return to the Register Summary Table. JESD204C / System Status Figure 8-18. JESD_STATUS Register 7 6 5 4 3 2 1 0 EB_ERR LINK_UP JSYNC_STATE REALIGNED ALIGNED PLL_LOCKED RESERVED R/W1C R R R/W1C R R R Table 8-19. JESD_STATUS Register Field Descriptions Bit Field Type Reset Description 7 EB_ERR R/W1C NA Elastic buffer experienced underflow/overflow. Check RBD. Write a 1 to clear this bit.

6 LINK_UP R NA When set, indicates that the JESD204C link is up (elastic buffer

released). 5 JSYNC_STATE R NA Returns the state of the JESD204C SYNC signal. 0 : SYNC asserted 1 : SYNC de-asserted

4 REALIGNED R/W1C NA When any clock dividers or the LMFC/LEMC counters are realigned

by SYSREF, this bit gets set. Write a 1 to clear this bit. The behavior of this bit is undefined when SUBCLASS=0.

3 ALIGNED R NA When set, indicates that the last SYSREF pulse was consistent with

the SYSREF-associated clock dividers (including the LMFC/LEMC). This bit is read-only (cannot be cleared via SPI). After JESD_EN is set, the part may require up to 7 SYSREF pulses to achieve full alignment and set this bit. The behavior of this bit is undefined when SUBCLASS=0. 2 PLL_LOCKED R NA When high, indicates that all enabled SerDes PLLs are locked. 1-0 RESERVED R NA

8.18 REFDIV Register (Offset = 0108h) [reset = 30h]

REFDIV is shown in Figure 8-19 and described in Table 8-20. Return to the Register Summary Table. JESD204C Reference Divider Figure 8-19. REFDIV Register 7 6 5 4 3 2 1 0 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Figure 8-19. REFDIV Register (continued) RESERVED REFDIV R/W-0b R/W-30h Table 8-20. REFDIV Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00b 5-0 REFDIV R/W 30h Specifies the frequency divisor to generate the PHY PLL reference clock (FREF) from the DAC clock (FCLK). See PLL Control. The following values are legal: 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40, 48. All other values are reserved and produce undefined behavior.

8.19 MPY Register (Offset = 0109h) [reset = 14h]

MPY is shown in Figure 8-20 and described in Table 8-21. Return to the Register Summary Table. JESD204C PLL Multiplier Figure 8-20. MPY Register 7 6 5 4 3 2 1 0 MPY R/W-14h Table 8-21. MPY Register Field Descriptions Bit Field Type Reset Description 7-0 MPY R/W 14h Specifies the PLL frequency multiplier for the PHY. See PLL Control. The following values are allowed for this design: MPY: Frequency Multiplier 16 (0x10): 4 20 (0x14): 5 33 (0x21): 8.25 40 (0x28): 10 Note: This register should only be changed when JESD_EN=0.

8.20 RATE Register (Offset = 010Ah) [reset = 00h]

RATE is shown in Figure 8-21 and described in Table 8-22. Return to the Register Summary Table. JESD204C Receive Rate Figure 8-21. RATE Register 7 6 5 4 3 2 1 0 RESERVED RATE R/W-00h R/W-00b Table 8-22. RATE Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 00h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 149 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-22. RATE Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 RATE R/W 00b Controls the frequency multiplier from the PHY PLL to the serial line rate. See PLL Control. Affects all lanes. RATE: Multiplier 00b: 4 01b: 2 10b: 1 11b: 0.5 Note: This register should only be changed when JESD_EN=0.

8.21 LB_VRANGE Register (Offset = 010Bh) [reset = 00h]

LB_VRANGE is shown in Figure 8-22 and described in Table 8-23. Return to the Register Summary Table. JESD204C PLL VCO Range. Note: This register should only be changed when JESD_EN=0. Figure 8-22. LB_VRANGE Register 7 6 5 4 3 2 1 0 RESERVED VRANGE R/W-0h R/W-0b Table 8-23. LB_VRANGE Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 VRANGE R/W 0b This bit must be set if the PLL/VCO frequency is below 2.17GHz. See PLL Control.

8.22 JSYNC_N Register (Offset = 0120h) [reset = 01h]

JSYNC_N is shown in Figure 8-7 and described in Table 8-8. Return to the Register Summary Table. JESD204C Manual Sync Request Figure 8-23. JSYNC_N Register 7 6 5 4 3 2 1 0 RESERVED JSYNC_N R/W-00h R/W1C Table 8-24. JSYNC_N Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 JSYNC_N R/W 1b Set this bit to 0 to manually assert the SYNC signal. For normal operation, leave this bit set to 1. Note: Behavior of JSYNC_N=0 is undefined when JENC=1.

8.23 JTEST Register (Offset = 0121h) [reset = 00h]

JTEST is shown in Figure 8-24 and described in Table 8-25. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Return to the Register Summary Table. JESD204C Test Control Figure 8-24. JTEST Register 7 6 5 4 3 2 1 0 RESERVED JTEST R/W-000b R/W-00h Table 8-25. JTEST Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 0h 4-0 JTEST R/W 0b PRBS Test Modes: 0 : Test mode disabled. Normal operation (default) 1 : PRBS7 test mode 2 : PRBS9 test mode 3 : PRBS15 test mode 4 : PRBS31 test mode 5-31: RESERVED When a PRBS test mode is enabled, see BER_EN. Note: This register should only be changed when JESD_EN=0.

8.24 JTIMER Register (Offset = 0124h) [reset = 00h]

JTIMER is shown in Figure 8-25 and described in Table 8-26. Return to the Register Summary Table. Note: This register should only be changed when JESD_EN=0. JESD204C Watchdog Timer Figure 8-25. JTIMER Register 7 6 5 4 3 2 1 0 JTPLL RESERVED JTR RESERVED JTT R/W-0b R/W-0b R/W-0b R/W-0b R/W-000b Table 8-26. JTIMER Register Field Descriptions Bit Field Type Reset Description

7 JTPLL R/W 1b When this bit is set, the SerDes PLL is also reset when the watchdog

timer expires. When this bit is 0, only the SerDes receiver is reset.

6 RESERVED R/W 0b

5-4 JTR R/W 00b This register determines how much the watchdog counter is decremented when the link is up and CRC_FAULT is not set. JTR : Watchdog Counter Decrement : Approximate Link Uptime % required to prevent the SerDes from being reset 0 : 1 : 99.25% 1 : 2 : 98.46% 2 : 8 : 94.12% 3 : 16 : 88.89%

3 RESERVED R/W 0b

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Table 8-26. JTIMER Register Field Descriptions (continued) Bit Field Type Reset Description 2-0 JTT R/W 0b JESD204C watchdog counter threshold. When the watchdog counter reaches the threshold defined by JTT, the PHY layer is reset (including the PHY PLL(s) if JTPLL=1) and the watchdog timer is reset. Larger values of JTT cause the watchdog timer to take longer to intervene. JTT : Watchdog Counter Threshold : Counter Duration [assuming FCLK = 10.24 GHz 0 : <Watchdog Timer Disabled> : <disabled> 1 : 217 : 102.4 μs 2 : 219 : 409.6 μs 3 : 232 : 1.63 ms 4 : 223 : 6.55 ms 5-7 : RESERVED : RESERVED Note: The watchdog may not detect link up events shorter than 210 (1024) CLK cycles.

8.25 SYNC_EPW Register (Offset = 0127h) [reset = 00h]

SYNC_EPW is shown in Figure 8-26 and described in Table 8-27. Return to the Register Summary Table. JESD204C SYNC Error Report Pulse Width Figure 8-26. SYNC_EPW Register 7 6 5 4 3 2 1 0 RESERVED SYNC_EPW R/W-00h R/W-000b Table 8-27. SYNC_EPW Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R/W 00h 2-0 SYNC_EPW R/W 000b Specifies the pulse width of SYNC that is used for reporting errors to the transmitter. When an error is detected that does not require link resynchronization, SYNC is asserted for SYNC_EPW link clock cycles (equal to 4*SYNC_EPW character durations). To disable error reporting over SYNC, set SYNC_EPW=0. The legal range for SYNC_EPW is 0 to 7. Note: This register should only be changed when JESD_EN= 0.

8.26 CRC_TH Register (Offset = 0128h) [reset = 00h]

CRC_TH is shown in Figure 8-27 and described in Table 8-28. Return to the Register Summary Table. JESD204C CRC Error Thresholds Figure 8-27. CRC_TH Register 7 6 5 4 3 2 1 0 RESERVED CRC_ERR_REC CFC_ERR_TH R/W-0h R/W-00b R/W-00b DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Figure 8-27. CRC_TH Register (continued) Table 8-28. CRC_TH Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-2 CRC_ERR_REC R/W 0b Specify how many contiguous, error-free multiblocks must be received to reset the CRC error counter (and un-trigger the CRC alarm if triggered). 0 : 1 multiblock 1 : 4 multiblocks 2 : 16 multiblocks 3 : 64 multiblocks 1-0 CRC_ERR_TH R/W 0b Specify how many multi-blocks must have CRC errors to trigger the CRC alarm. The receiver counts each error, but if a run of error- free multi-blocks occurs (as specified by CRC_ERR_REC), the error counter resets. 0 : 1 multiblock 1 : 2 multiblocks 2 : 4 multiblocks 3 : 8 multiblocks Note: For each lane, the internal signal, CRC_FAULT, is set if the number of multi-blocks with CRC errors exceeds the threshold set by CRC_ERR_TH without a run of contiguous, error-free multi-blocks specified by CRC_ERR_REC. CRC_FAULT is cleared when a run of contiguous, error-free multi-blocks specified by CRC_ERR_REC is detected. Note: This register should only be changed when JESD_EN=0.

8.27 LANE_ARSTAT Register (Offset = 012Ch) [reset = NA]

LANE_ARSTAT is shown in Figure 8-28 and described in Table 8-29. Return to the Register Summary Table. Lane Arrival Status Figure 8-28. LANE_ARSTAT Register 7 6 5 4 3 2 1 0 RESERVED LANE_ARR_R DY R/W-00h R Table 8-29. LANE_ARSTAT Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h

0 LANE_ARR_RDY R NA This bit is set when lane arrival times are captured and available for

read in LANE_ARR. Lane arrival data is captured when all lanes are ready and the chip attempts to release the elastic buffer. This bit is cleared when JESD_EN=0 or JESD_RST=1.

8.28 LANE_INV Register (Offset = 012Eh) [reset = 0000h]

LANE_INV is shown in Figure 8-29 and described in Table 8-30. Return to the Register Summary Table. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 153 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 8-29. LANE_INV Register 15 14 13 12 11 10 9 8 LANE_INV[15:8] R/W-00h 7 6 5 4 3 2 1 0 LANE_INV[7:0] R/W-00h Table 8-30. LANE_INV Register Field Descriptions Bit Field Type Reset Description 15-0 LANE_INV R/W 0000h Program LANE_INV[n]=1 to invert the bitstream through physical lane n. Use this if the differential pair is swapped between the transmitter and receiver.

8.29 LANE_SEL[15:0] Register (Offset = 0130h) [reset for LANE_SEL[ n ]= n ]

LANE_SEL[15:0] forms a crossbar switch, and is a set of 16 registers for specifying which physical lane is bound to logical lane n. LANE_SEL[15:0] is shown in Figure 8-30 and described in Table 8-31. Return to the Register Summary Table. SerDes Lane Select for Logical Lane n (n = 0 - 15). LANE_SEL[0] is at the lowest address. Figure 8-30. LANE_SEL[15:0] Register 7 6 5 4 3 2 1 0 RESERVED LANE_SEL[n] R/W-0h R/W-n Table 8-31. LANE_SEL[15:0] Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 LANE_SEL[n] R/W n Specify which physical lane (0 to 15) is bound to logical lane n. To bind physical lane p to logical lane n, program LANE_SEL[n]=p. For example, to bind logical lane 0 to physical lane 3, program LANE_SEL[0]=3. Note: This register should only be changed when JESD_EN=0.

8.30 LANE_ARR[15:0] Register (Offset = 0140h) [Read only, reset = NA]

LANE_ARR[15:0] is a set of 16 registers for measuring the arrival time of lane n. LANE_ARR[15:0] is shown in Figure 8-31 and described in Table 8-32. Return to the Register Summary Table. SerDes Lane n Arrival Time (n = 0 - 15). LANE_ARR[0] is at the lowest address. Figure 8-31. LANE_ARR[15:0] Register 7 6 5 4 3 2 1 0 RESERVED LANE_ARR[n] R-00b R DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-32. LANE_ARR[15:0] Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 0h 5-0 LANE_ARR[n] R NA Returns the arrival time of lane n with respect to the internal LMFC/ LEMC that is established by SYSREF. The value returned can be between 0 and 63 (inclusive), regardless of the multiframe/EMB length. These registers are valid only when LANE_ARR_RDY =1. See Programming RBD. Note: The lane arrival data is captured when attempting to release the elastic buffer and LANE_ARR_RDY=0. All values are from the same release attempt. Note: It may be necessary to use JESD_RST when starting the link to get accurate lane arrival values.

8.31 LANE_STATUS[15:0] Register (Offset = 0150h) [Read only, reset = NA]

LANE_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in Figure 8-32 and described in Table 8-33. Return to the Register Summary Table. SerDes Lane n Status (n = 0 - 15). LANE_STATUS[0] is at the lowest address. Figure 8-32. LANE_STATUS[15:0] Register 7 6 5 4 3 2 1 0 RESERVED LANE_STATUS[n] R-00h R Table 8-33. LANE_STATUS[15:0] Register Field Descriptions Bit Field Type Reset Description 7-3 RESERVED R 00h 2 F_EMB_SYNC[n] R NA Returns 1 if logical lane n has frame or EMB synchronization. 1 CG_BK_SYNC[n] R NA Returns 1 if logical lane n has code-group or block synchronization.

0 SIG_DET[n] R NA Returns 1 if logical lane n is detecting a data signal (using loss-of-

signal detector in PHY).

8.32 LANE_ERR[15:0] Register (Offset = 0160h) [reset = 00h]

LANE_ERR[15:0] is a set of 16 registers reporting errors for lane n. LANE_ERR[15:0] is shown in Figure 8-33 and described in Table 8-34. Return to the Register Summary Table. SerDes Lane n Error Flags (n = 0 - 15). LANE_ERR[0] is at the lowest address. Figure 8-33. LANE_ERR[15:0] Register 7 6 5 4 3 2 1 0 LANE_ERR[n] R/W1C www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 155 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-34. LANE_ERR[15:0] Register Field Descriptions Bit Field Type Reset Description 7-0 LANE_ERR[n] R/W1C 00h Sticky bits indicating various errors on lane n. A bit is set to indicate an error. Write a 1 to clear a bit. [7] Alignment character found at unexpected location (8b/10b) or (extended)-multi-block pilot signal not in expected location (64b/66b) [6] Multi-frame, multi-block, or extended-multi-block alignment lost. [5] Frame alignment was lost (8b/10b only) or CRC_FAULT=1 (64b/ 66b). [4] Code-group or block synchronization was lost. [3] RESERVED [2] Not-in-table or unexpected control character (8b/10b) or CRC (64b/66b) error occurred. [1] Disparity error (8b/10b) or invalid sync header (64b/66b) occurred. [0] Gearbox FIFO overflowed or underflowed. As long as the write clock frequency is correct the gearbox write clock can drift at least 3UI after this flag without causing data corruption. Note: Lane Error Flags for extra or disabled lanes are undefined. Note: LANE_ERR[6:1] are only detected for 8b/10b operation while sync_n=1

8.33 FIFO_STATUS[15:0] Register (Offset = 0170h) [Read only, reset = NA]

FIFO_STATUS[15:0] is a set of 16 registers showing the status of lane n. LANE_STATUS[15:0] is shown in Figure 8-34 and described in Table 8-35. Return to the Register Summary Table. SerDes Lane n Status (n = 0 - 15). FIFO_STATUS[0] is at the lowest address. Figure 8-34. FIFO_STATUS[15:0] Register 7 6 5 4 3 2 1 0 RESERVED PDIFF[n] R-000b R Table 8-35. FIFO_STATUS[15:0] Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R 000b DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-35. FIFO_STATUS[15:0] Register Field Descriptions (continued) Bit Field Type Reset Description 4-0 PDIFF[n] R NA This register returns the difference between the write and read pointers inside the gearbox FIFO for logical lane n. For 8b/10b, values from 0-14 will be returned. For 64b/66b, values from 0-16 will be returned. The values at the ends of the range (0 & 14 for 8b/10b or 0 & 16 for 64b/66b) indicate error positions that will cause the Gearbox FIFO overflow/underflow flag to be set in LANE_ERR. In both cases, 1 indicates minimum setup and the max value minus 1 indicates minimum hold. Values are measured in the read clock. The tread size is approximately ½ of the effective link layer clock period (0.5/ (LCR*FDR)). In terms of UI:

In 8b/10b mode, the nominal tread size is 20UI. The nominal tread size for the final tread (14) is 380UI±20UI.
In 64b/66b mode, the nominal tread size is 16.5UI. The nominal tread size for the final tread (16) is 412.5UI±16.5UI. The PDIFF[n] value for disabled lanes and lanes enabled by EXTRA_LANE are undefined.

8.34 BER_EN Register (Offset = 01A0h) [reset = 00h]

BER_EN is shown in Figure 8-35 and described in Table 8-36. Return to the Register Summary Table. BER Measurement Control Figure 8-35. BER_EN Register 7 6 5 4 3 2 1 0 RESERVED BER_EN R/W-0b R/W-0b Table 8-36. BER_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 BER_EN R/W 0b BER (bit-error-rate) test enable. After setting up the receiver parameters, the user can program JTEST to a PRBS mode, set JESD_EN, and then set BER_EN to enable the BER counters (see BER_CNTn). To clear and restart the counters, program BER_EN to 0 and then back to 1. The BER logic will self-synchronize to the incoming PRBS data after the rising edge of BER_EN.

8.35 BER_CNT Register (Offset = 01B0h) [reset = NA, read rnly]

BER_CNT is shown in Figure 8-36 and described in Table 8-37. Return to the Register Summary Table. BER Error Count for Lane n. Lane 0 is a the lowest address Figure 8-36. BER_CNT Register 7 6 5 4 3 2 1 0 BER_CNT[n] www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 157 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 8-36. BER_CNT Register (continued) R/W-0b Table 8-37. BER_CNT Register Field Descriptions Bit Field Type Reset Description 7-0 BER_CNT[n] R/W 0h Returns the number of bit errors detected on lane n. This value will saturate at 255. The BER for lane n can be computed as follows: BER = BER_CNT[n] / FBIT / TBER Where TBER is the number of seconds that has elapsed from when BER_EN was set to when BER_CNT[n] was read. TBER is measured by the host system or clock. Example: If BER_CNT[n] returns 2, and FBIT is 12.8Gbps, and TBER is 3600 seconds, the bit-error-rate is 2/12.8e9/3600 = 43e-15 Note: The error counters on disabled lanes and lanes enabled by EXTRA_LANE are undefined.

8.36 JPHY_CTRL Register (Offset = 01C1h) [reset = 43h]

JPHY_CTRL is shown in Figure 8-37 and described in Table 8-38. Return to the Register Summary Table. JESD204C SerDes Control. Note: This register should only be changed when JESD_EN = 0. Figure 8-37. JPHY_CTRL Register 7 6 5 4 3 2 1 0 RESERVED CDR RESERVED OC_EN LOS_EN R/W-0b R/W-100b R/W-0b R/W-1b R/W-1b Table 8-38. JPHY_CTRL Register Field Descriptions Bit Field Type Reset Description 6-4 CDR R/W 100b Control CDR (clock-data-recovery) setting. The default value should be appropriate, but other settings can be used to adjust the tracking rate or reduce CDR power consumption. The 2nd order modes are for tracking a frequency offset when the Tx and Rx do not share a common reference clock. This is not applicable to JESD204C. See CDR Settings. 3-2 RESERVED R/W 00b 1 OC_EN R/W 1b Enable offset compensation/calibration for all lanes. 0 LOS_EN R/W 1b Enable loss-of-signal detector for all lanes. Table 8-39. CDR Settings CDR Vote Threshold Tracking Rate [ppm] Order Settling Time [UI] Activity % 0 15 313 2nd 36 83 1 7 607 2nd 36 70 2 3 723 2nd 36 50 3 1 868 2nd 36 25 4 (default) 15 96 1st 36 83 5 3 289 1st 36 50 6 1 434 1st 36 25 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-39. CDR Settings (continued) CDR Vote Threshold Tracking Rate [ppm] Order Settling Time [UI] Activity % 7 7 13 1st 1524 5

8.37 EQ_CTRL Register (Offset = 01C2h) [reset = 00h]

EQ_CTRL is shown in Figure 8-38 and described in Table 8-40. Return to the Register Summary Table. SerDes Equalizer Control Figure 8-38. EQ_CTRL Register 7 6 5 4 3 2 1 0 RESERVED EQ_OVR EQZ_OVR EQHLD EQMODE R/W-000b R/W-0b R/W-0b R/W-0b R/W-00b Table 8-40. EQ_CTRL Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 000b

4 EQ_OVR R/W 0b When EQMODE=1, you can program EQ_OVR=1 to over-ride the

equalizer level using the EQLEVEL[n] registers. Affects all lanes.

3 EQZ_OVR R/W 0b Set this bit to enable the EQZERO register (to override the

equalizer’s zero frequency). When EQZ_OVR=0, the frequency is set based on the RATE register. Affects all lanes.

2 EQHLD R/W 0b When the equalizer is in fully-adaptive mode (EQMODE=1 and

EQ_OVR=0), programming EQHLD will freeze (hold) the adaptation loop (for all lanes). 1-0 EQMODE R/W 00b Sets the equalizer mode (for all lanes): See Equalizer. 0: Equalizer disabled. Flat response with maximum gain. 1: Equalizer enabled. The equalizer is fully adaptive if EQ_OVR=0. 2: Precursor equalization analysis. 3: Postcursor equalization analysis.

8.38 EQZERO Register (Offset = 01C3h) [reset = 00h]

EQZERO is shown in Figure 8-39 and described in Table 8-41. Return to the Register Summary Table. SerDes Equalizer Zero. Figure 8-39. EQZERO Register 7 6 5 4 3 2 1 0 RESERVED EQZERO R/W-000b R/W-00h Table 8-41. EQZERO Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 000b www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 159 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-41. EQZERO Register Field Descriptions (continued) Bit Field Type Reset Description 4-0 EQZERO R/W 00h When EQZ_OVR=1, this field over-rides the equalizer’s zero frequency (for all lanes). When EQZ_OVR=0, the zero frequency is set automatically based on the RATE setting. 0x1F: 365 MHz (default setting for full and half-rate, RATE = 0 or 1) 0x1E: 275 MHz 0x1D: 195 MHz 0x1B: 140 MHz (default setting for quarter-rate mode, RATE = 2) 0x19: 105 MHz 0x10: 75 MHz 0x08: 55 MHz (default setting for eighth-rate, RATE = 3) 0x00: 50 MHz

8.39 LANE_EQ[15:0] Register (Offset = 01D0h) [reset = 08h]

LANE_EQ[15:0] is shown in Figure 8-40 and described in Table 8-42. Return to the Register Summary Table. SerDes Equalizer Level for Physical Lane [n]. LANE_EQ[0] is at the lowest address. Figure 8-40. LANE_EQ[15:0] Register 7 6 5 4 3 2 1 0 RESERVED EQBOOST[n] EQLEVEL[n] R/W-0b R/W-00b R/W-00h Table 8-42. LANE_EQ[15:0] Register Field Descriptions Bit Field Type Reset Description 6-5 EQBOOST[n] R/W 00b Controls EQ boost for physical lane n. EQBOOST : GAIN Boost : BW Change : Power Increase 0 : 0dB : 0% : 0mW 1 : 2dB : -30% : 0mW 2 : 4dB : +10% : 5mW 3 : 6dB : -20% : 5mW 4-0 EQLEVEL[n] R/W 00h When EQ_OVR=1, this field controls the equalization level for lane n. The valid range is from 0 (least equalization) to 16 (most equalization).

8.40 LANE_EQS[15:0] Register (Offset = 01E0h) [reset = NA, read only]

LANE_EQS[15:0] is shown in Figure 8-41 and described in Table 8-43. Return to the Register Summary Table. Serdes Equalizer Status for Physical Lane n Figure 8-41. LANE_EQS[15:0] Register 7 6 5 4 3 2 1 0 RESERVED EQOVER[n] EQUNDER[n] EQLEVEL_S[n] R R R R DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-43. LANE_EQS[15:0] Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R

6 EQOVER[n] R EQOVER status for PHY lane n pre/post cursor analysis. See Pre/ Post Cursor Analysis Procedure. 5 EQUNDER[n] R EQUNDER status for PHY lane n pre/post cursor analysis. See Pre/ Post Cursor Analysis Procedure.. 4 EQLEVEL_S[n] R This field returns the equalizer level currently in effect for lane n. This is the count of the number of bits set in the thermometer encoded value from the stsrx EQLEVEL_S field for lane n.

8.41 ESRUN Register (Offset = 01F0h) [reset = 00h]

ESRUN is shown in Figure 8-42 and described in Table 8-44. Return to the Register Summary Table. Eye-Scan Run Control Figure 8-42. ESRUN Register 7 6 5 4 3 2 1 0 RESERVED ESRUN R/W-00h R/W-0b Table 8-44. ESRUN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 ESRUN R/W 0b After setting up eye-scan, set ESRUN=1 to run the eye-scan test. See Eye Scan Procedure.

8.42 ES_CTRL Register (Offset = 01F1h) [reset = 00h]

ES_CTRL is shown in Figure 8-43 and described in Table 8-45. Return to the Register Summary Table. Note: Only change this register while ESRUN=0. Eye-Scan Control Figure 8-43. ES_CTRL Register 7 6 5 4 3 2 1 0 RESERVED ESLEN ES R/W-00b R/W-00b R/W-0h Table 8-45. ES_CTRL Register Field Descriptions Bit Field Type Reset Description 7-6 ES_CTRL R/W 00b www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 161 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-45. ES_CTRL Register Field Descriptions (continued) Bit Field Type Reset Description 5-4 ESLEN R/W 00b Specify the length of the eye-scan test. Larger values will give more consistent results, but will take longer. ESLEN : Number of Samples Analyzed 0 : 127 1 : 1032 2 : 8191 3 : 65535 Note: Many eye-scan modes only analyze zeros (or ones). Since they don’t analyze every sample, those modes will take longer to complete compared to a mode that analyzes all samples. 3-0 ES R/W 0h Specify the eye-scan mode. Applies to all lanes. ES : Eye-Scan Mode 0 : Eye-scan disabled (default) 1 : Compare. Counts mismatches between the normal sampler and the eye-scan sampler. Analyzes zeros and ones. 2 : Compare zeros. Same as ES=1, but only analyzes zeros. 3 : Compare ones. Same as ES=1, but only analyzes ones. 4 : Count ones. Increments ECOUNTn when the eye-scan sample is 5-7 : RESERVED 8 : Average zero. Adjusts ESVO_Sn to the average voltage for a zero. 9 : Outer zero. Adjusts ESVO_Sn to the lowest voltage for a zero. 10 : Inner zero. Adjusts ESVO_Sn to the highest voltage for a zero. 11 : RESERVED 12 : Average one. Adjusts ESVO_Sn to the average voltage for a one. 13 : Outer one. Adjusts ESVO_Sn to the highest voltage for a one. 14 : Inner one. Adjusts ESVO_Sn to the lowest voltage for a one. 15 : RESERVED

8.43 ESPO Register (Offset = 01F2h) [reset = 00h]

ESPO is shown in Figure 8-44 and described in Table 8-46. Return to the Register Summary Table. Eye-Scan Phase Offset Figure 8-44. ESPO Register 7 6 5 4 3 2 1 0 RESERVED ESPO R/W-0b R/W-00h Table 8-46. ESPO Register Field Descriptions Bit Field Type Reset Description

7 RESERVED R/W 0h

6-0 ESPO R/W 0b Eye-scan phase offset for all lanes. This adjusts the sampling instant of the eye-scan sampler compared to the normal sampler. This is a signed value from -64 to +63 and the step size is 1/32th of a UI. Note: Only change this register while ESRUN=0. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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8.44 ESVO Register (Offset = 01F3h) [reset = 00h]

ESVO is shown in Figure 8-45 and described in Table 8-47. Return to the Register Summary Table. Eye-Scan Voltage Offset Figure 8-45. ESVO Register 7 6 5 4 3 2 1 0 RESERVED ESVO R/W-00b R/W-00h Table 8-47. ESVO Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 0h 5-0 ESVO R/W 00h Eye-scan voltage offset for all lanes. This adjusts the voltage threshold of the eye-scan sampler. This is a signed value from -32 to +31. The step size is about 10mV (giving an adjustment range of about -320mV to +310mV). This field is ignored for eye-scan modes that adjust the voltage offset automatically and return a result on ESVO_S[n]. Note: This register should only be changed when ESRUN=0.

8.45 ES_BIT_SELECT Register (Offset = 01F4h) [reset = 00h]

ES_BIT_SELECT is shown in Figure 8-46 and described in Table 8-48. Return to the Register Summary Table. Eye-Scan Bit Select. Figure 8-46. ES_BIT_SELECT Register 7 6 5 4 3 2 1 0 RESERVED ES_BIT_SELECT R/W-000b R/W-00h Table 8-48. ES_BIT_SELECT Register Field Descriptions Bit Field Type Reset Description 7-5 RESERVED R/W 000b 4-0 ES_BIT_SELECT R/W 00h Eye-scan only runs on every 20th bit. This field specifies which bit position the eye-scan runs on (valid range is 0 to 19). Eye-scans may be run with all possible values of ES_BIT_SELECT and the results combined. Alternatively, results can be kept separate to see the effects of any duty cycle distortion / repetitive jitter. Note: This register should only be changed when ESRUN=0.

8.46 ECOUNT_CLR Register (Offset = 01F5h) [reset = 00h]

ECOUNT_CLR is shown in Figure 8-47 and described in Table 8-49. Return to the Register Summary Table. SerDes Error Counter Clear www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 163 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 8-47. ECOUNT_CLR Register 7 6 5 4 3 2 1 0 RESERVED ECOUNT_CLR R/W-00h R/W-0b Table 8-49. ECOUNT_CLR Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h

0 ECOUNT_CLR R/W 0b Program this to a 1 and then to 0 to clear the ECOUNT counters

8.47 ESDONE Register (Offset = 01F6h) [reset = NA, read-only]

ESDONE is shown in Figure 8-48 and described in Table 8-50. Return to the Register Summary Table. Eye-Scan Process Done Figure 8-48. ESDONE Register 7 6 5 4 3 2 1 0 ESDONE[15:8] R ESDONE[7:0] R Table 8-50. ESDONE Register Field Descriptions Bit Field Type Reset Description 15-0 ESDONE[15:0] R NA ESDONE[n] returns a 1 to indicate that the eye-scan procedure is completed on physical lane n. You must make sure that ESDONE[n] returns 1 before reading ESVO_S[n] or ECOUNT[n].

8.48 ESVO_S[15:0] Register (Offset = 0200h) [reset = NA, read-only]

ESVO_S[15:0] is shown in Figure 8-49 and described in Table 8-51. Return to the Register Summary Table. Eye-Scan Voltage Offset for SerDes lane n, n = 0 - 15. ESVO_S[0] is at the lowest address. Figure 8-49. ESVO_S[15:0] Register 7 6 5 4 3 2 1 0 RESERVED ESVO_S[n] R R Table 8-51. ESVO_S[15:0] Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R NA 5-0 ESVO_S[n] R NA Returns the voltage offset result from the eye-scan on physical lane n. Applies to eye-scan modes that compute the voltage offset automatically. Only valid when ESDONE[n] returns 1. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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8.49 ESCOUNT[15:0] Register (Offset = 0210h) [reset = NA, read-only]

ESCOUNT[15:0] is shown in Figure 8-50 and described in Table 8-52. Return to the Register Summary Table. Eye-Scan Voltage Offset for SerDes lane n, n = 0 - 15. ESCOUNT[0] is at the lowest address. Figure 8-50. ESCOUNT[15:0] Register 7 6 5 4 3 2 1 0 ESCOUNT[15:8][n] R ESCOUNT[7:0][n] R Table 8-52. ESCOUNT[15:0] Register Field Descriptions Bit Field Type Reset Description 15-0 ESCOUNT[n] R NA Returns the mismatch count for physical lane n (applies to eye-scan modes that count mismatches). Only valid when ESDONE[n] returns

8.50 LOS_TH Register (Offset = 0234h) [reset = 08h]

LOS_TH is shown in Figure 8-51 and described in Table 8-53. Return to the Register Summary Table. SerDes Loss-of-signal Theshold Figure 8-51. LOS_TH Register 7 6 5 4 3 2 1 0 RESERVED LOS_TH R/W-0h R/W-0h Table 8-53. LOS_TH Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 LOS_TH R/W 0h Specifies the threshold for the loss-of-signal detector. Applies when LOS_EN=1. Affects all lanes. LOS_TH : Approximate Threshold (mV) 0, 1 : RESERVED 2 - 15 : 15*(LOS_TH)

8.51 EQCNTSZ Register (Offset = 0235h) [reset = 00h]

EQCNTSZ is shown in Figure 8-52 and described in Table 8-54. Return to the Register Summary Table. SerDes Equalizer Counter Size Figure 8-52. EQCNTSZ Register 7 6 5 4 3 2 1 0 R/W-0h R/W-0h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 165 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-54. EQCNTSZ Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 EQCNTSZ R/W 0h Equalizer counter size: Adjusts how many votes must be accumulated to cause the adaptive equalizer gain to change. Affects all lanes. This is for debug purposes only and the user should generally not need to change this setting. EQCNTSZ : Equalizer Vote Counter Size (votes required to adjust gain) 0 : (default) 511 1 : RESERVED 2 : 1 3 : 3 4 : 7 5 : 15 6 : 31 7 : 63 8 : 127 9 : 255 10-15 : RESERVED

8.52 CDRLOCK Register (Offset = 0238h) [reset = 00h]

CDRLOCK is shown in Figure 8-53 and described in Table 8-55. Return to the Register Summary Table. SerDes CDR Lock/Freeze. Figure 8-53. CDRLOCK Register 7 6 5 4 3 2 1 0 RESERVED CDRLOCK R/W-00h R/W-0b Table 8-55. CDRLOCK Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 CDRLOCK R/W 0b When set, the CDR is frozen and no longer tracks. When the CDR is operating in first-order mode, set CDRLOCK to freeze the CDRPHASE value to inspect it.

8.53 CDRPHASE Register (Offset = 0239h) [reset = NA, read-only]

CDRPHASE is shown in Figure 8-54 and described in Table 8-56. Return to the Register Summary Table. SerDes CDR Phase Status Figure 8-54. CDRPHASE Register 7 6 5 4 3 2 1 0 CDRPHASE R DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-56. CDRPHASE Register Field Descriptions Bit Field Type Reset Description 7-0 CDRPHASE R Returns the current CDR phase value for the lane specified by RXDLANE. It is recommended to set CDRLOCK=1 before reading this register. The format is gray-coded. Refer to CDRPHASE Status for the coding.

8.54 PLL_STATUS Register (Offset = 0250h) [reset = NA, read only]

PLL_STATUS is shown in Figure 8-7 and described in Table 8-8. Return to the Register Summary Table. SerDes PLL Status Figure 8-55. PLL_STATUS Register 7 6 5 4 3 2 1 0 PLL_LOCK_STS PLL_LOCK_LOST R-0h R/W1C-0h Table 8-57. PLL_STATUS Register Field Descriptions Bit Field Type Reset Description 7-4 PLL_LOCK_STS R 0h This field returns the LOCK signal from all four SerDes macros (3:0). This field can be used for functional (fault) testing of the PLL lock detectors. 3-0 PLL_LOCK_LOST R/W1C 0h PLL_LOCK_LOST[n] is set whenever the LOCK signal from a SerDes PLL is low. bit 0: lanes 0 - 3 bit 1: lanes 4 - 7 bit 2: lanes 8 - 11 bit 3: lanes 12 - 15 This bit is sticky (remains set even if the PLL acquires lock). Write 1 to clear a bit. These bits are for debug purposes and allow the SPI to monitor if any SerDes PLL loses lock even briefly.

8.55 JESD_RST Register (Offset = 0253h) [reset = 0x00]

JESD_RST is shown in Figure 8-56 and described in Table 8-58. Return to the Register Summary Table. JESD Reset Figure 8-56. JESD_RST Register 7 6 5 4 3 2 1 RESERVED JESD_RST R/W-00h R/W-0h Table 8-58. JESD_RST Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h RESERVED www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 167 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-58. JESD_RST Register Field Descriptions (continued) Bit Field Type Reset Description

0 JESD_RST R/W 0b When set, this bit holds the digital portion of the JESD circuitry in

reset but does not affect the physical lane. It may be necessary to set this bit prior to setting JESD_EN = 1 and then clear this bit at a later time to start processing the JESD data. This allows the supply to settle from the large change in power that occurs when starting the PHY and JESD clocks. This is especially important if the user plans to use the LANE_ARR values, since these values are captured only the first time the elastic buffer attempts to release.

8.56 EXTREF_EN Register (Offset = 02B0h) [reset = 00h]

EXTREF_EN is shown in Figure 8-57 and described in Table 8-59. Return to the Register Summary Table. Enable External Reference Figure 8-57. EXTREF_EN Register 7 6 5 4 3 2 1 0 RESERVED EXTREF_EN R/W-00h R/W-0b Table 8-59. EXTREF_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h

0 EXTREF_EN R/W 0b Setting this bit enable the use of an external reference voltage on the

EXTREF ball. CUR_2X_EN Register (Offset = 02B1h) [reset = 00h] CUR_2X_EN is shown in Figure 8-58 and described in Table 8-60. Return to the Register Summary Table. DAC Current Doubler Enable Figure 8-58. CUR_2X_EN Register 7 6 5 4 3 2 1 0 RESERVED CUR_2X_EN R/W-00h R/W-0b Table 8-60. CUR_2X_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 CUR_2X_EN R/W 0b Setting this bit doubles the DAC output current.

8.57 DAC_OFS_CHG_BLK Register (Offset = 02CFh) [reset = 00h]

DAC_OFS_CHG_BLK is shown in Figure 8-59 and described in Table 8-61. Return to the Register Summary Table. DAC Offset Adjustment Change Block DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Figure 8-59. DAC_OFS_CHG_BLK Register 7 6 5 4 3 2 1 0 RESERVED DAC_OFS_CH G_BLK R/W-00h R/W-0b Table 8-61. DAC_OFS_CHG_BLK Register Field Descriptions Bit Field Type Reset Description 7-1 R/W 00h

0 DAC_OFS_CHG_BLK R/W 0b When set, changes to DAC_OFS[n] are not propagated to the high-

speed clocks and both DACs continue to use their current value. When this is changed from 1 to 0 the new DAC_OFS[n] values will be applied to both DACs in the same clock cycle.

8.58 DP_EN Register (Offset = 02E0h) [reset = 00h]

DP_EN is shown in Figure 8-60 and described in Table 8-62. Return to the Register Summary Table. Datapath Enable. Figure 8-60. DP_EN Register 7 6 5 4 3 2 1 0 RESERVED DP_EN R/W-00h R/W-0b Table 8-62. DP_EN Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h 0 DP_EN R/W 0b Setting this bit enables datapath operation. When cleared, the datapath is held in reset. This bit should be set after the chip is configured for proper operation. Note: This register should only be changed from 0 to 1 when FUSE_DONE=1.

8.59 DUC_L Register (Offset = 02E1h) [reset = 00h]

DUC_L is shown in Figure 8-61 and described in Table 8-63. Return to the Register Summary Table. DUC Interpolation Factor. Figure 8-61. DUC_L Register 7 6 5 4 3 2 1 0 RESERVED DUC_L R/W-0h R/W-0h Table 8-63. DUC_L Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 169 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-63. DUC_L Register Field Descriptions (continued) Bit Field Type Reset Description 3-0 DUC_L R/W 0h DUC Interpolation Factor 0: 1x 1: 2x 2: 3x 3: 4x 4: 6x 5: 8x 6: 12x 7: 16x 8: 24x 9: 32x 10: 48x 11: 64x 12: 96x 13: 128x 14: 192x 15: 256x Note: This register should only be changed when JESD_EN=0 and DP_EN=0.

8.60 DUC_GAIN Register (Offset = 02E2h) [reset = 00h]

DUC_GAIN is shown in Figure 8-62 and described in Table 8-64. Return to the Register Summary Table. Figure 8-62. DUC_GAIN Register 7 6 5 4 3 2 1 0 DUC_GAIN3 DUC_GAIN2 DUC_GAIN1 DUC_GAIN0 R/W-00b R/W-00b R/W-00b R/W-00b Table 8-64. DUC_GAIN Register Field Descriptions Bit Field Type Reset Description 7-6 DUC_GAIN3 R/W 00b DUC_GAINn adjusts the gain of DUCn (in the channel bonder) 0: 0dB 1: -6dB 2: -12dB 3: RESERVED Note: When the DUCs are configured for complex output (DUC_FORMAT=1), DUC2 and DUC3 cannot be used. In that case, DUC_GAIN2 and DUC_GAIN3 adjust the gain of the imaginary outputs of DUC0 and DUC1 respectively. Note: This register should only be changed when DP_EN=0. 5-4 DUC_GAIN2 R/W 00b 3-2 DUC_GAIN1 R/W 00b 1-0 DUC_GAIN0 R/W 00b

8.61 DUC_FORMAT Register (Offset = 02E3h) [reset = 00h]

DUC_FORMAT is shown in Figure 8-63 and described in Table 8-65. Return to the Register Summary Table. DUC Output Format DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Figure 8-63. DUC_FORMAT Register 7 6 5 4 3 2 1 0 RESERVED DUC_FORMAT R/W-00h R/W-0b Table 8-65. DUC_FORMAT Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h

0 DUC_FORMAT R/W 0b 0: DUC outputs are real (DUC mixer converts complex to real by

discarding the imaginary part). Up to 4 DUCs can be enabled. 1: DUC outputs are complex. Up to 2 DUCs can be enabled (DUC0 and DUC1). Note: This register should only be changed when DP_EN=0.

8.62 DAC_SRC Register (Offset = 02E4h) [reset = 00h]

DAC_SRC is shown in Figure 8-64 and described in Table 8-66. Return to the Register Summary Table. DAC Source Figure 8-64. DAC_SRC Register 7 6 5 4 3 2 1 0 DAC_SRC1 DAC_SRC0 R/W-0h R/W-0h Table 8-66. DAC_SRC Register Field Descriptions Bit Field Type Reset Description 7-4 DAC_SRC1 R/W 0h When the DUCs are disabled (LT<=1), DAC_SRCn selects which input stream is sent to DACn. When the DUCs are enabled (LT>=2), DAC_SRCn controls which DUC outputs are routed (summed) to DACn (and the meaning of the bits depends on DUC_FORMAT). Signals Routed to DACn when DAC_SRCn[m] is set: LT=0.5 or 1 (DUCs disabled) DAC_SRCn[0]: Input Stream 0 (I) DAC_SRCn[1]: Input Stream 1 (Q) DAC_SRCn[2]: n/a DAC_SRCn[3]: n/a LT is 2 or higher (DUCs enabled) Register Bit DAC_SRCn[x] : DUC_FORMAT=0 (real) : DUC_FORMAT=1 (complex) DAC_SRCn[0] : DUC0 (real) : DUC0 (real) DAC_SRCn[1] : DUC1 (real) : DUC1 (real) DAC_SRCn[2] : DUC2 (real) : DUC0 (imag) DAC_SRCn[3] : DUC3 (real) : DUC1 (imag) If more than one signal is routed to the same DAC, the signals are summed together. Use DUC_GAIN to avoid saturation in this case. While it is possible to sum a real output with an imaginary output, no practical application requires that, so it is not tested or supported. When LT=0.5 or 1, no summing is supported. Only DAC_SRCn[0] or DAC_SRCn[1] should be set Note: This register should only be changed when DP_EN=0. 3-0 DAC_SRC0 R/W 0b www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 171 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

8.63 MXMODE Register (Offset = 02E8h) [reset = 00h]

MXMODE is shown in Figure 8-65 and described in Table 8-67. Return to the Register Summary Table. DAC Output Mode. Note: This register should only be changed when DP_EN=0. Figure 8-65. MXMODE Register 7 6 5 4 3 2 1 0 RESERVED MXMODE1 RESERVED MXMODE0 R/W-0b R/W-000b R/W-0b R/W-000b Table 8-67. MXMODE Register Field Descriptions Bit Field Type Reset Description 6-4 MXMODE1 R/W 000b Specify the DAC pulse format for DACB. 0: Normal mode (non-return-to-zero or NRZ) (sinc nulls at n*FS) 1: RF Mode (return to inverse or RTI) (sinc nulls at DC and 2n*FS) 2: Return-to-Zero (RTZ) (sinc nulls at 2n*FS) 3: DES2X – Samples provided by the DES interpolator (low-pass mode) 4: DES2XH – Samples provided by the DES interpolator (high-pass mode) 5: DES1X – Both samples are provided by the input stream 6: Disabled – DACA is disabled 7: RESERVED Note: If either MXMODE1 or MXMODE0 is set to DES1X, the other must be set to either DES1X or Disabled. User must also set DUC_L=0. 2-0 MXMODE0 R/W 0b Specify the DAC pulse format for DACA. 0: Normal mode (non-return-to-zero or NRZ) (sinc nulls at n*FS) 1: RF Mode (return to inverse or RTI) (sinc nulls at DC and 2n*FS) 2: Return-to-Zero (RTZ) (sinc nulls at 2n*FS) 3: DES2X – Samples provided by the DES interpolator (low-pass mode) 4: DES2XH – Samples provided by the DES interpolator (high-pass mode) 5: DES1X – Both samples are provided by the input stream 6: Disabled – DACA is disabled 7: RESERVED Note: If either MXMODE1 or MXMODE0 is set to DES1X, the other must be set to either DES1X or Disabled. User must also set DUC_L=0.

8.64 TRUNC_HLSB Register (Offset = 02EAh) [reset = 00h]

TRUNC_HLSB is shown in Figure 8-66 and described in Table 8-68. Return to the Register Summary Table. Truncation Half LSB Offset Figure 8-66. TRUNC_HLSB Register 7 6 5 4 3 2 1 0 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Figure 8-66. TRUNC_HLSB Register (continued) RESERVED TRUNC_HLSB R/W-00h R/W-0b Table 8-68. TRUNC_HLSB Register Field Descriptions Bit Field Type Reset Description 7-1 R/W 0h 0 TRUNC_HLSB R/W 0b adds ½ LSB offset for < 16-bit resolution modes or devices. For a mode or device with < 16-bit output resolution, setting this bit adds a 1/2 LSB offset to reduce the average offset introduced by truncation. Note: This register should only be changed when DP_EN=0

8.65 TX_EN_SEL Register (Offset = 02F8h) [reset = 03h]

TX_EN_SEL is shown in Figure 8-67 and described in Table 8-69. Return to the Register Summary Table. Transmitter Enable Control Selection. Figure 8-67. TX_EN_SEL Register 7 6 5 4 3 2 1 0 RESERVED QUIET_TX_DIS ABLE FAST_TX_EN USE_TX_EN1 USE_TX_EN0 R/W-0h R/W-0b R/W-0b R/W-1b R/W-1b Table 8-69. TX_EN_SEL Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h

3 QUIET_TX_DISABLE R/W 0b 0: Transmission is disabled after DEM and dither by sending a

static aging safe code. For some configurations and frequencies, the outputs will have higher noise than a static mid-scale code would normally have. However, this mode has the lowest latency from transmit enable to DAC output. 1: When transmission is disabled, the input to DEM and dither is muted to minimize the output noise. This increases the latency from transmit enable to DAC output by 56 DAC clocks Note: This bit may only be set when FAST_TX_EN=1.

2 FAST_TX_EN R/W 0b 0: When the transmit enables are both low, JESD and datapath

clocks are shutdown to save power. When transmission is re- enabled the outputs remain muted until valid data is available at the output. 1: No power saving is performed and transmit enables can be used independently. Latency from transmit enable to DAC outputs is reduced in this mode. 1 USE_TX_EN1 R/W 1b 0: DACB is controlled by the TXEN1 ball. In this mode, TX_EN1 register is ignored. 1: DACB is controlled by the TX_EN1 register. In this mode the TXEN1 ball input does not affect the transmit enable for DACB. Note: USE_TX_EN1 and USE_TX_EN0 should be programmed to the same value (individual channel control is not supported). www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 173 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-69. TX_EN_SEL Register Field Descriptions (continued) Bit Field Type Reset Description 0 USE_TX_EN0 R/W 1b 0: DACA is controlled by the TXEN0 ball. In this mode, TX_EN0 register is ignored. 1: DACA is controlled by the TX_EN0 register. In this mode the TXEN0 ball input does not affect the transmit enable for DACA. Note: USE_TX_EN1 and USE_TX_EN0 should be programmed to the same value (individual channel control is not supported).

8.66 TX_EN Register (Offset = 02F9h) [reset = 03h]

TX_EN is shown in Figure 8-68 and described in Table 8-70. Return to the Register Summary Table. Transmitter Enable Control Figure 8-68. TX_EN Register 7 6 5 4 3 2 1 0 TX_EN1 TX_EN0 R/W-00h R/W-1b R/W-1b Table 8-70. TX_EN Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 00h

1 TX_EN1 R/W 1b When USE_TX_EN1 = 1, this bit controls the transmit enable for

DACB. Note: TX_EN1 and TX_EN0 should be programmed to the same value (individual channel control is not supported).

0 TX_EN0 R/W 1b When USE_TX_EN0 = 1, this bit controls the transmit enable for

Note: TX_EN1 and TX_EN0 should be programmed to the same value (individual channel control is not supported).

8.67 NCO_CTRL Register (Offset = 0300h) [reset = 00h]

NCO_CTRL is shown in Figure 8-69 and described in Table 8-71. Return to the Register Summary Table. Note: This register should only be changed when DP_EN=0. NCO Enable Figure 8-69. NCO_CTRL Register 7 6 5 4 3 2 1 0 FR_EN RESERVED NCO_SC DDS_EN NCO_EN R/W-0b R/W-0h R/W-0b R/W-0b R/W-0b Table 8-71. NCO_CTRL Register Field Descriptions Bit Field Type Reset Description

7 FR_EN R/W 0b When set, the Fast Reconfiguration (FR) interface is enabled and

NCO frequency, phase, dither, and accumulator reset is controlled by the FR registers rather than the SPI registers. 6-3 RESERVED R/W 0h DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-71. NCO_CTRL Register Field Descriptions (continued) Bit Field Type Reset Description

2 NCO_SC R/W 0b Self-Coherent NCO Mode: When this bit is set, all NCOs use the

reference counter from the NCO in DDS/DUC channel 0. This is typically used along with the NCO_SS register. This only impacts phase-coherent mode (NCO_CONT=0).

1 DDS_EN R/W 0b When set, all DUCs are configured for DDS operation once DP_EN

is set. See DDS Operation in Section 7.4.1 for details. 0 NCO_EN R/W 0b When set, DUC samples are mixed with the NCO.

8.68 NCO_CONT Register (Offset = 0301h) [reset = 00h]

NCO_CONT is shown in Figure 8-70 and described in Table 8-72. Return to the Register Summary Table. NCO Phase Continuous Mode Figure 8-70. NCO_CONT Register 7 6 5 4 3 2 1 0 RESERVED NCO_CONT R/W-0h R/W-0h Table 8-72. NCO_CONT Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h 3-0 NCO_CONT R/W 0h For each bit NCO_CONT[n], if set, NCOn operates in phase- continuous mode. This means that frequency changes occur without seeding the phase accumulator. If the bit is clear, NCOn operates in phase-coherent mode. During frequency changes, the phase accumulator is seeded from a main counter. This means that if changing from frequency A to B and then back to A, the phase returns to what it would have been if the change never occurred. Note: This register should only be changed when DP_EN=0.

8.69 NCO_SYNC Register (Offset = 0302h) [reset = 00h]

NCO_SYNC is shown in Figure 8-71 and described in Table 8-73. Return to the Register Summary Table. NCO Synchronization Configuration Figure 8-71. NCO_SYNC Register 7 6 5 4 3 2 1 0 RESERVED NCO_SYNC_SRC R/W-00h R/W-00b Table 8-73. NCO_SYNC Register Field Descriptions Bit Field Type Reset Description 7-2 RESERVED R/W 00h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 175 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-73. NCO_SYNC Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 NCO_SYNC_SRC R/W 00b If FR_EN=0: This register determines how NCO synchronization events will be triggered. This includes both accumulator resets specified by NCO_AR and the application of changes to NCO_DITH_EN, FREQ, and PHASE. 0: Setting SPI_SYNC will immediately perform specified events. (All will occur in the same clock cycle.) 1: Setting SPI_SYNC will cause the specified events to occur on the next SYSREF rising edge. 2: While SPI_SYNC is high, the specified events will occur on every SYSREF rising edge. 3: While SPI_SYNC is high, the LSb of the “I” input to DUC0 will cause the specified events. To trigger the event, the LSb must be low for 4 or more consecutive samples and then high for 4 consecutive samples. The sync will occur coincident with the 4th high sample arriving at the DUC0 input. If FR_EN=1: This register determines how NCO synchronization events will be triggered. This includes both accumulator resets specified by FR_NCO_AR and the application of changes to FR_NCO_DITH_EN, FR_FREQL, FR_FREQS, and FR_PHASE. 0: If FRS is set, the specified events is performed at the rising edge of FRCS. (All will occur in the same clock cycle.) 1: Reserved 2: RESERVED 3: If FRS is set, the LSb of the “I” input to DUC0 will cause the specified events following the rising edge of FRCS. To trigger the event, the LSb must be low for 4 or more consecutive samples and then high for 4 consecutive samples. The sync will occur coincident with the 4th high sample arriving at the DUC0 input. While waiting for the LSb trigger, zero will be used for the LSb data. The LSb will immediately return to being used as data after the 4th consecutive high sample. Note: This register should only be changed when SPI_SYNC=0 and the FR interface is idle (FRCS=1).

8.70 NCO_AR Register (Offset = 0303h) [reset = 0Fh]

NCO_AR is shown in Figure 8-72 and described in Table 8-74. Return to the Register Summary Table. NCO Accumulator Reset Figure 8-72. NCO_AR Register 7 6 5 4 3 2 1 0 RESERVED NCO_AR R/W-0h R/W-0h Table 8-74. NCO_AR Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W 0h DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-74. NCO_AR Register Field Descriptions (continued) Bit Field Type Reset Description 3-0 NCO_AR R/W 0h For each bit NCO_AR[n], if set, the accumulator for NCOn will be reset on every sync event specified by NCO_SYNC_SRC. Note: This register has no effect when FR_EN=1.

8.71 SPI_SYNC Register (Offset = 0304h) [reset = 00h]

SPI_SYNC is shown in Figure 8-73 and described in Table 8-75. Return to the Register Summary Table. SPI Sync Bit Figure 8-73. SPI_SYNC Register 7 6 5 4 3 2 1 0 RESERVED SPI_SYNC R/W-00h R/W-0b Table 8-75. SPI_SYNC Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h

0 SPI_SYNC R/W 0b Writing ‘1’ to this register when it is ‘0’ will trigger synchronization

events that are bound to this register (see NCO_SYNC_SRC). This register will return the last value written. Note: Whether this register is edge or level sensitive depends on the setting for NCO_SYNC_SRC. Note: This register has no effect when FR_EN=1. NCO_SS Register (Offset = 0305h) [reset = 00h] NCO_SS is shown in Figure 8-74 and described in Table 8-76. Return to the Register Summary Table. NCO_SS Bit Figure 8-74. NCO_SS Register 7 6 5 4 3 2 1 0 RESERVED NCO_SS R/W-00h R/W-0b Table 8-76. NCO_SS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 177 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-76. NCO_SS Register Field Descriptions (continued) Bit Field Type Reset Description

0 NCO_SS R/W 0b When this bit is set, all NCOs will continuously self-synchronize

every 256 DAC clock cycles. In a radiation environment, the user can set NCO_SS to continuously transfer the upset-immune AMP, FREQ and PHASE register values to the internal (non-immune) registers inside the NCOs. This is helpful for generating tones under radiation without the need for an external, periodic synchronization source (such as SYSREF). NCO_SS can be changed while the NCOs are operating (DP_EN=1). To write a new FREQ, AMP, or PHASE value, clear NCO_SS first, and then set it again after the new values are written. All values go into effect simultaneously on all NCOs. The user should make sure that NCO_AR=0 whenever NCO_SS=1 (otherwise the NCO accumulators and/or reference counters keep getting reset). If the user also sets NCO_SC=1 and NCO_CONT=0, then all four NCOs maintain coherency with each other under radiation, but there may be no coherence with an external component. Each NCO accumulator is continuously seeded from the reference counter in DUC/DDS channel 0. This feature can be used to generate coherent harmonic tones to cancel out harmonic distortion in the DAC. AMP[3:0] Register (Offset = 0318h) [reset = 0000h] AMP[3:0] is described in Table 8-77. AMP[0] starts at address 0x0318, AMP[1] at address 0x031A, AMP[2] at address 0x031C and AMP[3] at address 0x031E. Return to the Register Summary Table. Table 8-77. AMP[3:0] Register Field Descriptions Bit Field Type Reset Description 15-0 AMP[3:0] R/W 0000h Specifies the DDS amplitude for DDS channel n. 16-bit signed value. This register only applies to DDS Operation. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.)FREQ[0] Register (Offset = 0320h) [reset = 0000000000000000h] FREQ[0] is described in Table 8-78. Return to the Register Summary Table. FREQ for NCO0 Accumulator. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-78. FREQ[0] Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ[0] R/W 0000 0000 0000 0000h The NCO frequency (FNCO) is: FNCO = FREQ[0] * 2-64 * FCLK where FCLK is the sample frequency of the DAC. FREQ[0] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid). Use this equation to determine the value to program: FREQ[0] = 264 * FNCO /FCLK Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1.

8.73 FREQ[1] Register (Offset = 0328h) [reset = 0000000000000000h]

FREQ[1] is described in Table 8-79. Return to the Register Summary Table. FREQ for NCO1 Accumulator. Table 8-79. FREQ[1] Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ[1] R/W 0000 0000 0000 0000h The NCO frequency (FNCO) is: FNCO = FREQ[1] * 2-64 * FCLK where FCLK is the sample frequency of the DAC. FREQ[1] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid). Use this equation to determine the value to program: FREQ[1] = 264 * FNCO /FCLK Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1.

8.74 FREQ[2] Register (Offset = 0330h) [reset = 0000000000000000h]

FREQ[2] is described in Table 8-80. Return to the Register Summary Table. FREQ for NCO2 Accumulator. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 179 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-80. FREQ[2] Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ[2] R/W 0000 0000 0000 0000h The NCO frequency (FNCO) is: FNCO = FREQ[2] * 2-64 * FCLK where FCLK is the sample frequency of the DAC. FREQ[2] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid). Use this equation to determine the value to program: FREQ[2] = 264 * FNCO /FCLK Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1.

8.75 FREQ[3] Register (Offset = 0338h) [reset = 0000000000000000h]

FREQ[3] is described in Table 8-81. Return to the Register Summary Table. FREQ for NCO3 Accumulator. Table 8-81. FREQ[3] Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ[3] R/W 0000 0000 0000 0000h The NCO frequency (FNCO) is: FNCO = FREQ[3] * 2-64 * FCLK where FCLK is the sample frequency of the DAC. FREQ[3] is the integer value of this register. This register can be interpreted as signed or unsigned (both interpretations are valid). Use this equation to determine the value to program: FREQ[3] = 264 * FNCO /FCLK Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1.

8.76 PHASE0 Register (Offset = 0340h) [reset = 0000h]

PHASE0 is described in Table 8-82. Return to the Register Summary Table. Phase for NCO0 Accumulator. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-82. PHASE0 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE0 R/W 0h Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO. This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE0* 2-16 * 2π. This register can be interpreted as signed or unsigned. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1.

8.77 PHASE1 Register (Offset = 0342h) [reset = 0000h]

PHASE1 is described in Table 8-83. Return to the Register Summary Table. Phase for NCO1 Accumulator. Table 8-83. PHASE1 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE1 R/W 0h Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO. This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE1 * 2-16 * 2π. This register can be interpreted as signed or unsigned. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1.

8.78 PHASE2 Register (Offset = 0344h) [reset = 0000h]

PHASE2 is described in Table 8-84. Return to the Register Summary Table. Phase for NCO2 Accumulator. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 181 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-84. PHASE2 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE2 R/W 0h Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO. This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE2 * 2-16 * 2π. This register can be interpreted as signed or unsigned. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1.

8.79 PHASE3 Register (Offset = 0346h) [reset = 0000h]

PHASE3 is described in Table 8-85. Return to the Register Summary Table. Phase for NCO3 Accumulator. Table 8-85. PHASE3 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE3 R/W 0h Phase is added late so this register can be written during operation to change the phase without needing to reset the NCO. This value is left justified into a 32−bit field and then added to the phase accumulator. The phase (in radians) is PHASE3 * 2-16 * 2π. This register can be interpreted as signed or unsigned. Note: Changes to this register do not take effect until the next sync event specified by NCO_SYNC_SRC. Note: This register should only be changed when DP_EN=0 or updates to the NCOs are scheduled to occur away from the change. (See NCO_SYNC.) Note: This register has no effect when FR_EN=1. AMP_R[3:0] Register (Offset = 0378h) [reset = NA] AMPR[3:0] is described in Table 8-86. AMP_R[0] starts at addess offset 0x0378, AMP_R[1] at address offset 0x37A, AMP_R[2] at address offset 0x37C and AMP_R[3] at address offset 0x37E Return to the Register Summary Table. Table 8-86. AMP_R[3:0] Register Field Descriptions Bit Field Type Reset Description 15-0 AMP_R[n] R NA This provides a readback of the amplitude setting that is currently in use by the DDS channel n. Format is 16-bit signed. This register is only applicable when DDS_EN=1. When DDS_EN=0, the return value is undefined. The value is sampled as each byte is read, so it may return incoherent data if the amplitude changes during readback.

8.80 FREQ_R0 Register (Offset = 0380h) [reset = NA, read-only]

FREQ_R0 is described in Table 8-87. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Return to the Register Summary Table. Readback for Frequency for NCO0 Table 8-87. FREQ_R0 Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ_R0 R NA This provides a readback of the FREQ setting that is currently in used by the system for NCO0. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

8.81 FREQ_R1 Register (Offset = 0388h) [reset = NA, read-only]

FREQ_R1 is described in Table 8-88. Return to the Register Summary Table. Readback for Frequency for NCO1 Table 8-88. FREQ_R1 Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ_R1 R NA This provides a readback of the FREQ setting that is currently in used by the system for NCO1. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

8.82 FREQ_R2 Register (Offset = 0390h) [reset = NA, read-only]

FREQ_R2 is described in Table 8-89. Return to the Register Summary Table. Readback for Frequency for NCO2 Table 8-89. FREQ_R2 Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ_R2 R NA This provides a readback of the FREQ setting that is currently in used by the system for NCO2. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

8.83 FREQ_R3 Register (Offset = 0398h) [reset = NA, read-only]

FREQ_R3 is described in Table 8-90. Return to the Register Summary Table. Readback for Frequency for NCO3 Table 8-90. FREQ_R3 Register Field Descriptions Bit Field Type Reset Description 63-0 FREQ_R3 R NA This provides a readback of the FREQ setting that is currently in used by the system for NCO3. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

8.84 PHASE_R0 Register (Offset = 03A0h) [reset = NA, read-only]

PHASE_R0 is described in Table 8-91. Return to the Register Summary Table. Readback for Phase Word for NCO0 Table 8-91. PHASE_R0 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE_R0 R/W 0h This provides a readback of the PHASE setting that is currently in used by the system for NCO0. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

8.85 PHASE_R1 Register (Offset = 03A2h) [reset = NA, read-only]

PHASE_R1 is described in Table 8-92. Return to the Register Summary Table. Readback for Phase Word for NCO1 Table 8-92. PHASE_R1 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE_R1 R/W NA This provides a readback of the PHASE setting that is currently in used by the system for NCO1. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

8.86 PHASE_R2 Register (Offset = 03A4h) [reset = NA, read-only]

PHASE_R2 is described in Table 8-93. Return to the Register Summary Table. Readback for Phase Word for NCO2 Table 8-93. PHASE_R2 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE_R2 R/W NA This provides a readback of the PHASE setting that is currently in used by the system for NCO2. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback.

8.87 PHASE_R3 Register (Offset = 03A6h) [reset = NA, read-only]

PHASE_R3 is described in Table 8-94. Return to the Register Summary Table. Readback for Phase Word for NCO3 Table 8-94. PHASE_R3 Register Field Descriptions Bit Field Type Reset Description 15-0 PHASE_R3 R/W NA This provides a readback of the PHASE setting that is currently in used by the system for NCO3. The value is sampled as each byte is read, so it may return incoherent data if the operating value changes during readback. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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8.88 FR_FRS_R Register (Offset = 03E0h) [reset = NA, read-only]

FR_FRS_R is shown in Figure 8-75 and described in Table 8-95. Return to the Register Summary Table. Readback for FR Syncrhonization Figure 8-75. FR_FRS_R Register 7 6 5 4 3 2 1 0 FR_FRS_R RESERVED R R Table 8-95. FR_FRS_R Register Field Descriptions Bit Field Type Reset Description 7 FR_FRS_R R NA This provides readback for the value of FRS in the last transaction. Note: This value is not synchronized and should only be read while the FR interface is static. 6-0 RESERVED R NA

8.89 FR_NCO_AR_R Register (Offset = 03E1h) [reset = NA, read-only]

FR_NCO_AR_R is shown in Figure 8-76 and described in Table 8-96. Return to the Register Summary Table. Readback for FR NCO Accumulator Reset Figure 8-76. FR_NCO_AR_R Register 7 6 5 4 3 2 1 0 RESERVED FR_NCO_AR_R R R Table 8-96. FR_NCO_AR_R Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R NA 3-0 FR_NCO_AR_R R NA This provides readback for the last value that was written to FR_NCO_AR. Note: This value is not synchronized and should only be read while the FR interface is static.

8.90 TS_TEMP Register (Offset = 0400h) [reset = NA, read-only]

TS_TEMP is shown in Figure 8-77 and described in Table 8-97. Return to the Register Summary Table. Temperature Reading in Celsius Figure 8-77. TS_TEMP Register 7 6 5 4 3 2 1 0 TS_TEMP R www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 185 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-97. TS_TEMP Register Field Descriptions Bit Field Type Reset Description 7-0 TS_TEMP R NA Returns the temperature sensor reading. This returns an unsigned value from 0 to 255. Subtract 80 from this value to get degrees Celsius. For example, a value of 110 indicates 30C. See Temperature Sensor. Note: Reads of this register require slower SPI timing. See Switching Characteristics. Note: This register will not return valid data unless TS_SLEEP=0.

8.91 TS_SLEEP Register (Offset = 0401h) [reset = 00h]

TS_SLEEP is shown in Figure 8-78 and described in Table 8-98. Return to the Register Summary Table. Temperature Sensor Sleep Figure 8-78. TS_SLEEP Register 7 6 5 4 3 2 1 0 RESERVED TS_SLEEP R/W-00h R/W-0b Table 8-98. TS_SLEEP Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 00h

0 TS_SLEEP R/W 0b If temperature conversions are not needed, set this bit to sleep the

temperature sensor.

8.92 SYNC_STATUS Register (Offset = 0410h) [reset = NA]

SYNC_STATUS is shown in Figure 8-79 and described in Table 8-99. Return to the Register Summary Table. Synchronization Status Figure 8-79. SYNC_STATUS Register 7 6 5 4 3 2 1 0 RESERVED CLK_REALIGN ED CLK_ALIGNED NCO_SYNC_D ET SYSREF_DET R R/W1C R R/W1C R/W1C Table 8-99. SYNC_STATUS Register Field Descriptions Bit Field Type Reset Description 7-4 RESERVED R/W NA

3 CLK_REALIGNED R/W1C NA This bit is set any time the clock dividers associated with SYSREF

(excluding LMFC/LEMC) are realigned to SYSREF. This bit is useful to confirm the internally sampled SYSREF signal has a correct and stable period in DDS mode (or for debug purposes in JESD204C mode). Write a 1 to clear this bit.

2 CLK_ALIGNED R NA When set, indicates that the last SYSREF pulse was consistent with

the SYSREF-associated clock dividers (except for the LMFC/LEMC). Since the LMFC/LEMC does not affect this bit, it is appropriate to use in DDS mode, but can also be used when the JESD204C interface is enabled. This bit is read-only (cannot be cleared via SPI). DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-99. SYNC_STATUS Register Field Descriptions (continued) Bit Field Type Reset Description 1 NCO_SYNC_DET R/W1C NA This bit is set any time one or more NCOs receives a sync event. Write a 1 to clear this bit. 0 SYSREF_DET R/W1C NA This bit is set when a SYSREF is detected. Write a 1 to clear the bit and allow it to be re-detected.

8.93 SYS_ALM Register (Offset = 0430h) [reset = NA, read/write 1 to clear]

SYS_ALM is shown in Figure 8-80 and described in Table 8-100. Return to the Register Summary Table. System Alarm Status Figure 8-80. SYS_ALM Register 7 6 5 4 3 2 1 0 JESD_LINK_D OWN_ALM JTIMER_EXPIR ED_ALM JESD_CRC_AL M RESERVED SYSRST_ALM SYSREF_ALM R/W1C R/W1C R/W1C R R/W1C R/W1C Table 8-100. SYS_ALM Register Field Descriptions Bit Field Type Reset Description

7 JESD_LINK_DOWN_ALM R/W1C This bit is set any time LINK_UP transitions from 1 to 0 while

JESD_EN=1. Write 1 to clear the alarm.

6 JTIMER_EXPIRED_ALM R/W1C This bit is set if the JESD link has been down (LINK_UP=0 while

JESD_EN=1) longer than allowed by JTIMER. Write 1 to clear the alarm. 5 JESD_CRC_ALM R/W1C This bit is set any time CRC_FAULT is detected on an enabled lane. Applies only to 64b/66b modes. Write 1 to clear the alarm. 4-2 RESERVED R

1 SYSRST_ALM R/W1C This bit is set any time the chip is reset due to the RESET ball,

power on reset, or SOFT_RESET. Write 1 to clear the alarm.

0 SYSREF_ALM R/W1C This bit is set any time a SYSREF edge is detected at an incorrect

alignment by either the clock dividers or by the JESD Subsystem (when JESD_EN=1). Write 1 to clear the alarm.

8.94 ALM_MASK Register (Offset = 0431h) [reset = 00h]

ALM_MASK is shown in Figure 8-81 and described in Table 8-101. Return to the Register Summary Table. Alarm Mask Figure 8-81. ALM_MASK Register 7 6 5 4 3 2 1 0 JESD_LINK_D OWN_MASK JTIMER_EXPIR ED_MASK JESD_CRC_M ASK RESERVED SYSREF_ALM_ MASK R/W-0b R/W-0b R/W-0b R/W-0h R/W-0b Table 8-101. ALM_MASK Register Field Descriptions Bit Field Type Reset Description

7 JESD_LINK_DOWN_MAS

K R/W 0h When set, alarms from the JESD_LINK_DOWN_ALM register are masked and will not impact the alarm output. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 187 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-101. ALM_MASK Register Field Descriptions (continued) Bit Field Type Reset Description

6 JTIMER_EXPIRED_MAS

K R/W 0b When set, alarms from the JTIMER_EXPIRED_ALM register are masked and will not impact the alarm output.

5 JESD_CRC_MASK R/W 0b When set, alarms from the JESD_CRC_ALM register are masked

and will not impact the alarm output. 4-1 RESERVED R/W 0h

0 SYSREF_ALM_MASK R/W 0b When set, alarms from the SYSREF_ALM register are masked and

will not impact the alarm output.

8.95 MUTE_MASK Register (Offset = 0432h) [reset = 21h]

MUTE_MASK is shown in Figure 8-82 and described in Table 8-102. Return to the Register Summary Table. DAC Mute Mask Figure 8-82. MUTE_MASK Register 7 6 5 4 3 2 1 0 RESERVED JESD_CRC_M UTE_MASK RESERVED SYSREF_MUT E_MASK R/W-00b R/W-1b R/W-0h R/W-1b Table 8-102. MUTE_MASK Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R/W 00b

5 JESD_CRC_MUTE_MAS

K R/W 1b JESD CRC alarms will mute the DACs according to JESD_CRC_REC unless this bit is set. 4-1 RESERVED R/W 0h

0 SYSREF_MUTE_MASK R/W 1b Alarms from the SYSREF_ALM register will mute the DACs unless

this bit is set.

8.96 MUTE_REC Register (Offset = 0433h) [reset = A0h]

MUTE_REC is shown in Figure 8-83 and described in Table 8-103. Return to the Register Summary Table. DAC Mute Recovery Figure 8-83. MUTE_REC Register 7 6 5 4 3 2 1 0 JESD_LINK_D OWN_REC RESERVED JESD_CRC_RE C RESERVED R/W-1b R/W-0b R/W-1b R/W-00h Table 8-103. MUTE_REC Register Field Descriptions Bit Field Type Reset Description 7-6 JESD_LINK_DOWN_REC R/W 1b 0: DAC will remain muted until the JESD_LINK_DOWN_ALM = 0. 1: DAC will unmute automatically when the JESD link recovers. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Table 8-103. MUTE_REC Register Field Descriptions (continued) Bit Field Type Reset Description K R/W 1b This bit is only used if JESD_CRC_MUTE_MASK = 0. 0: DAC will remain muted until the JESD_CRC_ALM=0 1: DAC will unmute automatically when CRC_FAULT=0. 4-0 RESERVED R/W 0h

8.97 FUSE_STATUS Register (Offset = 0600h) [reset = NA]

FUSE_STATUS is shown in Figure 8-82 and described in Table 8-102. Return to the Register Summary Table. Fuse Status Figure 8-84. FUSE_STATUS Register 7 6 5 4 3 2 1 0 RESERVED FUSE_DONE R-NA R-NA Table 8-104. FUSE_STATUS Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R NA

0 FUSE_DONE R NA Returns ‘1’ when the fuse controller is idle, meaning the controller

has completed the fuse auto-load sequence. The sequence takes less than 523,000 CLK cycles to complete, or FUSE_DONE can be polled until it is '1'. When FUSE_DONE is ‘0’ the user should not read or write any fuse-backed registers.

8.98 FINE_CUR_A Register (Offset = 0723h) [reset = varies]

FINE_CUR_A is shown in Figure 8-85 and described in Table 8-105. Return to the Register Summary Table. Fine Bias Current Control for DACA Figure 8-85. FINE_CUR_A Register 7 6 5 4 3 2 1 0 RESERVED FINE_CUR_A R-00b R/W-varies Table 8-105. FINE_CUR_A Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 00b default values varies to match output current specification.

8.99 COARSE_CUR_A Register (Offset = 0724h) [reset = 0Fh]

COARSE_CUR_A is shown in Figure 8-86 and described in Table 8-106. Return to the Register Summary Table. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 189 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Coarse Bias Current Control for DACA Figure 8-86. COARSE_CUR_A Register 7 6 5 4 3 2 1 0 DAC0_CBIAS_SLEEP COARSE_CUR_A R/W-0h R/W-0xF Table 8-106. COARSE_CUR_A Register Field Descriptions Bit Field Type Reset Description 7-4 DAC0_CBIAS_SLEEP R/W 0h DAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 9.1.6

8.100 FINE_CUR_B Register (Offset = 0725h) [reset = varies]

FINE_CUR_B is shown in Figure 8-87 and described in Table 8-107. Return to the Register Summary Table. Fine Bias Current Control for DAC B Figure 8-87. FINE_CUR_B Register 7 6 5 4 3 2 1 0 RESERVED FINE_CUR_B R-00b R/W-varies Table 8-107. FINE_CUR_B Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 00b default values varies to match output current specification.

8.101 COARSE_CUR_B Register (Offset = 0726h) [reset = 0Fh]

COARSE_CUR_B is shown in Figure 8-88 and described in Table 8-108. Return to the Register Summary Table. Coarse Bias Current Control for DACB Figure 8-88. COARSE_CUR_B Register 7 6 5 4 3 2 1 0 DAC1_CBIAS_SLEEP COARSE_CUR_B R/W-0h R/W-0xF Table 8-108. COARSE_CUR_B Register Field Descriptions Bit Field Type Reset Description 7-4 DAC1_CBIAS_SLEEP R/W 0h DAC coarse current setting during sleep. See discussion for DC coupled outputs in Section 9.1.6 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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8.102 DEM_ADJ Register (Offset = 0727h) [reset = 11h]

DEM_ADJ is shown in Figure 8-88 and described in Table 8-108. Return to the Register Summary Table DEM Adjust Table 8-109. Single Edge DEM Adjust 7 6 5 4 3 2 1 0 DEM_ADJ1 DEM_ADJ0 R/W-0x1 R/W-0x1 Table 8-110. DEM_ADJ Register Field Descriptions Bit Field Type Reset Description 7-4 DEM_ADJ1 R/W 0x1 Adjust DEM behavior for single-edge data-independent DEM for DAC1. This register has no effect unless DAC1 is configured for single-edge data-independent DEM. Only 0 to 3 are valid settings, 4 through 15 are reserved. 3-0 DEM_ADJ0 R/W 0x1 Adjust DEM behavior for single-edge data-independent DEM for DAC0. This register has no effect unless DAC0 is configured for single-edge data-independent DEM. Only 0 to 3 are valid settings, 4 through 15 are reserved.

8.103 DEM_DITH Register (Offset = 0729h) [reset = 00h]

DEM_DITH is shown in Figure 8-89 and described in Table 8-111. Return to the Register Summary Table. DAC DEM and Dither Control Figure 8-89. DEM_DITH Register 7 6 5 4 3 2 1 0 DEM_DACB DEM_DACA DITHER_DACB DITHER_DACA R/W-00b R/W-00b R/W-00b R/W-00b Table 8-111. DEM_DITH Register Field Descriptions Bit Field Type Reset Description 7-6 DEM_DACB R/W 00b 0 : Enable single-edge, data-independent DEM for DACB 1 : Enable dual-edge, data-independent DEM for DACB 2 : Enable data-dependent DEM for DACB 3 : DEM disabled for DACB 5-4 DEM_DACA R/W 00b 0 : Enable single-edge, data-independent DEM for DACA 1 : Enable dual-edge, data-independent DEM for DACA 2 : Enable data-dependent DEM for DACA 3 : DEM disabled for DACA 3-2 DITHER_DACB R/W 00b 0 : Enable single-edge dithering for DACB 1 : Enable dual-edge dithering for DACB 2 : RESERVED 3 : Dithering disabled for DACB www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 191 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 8-111. DEM_DITH Register Field Descriptions (continued) Bit Field Type Reset Description 1-0 DITHER_DACA R/W 00b 0 : Enable single-edge dithering for DACA 1 : Enable dual-edge dithering for DACA 2 : RESERVED 3 : Dithering disabled for DACA

8.104 DAC_OFS[0:1] Register (Offset = 072Ah) [reset = 00h]

DAC_OFS[0:1] is described in Table 8-112. Return to the Register Summary Table. DAC Offset Control. DAC_OFS[0] is at the lowest address. Table 8-112. DAC_OFS[0:1] Register Field Descriptions Bit Field Type Reset Description 15-13 Reserved R/W 000b 12-0 DAC_OFS[n] R/W 00b Offset adjustment for DACn (n = 0 or 1). The value in this register is added to the DACn output. This is a 2’s complement, 13-bit signed value. The LSB weight is one DAC LSB. The value programmed into this register passes through a saturation function to limit the adjustment to what is possible. If dithering is enabled on DACn (see DEM_DITH), DAC_OFS[n] is saturated to the range +/- 128. If dithering is disabled on DACn, the saturation range is +/-3968. See Section 7.3.4. Note: This value should only be changed when DP_EN=0 or DAC_OFS_CHG_BLK=1. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Startup Procedure for DUC/Bypass Mode

The list below is the startup procedure for the device: 1. Power up the device with ball RESET asserted using the procedure in Section 9.3.1. 2. Apply CLK and then de-assert RESET. 3. Wait for fuse values to be loaded (register FUSE_DONE returns 1). 4. Set up all the operational parameters (registers can be programmed in any order): a. Program interpolation factor in the DUC_L register. b. Determine the total interpolation factor (LT), which is needed in the next steps. Except for DES1X mode (dual edge sampling with no interpolation), LT = DUC_L. c. Determine many sample streams are needed and program the JESD_M register. d. Select a JESD204C mode from Table 7-22. Make sure the selected mode supports the value of LT computed previously and the desired link layer encoding. Also make sure the mode supports the number of desired streams set in the JESD_M register. Program the mode number into the JMODE register. e. Program the JENC register to select 8b/10b or 64b/66b operation. f. Compute the value of R using Table 7-22 and the LT value computed earlier. g. Using Table 7-17 (8b/10b) or Table 7-18 (64b/66b), identify a row that matches the R value and DAC clock frequency. Program REFDIV, MPY, RATE and VRANGE according to the tables. h. If necessary, program LANE_SELn to bind the appropriate physical lanes to logical lanes. Program LANE_INV if necessary to account for any lane inversion (differential pairs swapped on PCB). i. Program other common settings according to your desired usage (SUBCLASS, SFORMAT, SCR in JCTRL). j. If using 8b/10b encoding, program the KM1 register to set the K parameter. KM1 must match the link partner. Be sure to honor the constraint imposed by the KR parameter from Table 7-22. k. If subclass 1 operation is desired (SUBCLASS=1), you must also program RBD. Determine the appropriate value for RBD by referring to: Programming RBD. l. Optional Serdes parameters can also be programmed if necessary (that is, JPHY_CNTL, EQ_CNTL, EQZERO, LANE_EQn). m. Program any DAC or DUC related registers, for example the DAC_SRC register to route data to your desired DACs and configure MXMODE to set the DAC output mode. 5. Program the transmitter (link partner, that is, FPGA or ASIC), and instruct the transmitter to begin transmission. 6. Program JESD_EN=1 to start up the receiver. 7. Program DP_EN=1 to enable the datapath. This is required to allow data to flow to the DAC. If only JESD204C diagnostics are performed, you can leave DP_EN at 0. 8. Wait for the VDDDIG supply voltage to re-stablize as the supply current transient can result in a dip in the supply voltage. 80 microseconds is be sufficient, but this can be optimized based on actual measurements. 9. If SUBCLASS=1, SYSREF is necessary to establish the LMFC/LEMC phase in the receiver. Follow this procedure: a. Using two separate transactions, program SYSREF_RECV_SLEEP=0 and then SYSREF_PROC_EN=1 (both in register SYSREF_CNTL). b. Program SYSREF_SEL to a known good value (see SYSREF Windowing for details on how to calculate SYSREF_SEL using the SYSREF windowing function). c. Program SYSREF_ALIGN_EN=1. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 193 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

d. Apply at least five SYSREF pulses to the SYSREF input. The period of each SYSREF cycle must meet the requirements in Table 7-3. 10. Read the JESD_STATUS register to confirm operation of the link (LINK_UP field in JESD_STATUS = 1). If the LINK_UP field returns 0, verify these items: a. If the PLL_LOCKED field in JESD_STATUS returns 0, verify the correct PLL settings (REFDIV, MPY, RATE and VRANGE). Verify the CLK frequency is correct. b. If SUBCLASS = 1, and the ALIGNED field in JESD_STATUS returns 0, verify SYSREF has been applied and the SYSREF processor is enabled SYSREF_PROC_EN. c. If above are not the problem, then read the LANE_STATUSn (only read registers for logical lanes 0 to L-1). Identify if some lanes cannot acquire code group or block synchronization. If so, verify the transmitter has been programmed correctly. Verify LANE_SELn is programmed correctly. Consider performing PHY tests to verify/optimize PHY operation (PRBS testing using JTEST, eye-scan testing, or equalizer optimization). 11. If coherency between multiple NCOs is required, the NCOs must be re-synchronized using one of the methods described in section NCO Synchronization for multi-device/deterministic synchronization, or using SPI_SYNC with NCO_SYNC_SRC if only internal NCO phase is required. 12. To configure the part for a different mode, set DP_EN=0 and JESD_EN=0. Then return to step 4.

9.1.2 Startup Procedure for DDS Mode

The DUC channels can operate in DDS mode by setting the DDS_EN register before setting DP_EN. To use DDS mode, perform these steps: 1. Program DDS_EN=1 (the DDS isn’t enabled until DP_EN is set) 2. Program JESD_M to 2, 4, 6, or 8 to enable 1, 2, 3, or 4 DDS channels respectively 3. Program initial values for AMP, FREQ, and PHASE 4. There is no need to program NCO_EN (it’s implied by DDS_EN=1) 5. Program DUC_FORMAT=1 if complex output is desired. If DUC_FORMAT=1, JESD_M must be set to 2 or 4 (1 or 2 channels). 6. Program DAC_SRC to bind DUC (DDS) channels to DACs 7. Leave JESD_EN=0 8. Program DP_EN=1 9. Wait for the VDDDIG supply voltage to re-stablize as the supply current transient can result in a dip in the supply voltage. 80 microseconds is be sufficent, but this can be optimized based on actual measurements. 10. If coherency between multiple NCO's is required, the NCO's must be re-synchronized using one of the methods described in section NCO Synchronization for multi-device/deterministic synchronization, or using SPI_SYNC with NCO_SYNC_SRC if only internal NCO phase is required. 11. The DUC channels now run in DDS mode and begin outputting tones. Use AMP, FREQ, and PHASE to update the waveform parameters. You must re-synchronize the NCOs to apply new values to the NCOs. Use AMP_R, FREQ_R, and PHASE_R to inspect the values that are currently in effect. 12. Other NCO settings also apply to DDS mode such as NCO_AR, and NCO_CONT. The NCOs can be synchronized in the same fashion as DUC mode.

9.1.3 Understanding Dual Edge Sampling Modes

Dual edge sampling modes ( DES1X, DES2XL/H) outputs unique samples on both the rising and falling edge of CLK, doubling the sample rate for the same clock frequency compared to NRZ, RTZ or RF modes. DES1X mode requires input samples for both clock edges while DES2XL/H modes generate the falling edge samples by digital interpolation. The 2x DES interpolator has an 80% passband bandwidth, 55dB stopband attenuation and can be configured as low pass or high pass (The response is shown in Figure 9-1). The DES interpolator is lowpass in DES2XL mode, passing the signal below 0.4*F CLK and removing the image above 0.6*F CLK. IN DES2XH mode signals above 0.6*F CLK are passed and the image below 0.4*F CLK is removed. In the transition band between 0.4*F CLK and 0.6*F CLK, the passband is attenuated by up to 6dB and the image attenuation is significantly reduce. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 9 1 0 - 1 2 0 - 1 0 0 - 8 0 - 6 0 - 4 0 - 2 0 N R Z D E S 2 X L Figure 9-3. Output Spectra Comparing DES2XL and NRZ Modes RF and DES2XH mode behave similarly. Figure 9-4 shows a tone at 7997MHz with 10GHz clock in RF and DES2XH modes. HD2 and HD3 have folded frequencies around 6GHz in NRZ mode, these are suppressed > 10dB in DES2XH mode. Figure 9-4. Output Spectra Comparing DES2XH and RF Modes One additional benefit of DES2XL compared to NRZ mode is an improvement in additive phase noise of approximately 6dB in the 1/f region of the offset frequency (see Figure 9-5). This is due to DES2XL using both the rising and falling edges of the clock, which cancels some common mode noise in the clock path. Since RF mode also uses the falling edge to generate the inverse sample, there is no significant difference between RF mode and DES2XH mode. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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O f f s e t F r e q u e n c y ( H z ) SSB Phase Noise (dBc/Hz) 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 1 x 1 0 - 1 8 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 N R Z D E M / D i t h e r o f f N R Z D E M / D i t h e r o n D E S 2 X L D E M / D i t h e r o f f D E S 2 X L D E M / D i t h e r o n fCLK = 10.24GHz Figure 9-5. Phase Noise vs Offset Frequency at 1GHz There are 3 small disadvantages of DES2XL and DES2XH modes to be aware of: 1. the attenuation of the signal in the transition band of the DES interpolation filter between 0.4*FCLK and 0.6*FCLK 2. An increased latency of 97 clock cycles. or 9.7ns with a 10GHz clock, due to the DES interpolation filter 3. An increase in power of 250mW with a 10GHz clock, due to the DES interpolation filter

9.1.4 Eye Scan Procedure

The PHY layer contains features for generating eye diagrams. A variety of different modes are supported (see ES register for list of modes). The following sections describe how to generate eye-scan data from the part and some approaches for building an eye-diagram. 1. Configure the part for JESD204C operation by following the steps in the Startup Procedure for DUC Mode. Return here after setting JESD_EN=1. Eye-scan can be run with JESD204C bitstreams, but can also work with general PRBS input stimulus. Eye-scan is run on all enabled physical lanes simultaneously. 2. Program ES to the desired eye-scan mode. 3. If ES is less than 8, you must program ESVO to the desired voltage offset. For other modes, the eye-scan logic automatically adjusts the voltage offset of the eye-scan sampler. 4. Program ESPO to the desired phase offset. 5. Program ES_BIT_SELECT to a value from 0 to 19. Eye-scan analyzes every 20th received bit (decimate- by-20). ES_BIT_SELECT adjusts this decimation phase. For random stimulus, this does not impact the results. If the input has repeating patterns, this can affect the results. 6. Program ESLEN to the desired number of samples. Higher settings give more consistent results. 7. Set ECOUNT_CLR = 1 then set ECOUNT_CLR to clear the error counter. This step is recommended, but can be skipped if desired (e.g. to add up counts from multiple eye scan runs). This can also be skipped if ECOUNT won’t be used (for modes with ES of 8 or greater) 8. Program ESRUN = 1 to start the scan. 9. Poll ESDONE until ESDONE returns 1 for each of the lanes you want to run eye-scan on. 10. If the selected eye-scan mode modified the eye-scan voltage offset (inner/outer/average modes), read ESVO_S to get the inner/outer/average eye boundary. For other eye-scan modes, read ECOUNT to return the number of mismatches (or matches) recorded. 11. Program ESRUN = 0. 12. Return to step 2 to run another eye-scan data collection process. The receiver can remain enabled during multiple iterations of steps 2-12. There are two basic approaches to build an eye diagram using the eye-scan feature. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 197 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

1. Fast approach using ESVO_S: a. Repeat the procedure above for each valid value of ESPO. For each value of ESPO, run an inner-eye analysis of zeros and ones. This locates the maximum zero (ESVOmax0 ) and minimum one (ESVOmin1) for each value of ESPO. b. All the cells of the eye between ESVOmax0 and ESVOmin1 (inclusive) can be colored black, and all other cells colored white. c. Additional detail can be added to the eye-diagram by including outer and/or average analysis (see ES). For example, the ESVO_S values produced from average analysis can be colored red, while all other values between and including the inner and outer values colored white. 2. Detailed approach using ECOUNT: a. select an eye-scan mode that counts mismatches. Repeat the procedure outlined above for each valid value of ESVO and ESPO. b. After each run, record the value of ECOUNT (resetting ECOUNT before each run). c. Each eye-scan run corresponds to one cell of the eye-diagram. ESPO is the x-coordinate of the cell. ESVO is the y-coordinate of the cell. The intensity of the cell is proportional to ECOUNT/Nsamples, where Nsamples is the number of analyzed samples per run (determined by ESLEN). d. This approach takes much more time to run, but can provide a more granular eye-diagram.

9.1.5 Pre/Post Cursor Analysis Procedure

Pre/Post Cursor Analysis can be used to determine an optimum setting for pre-emphasis in the transmitter. 1. Program JESD_EN = 0 if necessary. Program EQMODE = 1. Program JESD_EN = 1 and allow sufficient time for the equalizer to adapt and settle. You can read EQLEVEL_S multiple times to verify the value is stable or toggling between adjacent values. 2. Set EQHOLD = 1 to lock the equalizer (disable adaptation). This also causes EQOVER and EQUNDER fields to become low. 3. Wait at least 48UI, and proportionally longer if the CDR activity is less than 100% so the 1 on EQHOLD is sampled and acted upon. The SPI is slow enough that no explicit delay is be necessary. 4. Set EQMODE to 2 or 3 to select pre or post cursor analysis respectively. With a separate SPI transaction, set EQHOLD = 0. The equalization characteristics of the received signal are analyzed (the equalizer response continues to be locked). 5. Wait at least 150,000UI to allow time for the analysis to occur, proportionately longer if the CDR activity is less than 100% 6. Examine EQOVER and EQUNDER for results of analysis: a. EQOVER high indicates the signal is over equalized; b. EQUNDER high indicates the signal is under equalized; 7. Set EQHOLD = 1 8. Adjust the transmitter pre-emphasis and repeat steps 3 thru 7 if required. 9. Set EQMODE = 1, and with a separate SPI transaction, set EQHOLD = 0 to exit analysis mode and return to normal adaptive equalization.

9.1.6 Sleep and Disable Modes

There are several methods to power down or temporarily disable the DAC outputs. To prevent asymmetric aging of the device circuits, in some options a low level output from the DACs is maintained. Table 9-1 lists the options for sleep or disabling the DAC outputs. The most power is saved in full power down, which is enable by setting the MODE register to 0x3. In this mode a low level output signal is maintained to prevent asymmetric aging. Returning to full operation from full power down takes 100's of microseconds. One or both DAC outputs can be disabled by setting the corresponding MXMODE register to 0x6. This saves some power and the DAC outputs a low level signal to prevent asymmetric aging. If only one channel is DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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disabled, low level spurs from the disabled channel can feed into the active channel, creating spurs around -80 dBFS. The TX ENABLE function, either through the TXEN0/1 balls or TX_EN registers, provides a method to quickly disable the DAC output by forcing the digital code to 0 (midscale) (see Section 6.9 for the TX ENABLE latency). When the QUITE_TX_ENABLE register is 0, a low level signal is still maintained at the output to prevent saturation. When QUITE_TX_ENABLE is 1, if data independent DEM and Dither is enable, this prevents asymmetric aging. If DEM and dither are disabled or DEM is set to data dependent DEM, the DAC can degrade over the lifetime of the device if a significant faction of the lifetime is spent in this mode. The degradation is channel specific, only affecting the channel that is disabled. Table 9-1. DAC Sleep and Output Disable Options Option MXMODE TX_EN QUIET_TX_DISABLE DEM DITHER Low level output long term degradation Power Savings Device Full Power Down (MODE = 0b11) - - - - - yes no Most DAC disable 6 1 - - - yes no Some TX Enable any 0 0 - - yes no Least TX Enable 0-5 0 1 0,1 0,1 no no Least TX Enable 0-5 0 1 2, 3 3 no yes Least TX Enable 6 0 1 0,1 0,1 no no Least TX Enable 6 0 1 2,3 3 no yes Least When the DAC is in full power down, the common mode voltage at the DAC output during sleep needs to be maintained below 2V. For AC coupled outputs, the bias is usually provided by an inductor or a balun center tap to 1.8V which forces the common mode also to 1.8V. For DC coupled output, which are typically terminated through a resistor to a voltage above 1.8V (for example, 2.3V), sufficient DAC output current must be provided to reduce the common mode voltage to less than 2V. This is achieved by programming DACx_CBIAS_SLEEP (Address 0x724 bits 7:4 for DACA and Address 0x726 bits 7:4 for DACB) according to the following equation: D AC _ C BI AS _ SL EE P = c ei l 2 ∙ V BI A S − V OU T _ C M _ SL EE P R T ERM − 7.36 m A 1.47 m A (4) where:

VOUT_SLEEP is the DAC output common mode in sleep (≤ 2V)
VBIAS is the external DC bias
RTERM is the external bias resistor/termination to VBIAS
ceil is the ceiling operator (integer round up)

9.1.7 Radiation Environment Recommendations

Careful consideration must be given to the environmental conditions when using a product in a radiation environment. Table 9-2 provides a summary of radiation tolerance for device features. Table 9-2. Summary of Radiation Tolerance Feature Radiation Tolerance Writable SPI registers (excluding write-to-clear registers) Implemented with upset immune flip flops. Radiation does not alter the state. Read-only SPI registers that return constant values Radiation does not alter the state (that is, CHIP_TYPE, CHIP_ID, CHIP_VERSION, VENDOR_ID) www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 199 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Table 9-2. Summary of Radiation Tolerance (continued) Feature Radiation Tolerance Read-only SPI status registers associated with JESD204C physical or link layers (excluding write-to-clear registers) The value returned can be affected by radiation (SYSREF_POS, LINK_UP, JSYNC_STATE, PLL_LOCKED, LANE_ARR, FIFO_STATUS, JCAP_STATUS, JCAP, BER_CNT, LANE_EQS, ESDONE, ESVO_S, ECOUNT, RXDMUX, CDRPHASE, RXCSA_S). FUSE_DONE register FUSE_DONE is upset-immune. OCSTS register Once the PHY is initialized and offset calibration is completed, OCSTS returns offset values that are upset immune. However, an upset can cause a PHY PLL to lose lock which can re-trigger the offset calibration process, generating new offset calibration values. Sticky SPI status registers (write-to-clear) These bits are set when certain events occur in upset-vulnerable logic. An upset can cause the event to occur, and set the sticky bit. An upset can also prevent an event from setting the sticky bit; however this is unlikely as the window of time that this can occur is small. Once the sticky bit is set, an upset does not clear the bit (the flop that is read by SPI is upset immune). Examples: LANE_ERR, PLL_LOCK_LOST, SYS_ALM, REALIGNED, CLK_REALIGNED. JESD204C Receiver The JESD204C receiver is not upset immune, but is designed to be free from functional interrupts (can recover automatically from upsets). See JESD204C Reliability. Interpolation Filters (DUC and DES2X filters) The interpolation filters are not upset immune and can generate glitches when upset. The filters do not suffer from functional interrupts. NCOs in DUCs The radiation sensitivity of the NCO is TBD. Temperature Sensor The ADC inside the temperature sensor is not upset immune. To improve reliability, the recommendation is to read TS_TEMP three or more times, and compute the median value.

9.1.7.1 SPI Programming

The SPI interface and register set are implemented with upset immune logic. The state of writable SPI registers will not be altered by radiation. The Fast-Reconfiguration interface is not upset immune and should not be enabled in radiation environments.

9.1.7.2 JESD204C Reliability

The JESD204C receiver is implemented with high speed flip-flops that are not single-upset-immune. As a result, the JESD204C link can experience various errors when exposed to radiation. To improve the overall reliability of the link and make sure the link can automatically recover from an upset, several recommendations should be followed. 1. Use subclass 1 operation by setting SUBCLASS=1. 2. 64b/66b link encoding (JENC=1) is preferred over 8b/10b encoding. The 64b/66b link layer provides full-time block and EMB synchronization (pilot) signals, so misalignment caused by radiation can be detection quickly and consistently. In contrast, the 8b/10b link layer relies on synchronization characters that do not have a high occurrence rate, so misalignment takes longer to detect. 3. Use a periodic and continuous SYSREF signal. Keep SYSREF alignment enabled at all times in the Tx and Rx devices. If radiation upsets the Tx or Rx LMFC/LEMC, the SYSREF signal will re-establish their phase and keep the Rx and Tx synchronized. If this recommendation is not followed, radiation can cause a persistent change in the link latency, or cause lanes to be persistently misaligned (causing persistent, corrupt samples to be sent to the DAC). 4. 4. The transmitting logic device that provides data to the SerDes receiver should be designed with radiation tolerance in mind. Recommendations include: a. When possible, align counters continuously to SYSREF. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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b. FIFOs should have a means to detect and recover automatically from upsets that might cause overflow/ underflow conditions. 5. the user may program JTT to get an additional level of protection from functional interrupts.

9.1.7.3 NCO Reliability

The NCO does not include radiation immune flip-flops; however, there are two general strategies described in the following sections that can be employed to make sure the NCO recovers from upset events.

9.1.7.3.1 NCO Frequency and Phase Correction (Strategy #1)

This strategy uses a periodic reference signal to correct any upsets in the NCO accumulator. This strategy is appropriate for phased-array systems or other systems where the NCO phase must remain coherent with other system components. 1. Program NCO_AR=1 to configure the accumulator to be reset on every synchronization event. 2. Configure the NCO to use SYSREF as the synchronization source (NCO_SYNC_SRC=2). Program SPI_SYNC=1. 3. Make sure the SYSREF generator is configured for continuous/periodic output. 4. Since the accumulator is reset periodically, the user must make sure that the programmed NCO frequency is an integer multiple of the SYSREF frequency. Consider the frequency raster that the system requires when choosing the SYSREF frequency. 5. If the user cannot choose a SYSREF frequency that satisfies the frequency raster and is also a sub- harmonic of the multiframe/EMB frequency, then use the LSB of the JESD204C data stream to periodically synchronize the NCO. Use NCO_SYNC_SRC=3, and provide a periodic reference signal on the LSB of the I samples for DUC0. 6. If any NCO accumulator or internal frequency register is upset, it is restored on the next synchronization event. This strategy also uses a periodic synchronization signal, but the NCO accumulator is not reset. Only the internal frequency registers inside each NCO are corrected by the synchronization signal. This makes sure the NCO returns to the proper frequency after an upset occurs, but the phase of the NCO is not corrected. This strategy is appropriate for non-phased-array systems where an occasional, arbitrary phase jump can be tolerated. 1. Program NCO_AR=0 to configure the accumulator to NOT be reset by a synchronization event. 2. Configure the NCO to use SYSREF as the synchronization source (NCO_SYNC_SRC=2). Program SPI_SYNC=1. 3. Make sure the SYSREF generator is configured for continuous/periodic output. 4. Since the accumulator is not reset periodically, the user has the freedom to program any NCO frequency regardless of the SYSREF frequency. The period of SYSREF must still be a multiple of the multiframe/EMB period. 5. While the NCO is operating, any upset to the internal frequency register is corrected on the next SYSREF pulse (the frequency word is re-copied from the SEU-immune FREQ register). The NCO operates for a brief time at an improper frequency before returning to the correct frequency, but with arbitrary phase.

9.2 Typical Application

9.2.1 S-Band Radar Transmitter

9.2.2 Design Requirements

S-band covers a frequency range of 2GHz to 4GHz. For this example, use a radar with signal bandwidth of 200MHz and a center frequency of 3.2GHz. Doppler radars use the frequency shift in the returned signal to measure the velocity of object. Large reflected signals from for example ground clutter mix with the TX and RX phase noise, which can potentially swamp the www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 201 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

return signal from a small moving object. This places a requirement on close in phase noise for the close in phase noise of the radar chirp. Radars are also sensitive to spurious signals, and for this example, assume 90dBFS is required for the inband SFDR.

9.2.3 Detailed Design Procedure

A summary of the design parameters are listed in Table 9-3. A input sample rate of 250MSPS complex covers the 200MHz signal bandwidth, and interpolation by 32x is used to increase the TX sample rate to 8GSPS. The device's numerically controlled oscillator (NCO) is used to place the signal at the TX output at 3.2GHz. An addition 2x interpolation is applied in DES2XL mode, increasing the sample rate to 16GSPS. The suppression of the image at 4.7 - 4.9GHz in DES2XL mode would be limited by the 2x DES interpolator to 40dB. To optimize the low offset frequency phase noise, DEM and dither are disabled. The JESD204C interface is configured in JMODE 5 with 4 streams (2 IQ pairs) and 1 Serdes lane per IQ pair. With 64/66 bit encoding, the Serdes baud rate is 8.25Gbps. Table 9-3. Design Parameters for an S-band Transmitter Parameter Value Input Clock 8GHz DAC Sample Rate 16GSPS Output Mode DES2XL DEM and Dither Settings Off TX Interpolation Factor 32x TX Input Rate 250MSPS Complex NCO frequency 3.2GHz JMODE 5 # Streams 4 (2x IQ pairs, 1/DAC) # Serdes Lanes 2 Encoding 64/66 Serdes Baud Rate 8.25Gbps

9.2.4 Detailed Clocking Subsystem Design Procedure

One of the major advantages of the DAC39RF10-Sx and 'RFS10-Sx in applications like Doppler radar, Quantum Computing and Wireless Test is the ability to directly synthesize very low phase noise signals all the way through X-band (12GHz). To take full advantage of the exceptionally low additive phase noise of the DAC, a high-performance clock is required. Equally important in most systems is the impact of Size, Weight, Area, Power and Cost (SWAP-C). This means each system architect must weight tradeoffs in performance vs. overall system SWAP-C based on system requirements. This section presents three clocking examples based on SWAP-C vs. performance tradeoffs. Figure 9-6 shows a plot of phase noise for an 8GHz sample clock produced by an integrated PLL+VCO, integrated PLL with external high performance VCO and a fully discrete high performance analog PLL. All examples assume a reference clock is provided as an input to the synthesizer, which can range from low cost surface mount crystal oscillators all the way to expense reference subsystems. The DAC39RF10-Sx and 'RFS10-Sx additive phase noise at 8GHz is also provided for comparison , even for the analog PLL, the clock phase noise degrades the DAC39RF10-Sx and 'RFS10-Sx output phase noise for offset frequencies below 5MHz. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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Figure 9-6. Phase Noise of DAC Clock Examples with the Device Additive Phase Noise

9.2.4.1 Example 1: SWAP-C Optimized

The best SWAP-C sub-system leverages the high levels of integration offered by modern PLL+VCO devices, such as the LMX2820. Figure 9-7 shows a block diagram of the clocking sub-system. An external reference clock feeds the LMX2820 input, which is then used to lock the internal PLL+VCO before being fed to the output buffers. Only external passives are required to construct the loop filter and complete the sub-system system. PFD + CP VCO Loop Filter LMX2820

400 MHz

/20 To DAC Clock Distribution 50/g10.1uF CPOUT VTUNE Figure 9-7. LMX2820 with Internal VCO The LMX2820 is a flexible device and configuration can be overwhelming. For example, deciding how to decipher configure dividers, set loop filter components, and so on. A few high-level guidelines can be taken into consideration to optimize phase noise. First,always operate the LMX2820 in integer mode when possible, as opposed to fractional mode. This implies that relationship between reference clock and output clock follows the general form: FOUT = (FREF/NREF) x NDIV/NOUT (5) where N REF, N DIV and N OUT are the reference, feedback and output dividers respectively. F REF is the input reference frequency and FOUT is the output frequency used as the DAC clock. If this ratio cannot be found, then fractional mode must be used at the expense of degraded overall phase noise. Second, the best in-band phase noise is achieved when the phase detector frequency is maximized and the feedback divider is minimized. The LMX2820 has a maximum phase detector frequency of 400MHz and an optional reference doubler is available for reference inputs up to 200MHz. For the same output frequency, each doubling of phase detector frequency (while halving the feedback divider) results in 3dB of in band phase noise reduction. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 203 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

For an 8GHz output, use the maximum phase detector frequency of 400MHz. Set NREF = 1, NDIV = 20, and NOUT = 1 (divider bypass). For a slight degradation in in-band noise, the input can be set to 200MHz and the reference doubler is used. Third, note that any noise on the reference input impacts close in phase noise before the in-band noise begins to dominate. In-band noise is a combination of PLL noise (phase detector, charge pump and dividers) and VCO noise, while wideband noise is limited by the noise floor of the output buffers. Close in noise is limited by the device flicker, which is independent of phase detector frequency and scales 20 x LOG base10 with output frequency. Finally, when operating the LMX2820 above 11GHz, the integrated output doubler must be used and this results in a sub-harmonic (that is, output frequency divided by 2) that possibly requires external filtering using either a high-pass or bandpass filter (depending on system requirements). Following the LMX2820 output with a narrow bandpass filter can also be used to suppress wideband noise. The PLLatinumSim software is available from TI to design the external loop filter passive values.

9.2.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO

An external VCO can significantly improve in-band and wideband noise, with best phase noise typically achieved with narrow band VCOs such as Voltage Controlled Crystal Oscillators (VCXO), Voltage Controlled Surface Acoustic Wave Oscillators (VCSO) and Dielectric Resonance Oscillators (DRO). For this design, a Synergy Microwave 8GHz DRO (SDRO800-8), is used for the wideband noise (-170dBc/Hz) and low flicker noise corner (-160dBc/Hz at 1MHz). DROs are typically available from about 5 to over 25GHz. Figure 9-8 shows a block diagram of the synthesizer. An external active loop filter is used to improve noise performance and extend the tuning voltage range required for the DRO (0 to 10V). The DROs output is split, with one output feeding back into the LMX2820 and the other being sent to the DAC clock distribution network. PFD + CP/1 LMX2820 /20 50/g10.1uF -2V THS4031 390/g168nF 1.5nF +1.2V VCO DRO 8V EP2C+ To DAC Clock Distribution RFIN CPOUT VTUNE Figure 9-8. External LMX2820 with an External VCO In this implementation, the loop bandwidth was set to around 24kHz, where the flicker noise of the PLL intersects the open loop noise of the DRO. This offers the best overall integrated phase noise. The noise floor is improved by about 10dB from the fully integrated example since the output buffers were not used and the DRO has exceptional broadband noise of around -170dBc/Hz. As with the integrated VCO, the loop filter components can be designed using PLLatinumSim software.

9.2.4.3 Example 3: Discrete Analog PLL for Best DAC Performance

When phase noise performance is paramount, a discrete analog PLL (APLL) offers substantially lower phase noise than the integrated examples. The trade off is increased SWAP-C. Figure 9-9 shows the block diagram of such an implementation that uses the same Synergy Microwave 8GHz DRO as the LMX2820 external VCO example discussed previously. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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1 GHz

-2V THS4031 SIM-153LH+ EP2C+ To DAC Clock Distribution R2C1 Figure 9-9. Discrete Analog PLL The APLL outperforms the previous examples by avoiding use of digital dividers and phase detectors, which significantly degrade phase noise. Instead passive diode-based frequency multipliers and mixers are used, which contribute little additive phase noise. Like all synthesizers, a frequency reference with very good close in phase noise, below the loop bandwidth of the APLL, is required for best performance. In this case, a 1GHz reference was chosen as the reference is a convenient division of the sample rate and is available either as an output of an R&S SMA100B RF signal generator or as a standalone unit from Wenzel Associates. As mentioned previously, the APLL does not use digital dividers or phase detectors, which significantly degrade phase noise. Instead the reference is multiplied up to the output frequency using passive multiplier stages (see Figure 9-10). A passive mixer is used as a phase detector that feeds a low noise operational amplifier loop filter. The DRO output is split with one output going to the DAC clock distribution network and the other feeding back into the RF port of the mixer. SYK-2R+PSA-14+

2 GHz

1.2 GHz

4 GHz2.75 GHz PSA-14+ EP2C+

4 GHz

8 GHz4.4 GHz PMA2-183LN+

8 GHz

Figure 9-10. Reference Multiplier Chain The multiplier chain uses low noise amplifiers, passive diode multipliers and bandpass filters. For this part of the circuit, what is most critical is the close in phase noise below the loop bandwidth of the PLL. Not all amplifiers demonstrate good close in noise, especially when driven near or into compression. Generally, heterojunction bipolar transistor (HBT) amplifiers, have low flicker noise and operate well when driven into compression. Bandpass filters were selected to remove the F IN and 3 x F IN/2 harmonics that are only partially suppressed by the multipliers. In some implementations the driving amplifier can be filtered to prevent degradation of the harmonic suppression performance. This chain was experimentally optimized, but additional attenuation between stages can be added to manage reflections and amplifier operating conditions. The loop filter bandwidth is set near where the open loop DRO phase noise crosses the multiplied reference noise with a damping factor set to give a smooth role off that minimizes integrated phase noise. An optional additional feedback cap can be used to speed up the role off if desired (C2 is set roughly to 1/10 th to 1/100th of C1). The loop filter component values were determined experimentally for this design. In some implementations a start-up circuit is needed to help the loop acquire lock. In practice, the initial power up was all that is needed for the loop to pull in and lock. 9.2.4.4 10GHz Clock Generation For higher sample rates several options are available. First, a DRO can be selected that operates directly at the desired frequency and the multiplier chain and or reference frequency can be modified accordingly. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 205 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

An alternative is to use dividers and mixers to translate the APLL output to a new higher frequency. Figure 9-11 shows an example for a 10GHz clock synthesizer. This uses the same reference multiplier chain and APLL as described above and adds a mixing stage to translate the DAC clock from 8 to 10GHz. 50/g10.1uF 50/g10.1uF LMX1204 EP2C+ CMD275P4 LO IF RF MDB-24H+ PMA2-183LN+

10 GHz

-2V THS4031 SIM-153LH+ EP2C+ R2C1 PMA2-183LN+ To DAC Clock Distribution Reference Multiplier 8 GHz Analog PLL 8 to 10 GHz Mixing Stage Figure 9-11. 10GHz Clock Synthesizer The LMX1204 can operate as a buffer, multiplier or divider. In this case the LMX1204 is used to divide the 8GHz APLL output by 4, which is then mixed with the input to translate the clock to 10GHz. A bandpass filter is required after mixing to remove the LO feedthrough and undesirable mixing products. Figure 9-12 shows the input 8GHz scaled to 10GHz and resulting 10GHz after mixing. As with the reference multiplier chain, special care must be taken selecting the components and operating points for best phase noise. A slight improvement in noise floor was found by power combining two the of the LMX1204 outputs before feeding the IF input of the mixer. O f f s e t F r e q u e n c y ( H z ) Single Sideband Phase Noise (dBc/Hz) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 - 1 7 0 - 1 6 0 - 1 5 0 - 1 4 0 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 1 0 G H z C l o c k

8 G H z C l o c k ( s c a l e d t o 1 0 G H z )

Figure 9-12. 8GHz and 10GHz Clock Phase Noise

9.2.5 Application Curves

The radar chip waveform used for testing is a non-linear frequency modulated (NLFM) pulse, lasting 4096 samples at the 250MSPS complex input rate. At baseband, the frequency ramps from -100MHz to + 100MHz, following a frequency ramp curve developed by Price and shown in Equation 6 [Price R. Chebyshev Low Pulse Compression Sidelobes via a Nonlinear FM. National Radio Science Meeting of URSI; PortSaid, Egypt: 1979.] with T = 4096 samples, B = 0.8, Bl = 0.5611 and Bc = 0.238. f f , B l , B c = B × t − T 2 T × B l + B c 1 − 4 t − T 2 T 2 (6) DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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F r e q u e n c y ( G H z ) Amplitude (dBm) 0 1 2 3 4 5 6 7 8 - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 Figure 9-17. NLFM Chirp Output Spectra Across 0 - 8GHz F r e q u e n c y ( G H z ) Amplitude (dBm) - 1 3 0 - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 Figure 9-18. NLFM Chirp Output Spectra Across 1GHz F r e q u e n c y ( G H z ) Amplitude (dBm) - 1 2 0 - 1 1 0 - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0 - 3 0 - 2 0 - 1 0 Figure 9-19. In Band Single Tone Frequency Spectra with fOUT = 3.211GHz DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

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9.3 Power Supply Recommendations

The device has three supply voltages and requires seven supply domains to achieve data sheet performance as shown in Table 9-4. Table 9-4. Recommended Power Supply Domains Voltage Supply Domain Device Supplies +1.8V VDDA VDDA18A, VDDA18B VDDIO VDDIO VDDCSR VDDCLK, VDDSYS, VDDR +1V VDDL VDDLA, VDDLB VDDCLK VDDCLK10 DVDD VDDDIG, VDDT, VDDDEA and VDDDEB -1.8V VEEx VEEAM18, VEEBM18 The recommended power supply is shown in Figure 9-20 for -SP grade and Figure 9-21 for -SEP grade. The power-supply voltages must be low in noise and provide the needed current to achieve rated device performance. A step down high-efficiency switching converter is used first, followed by a second stage of regulation using LDOs to provide switching noise reduction and improved voltage accuracy. The user can also refer to the TI WEBENCH® Power Designer which can be used to select and design the individual power supply elements as needed. The recommended switching regulators for are:

-SP Grade: – TPS50601A-SP = +2.2V for the VDDLA, VDDLB and VDDCCLK10 domains – TPS50601A-SP = +3V for the VDDA18A, VDDA18B, VDDIO, VDDSYS18, VDDR18 and VDDCLK18 domains – TPS50601A-SP = +1V for VDDDIG, VDDEA, VDDEB and VDDT – TPS7H4011-SP = -4.2V for VEEAM18 and VEEBM18 domains
-SEP Grade: – TPS7H4010-SEP = +2.2V for the VDDLA, VDDLB and VDDCCLK10 domains – TPS7H4010-SEP = +3V for the VDDA18A, VDDA18B, VDDIO, VDDSYS18, VDDR18 and VDDCLK18 domains – TPS7H4010-SEP = +1V for VDDDIG, VDDEA, VDDEB and VDDT – TPS7H4010-SEP = -3.3V for VEEAM18 and VEEBM18 domains and recommended LDOs include:
-SP grade – TPS7H1111-SP for +1.8V and +1V – TPS7A4501-SP for -1.8V
-SEP grade – TPS7H1111-SEP for +1.8V and +1V – TPS7H1210-SEP for -1.8V www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 209 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

+7 to 3.6V VDDALDO TPS7H1111-SP SW SUPPLY TPS50601A-SP SW SUPPLY TPS50601A-SP TPS7H4011-SP Inv Buck-boost -4.2V +3.0V FB 10u 0.1u 10u 0.1u 10u 0.1u10u 0.1u +1.0V VDDCSR VDDA18A, +1.8V VDDA18B, +1.8V +1.8V VDDIO, +1.8V VDDCLK18, +1.8V VDDSYS18, +1.8V VDDR18, +1.8V VEExA, -1.8VLDO TPS7A4501-SP 10u 0.1u10u 0.1u VEExB, -1.8VLDO TPS7A4501-SP 10u 0.1u10u 0.1u VDDLLDO TPS7H1111-SP FB FB 10u 0.1u VDDLA, +1.0VFC FC VDDLB, +1.0V +1.0V VDDCLK10, +1.0V 0.1u FC FB FC FC FC FC FC FC FC FC FC NOTES: FB = Ferrite Bead FC = 3-Terminal Feedthru Cap FC LDO TPS7H1111-SP 10u 0.1u0.1u FB +1.0V -1.8V -1.8V SW SUPPLY TPS50601A-SP FB +2.2V NOTE: use separate LDOs if best DAC output isolaon is needed Figure 9-20. Recommended -SP Power Supply Block Diagram DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

+28.7 to 3.6V VDDALDO TPS7H1111-SEP SW SUPPLY TPS7H4010-SEP SW SUPPLY TPS7H4010-SEP TPS7H4010-SEP Inv Buck-boost -3.3V +2.2V FB 10u 0.1u 10u 0.1u 10u 0.1u10u 0.1u +1.0V DVDD, +1.0V (VDDDIG, VDDT, VDDDEA, VDDDEB) VDDCSR VDDA18A, +1.8V VDDA18B, +1.8V +1.8V VDDIO, +1.8V VDDCLK18, +1.8V VDDSYS18, +1.8V VDDR18, +1.8V VEExA, -1.8VLDO TPS7H1210-SEP 10u 0.1u10u 0.1u VEExB, -1.8VLDO TPS7H1210-SEP 10u 0.1u10u 0.1u VDDLLDO TPS7H1111-SEP FB FB 10u 0.1u VDDLA, +1.0VFC FC VDDLB, +1.0V +1.0V VDDCLK10, +1.0V 0.1u FC FB FC FC FC FC FC FC FC FC FC NOTES: FB = Ferrite Bead FC = 3-Terminal Feedthru Cap FC LDO TPS7H1111-SEP 10u 0.1u0.1u FB +1.0V -1.8V -1.8V SW SUPPLY TPS7H4010-SEP FB +3.0V NOTE: use separate LDOs if best DAC output isolaon is needed Figure 9-21. Recommended -SEP Power Supply Block Diagram The VDDA supply is regulated by an LDO, or low-noise drop-out linear regulator, with a +1.8V output and is further broken down into the following subgroup power domains:

VDDA: VDDA18A, VDDA18B
VDDIO
VDDCSR: VDDCLK18, VDDSYS18, VDDR18 Each device supply can be tied to a single LDO but are isolated with a ferrite bead and/or three-terminal capacitor or similar. The VDDL supply is +1V and is further broken down into VDDLA and VDDLB. Each device supply can be tied to a single LDO but are isolated with a ferrite bead and/or three-terminal capacitor or similar. The VDDCLK10 supply is +1V and is the most sensitive for achieving the best phase noise performance. VDDCLK10 should be isolated to a LDO by itself to prevent noise from other 1.0V supplies coupling into the clock path. The DVDD supply is +1V and can be directly connected to a switching power supply. The DVDD encompasses the following device supplies, VDDDIG10, VDDT, VDDEA and VDDEB, which can all be connected together. No further isolation with a ferrite bead and/or three-terminal capacitor or similar is required. The VEEx supply is -1.8V derived from a single LDO and is further broken down into VEEAM18 and VEEBM18, which are isolated with a ferrite bead and/or three-terminal capacitor or similar. It is also highly recommended to follow these important power supply design considerations: 1. Decouple all power supply rails and bus voltages as they come onto the system board. Further place additional decoupling at or near the DAC itself for each power domain. Typically, one decoupling capacitor per power supply pin is suffice unless specified in the data sheet or EVM assembly. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 211 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Remember that approximately 20dB/decade noise suppression is gained for each additional filtering stage. 3. Decouple for both high and low frequencies, which might require multiple capacitor values. 4. Series ferrite beads and feed through capacitors are commonly used at the power plain entry point, and can be used for addition power domain isolation. This should be done for each individual supply voltage on the system board whether it comes from an LDO or a switching regulator. 5. For added capacitance, use tightly stacked power and ground plane pairs (≤4 mil spacing) this adds inherent high-frequency (>500MHz) decoupling to the PCB design. 6. Keep supplies away from sensitive analog circuitry such as the front-end RF stage of the DAC and high- speed clocking and digital circuits if possible. 7. Keep power domains that demand higher currents, near the top of the stack-up or layer that has power plain entry point. This minimizes the overall loop inductance. 8. Any open or voided areas on power plane, fill with ground to provide additional isolation and shielding. 9. Keep a 20 to 25 mil gap between all adjacent power and/or ground plane fills. This helps eliminate all gap coupling between adjacent power domains and/or grounds within the same layer. 10. Some switcher regulator circuitry/components could be located on the opposite side of the PCB for added isolation. 11. Follow the IC manufacture recommendations; if the recommendations are not directly stated in an application note or data sheet, then study the evaluation board. These are great tools from which to learn. Applying the points listed above can help provide a solid power supply design yielding data sheet performance in many applications. Each application has different tolerances for noise on the supply voltage, so understanding these trades is best described in the following two application notes for more details:

Clutter-free power supplies for RF converters in radar applications (Part 1)
Clutter-free power supplies for RF converters in radar applications (Part 2) Also refer to Figure 9-29 through Figure 9-32 to illustrate the one power supply layout and stack-up approach.

9.3.1 Power Up and Down Sequence

At power up, ramp up the power supplies in the following order: 1. Ramp 1.8V supplies, including the bias voltage for DACOUTA+/- and DACOUTB+/- 2. Ramp -1.8V supplies 3. Ramp 1V supplies Use the reverse order for ramp down. 1. Ramp down 1V supplies 2. Ramp down -1.8V supplies 3. Ramp down 1.8V supplies, including the bias voltage for DACOUTA+/- and DACOUTB+/- DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

9.4 Layout

9.4.1 Layout Guidelines and Example

There are many critical signal connections that require specific care and attention during PC board design: 1. DAC analog output signals 2. Sampling clock 3. Serdes (JESD204x) data inputs 4. Power supplies 5. Power and grounding strategy There are many considerations to take note of when developing a high-speed PCB design. Here are a few recommendations and example figures to follow for any high-speed PCB design: 1. Route using loosely coupled 100Ω differential traces when possible on the Serdes inputs. This routing minimizes impact of corners and length-matching serpentines on pair impedance. 2. Provide adequate pair-to-pair spacing to minimize crosstalk, especially with loosely coupled differential traces. Tightly coupled differential traces can be used to reduce self-radiated noise or to improve neighboring trace noise immunity when adequate spacing cannot be provided. 3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces. Any ground plane pour must have sufficient via connections to the main ground plane of the board. Do not use floating or poorly connected ground pours. 4. Use smoothly radiused corners and avoid 45- or 90-degree bends to reduce impedance mismatches on all high-speed inputs/outputs for both analog and digital signal traces. See Figure 9-22 as an example. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 213 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 9-22. Radius Corner and Stitch Vias Next to High_Speed Signal Trace 5. Incorporate any ground plane cutouts necessary at component landing pads, for example – SMA connectors, baluns, and so on, to avoid impedance discontinuities at these locations. Cut-outs below these landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50Ω, single-ended impedance. See Figure 9-23 and Figure 9-24 as an examples. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 9-23. Ground Cut-outs Below Balun and Bias-T Pins www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 215 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 9-24. Ground Cut-out Below SMA Connector Center Pin 6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include cuts in the ground plane or ground plane clearances associated with power and signal vias and through-hole component leads. 7. Provide symmetrically located ground tie stitching vias adjacent to any high-speed signal at an appropriate spacing as determined by the maximum frequency the trace transports (λ/4). See Figure 9-22 as an example. 8. When high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs. Always place two ground vias (“return vias”) close to critical high-speed signal trace via when transitioning between layers to provide a nearby ground return path. See Figure 9-25 and Figure 9-26 as examples. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 9-25. Return Vias for High Speed Clock www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 217 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

Figure 9-26. Return Vias for High Speed Clock Near Clock Generator 9. Pay particular attention to potential coupling between JESD204x data input routing and the analog output routing. Switching noise from the JESD204x inputs can couple into the analog output traces and show up as wideband noise due to the high bandwidth of the DAC. Route the Serdes JESD204x data inputs on a separate layer, if possible, from the DAC output traces to avoid noise coupling, see Figure 9-27 and Figure 9-28 as examples. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

High Speed Data Inputs Lines Isolated by Distance and Ground Fill between Analog Outputs Figure 9-27. Serdes Top Layer Routing with Ground Fill Isolation www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 219 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

High Speed Data Inputs Lines Routed on Bo om Layer and Isolated with Ground Figure 9-28. Serdes Bottom Layer Routing with Ground Isolation 10. A reduction in the clock amplitude can degrade the DAC noise performance, so make sure the clock signal has adequate drive strength, especially for high frequencies. To help avoid this, keep the clock source close to the DAC if using a passive balun to drive or interface with the sampling clock pins of the converter. If trace DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

routes are longer than a few inches, impedance matching at the DACs sampling clock input pins can be necessary. Examples of the power plane design is show in Figure 9-29 through Figure 9-32. Layer3 / PWR1 DAC DVDD = WHITE Other PWR Planes = AUX Supplies Figure 9-29. Power Plane Layout for Layer 3 www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 221 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

DAC VDDLA = RED DAC VDDLB = YELLOW DAC VDDCLK1P0V = GREEN Figure 9-30. Power Plane Layout for Layer 5 DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

DAC VDDA18A = RED DAC VDDA18B = ORANGE DAC VDDB = YELLOW DAC VEExA = GREEN DAC VEExB = BLUE VDDIO = WHITE Figure 9-31. Power Plane Layout for Layer 12 www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 223 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

DAC VDDR = RED DAC VDDSYS18 = GREEN DAC VDDCLK18 = BLUE VDDIO = WHITE Figure 9-32. Power Plane Layout for Layer 14 In addition, TI recommends the following general PCB fabrication considerations for all high-speed PCB designs: 1. Use high quality dielectric materials for any critical signal layers within the PCB stack-up. Typically, the top and bottom layers are the most critical and more board houses can implement a mix of high and standard quality dielectrics, also known as a hybrid stack-up. 2. Use multiple power layers if necessary to provide a robust power delivery system to the converter. 3. Use multiple ground, power, ground layer stacks within the PCB to develop high frequency decoupling within the PCB, the recommendation for these layers is 4 mils or less. 4. Use a solid ground plane, do not split or “slot” the ground plane to create an analog versus digital grounding barrier or divider to avoid harm. DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com

Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

10.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

10.2 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.3 Trademarks

TI E2E™ is a trademark of Texas Instruments. WEBENCH® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners.

10.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.5 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (March 2024) to Revision A (February 2026) Page

Added wideband and highspeed data transmission and RF synthesis for clocking or local oscillator (LO) to

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 225 Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP

www.ti.com 20-Mar-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) DAC39RF10ACL-MLS Active Production FCBGA (ACL) | 256 90 | JEDEC TRAY (5+1) - Call TI Call TI -55 to 125 DAC39RF10 MLS DAC39RF10ACLNSP Active Production FCBGA (ACL) | 256 90 | JEDEC TRAY (5+1) No SNPB Level-3-220C-168 HR -55 to 125 DAC39RF10 NSP DAC39RFS10ACL-MLS Active Production FCBGA (ACL) | 256 90 | JEDEC TRAY (5+1) - Call TI Call TI -55 to 125 DAC39RFS10 MLS DAC39RFS10ACLNSP Active Production FCBGA (ACL) | 256 90 | JEDEC TRAY (5+1) No SNPB Level-3-220C-168 HR -55 to 125 DAC39RFS10 NSP PDAC39RF10ACL Active Preproduction FCBGA (ACL) | 256 90 | JEDEC TRAY (5+1) - Call TI Call TI 25 to 25 PDAC39RFS10ACL Active Preproduction FCBGA (ACL) | 256 90 | JEDEC TRAY (5+1) - Call TI Call TI 25 to 25 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1

www.ti.com 20-Mar-2026 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DAC39RF10-SEP, DAC39RF10-SP, DAC39RFS10-SEP, DAC39RFS10-SP :

Catalog : DAC39RF10 , DAC39RFS10
Space : DAC39RF10-SP , DAC39RFS10-SP NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Mar-2026 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) DAC39RF10ACL-MLS ACL FCBGA 256 90 6 x 15 150 315 135.9 7620 19.5 21 19.2 DAC39RF10ACLNSP ACL FCBGA 256 90 6 x 15 150 315 135.9 7620 19.5 21 19.2 DAC39RFS10ACL-MLS ACL FCBGA 256 90 6 x 15 150 315 135.9 7620 19.5 21 19.2 DAC39RFS10ACLNSP ACL FCBGA 256 90 6 x 15 150 315 135.9 7620 19.5 21 19.2 Pack Materials-Page 1

www.ti.com PACKAGE OUTLINE C 2.78 2.34

0.529 TYP

(0.360 MIN.) TYP

15 TYP

1 TYP

256X 0.7 0.6 PIN 1 ID (OPTIONAL) ( 16.6) B 17.2 16.8 A 17.2 16.8 (1) TYP (1) TYP ( 13.6) ( 11.6) FCBGA - 2.78 mm max heightACL0256A BALL GRID ARRAY 4229409/A 02/2023 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. BALL A1 CORNER SEATING PLANE BALL TYP 0.2 C T R P N M L K J H G F E D C B A 1 2 3

0.25 C A B

0.1 C SYMM SYMM 4 5 6 7 8 9 10 SCALE 0.900

www.ti.com EXAMPLE BOARD LAYOUT 256X ( 0.5) (1) TYP (1) TYP ( 0.5) METAL

0.07 MAX

( 0.5) SOLDER MASK OPENING

0.07 MIN

FCBGA - 2.78 mm max heightACL0256A BALL GRID ARRAY 4229409/A 02/2023 NOTES: (continued) 3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SNOWN SCALE:6X A B C D E F G H J K L M N P 2 3 4 5 6 7 8 9 10 11 12 13 14 R T 15 16 NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS NOT TO SCALE EXPOSED METAL SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 256X 0.5 (1) TYP (1) TYP FCBGA - 2.78 mm max heightACL0256A BALL GRID ARRAY 4229409/A 02/2023 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. SOLDER PASTE EXAMPLE BASED ON 0.15 mm THICK STENCIL SCALE: 6X A B C D E F G H J K L M N P 2 3 4 5 6 7 8 9 10 11 12 13 14 R T 15 16 SYMM SYMM METAL TYP

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated Last updated 10/2025

Product Information

PDAC39RFS10ACL specifications and overview.

Summary

DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface REVISED FEBRUARY 2026

Description

DAC39RFx10-SP DAC39RFx10-SEP 10.4 or 20.8GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204C Interface REVISED FEBRUARY 2026

Source title PDAC39RFS10ACL Datasheet(PDF) - Texas Instruments

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