VL-PS-PDA320240D-02 VARITRONIX | Alldatasheet
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VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 2 OF 16 DOCUMENT REVISION HISTORY DOCUMENT REVISION F R O M T O DATE DESCRIPTION CHANGED BY CHECKED BY A 2005.06.24 First Release. Based on a.) Test Specification: VL-TS-PDA320240D-02 REV . A 2005.06.10 b.) VL-QUA-012B, REV . W, 2004.03.20 According to VL-QUA-012B, LCD size is middle because Unit Per Laminate=6 which is in the range of 2pcs/Laminate to 6pcs /Laminate. ZHANG YAN FANG LIU ZHI QIANG
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 4 OF 16 V ARITRONIX LIMITED Preliminary Specification of LCD Module Type PDA320240D-02 1. General Description z 320 X 240 dots. z FSTN Positive Black & White Transflective LCD Graphic Module. z Viewing Angle: 6 O’clock direction. z Driving scheme: 1/240 Duty, 1/13 bias. z ‘NOV ATEK’ NT7701 (TCP form) 160 Output LCD Segment/Common Drivers or equivalent. z ‘NOV ATEK’ NT7702 (TCP form) 240 Output LCD Segment/Common Drivers or equivalent. z DC/DC Converters. z White LED05 backlight. z FFC connection. 2. Mechanical Specifications The mechanical detail is shown in Fig. 1(a) and summarized in Table 1 below. T a b l e 1 Parameter Specifications Unit Outline dimensions 95.4(W) x 128.88(H) x 7.8 (D) (Include FFC & backlight terminals, exclude TAB) mm Viewing area 79.78(W) x 60.58(H) mm Active area 76.785(W) x 57.585(H) mm Display format 320 (H) dots x 240 (V) dots - Dot size 0.225(W) x 0.225(H) mm Dot spacing 0.015(W) x 0.015(H) mm Dot pitch 0.24(W) x 0.24(H) mm Overall Weight TBD gram
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 5 OF 16 Figure 1(a): Module specification
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 6 OF 16 PDA320240D LCD GRAPHIC DISPLAY
320 X 240 DOTS
'NOVATEK' NT7702 (TCP) LCD SEGMENT DRIVER 'NOVATEK' NT7701 (TCP) 240 160 CL1 M CL2 DB0~DB3 V0,V1,V4 C240 S1 S320 COM1 COM240 SEG1 SEG160 DC/DC Conveters and bias voltage circuit LCD SEGMENT DRIVER 'NOVATEK' NT7701 (TCP) 160 XCK FR LP FR D0~3 D0~3 VDD LP XCK V0,V2,V3 LP VSS FLM EIO2 D-OFF FR 3 3 DISPOFF DISPOFF DISPOFF WHITE LED05 BACKLIGHT A K Figure 1(b): Block Diagram of the module.
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 7 OF 16 3. Absolute Maximum Ratings
3.1 Electrical Maximum Ratings – for IC Only
Parameter Symbol Min. Max. Unit Supply voltage range (Logic) VDD - VSS -0.3 +7.0 V Supply voltage (LCD) V0 -0.3 +30.0 V Input voltage range VIN -0.3 VDD+0.3 V Note: 1.) The module may be destroyed if they are used beyond the absolute maximum ratings. 2.) All voltage values are referenced to VSS= 0V .
3.2 Environmental Conditions
(Topr) Storage Temperature (Tstg) (Note1) Item Min. Max. Min. Max. Remark Ambient Temperature (Except Touch Panel) 0°C +50 °C- 2 0 °C +70 °C Dry Humidity 90% max. RH for Ta ≤ 40 °C No condensation Vibration (IEC 68-2-6) cells must be mounted on a suitable connecto r Frequency: 10 ∼ 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. 3 directions Shock (IEC 68-2-27) Half-sine pulse shape Pulse duration: 11 ms Peak acceleration: 981 m/s2 = 100 g Number of shocks: 3 shocks in 3 mutually perpendicular axes. 3 directions Note 1: Product cannot sustain in extreme storage conditions for a long time.
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 8 OF 16 4. Electrical Specifications
4.1 Interface signals
Table 4: Pin description (LCD Driver) Pin No. Symbol Description 1 FLM Input/output for chip select or data of the shift register.
2 M AC signal input for LCD driving waveform
-The input signal is level-shifted from logic voltage level to the LCD driver voltage level, and it controls the LCD driver circuit -Normally, inputs a frame inversion signal. The LCD driver output pin’s output voltage level can be set using the shift register output signal and the FR signal. 3 CL1 Latch pulse input/shift clock input for the shift register. 4 CL2 Display data shift clock input for segment mode.
5 D-OFF
Control input for deselect output level.
6 DB0
7 DB1
8 DB2
9 DB3
Input pin for display data. 10 VDD Power supply for logic.
11 VSS Ground (0V)
12 VEE * Positive power supply for LCD driving voltage. *
13 VSS Ground (0V)
14 NC No connection
15 A Anode of backlight
16 K Cathode of backlight.
17 TP_R RIGHT Input Position
18 TP_D BOTTOM Input Position
19 TP_L LEFT Input Position
20 TP_U TOP Input Position
- This pin should be NC (No Connection) when Built-in DC/DC converter is used
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 9 OF 16
4.2 Typical Electrical Characteristics
At Ta = 25 °C, VDD = 3.0V±5%, VSS = 0V . Ta=25°C Table 5 Parameter Symbol Conditions Min. Typ. Max. Unit Supply voltage (Logic) VDD-VSS 2.85 3.0 3.15 V Supply voltage (LCD) (Build-in) VLCD VDD=3.0V , Ta=25°C, Note 1 16.3 16.5 16.7 V VIH “High” level, Note 2
0.8 VDD - - V Input signal voltage
VIL “Low” level, Note 2 - - 0.2 VDD V Character mode, VDD = 3.0V . Ta=25°C, Note (1) - 20 30 mA Supply Current (Logic & LCD) IDD Checker board mode, VDD = 3.0V . Ta=25°C, Note (1) - 30 45 mA Supply voltage of White LED05 backlight VLED 3.0 3.2 3.4 V Luminance (on the backlight surface) Forward current =20mA Number of LED chips=1x4=4 70 100 - cd/m Note 1: There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. Note 2: Apply to pins DB0~DB3 (or D0~D3), FLM (or EIO2), CL1 (or LP), CL2 (or XCK), DISPOFF M (or FR), and D-OFF (or DISPOFF
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 10 OF 16
4.3 Timing Specifications
Refer to Fig. 2, Segment mode characteristics (NT7701) At Ta = 0 °C to +50 °C, VDD = 3.0V±5%, VSS = 0V . T a b l e 6
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 11 OF 16 Figure 2: Timing waveform of the segment mode (NT7701) DB0~3
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 12 OF 16 Refer to Fig. 3, Common mode characteristics (NT7702). At Ta = 0 °C to +50 °C, VDD = 3.0V±5%, VSS = 0V . T a b l e 7
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 13 OF 16 Figure 3: Timing waveform of the common mode (NT7702)
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 14 OF 16
4.4 Precaution when Connecting and Disconnecting the Power
Be careful when connecting or disconnecting the power. This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occur, if a voltage is supplied to th e LCD driver power supply while the logic system power supply is floating. The details are as follows: z When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. z We recommend that you connect a serial resistor (50-100 Ω) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade. In addition, when connecting the logic power supply, the logic condi tion of this LSI inside is insecure. Therefore connect the LCD driver powe r supply after resetting the logic condition of this LSI inside on /DOFF function. After that , the /DOFF cancel the function after the LCD driver power supply has become stable. Furthe rmore, when disconnecting the power, set the LCD driver output pins to level VSS on the / DOFF function. After that , disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown. Figure 4: Power sequence
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 15 OF 16 5. Remark
VL-PS-PDA320240D-02 REV . A (PDA320240D-02) JUN/2005 PAGE 16 OF 16 6. LCD Cosmetic Conditions a.) Reference document follow VL-QUA-012B. b.) LCD size of the product is middle. “Varitronix Limited reserves the right to change this specification.” FAX:(852) 2343-9555. URL:http://www.varitronix.com - END -