PD85004 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical data
  • 1.1 Maximum ratings
  • 1.2 Thermal data
  • 2 Electrical characteristics
  • 2.1 Static
  • 2.2 Dynamic
  • 2.3 ESD protection characteristics
  • 2.4 Moisture sensitivity level
  • 3 Impedances
  • 4 DC curves
  • 5 RF curves
  • 6 Schematic and BOM
  • 7 Demonstration board photo
  • 8 Package mechanical data
  • 8.1 Thermal pad and via design
  • 8.2 Soldering profile
  • 9 Revision history

Features

■ Excellent thermal stability ■ Common source configuration ■ Broadband performances POUT = 4 W with 17 dB gain @ 870 MHz ■ Plastic package ■ ESD protection ■ Supplied in tape and reel ■ In compliance with the 2002/95/EC european directive

Description

The PD85004 is a common source N-channel, enhancement-mode lateral field-effect RF power transistor. It is designed for high gain, broad band commercial and industrial applications. It operates at 13.6 V in common source mode at frequencies of up to 1 GHz. PD85004’s superior gain and efficiency makes it an ideal solution for mobile radio. Figure 1. Pin connection Table 1. Device summary

1 Electrical data

1.1 Maximum ratings

1.2 Thermal data

Table 2. Absolute maximum ratings (TCASE = 25 °C) Table 3. Thermal data

2 Electrical characteristics

2.1 Static

2.2 Dynamic

2.3 ESD protection characteristics

2.4 Moisture sensitivity level

Table 4. Static Table 5. Dynamic Table 6. ESD protection characteristics Table 7. Moisture sensitivity level

3 Impedances

Figure 2. Impedances Table 8. Broadband impedances

4 DC curves

Figure 3. DC output characteristics Figure 4. ID vs V GS Figure 5. Capacitances vs drain

5 RF curves

Figure 6. Output power and drain efficiency

13.6 V / 50 mA / Pin = 19 dBm

Figure 7. Gain vs frequency

13.6 V / 50 mA

Figure 8. Input return loss vs frequency Figure 9. Gain vs output power Figure 10. Drain current vs output power Figure 11. Output power vs input power

860 MHz 900 MHz 960 MHz

Figure 12. Harmonics vs frequency

6 Schematic and BOM

Figure 13. Schematic

Table 9. Components part list

7 Demonstration board photo

Figure 14. Demonstration board photo

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

Figure 15. Package dimensions Table 10. SOT-89 mechanical data

8.1 Thermal pad and via design

electrical requirements of the device. Figure 16. Pad layout details

8.2 Soldering profile

where a Pb-free solder is used. Figure 17. Recommended solder profile leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 18. Recommended solder profile for leaded devices

Figure 19. Reel information

9 Revision history

Table 11. Document revision history 05-Dec-2007 1 Initial release.