PD84002 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Datasheet sections

  • 1 Electrical data
  • 1.1 Maximum ratings
  • 1.2 Thermal data
  • 2 Electrical characteristics
  • 2.1 Static
  • 2.2 Dynamic
  • 2.3 ESD protection characteristics
  • 2.4 Moisture sensitivity level
  • 3 Impedances
  • 4 DC curves
  • 5 RF curves
  • 6 Schematic and BOM
  • 7 Photo
  • 8 Package mechanical data
  • 8.1 Thermal Pad and Via design
  • 8.2 Soldering profile
  • 9 Revision history

1 Electrical data

1.1 Maximum ratings

1.2 Thermal data

Table 1. Absolute maximum ratings (TCASE = 25°C) Table 2. Thermal data

2 Electrical characteristics

2.1 Static

2.2 Dynamic

2.3 ESD protection characteristics

2.4 Moisture sensitivity level

Table 3. Static Table 4. Dynamic Table 5. ESD protection characteristics Table 6. Moisture sensitivity level

3 Impedances

Figure 3. Impedances Table 7. Impedances

4 DC curves

Figure 4. DC output characteristics Figure 5. ID vs V GS Figure 6. Capacitances vs drain

5 RF curves

Figure 7. Output power and efficiency vs Figure 8. Gain vs frequency 7.2 V - 100 mA Figure 9. Input return loss vs frequency

7.2 V / 100 mA

Figure 10. Harmonics vs frequency Figure 11. Output power and efficiency vs

9 V / 100 mA / Pin = 22 dBm

6 Schematic and BOM

Figure 12. Schematic Table 8. Components part list

7 Photo

Figure 13. Photo Table 8. Components part list (continued)

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

Figure 14. Package dimensions Table 9. SOT-89 mechanical data

8.1 Thermal pad and via design

electrical requirements of the device. Figure 15. Pad layout details

8.2 Soldering profile

where a Pb-free solder is used. Figure 16. Recommended solder profile leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 17. Recommended solder profile for leaded devices

Figure 18. Reel information

9 Revision history

Table 10. Document revision history 05-Dec-2007 1 Initial release.