PD84001 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 18

Technical content

Datasheet sections

  • 1 Electrical data
  • 1.1 Maximum ratings
  • 1.2 Thermal data
  • 2 Electrical characteristics
  • 2.1 Static
  • 2.2 Dynamic
  • 2.3 ESD protection characteristics
  • 2.4 Moisture sensitivity level
  • 3 Impedance
  • 4 Typical performance
  • 5 Test circuit
  • 6 Package mechanical data
  • 6.1 Thermal pad and via design
  • 6.2 Soldering profile
  • 7 Revision history

Features

■ Excellent thermal stability ■ Common source configuration ■ Broadband performances POUT = 1 W with 15 dB gain @ 870 MHz ■ Plastic package ■ ESD protection ■ Supplied in tape and reel ■ In compliance with the 2002/95/EC european directive

Description

The PD84001 is a common source N-channel, enhancement-mode lateral field-effect RF power transistor. It is designed for high gain, broad band commercial and industrial applications. It operates at 7 V in common source mode at frequencies of up to 1 GHz. PD84001’s superior gain and efficiency makes it an ideal solution for portable radio and UHF RFID reader. Figure 1. Pin connection Table 1. Device summary

1 Electrical data

1.1 Maximum ratings

1.2 Thermal data

Table 2. Absolute maximum ratings (TCASE = +25 °C) Table 3. Thermal data

2 Electrical characteristics

2.1 Static

2.2 Dynamic

2.3 ESD protection characteristics

2.4 Moisture sensitivity level

Table 4. Static (TCASE = +25 oC) Table 5. Dynamic Table 6. ESD protection characteristics Table 7. Moisture sensitivity level

3 Impedance

Figure 2. Current conventions Table 8. Impedance data

4 Typical performance

Figure 3. V GS vs ID Figure 4. DC output characteristics

Figure 8. Gain vs output power and Figure 9. Output power vs input power and Figure 10. Efficiency vs output power and Figure 11. Gain and efficiency vs frequency

840 MHz 870 MHz 900 MHz

Figure 16. Gain and efficiency vs pin

5 Test circuit

Figure 17. Test circuit schematic / 840-900 MHz

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

Figure 18. Package dimensions Table 9. SOT-89 mechanical data

6.1 Thermal pad and via design

electrical requirements of the device. Figure 19. Pad layout details

6.2 Soldering profile

where a Pb-free solder is used. Figure 20. Recommended solder profile leaded solder, or for devices with leaded terminal plating used with a leaded solder. Figure 21. Recommended solder profile for leaded devices

Figure 22. Reel information

7 Revision history

Table 10. Document revision history