PD78F0833Y

PD78F0833Y_15 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 3.1 Port Pins
• 3.2 Non-Port Pins
• 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
• 7.1 Selection of Communication Mode
• 7.2 Flash Memory Programming Functions
• 7.3 Flashpro II and Flashpro III Connection
• 7.4 Flash Memory Programming by Self Write

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© 2001

DESCRIPTION

The µPD78F0833Y is a product of the µPD780833Y Subseries in the 78K/0 Series, and equivalent to the µPD780833Y with a flash memory in place of internal ROM. This device can be programmed (write, delete, rewrite) without being removed from the board. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µPD780833Y Subseries User's Manual: U13892E 78K/0 Series User’s Manual Instructions: U12326E

FEATURES

• Pin-compatible with mask ROM versions (except V PP pin)
• Flash memory: 60 KB (self-programming supported)
• Internal high-speed RAM: 1,024 bytes
• Internal expansion RAM: 2,048 bytes
• Supply voltage: V DD = 4.5 to 5.5 V Remark For the differences between the flash memory version and the mask ROM version, refer to 4 DIFFERENCES BETWEEN µPD78F0833Y AND MASK ROM VERSION.

APPLICATIONS

Car audios, etc.

ORDERING INFORMATION

µPD78F0833YGC-8BT 80-pin plastic QFP (14 × 14) 8-BIT SINGLE-CHIP MICROCONTROLLERS Document No. U15013EJ2V0DS00 (2nd edition) Date Published January 2001 N CP(K) Printed in Japan MOS INTEGRATED CIRCUIT µPD78F0833Y The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

µPD78F0833Y Data Sheet U15013EJ2V0DS2 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. 64-pin 64-pin 64-pin 64-pin 42/44-pin 64-pin 80-pin 100-pin 80-pin 64-pin 80-pin 80-pin PD78058F 80-pin 80-pin 80-pin 100-pin 100-pin 100-pin 100-pin PD780058 PD78078 PD78070A PD78075B 80-pin 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 100-pin 80-pin 120-pin 120-pin 120-pin µµ µ µ µ PD780058Yµ µ PD78058FYµ µ PD78054Yµ µ PD780078Yµ PD780034AYµ µ PD780024AYµ µ PD78018FYµ µ PD78054µ PD780065µ µ PD780078µ µ PD780034Aµ PD780024Aµ PD78014Hµ µ PD78018Fµ PD78083µ PD780988µ PD780208µ µ PD780232µ PD78044Hµ µ PD78044Fµ PD780338µ µ PD780328µ µ PD780318µ PD780308µ PD780308Yµ PD78064Bµ PD78064µ µ µ µ PD780948µ PD78098Bµ PD78064Yµ PD780701Yµ µ PD780958µ PD780852µ PD780824µ PD780833Yµ PD78078Yµ µ PD78070AYµ µ PD780018AYµ µ Products in mass production Products under development Y subseries products are compatible with I2C bus. Control Inverter control VFD drive LCD drive Bus interface supported Meter control PD78078 with reduced EMI noise PD78054 with timer added and enhanced external interface ROMless version of PD78078 For automobile meter drive. On-chip DCAN controller PD78078Y with enhanced serial I/O and limited functions PD78054 with enhanced serial I/O PD78054 with reduced EMI noise PD78018F with UART and D/A added, and enhanced I/O PD780024A with expanded RAM PD780034A with timer added and enhanced serial I/O PD780024A with enhanced A/D PD78018F with enhanced serial I/O PD78018F with reduced EMI noise Basic subseries for control On-chip UART and capable of low voltage operation (1.8 V) On-chip inverter controller and UART. Reduced EMI noise. PD78044F with enhanced I/O and VFD C/D. Display output total: 53 For panel control. On-chip VFD C/D. Display output total: 53 PD78044F with N-ch open drain I/O added. Display output total: 34 Basic subseries for driving VFD. Display output total: 3478K/0 Series PD780308 with enhanced display function and timer. Segment signal output: 40 pins max. PD780308 with enhanced display function and timer. Segment signal output: 32 pins max. PD780308 with enhanced display function and timer. Segment signal output: 24 pins max. PD78064 with enhanced SIO and expanded ROM, RAM PD78064 with reduced EMI noise Basic subseries for driving LCD. On-chip UART. On-chip DCAN controller PD78054 with IEBusTM controller added. Reduced EMI noise. On-chip DCAN/IEBus controller On-chip J1850 (CLASS2) controller For industrial meter control On-chip controller/driver for automobile meter drive Remark VFD (Vacuum Fluorescent Display) is referred to as FIP TM (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same.

µPD78F0833Y Data Sheet U15013EJ2V0DS 3 The major functional differences among the subseries are listed below. Function ROM Timer 8-bit 10-bit 8-bit Serial Interface I/O External Subseries Name Capacity 8-bit 16-bit Watch WDT A/D A/D D/A Expansion Control µPD78078Y 48 K to 60 K 4 ch 1 ch 1 ch 1 ch 8 ch – 2 ch 3 ch (UART: 1 ch, 88 1.8 V Yes µPD78070AY – I2C: 1 ch) 61 2.7 V µPD780018AY 48 K to 60 K – 3 ch (I 2C: 1 ch) 88 µPD780058Y 24 K to 60 K 2 ch 2 ch 3 ch (time-division 68 1.8 V UART: 1ch, I 2C: 1 ch) µPD78058FY 48 K to 60 K 3 ch (UART: 1 ch, 69 2.7 V µPD78054Y 16 K to 60 K I2C: 1 ch) 2.0 V µPD780078Y 48 K to 60 K 2 ch – 8 ch – 4 ch (UART: 2 ch, 52 1.8 V I2C: 1 ch) µPD780034AY 8 K to 32 K 1 ch 3 ch (UART: 1 ch, 51 µPD780024AY 8 ch – I2C: 1 ch) µPD78018FY 8 K to 60 K 2 ch (I 2C: 1 ch) 53 LCD µPD780308Y 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch – – 3 ch (time-division 57 2.0 V – drive UART: 1 ch, I 2C: 1 ch) µPD78064Y 16 K to 32 K 2 ch (UART: 1 ch, I2C: 1 ch) Bus µPD780701Y 60 K 3 ch 2 ch 1 ch 1 ch 16 ch – – 4 ch (UART: 1 ch, 67 3.5 V – interface µPD780833Y I2C: 1 ch) 65 4.5 V supported VDD MIN. Value

µPD78F0833Y Data Sheet U15013EJ2V0DS4 FUNCTION OVERVIEW Item µPD78F0833Y Internal memory Flash memory 60 KB High-speed RAM 1,024 bytes Expansion RAM 2,048 bytes Memory space 64 KB General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time On-chip minimum instruction execution time variable function Instruction set • 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, and Boolean operation)
• BCD adjust, etc. I/O ports Total: 65
• CMOS input: 54
• TTL input/CMOS output: 8
• N-ch open-drain I/O: 3 A/D converter • 8-bit resolution × 8 channels × 2 Serial interface • 3-wire serial I/O mode: 2 channels
• UART mode: 1 channel
• I2C bus mode: 1 channel Timer • 16-bit timer/event counter: 2 channels
• 8-bit timer/event counter: 3 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel Timer outputs 5 (8-bit PWM output: 3) 4.19 MHz (@ 4.19 MHz operation with system clock) Bus controller J1850 (CLASS2) bus interface Vectored interrupts Maskable Internal: 19 External: 9 Non-maskable Internal: 1 Software 1 Power supply voltage V DD = 4.5 to 5.5 V Operating ambient temperature T A = –40 to +85 °C Package 80-pin plastic QFP (14 × 14)

µPD78F0833Y Data Sheet U15013EJ2V0DS6 1. PIN CONFIGURATION (TOP VIEW)

• 80-pin plastic QFP (14 × 14) µPD78F0833YGC-8BT Cautions 1. Connect the V PP pin directly to V SS0 or VSS1 in normal operation mode. 2. Connect the AV DD0 pin to V DD0. 3. Connect the AV SS0 and AV SS1 pins to V SS0. P70/PCL P71/SDA0 P72/SCL0 P73/TO01 P74/TI001 P75/TI011 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 AV REF1 P80/ANI01 P81/ANI11 P82/ANI21 P83/ANI31 P84/ANI41 P85/ANI51 P86/ANI61 P87/ANI71 AV SS1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVSS0 P97/ANI70 P96/ANI60 P95/ANI50 P94/ANI40 P93/ANI30 P92/ANI20 P91/ANI10 P90/ANI00 AV REF0 AVDD0 VDD1 VSS1 V PP RESET C2TX C2RX P67 P66 P65 P64 P27/TI51/TO51 P26/ASCK0/TI52/TO52 P25/TxD0 P24/RxD0 P23/TI50/TO50 P07/INTP7 P06/INTP6 P05/INTP5 P04/INTP4 P22/SCK31 P21/SO31 P20/SI31 P57 P56 P55 P54 P53 P40 P41 P42 P43 P44 P45 P46 P47 P30/SI30 P31/SO30 P32/SCK30 V DD0 VSS0 P33 P34/TO00 P35/TI000 PTI010 P50 P51 P52

µPD78F0833Y Data Sheet U15013EJ2V0DS 7 PIN IDENTIFICATION ANI00 to ANI70, ANI01 to ANI71: Analog input ASCK0: Asynchronous serial clock AVDD0: Analog power supply AVREF0, AVREF1: Analog reference voltage AVSS0, AVSS1: Analog ground C2RX: CLASS2 receive data C2TX: CLASS2 transmit data INTP0 to INTP7: External interrupt input P00 to P07: Port 0 P20 to P27: Port 2 P30 to P36: Port 3 P40 to P47: Port 4 P50 to P57: Port 5 P64 to P67: Port 6 P70 to P75: Port 7 P80 to P87: Port 8 P90 to P97: Port 9 PCL: Programmable clock RxD0: Receive data RESET: Reset SCK30, SCK31: Serial clock SCL0: Serial clock SDA0: Serial data SI30, SI31: Serial input SO30, SO31: Serial output TI000, TI010, TI001, TI011, TI50, TI51, TI52: Timer input TO00, TO01, TO50, TO51, TO52: Timer output TxD0: Transmit data V DD0, VDD1: Power supply VPP: Programming power supply VSS0, VSS1: Ground X1, X2: Crystal

µPD78F0833Y Data Sheet U15013EJ2V0DS8 2. BLOCK DIAGRAM 16-bit timer/ event counter 00 16-bit timer/ event counter 01 Serial interface 30 Serial interface 31 Watchdog timer Watch timer UART0 I2C bus J1850 bus I/F (CLASS2) Interrupt control Clock output control A/D converter 00 A/D converter 01 TO00/P34 TI000/P35 TI010/P36 TO01/P73 TI001/P74 TI011/P75 8-bit timer/ event counter 50 8-bit timer/ event counter 51 TI50/TO50/P23 TI51/TO51/P27 8-bit timer/ event counter 52TI52/TO52/P26 SI30/P30 SO30/P31 SCK30/P32 SI31/P20 SO31/P21 SCK31/P22 RxD0/P24 TxD0/P25 ASCK0/P26 AVDD0 AVSS0 AVREF0 SDA0/P71 SCL0/P72 ANI00/P90 to ANI70/P97 AVSS1 AVREF1 C2RX PCL/P70 C2TX ANI01/P80 to ANI71/P87 INTP0/P00 to INTP7/P07 78K/0 CPU core Flash memory Internal expansion RAM 2,048 bytes Internal high-speed RAM 1,024 bytes VDD0 VDD1 VSS0 VSS1 VPP Port 0 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 P00 to P07 P20 to P27 P30 to P36 P40 to P47 P50 to P57 P64 to P67 P70 to P75 P80 to P87 P90 to P97 System control RESET

µPD78F0833Y Data Sheet U15013EJ2V0DS 9 3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin Name I/O Function After Reset Alternate Function P00 to P07 I/O Input INTP0 to INTP7 P20 I/O Input SI31 P21 SO31 P22 SCK31 P23 TI50/TO50 P24 RxD0 P25 TxD0 P26 ASCK0/TI52/TO52 P27 TI51/TO51 P30 I/O Input SI30 P31 SO30 P32 SCK30 P33 — P34 TO00 P35 TI000 P36 TI010 P40 to P47 I/O Port 4 Input — 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Interrupt request flag (KRIF) is set to 1 by falling edge detection. P50 to P57 I/O Port 5 Input — 8-bit I/O port TTL level input/CMOS output Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. P64 to P67 I/O Input — Port 0 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Port 2 8-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. Port 3 7-bit I/O port Input/output can be specified in 1- bit units. An on-chip pull-up resistor can be specified by software. An on-chip pull-up resistor can be specified by software. Port 6 4-bit I/O port Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by software. N-ch open-drain I/O port LEDs can be driven directly.

µPD78F0833Y Data Sheet U15013EJ2V0DS10

3.1 Port Pins (2/2)

Pin Name I/O Function After Reset Alternate Function P70 I/O Input PCL P71 SDA0 P72 SCL0 P73 TO01 P74 TI001 P75 TI011 P80 to P87 I/O Input ANI01 to ANI71 P90 to P97 I/O Input ANI00 to ANI70

3.2 Non-Port Pins (1/2)

Pin Name I/O Function After Reset Alternate Function INTP0 to Input External interrupt request input for which valid edge can be Input P00 to P07 INTP7 specified (rising edge, falling edge, both rising and falling edges) SI30 Input Serial interface SIO30 serial data input Input P30 SI31 Serial interface SIO31 serial data input P20 SO30 Output Serial interface SIO30 serial data output Input P31 SO31 Serial interface SIO31 serial data output P21 SDA0 I/O Serial interface IIC0 serial data input/output Input P71 SCK30 I/O Serial interface SIO30 serial clock input/output Input P32 SCK31 Serial interface SIO31 serial clock input/output P22 SCL0 Serial interface IIC0 serial clock input/output P72 RxD0 Input Asynchronous serial interface serial data input Input P24 TxD0 Output Asynchronous serial interface serial data output Input P25 ASCK0 Input Asynchronous serial interface serial clock input Input P26/TI52/TO52 TI000 Input External count clock input to 16-bit timer/event counter 00 Input P35 Capture trigger input to capture register (CR000 and CR010) of 16-bit timer/event counter 00 TI010 Capture trigger input to capture register (CR000) of 16-bit P36 timer/event counter 00 TI001 External count clock input to 16-bit timer/event counter 01 P74 Capture trigger input to capture register (CR001 and CR011) of 16-bit timer/event counter 01 TI011 Capture trigger input to capture register (CR001) of 16-bit P75 timer/event counter 01 Port 8 1-bit I/O port Input/output can be specified in 1-bit units. Port 9 1-bit I/O port Input/output can be specified in 1-bit units. Port 7 6-bit I/O port Input/output can be specified in 1- bit units. An on-chip pull-up resistor can be specified by software. N-ch open-drain I/O port An on-chip pull-up resistor can be specified by software.

µPD78F0833Y Data Sheet U15013EJ2V0DS 11

3.2 Non-Port Pins (2/2)

Pin Name I/O Function After Reset Alternate Function TI50 Input External count clock input to 8-bit timer/event counter 50 Input P23/TO50 TI51 External count clock input to 8-bit timer/event counter 51 P27/TO51 TI52 External count clock input to 8-bit timer/event counter 52 P26/ASCK0/TO52 TO00 Output 16-bit timer/event counter 00 output Input P34 TO01 16-bit timer/event counter 01 output P73 TO50 8-bit timer/event counter 50 output P23/TI50 TO51 8-bit timer/event counter 51 output P27/TI51 TO52 8-bit timer/event counter 52 output P26/ASCK0/TI52 PCL Output Clock output Input P70 ANI00 to Input A/D converter (AD00) analog input Input P90 to P97 ANI70 ANI01 to A/D converter (AD01) analog input P80 to P87 ANI71 AVREF0 — A/D converter (AD00) reference voltage input —— AVREF1 A/D converter (AD01) analog power supply and reference — voltage input AVDD0 A/D converter (AD00) analog power supply — AVSS0 A/D converter (AD00) ground potential. Make the same — potential as V SS0 or VSS1. AVSS1 A/D converter (AD01) ground potential. Make the same — potential as V SS0 or VSS1. C2RX Input CLASS 2 data input — C2TX Output CLASS 2 data output — RESET Input System reset input — X1 Input Connecting crystal resonator for oscillation — X2 — — VDD0 Positive power supply for ports — VDD1 Positive power supply (other than for ports) — VSS0 Ground potential for ports — VSS1 Ground potential (other than for ports) — VPP Applying high voltage for program write/verify — Connect directly to V SS0 or V SS1 in normal operation mode.

µPD78F0833Y Data Sheet U15013EJ2V0DS12

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, see Figure 3-1. Table 3-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (1/2) Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins P00/INTP0 to P07/INTP7 8-C I/O Input: Independently connect to V SS0 via a resistor. Output: Leave open. P20/SI31 Input: Independently connect to V DD0 or V SS0 via a P21/SO31 5-H resistor. P22/SCK31 8-C Output: Leave open. P23/TI50/TO50 P24/RxD0 P25/TxD0 5-H P26/ASCK0/TI52/TO52 8-C P27/TI51/TO51 P30/SI30 P31/SO30 5-H P32/SCK30 8-C P33 13-P Input: Independently connect to V DD0 via a resistor. Output: Leave open. P34/TO00 5-H Input: Independently connect to V DD0 or V SS0 via a P35/TI000 8-C resistor. P36/TI010 Output: Leave open. P40 to P47 5-H Input: Independently connect to V DD0 via a resistor. Output: Leave open. P50 to P57 5-T Input: Independently connect to V DD0 or V SS0 via a P64 to P67 5-H resistor. P70/PCL Output: Leave open. P71/SDA0 13-R Input: Independently connect to V DD0 via a P72/SCL0 resistor. Output: Leave open. P73/TO01 5-H Input: Independently connect to V DD0 or V SS0 via a P74/TI001 8-C resistor. P75/TI011 Output: Leave open. P80/ANI01 to P87/ANI71 11-E P90/ANI00 to P97/ANI70 C2RX 2 Input Connect to V SS0 via a resistor. C2TX 3-B Output Leave open. RESET 2 Input —

µPD78F0833Y Data Sheet U15013EJ2V0DS 13 Table 3-1. Pin I/O Circuit Types and Recommended Connection of Unused Pins (2/2) Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins AVDD0 —— Connect to V DD0. AVREF0 AVREF1 AVSS0 Connect to V SS0. AVSS1 VPP Connect directly to V SS0 or VSS1.

µPD78F0833Y Data Sheet U15013EJ2V0DS14 Figure 3-1. Pin I/O Circuit List (1/2) TYPE 2 Schmitt-triggered input with hysteresis characteristics IN TYPE 5-H TYPE 3-B TYPE 8-C TYPE 5-T TYPE 11-E Data Output disable P-ch IN/OUT VDD0 N-ch P-ch VDD0 Pull-up enable VSS0 Data Output disable P-ch IN/OUT VDD0 N-ch Input enable P-ch VDD0 Pull-up enable VSS0 IN/OUT Output disable Data VDD0 P-ch N-ch P-ch Comparator AVSS Input enable VREF (threshold voltage) – N-ch VSS0 OUTData VDD0 P-ch N-ch VSS0 Pull-up enable VDD0 P-ch IN/OUT Input enable Output disable Data VDD0 P-ch N-ch VSS0 TTL input

µPD78F0833Y Data Sheet U15013EJ2V0DS 15 Figure 3-1. Pin I/O Circuit List (2/2) TYPE 13-R TYPE 13-P Data Output disable IN/OUT N-ch VSS0 Data Output disable IN/OUT N-ch Input enable VSS0

µPD78F0833Y Data Sheet U15013EJ2V0DS16 4. DIFFERENCES BETWEEN µPD78F0833Y AND MASK ROM VERSION The µPD78F0833Y incorporates flash memory in which a program can be written, deleted, and overwritten while mounted on the board. Table 4-1 lists the differences between the µPD78F0833Y and the mask ROM versions. Table 4-1. Difference Between µPD78F0833Y and Mask ROM Version Item µPD78F0833Y µPD780833Y Internal ROM capacity 60 KB Internal ROM structure Flash memory Mask ROM IC pin Not provided Provided VPP pin Provided Not provided Electrical specifications, recommended Refer to the data sheet of individual products. soldering conditions Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering sample, ES) of the mask ROM version.

µPD78F0833Y Data Sheet U15013EJ2V0DS 17 5. MEMORY SIZE SWITCHING REGISTER (IMS) This register sets the internal memory capacity by software. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to CFH. Figure 5-1. Format of Memory Size Switching Register (IMS) 76543210 RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 Address FFF0H Symbol IMS After reset CFH R/W R/W RAM2 RAM1 RAM0 Selection of internal high-speed RAM capacity 1 1 0 1,024 bytes Setting prohibitedOther than above ROM3 ROM2 ROM1 Selection of internal ROM capacity 1 1 0 48 KB 60 KB Other than above 111 Setting prohibited ROM0

µPD78F0833Y Data Sheet U15013EJ2V0DS18 6. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) This register sets the internal expansion RAM capacity by software. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0CH. Caution The default value of IXS is 0CH (setting prohibited). Be sure to set 08H as the initial setting. Figure 6-1. Format of Internal Expansion RAM Size Switching Register (IXS) 76543210 0 0 0 IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Address FFF4H Symbol IXS After reset 0CH R/W R/W IXRAM4 IXRAM3 IXRAM2 Selection of internal high-speed RAM capacity 0 1 0 2,048 bytes Setting prohibitedOther than above IXRAM0 IXRAM1

µPD78F0833Y Data Sheet U15013EJ2V0DS 19 7. FLASH MEMORY PROGRAMMING Writing to flash memory can be performed without removing the memory from the target system. Writing is performed with the dedicated flash programmer Flashpro II (part number: FL-PR2) and Flashpro III (part number: FL- PR3 and PG-FP3) connected to the host machine and the target system. Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro II or Flashpro III. Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd.

7.1 Selection of Communication Mode

Writing to flash memory is performed using Flashpro II or Flashpro III via a serial communication mode. The communication mode is selected from those in Table 7-1. The selection of the communication mode is made by using the format shown in Figure 7-1. Each communication mode is selected by the number of V PP pulses shown in Table 7-1. Table 7-1. List of Communication Modes Communication Mode Channels Pin Used Note VPP Pulses 3-wire serial I/O (SIO3) 2 SI30/P30 2 SO30/P31 SCK30/P32 SI31/P20 1 SO31/P21 SCK31/P22 Note Shifting to the flash memory programming mode sets all pins not used for flash memory programming to the same state as immediately after reset. Therefore, all ports enter an output high-impedance state. If the external devices do not acknowledge an output high-impedance state, handling such as connecting to VDD via a resistor or connecting to V SS via a resistor is required. Cautions 1. Be sure to select the number of V PP pulses shown in Table 7-1 for the communication mode. 2. If performing write operations to flash memory via the UART communication mode, set the system clock oscillation frequency to 3 MHz or higher. Figure 7-1. Format of Communication Mode Selection VDD VPP RESET VSS VDD VSS 10 V VPP pulses 21n Flash memory write mode

µPD78F0833Y Data Sheet U15013EJ2V0DS20

7.2 Flash Memory Programming Functions

Operations such as writing to flash memory are performed by various command/data transmission and reception operations according to the selected communication mode. Table 7-2 shows major functions of flash memory programming. Table 7-2. Major Functions of Flash Memory Programming Function Description Reset Used to detect write stop and communication synchronization. Batch verify Compares entire memory contents and input data. Batch contents verify Compares entire memory contents in the different modes. Batch delete Deletes the entire memory contents. Batch blank check Checks the deletion status of the entire memory. High-speed write Writes to flash memory according to write start address and number of write data (bytes). Continuous write Successively writes using the data input in a high-speed write operation. Batch prewrite Writes 00H to entire memory. Status Checks the current operation mode and whether operation has ended. Oscillation frequency setting Inputs the resonator oscillation frequency information. Delete time setting Inputs the memory delete time. Silicon signature read Outputs the device name, memory capacity, and device block information.

7.3 Flashpro II and Flashpro III Connection

The connection of the Flashpro II and Flashpro III and the µPD78F0833Y is shown in Figure 7-2. Figure 7-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O (SIO3) Mode VPP VDD RESET SCK SO SI GND VPP VDD0 RESET SCK3n SI3n SO3n VSS0 Flashpro II or Flashpro III PD78F0833Y µ n = 0, 1

µPD78F0833Y Data Sheet U15013EJ2V0DS 21

7.4 Flash Memory Programming by Self Write

With the µPD78F0833Y, it is possible to rewrite the flash memory using a program. (1) Flash memory configuration The configuration of the flash memory is shown in Figure 7-3. Figure 7-3. Flash Memory Configuration Flash memory area (60 KB) Normal operation mode Self-write mode FLPMC ← 09H FLPMC ← 08H Flash memory area (60 KB) * This area cannot be accessed with a normal instruction. Erase/write routine call 9BFFH 8000HErase/ write Internal expansion RAM area (2 KB) Internal expansion RAM area (2 KB) Firmware area (including erase/ write routine) F7FFH F000H EFFFH 0000H F7FFH F000H EFFFH 0000H (2) Flash programming mode control register (FLPMC) The flash programming mode control register (FLPMC) is a register for checking the operating mode selection and V PP pin status. FLPMC is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 08H.

µPD78F0833Y Data Sheet U15013EJ2V0DS22 Figure 7-4. Format of Flash Programming Mode Control Register (FLPMC) Notes 1. Bit 2 changes depending on the level of the V PP pin. 2. Bit 2 is read-only. Cautions 1. Be sure to set bits 1 and bits 4 to 7 to 0, and set bit 3 to 1. 2. The VPP bit indicates the status of the voltage applied to the V PP pin. If the VPP bit is 0, the voltage required for erase/write is not applied. However, even if VPP bit is 1, it does necessarily mean that the voltage required for erase/write is applied. Configure the hardware so that the voltage required for erase/write is applied to the V PP pin. Also, if software will be used in addition to hardware to check that the voltage required for erase/write is applied, provide an external hardware detection circuit and use its output. (3) Self-write procedure The procedure for performing self write is shown below (see Figure 7-5 ). (1) Disable interrupts. (2) Designate the self-write mode (FLPMC = 09H). (3) Select register bank 3. (4) Specify the start address of the entry RAM for the HL register. (5) V PP: ON (ON signal for power supply IC) (6) Check the V PP level. (7) Initialize the flash subroutine. (8) Set the parameters. (9) Control the flash memory (erase, write, etc.). (10) V PP: OFF (OFF signal for power supply IC) (11) Designate the normal operating mode (FLPMC = 08H). 76543210

00001 V P P 0 FLSPM0

VPP V PP pin voltage application status 0 The voltage required for flash memory erase/write is not applied to V PP pin. Voltage greater than that of VDD pin is applied to VPP pin.1 FLSPM0 Operating mode selection

0 Normal operating mode

µPD78F0833Y Data Sheet U15013EJ2V0DS 23 Figure 7-5. Self-Programming Flowchart Note Differs depending on the user program. Disable interrupts. Select register bank 3. Specify the entry RAM address. Initialize the flash subroutine. Set the parameters. Pre-write Erase Error? Write data Verify VPP: OFF(10) (9) (8) (7) (6) (5) (1) (2) (3) (4) (11) Designate normal operating mode (FLPMC = 08H). Error? Number of errors? Flash memory error VPP: ON VPP = 1? No Yes No No Yes nth timeNote Less than n timesNote Error? No Yes Yes Designate the self-write mode (FLPMC = 09H).

µPD78F0833Y Data Sheet U15013EJ2V0DS24 Figure 7-6. Self-Write Timing VDD VPP RESET CPU operation and program processing Reset mode Reset mode Normal operating mode FLPMC ← 09H V PP: ON Writing to flash memory. VPP = 10 V ±0.3 V VPP: OFF FLPMC ← 08H Normal operating modeSelf-write mode Normal program processing Normal program processing Mode setting Erase Write Verify Mode setting 5 V 0 V 10 V 0 V 5 V 0 V 4.5 V 9.7 V 0.2VDD 0.2VDD0.2VDD 4.5 V TRSL

µPD78F0833Y Data Sheet U15013EJ2V0DS 25 (4) CPU resources The CPU resources used during self write are as follows:

• Register bank: BANK3 (8 bytes) B register: Status flag C register: Function number HL register: Entry RAM area start address
• Stack area: Maximum 16 bytes
• Write data storage area: 1 to 256 bytes
• Entry RAM area: 32 bytes RAM area used by the self-write subroutines. Can be specified by the user using the HL register.
• Status register 76543210 Parameter —— Verify error Write error — Blank check — setting error error (5) Entry RAM area A description of the entry RAM area is shown in Table 7-3. Table 7-3. Entry RAM Area Offset Value Description +0 Reserved area (1 byte) +1 Reserved area (1 byte) +2 Flash memory start address (2 bytes) +4 Flash memory end address (2 bytes) +6 Number of bytes written to flash memory (1 byte) +7 Write time data (1 byte) +8 Erase time data (3 bytes) +11 Reserved area (3 bytes) +14 Write data storage buffer start address (2 bytes) +16 Total block number (1 byte) +17 Total area number (1 byte) +18 Reserved area (14 bytes) Example When the value of the HL register of register bank 3 is 0FD00H 0FD00H: Status 0FD02H: Flash memory start address 0FD06H: Number of bytes written to flash memory

µPD78F0833Y Data Sheet U15013EJ2V0DS26 Next, the entry RAM area will be explained in detail. (a) Flash memory start address This is the flash memory address value used by the _FlashByteWrite subroutine. (b) Flash memory end address This is the flash memory address value used by the _FlashGetInfo subroutine. (c) Number of bytes written in flash memory Area number and number of bytes written in the flash memory. (d) Write time data Set the following values based on the operating frequency. fX (MHz) Setting Value 1.00 to 1.28 20H 1.29 to 2.56 40H 2.57 to 5.12 60H 5.13 to 8.38 80H (e) Erase time data Setting value = Erase time (s) × Operating frequency/2 9 + 1 (Erase time range: 0.5 to 20 seconds) Example Erase time: 2 seconds, operating frequency: 4.19 MHz Setting value = 2 × 4194304/512 + 1 = 16385 (decimal) = 4001H (hexadecimal) (f) Write data storage buffer start address This area contains the start address of the write data storage buffer area. The RAM data (write data), for which the data in this area is specified as the address, is written to the flash memory (_FlashByteWrite subroutine). The data in this area is specified as the start address and it is possible to specify up to a maximum of 256 bytes of write data. (g) Total block number This is the total flash memory block number used by the _FlashGetInfo subroutine. (h) Total area number This is the total flash memory area used by the _FlashGetInfo subroutine.

µPD78F0833Y Data Sheet U15013EJ2V0DS 27 (6) Self-write subroutines The self-write subroutines and their functions are shown in Table 7-4 below. Table 7-4. List of Self-Write Subroutines Function Number Subroutine Name Function Decimal Hexadecimal 0 00H _FlashEnv Initializes the flash subroutine. 1 01H _FlashSetEnv Sets the parameters. 2 02H _FlashGetInfo Reads flash memory data 16 10H _FlashAreaBlankCheck Performs a blank check of a specified area. 32 20H _FlashAreaPreWrite Performs prewrite for a specified area. 48 30H _FlashAreaErase Erases a specified area. 80 50H _FlashByteWrite Writes continuously in byte units. 96 60H _FlashAreaVerify Performs internal verification of a specified area. (7) Self-write circuit configuration The configuration of the self-write circuit is shown in Figure 7-7. Figure 7-7. Self-Write Circuit Configuration PD78F0833Yµ VOUT = 9.7 to 10.2 V V IN = 11 to 13.5 V IC for power supply ( PC29S10, etc.) VDD VSS VPP Output port ≥ 10 kΩ 10 kΩ OUTPUT INPUT VSSON/OFF µ

µPD78F0833Y Data Sheet U15013EJ2V0DS28 Parameter Symbol Conditions Ratings Unit Supply voltage V DD VDD = AV DD = AV REF –0.3 to +6.5 V AVDD V AVREF V VPP –0.3 to +10.5 V AVSS –0.3 to +0.3 V Input voltage V I1 P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to –0.3 to V DD + 0.3 V P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2RX, X1, X2, RESET VI2 P33 N-ch open-drain –0.3 to +16 V Output voltage V O P00 to P07, P20 to P27, P30 to P36, P40 to P47, P50 to –0.3 to V DD + 0.3 V P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2TX Analog input V AN ANI00 to ANI70 Analog input pin AVSS – 0.3 to AV REF + 0.3 V voltage ANI01 to ANI71 and –0.3 to V DD + 0.3 Output current, I OH Per pin for P00 to P07, P20 to P27, P30 to P32, P34 to –10 mA high P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P75, P80 to P87, P90 to P97, C2TX Total for all pins –30 mA Output current, I OL Per pin for P00 to P07, P20 to P27, P30 to Peak value 20 mA lowNote P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 rms value 10 mA to P97, C2TX P33 Peak value 30 mA rms value 15 mA Total for all pins Peak value 100 mA rms value 60 mA Operating ambient T A During normal operation –40 to +85 °C temperature During flash memory programming +10 to +40 °C Storage T stg –65 to +150 °C temperature Note The rms value should be calculated as follows: [rms value] = [Peak value] × √Duty Caution Product quality may suffer if the absolute maximum rating is exceeded for even single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions ensuring that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A = 25°C)

µPD78F0833Y Data Sheet U15013EJ2V0DS 29 Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic Oscillation 4.0 8.4 MHz resonator frequency (f X)Note 1 Oscillation 4 ms stabilization time Note 2 Crystal Oscillation 4.0 4.2 MHz resonator frequency (f X)Note 1 Oscillation 10 ms stabilization time Note 2 Notes 1. Indicates only oscillator characteristics. 2. Time required to stabilize oscillation after reset or STOP mode release. Caution When using the system clock oscillator, wiring in the area enclosed with the broken line in the above figures should be carried out as follows to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a line through which a high fluctuating current flows.
• Always keep the ground point of the oscillator to the same potential as V SS1.
• Do not ground the capacitor to a ground pattern in which a high current flows.
• Do not fetch signals from the oscillator. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. System Clock Oscillator Characteristics (T A = –40 to 85 °C, VDD = 4.5 to 5.5 V) X2 X1 VPP X2 X1 VPP

µPD78F0833Y Data Sheet U15013EJ2V0DS30 Capacitance (T A = 25°C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input C IN f = 1 MHz 15 pF capacitance Unmeasured pins returned to 0 V. Output C OUT f = 1 MHz 15 pF capacitance Unmeasured pins returned to 0 V. I/O capacitance C IO f = 1 MHz P00 to P07, P20 to 15 pF Unmeasured pins returned to 0 V. P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97 P33 20 pF Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

µPD78F0833Y Data Sheet U15013EJ2V0DS 31 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, V IH1 P21, P25, P31, P34, P40 to P47, P64 to P67, P70 to 0.7V DD VDD V high P73, P80 to P87, P90 to P97 VIH2 P00 to P07, P20, P22 to P24, P26, P27, P30, P32, P35, 0.8V DD VDD V P36, P74, P75, RESET VIH3 P50 to P57 2.3 V DD V VIH4 P33 (N-ch open-drain) 0.7V DD 15 V VIH5 X1, X2 V DD − 0.5 V DD V VIH6 C2RX 0.8V DD VDD + 0.2 V Input voltage, V IL1 P21, P25, P31, P34, P40 to P47, P64 to P67, P70 to 0 0.3V DD V low P73, P80 to P87, P90 to P97 VIL2 P00 to P07, P20, P22 to P24, P26, P27, P30, P32, P35, 0 0.2V DD V P36, P74, P75, C2RX, RESET VIL3 P50 to P57 0 0.75 V VIL4 P33 (N-ch open-drain) 0 0.3V DD V VIL5 X1, X2 0 0.4 V Output voltage, V OH1 IOH = −1 mA P00 to P07, P20 to P27, P30 to P32, V DD − 1.0 V DD V high P34 to P36, P40 to P47, P50 to P57, VOH2 IOH = −100 µA P64 to P67, P70, P73 to P75, P80 to VDD − 0.5 V DD V P87, P90 to P97, C2TX Output voltage, V OL1 IOL = 15 mA P33 0.4 2.0 V low VOL2 IOL = 1.6 mA P71, P72 0.4 V VOL3 IOL = 1 mA P00 to P07, P20 to P27, P30 to P32, 1.0 V P34 to P36, P40 to P47, P50 to P57, VOL4 IOL = 500 µA P64 to P67, P70, P73 to P75, P80 to 0.5 V P87, P90 to P97, C2TX Input leakage I LIH1 VIN = VDD P00 to P07, P20 to P27, P30 to P32, 3 µA current, high P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2RX, RESET ILIH2 X1 20 µA ILIH3 VIN = 15 V P33 80 µA Input leakage I LIL1 VIN = 0 V P00 to P07, P20 to P27, P30 to P32, −3 µA current, low P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2RX, RESET ILIL2 X1 −20 µA ILIL3 P33 −3Note µA Note A low-level input leakage current of −200 µA (MAX.) flows only for 1 clock after a read instruction has been executed to P33 or port 33 (P33). At times other than this 1-clock interval a −3 µA (MAX.) current flows. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DC Characteristics (T A = –40 to +85 °C, VDD = AVDD = AVREF = 4.5 to 5.5 V)

µPD78F0833Y Data Sheet U15013EJ2V0DS32 Parameter Symbol Conditions MIN. TYP. MAX. Unit Output leakage I LOH VOUT = VDD P00 to P07, P20 to P27, P30 to P32, 3 µA current, high P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P75, P80 to P87, P90 to P97, C2TX Output leakage I LOL VOUT = 0 V P00 to P07, P20 to P27, P30 to P36, −3 µA current, low P40 to P47, P50 to P57, P64 to P67, P70 to P75, P80 to P87, P90 to P97, C2TX Software pull-up R 1 VIN = 0 V P00 to P07, P20 to P27, P30 to P32, 15 30 90 k Ω resistor P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P75 Supply I DD1 4.19 MHz crystal oscillation operation mode Note 2 61 2 m A currentNote 1

8.38 MHz crystal oscillation operation mode Note 2 11 22 mA

IDD2 4.19 MHz crystal oscillation HALT mode Note 3 400 700 µA

8.38 MHz crystal oscillation HALT mode Note 3 700 1,200 µA

IDD3 STOP mode 0.1 30 µA Notes 1. Total current flowing in the internal power supply (V DD1 and VSS1). AVREF, AVDD, and port current (on- chip pull-up resistor) are not included. 2. During high-speed mode operation (when the processor clock control register (PCC) is set to 00H). 3. During low-speed mode operation (when the processor clock control register (PCC) is set to 04H). The WTN0 operating current and the receive wait state operating current of the CLASS2 signal (when bits 5 and 4 (C2SC1 and C2SC0) of the class2 clock selection register (C2CLK) are set to 00B) are included. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. DC Characteristics (T A = –40 to +85 °C, VDD = AVDD = AVREF = 4.5 to 5.5 V)

µPD78F0833Y Data Sheet U15013EJ2V0DS 33 Parameter Symbol Conditions MIN. TYP. MAX. Unit Cycle time T CY Using ceramic resonator 0.238 8 µs (Minimum instruction Using crystal resonator 0.476 8 µs execution time) TI000, TI010, t TIH0 2/fsam µs TI001, TI011 input t TIL0 + 0.1Note high-/low-level width TI50, TI51, TI52 f TI5 0 2.5 MHz input frequency TI50, TI51, TI52 t TIH5 160 ns input high-/low-level t TIL5 width Interrupt request t INTH INTP0 to INTP7, P40 to P47 10 µs input high-/low-level t INTL width RESET t RSL 10 µs low-level width Note Selection of fsam = fX, fX/4, fX/64 is available with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode register 0n (PRM0n). However, if the TI00n valid edge is selected as the count clock, the value becomes f sam = fX/ 8 (n = 0, 1). AC Characteristics (1) Basic operation (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V)

µPD78F0833Y Data Sheet U15013EJ2V0DS34 (2) Serial interface (T A = –40 to +85 °C, VDD = 4.5 to 5.5 V) (a) SIO3 3-wire serial I/O mode (internal clock output): SIO30, SIO31 Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK3 cycle time t KCY1 952 ns SCK3 high-/low-level t KH1, tKL1 tKCY1/2 – 50 ns width SI3 setup time t SIK1 100 ns (to SCK3↑) SI3 hold time t KSI1 400 ns (from SCK3 ↑) Delay time from SCK3 ↓ tKSO1 C = 100 pF Note 300 ns to SO3 output Note C is the load capacitance of the SCK3 and SO3 output lines. (b) SIO3 3-wire serial I/O mode (external clock input): SIO30, SIO31 Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK3 cycle time t KCY2 800 ns SCK3 high-/low-level t KH2, tKL2 400 ns width SI3 setup time t SIK2 100 ns (to SCK3↑) SI3 hold time t KSI2 400 ns (from SCK3 ↑) Delay time from SCK3 ↓ tKSO2 C = 100 pF Note 300 ns to SO3 output Note C is the load capacitance of the SO3 output line. (c) UART0 (dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 131,250 bps (d) UART0 (external clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK0 cycle time t KCY3 800 ns ASCK0 high-/low-level t KH3, tKL3 400 ns width Transfer rate 39,063 bps

µPD78F0833Y Data Sheet U15013EJ2V0DS 35 (e) I 2C bus mode Parameter Symbol Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. SCL0 clock frequency f SCL 0 100 0 400 kHz Bus free time t BUF 4.7 1.3 µs (between stop and start condition) Hold time Note 1 tHD:STA 4.0 0.6 µs SCL0 clock low-level width t LOW 4.7 1.3 µs SCL0 clock high-level width t HIGH 4.0 0.6 µs Start/restart condition setup time t SU:STA 4.7 0.6 µs Data hold time CBUS compatible master t HD:DAT 5.0 —— µs I2C bus 0 Note 2 0Note 2 0.9Note 3 µs Data setup time t SU:DAT 250 100 Note 4 ns SDA0 and SCL0 signal rise time t R 1,000 300 ns SDA0 and SCL0 signal fall time t F 300 300 ns Stop condition setup time t SU:STO 4.0 0.6 µs Capacitive load per each bus line Cb 400 400 pF Notes 1. Upon occurrence of the start condition, the first clock pulse is generated after hold period. 2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide a SDA0 signal (on V IHmin. of SCL0 signal) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low hold time (t LOW), only the maximum data hold time tHD:DAT needs to be fulfilled. 4. The high-speed-mode I 2C bus is available in the standard-mode I 2C bus system. At this time, the conditions described below must be satisfied.

• If the device does not extend the SCL0 signal low state hold time t SU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns by standard mode I 2C bus specification).

µPD78F0833Y Data Sheet U15013EJ2V0DS36 (3) CLASS2 (T A = –40 to +85 °C, VDD = 4.5 to 5.5 V) (a) Internal clock count limit Parameter Symbol Conditions MIN. TYP. MAX. Unit Internal clock cycle time t CCLK 467 510 ns (b) In normal mode Parameter Symbol Conditions MIN. TYP. MAX. Unit Rise transfer delay time t PDR 62 tCCLK µs (from C2TX ↑ to C2RX ↑) Fall transfer delay time t PDF 62 tCCLK µs (from C2TX ↓ to C2RX ↓) (c) In ×4 speed mode Parameter Symbol Conditions MIN. TYP. MAX. Unit Rise transfer delay time t PDRX 8 tCCLK µs (from C2TX ↑ to C2RX ↑) Fall transfer delay time t PDFX 8 tCCLK µs (from C2TX ↓ to C2RX ↓) (d) Transmit and receive pulse width (in normal mode) Symbol t XMIN tXNOM tXMAX tRMIN tRMAX Unit When Passive “0”, Active “1” 60 64 68 37 91 or lower µs When Passive “1”, Active “0” 122 128 134 100 157 or lower µs When Active “SOF” 193 200 207 170 230 µs When Passive “EOF” 271 280 289 249 320 or lower µs Idle point 320 or higher 8 t CCLK µs When Active “Break” 768 249 or higher µs (e) Transmit and receive pulse width (in ×4 speed mode) Symbol t XMIN tXNOM tXMAX tRMIN tRMAX Unit When Passive “0”, Active “1” 15 16 17 10 22 µs When Passive “1”, Active “0” 30 32 34 25 39 µs When Active “SOF” 48 50 52 43 57 µs When Passive “EOF” 68 70 72 63 80 µs Idle point 80 8 t CCLK µs When Active “Break” 768 63 µs

µPD78F0833Y Data Sheet U15013EJ2V0DS 37 AC Timing Test Points (Excluding X1 Input) Clock Timing TI Timing 0.8VDD 0.2VDD Test points 0.8VDD 0.2VDD X1 input VIH5 (MIN.) VIL5 (MAX.) 1/fX tXL tXH TI000, TI010, TI001, TI011 tTIL0 tTIH0 TI50, TI51, TI52 1/fTI5 tTIL5 tTIH5 Interrupt Request Input Timing RESET Input Timing RESET tRSL INTP0 to INTP7 tINTL tINTH

µPD78F0833Y Data Sheet U15013EJ2V0DS38 Serial Transfer Timing 3-wire serial I/O mode: UART mode (external clock input): I2C bus mode SI30, SI31 SO30, SO31 tKCYn tKLn tKHn tSIKn tKSIn Input data tKSOn Output data SCK30, SCK31 ASCK0 tKH3tKL3 tKCY3 SCL0 SDA0 tHD:STA tBUF tHD:DAT tF tSU:DAT tSU:STA tSP tSU:STO tR Stop condition Start condition Stop condition Restart condition tHIGH tHD:STA tLOW

µPD78F0833Y Data Sheet U15013EJ2V0DS 39 CLASS2 Transfer Waveform (Example of Short Pulse Width) Remarks 1. The meanings of the symbols in above figure are as follows. tPDR: CLASS2 transceiver rise transfer delay time in normal mode tPDF: CLASS2 transceiver fall transfer delay time in normal mode tPDRX: CLASS2 transceiver rise transfer delay time in ×4 speed mode tPDFX: CLASS2 transceiver fall transfer delay time in ×4 speed mode 2. The values of t PDR, tPDF, tPDRX, and tPDFX can be specified using the class 2 rise transfer delay time correct register (C2PDR) and the class 2 fall transfer delay time correct register (C2PDF). tPDR C2TX C2RX 64 s-tPDFµ 64 sµ 64 sµ tPDF tPDR64 s-tPDRµ tPDRX C2TX C2RX 16 s-tPDFXµ 16 sµ 16 sµ tPDFX tPDRX16 s-tPDRXµ

µPD78F0833Y Data Sheet U15013EJ2V0DS40 A/D Converter Characteristics (T A = –40 to +85 °C, VDD = AVDD = AVREF = 4.5 to 5.5 V, V SS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 888 b i t Overall error Note ±0.6 %FSR Conversion time t CONV 14 100 µs Analog input voltage V IAN AVSS AVREF V AVREF resistance R AIREF 9.5 15 37 k Ω Note Excluding quantization error ( ±1/2%FSR). This value is indicated as a ratio to the full-scale value. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T A = –40 to +85 °C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention power V DDDR 2.0 5.5 V supply voltage Data retention I DDDR VDDDR = 2.0 V 0.1 10 µA power supply current Release signal set time tSREL 0 µs Oscillation stabilization wait time t WAIT Release by RESET 2 17/fX ms Release by interrupt request Note ms Note Selection of 2 12/fX, 214/fX, 2 15/fX, 216/fX, and 2 17/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Retention Timing (STOP Mode Release by RESET) VDD STOP instruction execution RESET STOP mode Data retention mode VDDDR Internal reset operation HALT mode Operating mode tWAIT tSREL

µPD78F0833Y Data Sheet U15013EJ2V0DS 41 Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) Standby release signal (Interrupt request) VDD STOP instruction execution STOP mode Data retention mode VDDDR HALT mode Operating mode tWAIT tSREL

µPD78F0833Y Data Sheet U15013EJ2V0DS42 Flash Memory Programming Characteristics (V DD = 2.7 to 5.5 V, V SS = 0 V, V PP = 9.7 to 10.3 V) (1) Basic Characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD supply voltage V DD Operating voltage during write operation 4.5 5.5 V VPP supply voltage V PPL When detecting V PP low level 0 0.2V DD V VPP When programming flash memory 9.7 10.0 10.3 V VPP supply current I PP VPP = 10.0 V 100 mA Programming temperature T PRG +10 +40 °C Write time C WRT TPRG = +10 to +40 °C 20 20 20 Times Remark The operating clock range in flash memory programming mode is the same as in normal operating mode. (2) Write Operation Characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit VPP set time t PSRON VPP high voltage 1.0 µs Set time from V DD↑ to VPP↑ tDRPSR VPP high voltage 1.0 µs Set time from V PP↑ to RESET↑ tPSRRF VPP high voltage 1.0 µs Time from RESET ↑ to VPP tRFCF 1.0 µs count start Count execution time t COUNT 2.0 ms VPP counter high-/low-level t CH, tCL 8.0 µs width V PP counter noise elimination t NFW 40 ns width (3) Self-Programming Characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Time from V PP↓ to RESET ↑ tPAFRF 0 µs Time from RESET ↓ to VDD tRFDF 0 µs

µPD78F0833Y Data Sheet U15013EJ2V0DS 43 Flash Write Mode Setting Timing FLPMC ← 09H VPP on During flash memory write VPP = 10 V ±0.3 V VPP off FLPMC ← 08H 5 V 0 V VDD 10 V 0 V VPP 5 V 0 V RESET 4.5 V 4.5 V 9.7 V 0.2VDD 0.2VDD 0.8VDD TRSL 0.2VDD Reset mode CPU operation and program processing Reset mode Normal operation mode Normal program processing Normal program processing Mode setting Erase VerifyWrite Normal operation modeSelf-write mode Mode setting TPAFRF TRFDF TRSL

µPD78F0833Y Data Sheet U15013EJ2V0DS44 9. PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A B D G 17.20 ±0.20 14.00 ±0.20 0.13 0.825 I 17.20 ±0.20 J C 14.00 ±0.20 H 0.32 ±0.06 0.65 (T.P.) K 1.60 ±0.20 P 1.40 ±0.10 Q 0.125 ±0.075 L 0.80 ±0.20 F 0.825 N 0.10 M 0.17 +0.03 −0.07 P80GC-65-8BT-1 S 1.70 MAX. R3 °+7° −3° 4160 4061 2180 201 S SN J detail of lead end C D A B R K M L P I S Q G F MH

µPD78F0833Y Data Sheet U15013EJ2V0DS 45 10. RECOMMENDED SOLDERING CONDITIONS The µPD78F0833Y should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E) . For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions µPD78F0833YGC-8BT: 80-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Time: 30 seconds max. (at 210 °C or higher), IR35-107-3 Count: Three times or less, Exposure limit: 7 days Note (after that, prebake at 125°C for 10 hours) Count: Three times or less, Exposure limit: 7 days Note (after that, prebake at 125°C for 10 hours) Wave soldering Solder bath temperature: 260 °C max., Time 10 seconds max., Count: Once, WS60-107-1 Preheating temperature: 120 °C max. (package surface temperature), Exposure limit 7 days Note (after that, prebake at 125 °C for 10 hours) Partial heating Pin temperature: 300 °C max., Time: 3 seconds max. (per pin row) − Note After opening the dry pack, store it at 25 °C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).

µPD78F0833Y Data Sheet U15013EJ2V0DS46 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD78F0833Y. Also refer to (5) Cautions on using development tools. (1) Language Processing Software RA78K0 Assembler package common to 78K/0 Series CC78K0 C compiler package common to 78K/0 Series DF780833 Device file for µPD780833Y Subseries CC78K0-L C compiler library source file common to 78K/0 Series (2) Flash Memory Writing Tools Flashpro II (FL-PR2), Flash programmer dedicated to on-chip flash memory microcontroller Flashpro III (FL-PR3, PG-FP3) FA-80GC Adapter for flash memory writing used with connected to Flashpro II or Flashpro III. 80-pin plastic QFP (GC-8BT type). (3) Debugging Tools

• When using in-circuit emulator IE-78K0-NS IE-78K0-NS In-circuit emulator common to 78K/0 Series IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-70000-98-IF-C Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) IE-70000-CD-IF-A PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/AT TM compatible as host machine (ISA bus supported) IE-70000-PCI-IF-A Adapter necessary when using on-chip PCI bus PC as host machine IE-780833-NS-EM4 Emulation board to emulate µPD780833Y Subseries IE-78K0-NS-P02 I/O board necessary when using IE-780833-NS-EM4 NP-80GC Emulation probe for 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket for connecting target system board designed to mount an 80-pin plastic QFP (GC- 8BT type) and NP-80GC ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780833 Device file common to µPD780833Y Subseries

µPD78F0833Y Data Sheet U15013EJ2V0DS 47

• When using in-circuit emulator IE-78001-R-A IE-78001-R-A In-circuit emulator common to 78K/0 Series IE-70000-98-IF-C Interface adapter when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported) IE-70000-PC-IF-C Interface adapter when using IBM PC/AT compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter necessary when using on-chip PCI bus PC as host machine IE-78000-R-SV3 Interface adapter and cable when using EWS as host machine IE-780833-NS-EM4 Emulation board to emulate µPD780833Y Subseries IE-78K0-NS-P02 I/O board necessary to use IE-780833-NS-EM4 IE-78K0-R-EX1 Emulation probe conversion board necessary to use IE-780833-NS-EM4 + IE-78K0-NS-P02 on IE- 78001-R-A EP-78230GC-R Emulation probe for 64-pin plastic QFP (GC-AB8 type) EV-9200GC-80 Conversion socket to connect target system board for 64-pin plastic QFP (GC-AB8 type) and EP- 78230GC-R ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780833 Device file common to µPD780833Y Subseries (4) Real-time OS RX78K0 Real-time OS for 78K/0 Series MX78K0 OS for 78K/0 Series

µPD78F0833Y Data Sheet U15013EJ2V0DS48 (5) Cautions on using development tools

• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780833.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780833.
• The FL-PR2, FL-PR3, FA-80GC, and NP-80GC are products made by Naito Densei Machida Mfg. Co., Ltd.
• For third-party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide (U11069E) .
• The host machines and OSs supporting each software are as follows. Host Machine PC EWS [OS] PC-9800 series [Windows TM] HP9000 series 700 TM [HP-UX TM] IBM PC/AT compatible SPARCstation TM [SunOSTM, Solaris TM] Software [Japanese/English Windows] NEWS TM (RISC) [NEWS-OS TM] RA78K0 √ Note √ CC78K0 √ Note √ ID78K0-NS √ — ID78K0 √√ SM78K0 √ — RX78K0 √ Note √ MX78K0 √ Note √ Note DOS-based software

µPD78F0833Y Data Sheet U15013EJ2V0DS 49 Conversion Socket (EV-9200GC-80) Package Drawing and Recommended Board Mounting Pattern Figure A-1. EV-9200GC-80 Package Drawing (for reference) (unit: mm) A F D No.1 pin index E EV-9200GC-80 B C M N O L K S RQ P I H J G EV-9200GC-80-G0E ITEM MILLIMETERS INCHES A B C D E F G H I J K L M O N P Q R S 18.0 14.4 14.4 18.0 4-C 2.0 0.8 6.0 16.0 18.7 6.0 16.0 18.7 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.709 0.567 0.567 0.709 4-C 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014 0.091 0.059 φ Based on EV-9200GC-80 (1) Package drawing (in mm) φ

µPD78F0833Y Data Sheet U15013EJ2V0DS50 Figure A-2. EV-9200GC-80 Recommended Board Mounting Pattern (for reference) (unit: mm) A F D E C B G J K L HI 0.026 0.748=0.486 EV-9200GC-80-P1E ITEM MILLIMETERS INCHES A B C D E F G H I J K L 19.7 15.0 15.0 19.7 6.0 ±0.05 6.0 ±0.05 0.35 ±0.02 2.36 ±0.03 2.3 1.57 ±0.03 0.776 0.591 0.591 0.776 0.236 0.236 0.014 0.093 0.091 0.062 φ φ +0.001 –0.002 +0.003 –0.002 +0.001 –0.002 +0.003 –0.002 +0.003 –0.002 +0.003 –0.002 +0.001 –0.001 +0.001 –0.002 φ +0.001 –0.002 φ φ Based on EV-9200GC-80 (2) Pad drawing (in mm) Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Caution φ

µPD78F0833Y Data Sheet U15013EJ2V0DS 51 APPENDIX B. RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µPD780833Y Subseries User ’s Manual U13892E µPD780833Y Data Sheet U15012E µPD78F0833Y Data Sheet This document 78K/0 Series User ’s Manual Instructions U12326E 78K/0, 78K/0S Series Application Note Flash Memory Write U14458E Documents Related to Development Tools (User ’s Manuals) Document Name Document No. RA78K0 Assembler Package Operation U11802E Language U11801E Structured Assembly Language U11789E CC78K0 C Compiler Operation U11517E Language U11518E PG-FP3 Flash Memory Programmer U13502E IE-78K0-NS U13731E IE-78K0-R-EX1 To be prepared IE-780833-NS-EM4 To be prepared SM78K0S, SM78K0 System Simulator Windows Based Operation U14611E SM78K Series System Simulator Ver. 2.10 or Later External Part User Open Interface To be prepared Specifications ID78K0-NS Integrated Debugger Ver. 2.00 or Later Windows Operation U14379E Based ID78K0 Integrated Debugger Windows Based Guide U11649E Reference U11539E Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing.

µPD78F0833Y Data Sheet U15013EJ2V0DS52 Documents Related to Embedded Software (User ’s Manuals) Document Name Document No. 78K/0 Series Real-Time OS Fundamentals U11537E Installation U11536E 78K/0 Series OS MX78K0 Fundamental U12257E Other Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The above related documents are subject to change without notice. Be sure to read the latest documents before designing.

µPD78F0833Y Data Sheet U15013EJ2V0DS 53 [MEMO]

µPD78F0833Y Data Sheet U15013EJ2V0DS54 Purchase of NEC I 2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. FIP and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µPD78F0833Y Data Sheet U15013EJ2V0DS 55 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 NEC Electronics (France) S.A. Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Singapore Pte. Ltd. United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829 J00.7

µPD78F0833Y M8E 00. 4 The information in this document is current as of October, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).