PD78F0544

78K0 ETC | Alldatasheet

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Preliminary Product Information 8-BIT SINGLE-CHIP MICROCONTROLLER ©NEC Electronics Corporation 2004 This information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final produc tion or NEC Electronics Corporation, at its own discretion,, may withdraw the product prior to its production. Not all pr oducts and/ or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) The 78K0/KF2 products are 8-bit single-chip microcontrollers of the 78K0 series. These microcontrollers feature Single-voltage Self-programming Flash memory and many peripherals.

FEATURES

• 78K0 CPU core, 8-bit CISC architecture
• Flash EEPROM and RAM sizes Item Product name Program memory (Flash EEPROM) Data memory (RAM) µPD78F0547 128K bytes (Flash) 7K bytes µPD78F0546 96K bytes (Flash) 5K bytes µPD78F0545 60K bytes (Flash) 3K bytes µPD78F0544 48K bytes (Flash) 2K bytes Minimum instruction cycle 0.1µs (20MHz@4.0V to 5.5V) 0.2µs (10MHz@2.7V to 5.5V) 0.4µs ( 5MHz@1.8V to 5.5V) Clock
• MAIN CLOCK - Internal Ring-oscillator 8MHz (Typ.) - Ceramic/Crystal Oscillator/External CLK (2MHz to 20MHz) (Instruction execution time = 100ns(min.) @20MHz)
• SUB CLOCK - 32.768KHz Crystal oscillator/ External CLK
• WDT CLOCK - Internal Ring-oscillator 240KHz (Typ.) Peripherals.
• On-Chip Power-On-Clear (POC) Circuit
• Low-Voltage Detector (LVI) Circuit
• Timer - 16bit Timer 2ch - 8bit Timer 4ch - Watch Timer - Watchdog Timer (Operable with 240KHz Ring-OSC)
• Serial Interface - UART/CSI 1ch - UART (with LIN-bus) 1ch - Auto-CSI 1ch - CSI 1ch - IIC 1ch
• Key Interrupt 8ch
• AD CONVERTER - 10-bit resolution A/D converter 8ch
• I/O PORT Total : 71 CMOS I/O : 66 CMOS Output: 1 N-ch O.D I/O: 4
• MULTUPLIER/DIVIDER - 16bit x 16bit, 32bit / 16bit
• Other - Self programming - PCL / BUZ OUTPUT - On-chip debug function (P roduct name is undecided.) Interrupt - Internal 20ch - External 9ch Operation Voltage 1.8V to 5.5V Package 80-pin LQFP (12mm x 12mm, 0.5mm pitch) 80-pin LQFP (14mm x 14mm, 0.65mm pitch)

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) 1. Block Diagram Fig. 78K0/KF2 16bit Timer (TM00) TO00 TI000 TI010 8bit Timer (TMH0) TOH0 8bit Timer (TMH1) TOH1 UART-LIN (UART6) RxD6 TxD6 Watchdog Timer 78K0 CPU CORE RAM RESET Reset CTL System Control FLMD0 REGC VDD VSS X2/ EXCLK XT1 XT2/ EXSCLKS Internal High-speed Ring-OSC (8MHz typ.) 16bit Timer (TM01) TO01 TI001 TI011 8bit Timer (TM50) TO50 TI50 8bit Timer (TM51) TO51 TI51 UART (UART0) RxD0 TxD0 3wire Serial I/F (CSI10) SCK10 SI10 SO10 3wire Serial I/F (CSI11) SCK11 SI11 SO11 Automatic 3wire Serial I/F (AUTOCSI) SCKA0 SIA0 SOA0 Port0 Multi master IIC (IIC0) EXSCL0 SCL0 SDA0 Watch Timer (WT) 10bit AD converter AVSS AVREF ANI0 - ANI7 BUSY0 STB0 External Interrupt INTP0 - INTP7 Key ReturnKR0 - KR7 EXLVI Low voltage Indicator (LVI) P00 -P06 Port1 P10 -P17 Port2 P20 -P27 Port3 P30 -P33 Port4 P40 -P47 Port5 P50 -P57 Port6 P60 -P67 Port7 P70 -P77 Port12 P120 -P124 Port13 P140 -P145Port14 P130 Power On Clear (POC) Internal Low-speed Ring-OSC (240kHz typ.) High-speed system clock OSC Subsystem clock OSC EVDD EVSS SSI11 Multiplier /Divider (16x16, 32/16) Flash EEPROM Clock output control Buzzer output PCL BUZ

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) 2. Pin Lay Out 78K0/KF2 80-pin plastic QFP (14 x 14mm 0.65mm pitch) µPD78F0547GC-UBT, µPD78F0546GC-UBT µPD78F0545GC-UBT, µPD78F0544GC-UBT 80-pin plastic LQFP (12 x 12mm 0.5mm pitch) µPD78F0547GK-8EU, µPD78F0546GK-8EU µPD78F0545GK-8EU, µPD78F0544GK-8EU 80pin QFP 2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041 606162636465666768697071727374757677787980 P120/INTP0/EXLVI P47 P46 P45 P44 P43 P42 P41 P40 RESET P124/XT2/EXCLKS P123/XT1 IC/FLMD0 P122/X2/EXCLK P121/X1 REGC VSS EVSS VDD EVDD P60/SCL0 P61/SDA0 P62/EXSCL0 P63 P33/TI51/TO51/INTP4 P64 P65 P66 P67 P77/KR7 P76/KR6 P75/KR5 P74/KR4 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P06/TI011/TO01 P05/TI001/SSI11 P32/INTP3 P31/INTP2 P50 P51 P52 P53 P30/INTP1 P17/TI50/TO50 P16/TOH1/INTP5 P15/TOH0 P14/RXD6 P13/TXD6 P12/SO10 P11/SI10/RXD0 P10/SCK10/TXD0 P54 P55 P56 P57 AVREF AVSS P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1 P20/ANI0 P130 P04/SCK11 P03/SI11 P02/SO11 P01/TI010/TO00 P00/TI000 P145/STB0 P144/SOA0 P143/SIA0 P142/SCKA0 P141/BUZ/BUSY0/INTP7 P140/PCL/INTP6 80pin QFP 2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041 606162636465666768697071727374757677787980 P120/INTP0/EXLVI P47 P46 P45 P44 P43 P42 P41 P40 RESET P124/XT2/EXCLKS P123/XT1 IC/FLMD0 P122/X2/EXCLK P121/X1 REGC VSS EVSS VDD EVDD P60/SCL0 P61/SDA0 P62/EXSCL0 P63 P33/TI51/TO51/INTP4 P64 P65 P66 P67 P77/KR7 P76/KR6 P75/KR5 P74/KR4 P73/KR3 P72/KR2 P71/KR1 P70/KR0 P06/TI011/TO01 P05/TI001/SSI11 P32/INTP3 P31/INTP2 P50 P51 P52 P53 P30/INTP1 P17/TI50/TO50 P16/TOH1/INTP5 P15/TOH0 P14/RXD6 P13/TXD6 P12/SO10 P11/SI10/RXD0 P10/SCK10/TXD0 P54 P55 P56 P57 AVREF AVSS P27/ANI7 P26/ANI6 P25/ANI5 P24/ANI4 P23/ANI3 P22/ANI2 P21/ANI1 P20/ANI0 P130 P04/SCK11 P03/SI11 P02/SO11 P01/TI010/TO00 P00/TI000 P145/STB0 P144/SOA0 P143/SIA0 P142/SCKA0 P141/BUZ/BUSY0/INTP7 P140/PCL/INTP6

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) 3. Pin Function Table (1/2) PIN NAME Function VDD Positive power supply except for ports (except P20-P27 and P121-P124) and AD converter VSS Ground potential except for ports (except P20-P27 and P121-P124) and AD converter EVDD Positive power supply for ports (except P20-P27 and P121-P124) EVSS Ground potential for ports (except P20-P27 and P121-P124) RESET System reset input FLMD0 Flash EEPROM programming mode setting REGC Connecting regulator stabilization capacitor. Connect to GND via a capacitor (0.47µF). AVREF A/D converter analog power supply and power supply for P20-P27 AVSS Ground potential for A/D converter and P20 - P27. I/O port P00 /TI000 External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of16-bit timer/event counter 00 (TM00) I/O port Capture trigger input to capture register (CR000) of 16-bit timer/event counter 00 (TM00) P01 /TI010 /TO00 16-bit timer/event counter 00 output (TM00) I/O port P02 /SO11 Serial data output from serial interface (CSI11) I/O port P03 /SI11 Serial data input to serial interface (CSI11) I/O port P04 /SCK11 Clock input/ output for serial interface (CSI11) I/O port External count clock input to 16-bit timer/event counter 01 Capture trigger input to capture registers (CR001, CR011) of16-bit timer/event counter 01 (TM01) P05 /TI001 /SSI11 Chip select input for serial interface (CSI11) I/O port Capture trigger input to capture register (CR001) of 16-bit timer/event counter 01 (TM01) P06 /TI011 /TO01 16-bit timer/event counter 01 output (TM01) I/O port Clock input/ output for serial interface (CSI10) P10 /SCK10 /TXD0 Serial data output from asynchronous serial interface (UART0) I/O port Serial data input to serial interface (CSI10) P11 /SI10 /RXD0 Serial data input to asynchronous serial interface (UART0) I/O port P12 /SO10 Serial data output form serial interface (CSI10) I/O port P13 /TXD6 Serial data output from asynchronous serial interface (UART6) I/O port P14 /RXD6 Serial data input to asynchronous serial interface (UART6) I/O port P15 /TOH0 8-bit timer H0 output (TMH0) I/O port 8-bit timer H1 output (TMH1) P16 /TOH1 /INTP5 External interrupt request input with specifiable valid edges I/O port External count clock input to 8-bit timer/event counter 50 (TM50) P17 /TI50 /TO50 8-bit timer/event counter 50 output (TM50)

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) Table(2/2) PIN NAME Function P20- P27 / ANI0- ANI7 I/O ports A/D converter analog input P30/INTP1 P31/INTP2 P32/INTP3 I/O port External interrupt request input with specifiable valid edges I/O port External count clock input to 8-bit timer/event counter 51(TM51) 8-bit timer/event counter 51output(TM51) P33 /TI51 /TO51 /INTP4 External interrupt request input with specifiable valid edges P40 - P47 I/O port P50 – P57 I/O port I/O port (N-ch Open drain) P60 /SCL0 Clock input/ output for serial interface (IIC0) I/O port (N-ch Open drain) P61 /SDA0 Serial data input/ output for serial interface (IIC0) I/O port (N-ch Open drain) P62 /EXSCL0 External clock input for serial interface (IIC0) P63 I/O port (N-ch Open drain) P64 – P67 I/O ports I/O ports P70 – P77 /KR0 – KR7 Key interrupt input I/O port External interrupt request input with specifiable valid edges P120 /INTP0 /EXLVI Reference voltage input for Low voltage Indicator I/O port (An external oscillation circuit is not used) P121 /X1 Connecting resonator for main system clock oscillation I/O port (An external oscillation circuit is not used) Connecting resonator for main system clock oscillation P122 /X2 /EXCLK External clock input for main system clock I/O port (An external oscillation circuit is not used) P123 /XT1 Connecting resonator for subsystem clock oscillation I/O port (An external oscillation circuit is not used) Connecting resonator for subsystem clock oscillation P124 /XT2 /EXCLKS External clock input for subsystem clock P130 Output port I/O port Clock output P140 /PCL /INTP6 External interrupt request input with specifiable valid edge I/O port Buzzer output External interrupt request input with specifiable valid edge P141 /BUZ / INTP7 / BUSY0 Busy signal input for serial interface (AUTOCSI) I/O port P142 /SCKA0 Clock input/ output for serial interface (AUTOCSI) I/O port P143 /SIA0 Serial data input to serial interface (AUTOCSI) I/O port P144 /SOA0 Serial data output form serial interface (AUTOCSI) I/O port P145 /STB0 Strobe signal input to serial interface (AUTOCSI)

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) 4. Memory space 78K0/KF2 have 64kB linear address area. To access more than 64KB ROM area, 96KB and 128KB ROM products have BANK type ROM at address of 8000H to C000H. All BANK ROM size is 16KB. Clock 78K0/KF2 have 2 type internal Ring-OSC and 2 type external resonator oscillation circuit. 78K0/KF2 can be operated high-speed internal Ri ng-OSC only. Low-speed Ring-OSC can connect to Watch dog timer and 8bit timer (TMH1) only for high secure. Common ROM Bank ROM Products ROM size Address Address Number of Bank µPD78F0547 128KB 0000H-7FFFH (32KB) 8000H-BFFFH (16KB) 6 µPD78F0546 96KB 0000H-7FFFH (32KB) 8000H-BFFFH (16KB) 4 µPD78F0545 60KB 0000H-EFFFH (60KB) - - µPD78F0544 48KB 0000H-BFFFH (48KB) - - Low-speed Ring-OSC (240kHz typ) High-speed Ring-OSC (8MHz typ) High-speed system clock oscillation circuit (2-20MHz) Watchdog timer CPU Peripheral Subsystem clock oscillation circuit (32.768kHz) MPX MPX Watch timer PCL 8bit timer (TMH1) External resonator or External clock External resonator or External clock Fig. Clock connecting block image

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) 6. Outline of Functions of KF2 µ PD78F0544 µ PD78F0545 µ PD78F0546 µ PD78F0547 Flash Memory 48 K 60 K 96 K 128 K Bank - - 4 6 Internal Memory (Byte) High Speed RAM 1K Extend RAM 1 K 2 K 4 K 6 K Ceramic/Crystal - 2 to 20 MHz: V DD = 4.0 to 5.5 V - 2 to 10 MHz: VDD = 2.7 to 5.5 V - 2 to 5 MHz: VDD = 1.8 to 5.5 V Main System Clock Internal Ring-OSC - 8 MHz(TYP.) Sub System Clock - 32.768 kHz(TYP.) Internal Low Speed Ring-OSC (For TMH1, WDT) - 240 kHz(TYP.) Minimum Instruction Cycle - 0.1 µ s (Ceramic/ Crystal Operation f XH = 20 MHz VDD = 4.0 to 5.5 V) I/O Total :71 - C M O S I / O : 6 6 - CMOS Out :1 - N-ch O.D. :4 Timer - 16 Bit Timer/Event Counter:2ch - 8 Bit Timer/Event Counter:2ch - 8 bit Timer:2ch - Watch Timer:1ch - Watch Dog Timer:1ch Timer Output -6(PWM:4) PCL output - 156.25kHz, 312.5kHz, 615kHz , 1.25MHz, 2.5MHz, 5MHz, 10MHz (fPRS = 20 MHz) Buzzer Output - 2.44 kHz, 4.88 kHz, 9.77 kHz, 19.54 kHz(f PRS = 20 MHz) A/D Converter - 10bit x 8ch Serial Interface - UART (with LIN-bus):1ch - CSI/ UART:1ch - CSI:1ch -Auto-CSI: 1chI - I2C:1ch Multiplier/Divider 16bitx16bit, 32bit/8bit Internal 20 Interrupt External 9 Key Return 8ch On Chip Debug Function Product name is undecided. Voltage Range V DD = 1.8 to 5.5 V Operation temperature Ta = -40°C to +85°C Package - 80pin LQFP(12x12) 0.5mm pitch - 80pin QFP(14x14) 0.65mm pitch

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) 4. Electrical specification of KF2 (Target) Cautionç These specifications show target values, which may change after device evaluation. The operating voltage range may also change. Absolute Maximum Ratings(TA = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit VDD -0.5 to +6.5 V EVDD -0.5 to +6.5 V VSS -0.5 to +0.3 V EVSS -0.5 to +0.3 V AVREF -0.5 to +6.5 V Supply voltage AVSS -0.5 to +0.3 V VI1 -0.3 to V DD = EVDD +0.3 Note V Input voltage VI2 P60-P63(N-ch open drain) -0.3 to +6.5 V Output voltage V O -0.3 to V DD = EVDD +0.3 Note V Analog input voltage V AN -0.3 to AV REF+0.3 Note V Per pin -10 mA P00-P04, P40-P47, P120-P124, P130, P140-P145, -25 mA Output current, high I OH Total of all pins -80 mA P05-P06, P10-P17,P30-P33, P50-P57,P60-P67, P70-P77 -55 mA Note Must be 6.5 V or lower. Caution Product quality may suffer if the absolute maxi mum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which t he product is on the verge of suffering physical damage, and t herefore the product must be used under conditi ons that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) Absolute Maximum Ratings(TA = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Per pin 30 mA P00-P04, P40-P47, P120-P124, P130, P140-P145, 60 mA Output current, low I OL Total of all pins 200 mA P05-P06, P10-P17,P30-P33, P50-P57,P60-P67, P70-P77 140 mA In normal operation mode Operating ambient temperature TA In flash memory programming mode -40 to +85 °C Storage temperature T stg -65 to +150 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) High-Speed System Clock (Crystal/Ceramic) Oscillator Characteristics (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD= EVDD, VSS = EVSS = AVSS = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 2.7 V ≤ VDD < 4.0 V 2.0 10.0 Ceramic resonator X2X1VSS Oscillation frequency(fXH)Note 1.8 V ≤ VDD < 2.7 V 2.0 5.0 MHz 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 2.7 V ≤ VDD < 4.0 V 2.0 10.0 Crystal resonator Oscillation frequency(f XH)Note 1.8 V ≤ VDD < 2.7 V 2.0 5.0 MHz Note Indicates only oscillator characte ristics. Refer to AC Characterist ics for instruction execution time. Cautions 1. When using the high-speed system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the o scillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator. 2. Since the CPU is started by the Ring-OSC after re set is released, check the oscillation stabilization time of the high-speed system clock using the oscill ation stabilization time st atus register (OSTC). Determine the oscillation stabilization time of the OSTC register and oscillation stabilization time select register (OSTS) after suffi ciently evaluating the oscillation st abilization time with the resonator to be used. Remark For the resonator selection and oscillator co nstant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. X2X1 VSS

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) Ring-OSC Oscillator Characteristics (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD= EVDD, VSS = EVSS = AVSS = 0 V) Resonator Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency(f RH)Note1 MHz 2.7 V ≤ VDD ≤ 5.5 V 216 240 264 240 kHz Ring-OSC oscillator Low-speed Ring-OSC kHz Note 1. Indicates only oscillator characteristics. Refer to AC Characteristics fo r instruction execution time. 2. This is the frequency in the case of RSTS(RCM .7)=1. This is 5 MHz(TYP .) in the case of RSTS=0. Subsystem Clock Oscillator Characteristics (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD= EVDD, VSS = EVSS = AVSS = 0 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Crystal resonator Oscillation frequency(fSUB)Note 32 32.768 35 kHz Note Indicates only oscillator characte ristics. Refer to AC Characte ristics for instru ction execution time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the o scillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator. çç 2 . The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power consumption, and is more prone to malfunction du e to noise than the high-speed system clock oscillator. Particular care is therefore requir ed with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator co nstant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 9595 $ $ VSS

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) DC Characteristics (1/4) (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Per pin of P00-P06, P10-P17, P30-P33, P40-P47, P50-P57, P64-P67, P70-P77, P120, P130, P140-P145 mA 2.7 V ≤ VDD < 4.0V -10.0 Total of P00-P04, P40-P47, P120, P130, P140-P145 mA 2.7 V ≤ VDD < 4.0V -19.0 Total of P05-P06, P10-P17, P30-P33, P50-P57, P64-P67, P70-P77 1.8 V ≤ VDD < 2.7V -10.0 mA 2.7 V ≤ VDD < 4.0V -29.0 IOH1 Total of all pins 1.8 V ≤ VDD < 2.7V -15.0 mA Output current, high IOH2 Per pin of P20-P27, P121-P124 Note 1.8V ≤ VDD ≤ 5.5V -0.1 mA 4.0V ≤ VDD ≤ 5.5V 8.5 2.7 V ≤ VDD < 4.0V 5.0 Per pin of P00-P06, P10-P17, P30-P33, P40-P47, P50-P57, P64-P67, P70-P77, P120, P130, P140-P145 1.8 V ≤ VDD < 2.7V 2.0 mA 4.0V ≤ VDD ≤ 5.5V 15.0 2.7 V ≤ VDD < 4.0V 5.0 Per pin of P60-P63 1.8 V ≤ VDD < 2.7V 2.0 mA 4.0V ≤ VDD ≤ 5.5V 20.0 2.7 V ≤ VDD < 4.0V 15.0 Total of P00-P04, P40-P47, P120, P130, P140-P145 1.8 V ≤ VDD < 2.7V 9.0 mA 4.0V ≤ VDD ≤ 5.5V 45.0 2.7 V ≤ VDD < 4.0V 35.0 Total of P05-P06, P10-P17, P30-P33, P50-P57, P64-P67, P70-P77 1.8 V ≤ VDD < 2.7V 20.0 mA 4.0V ≤ VDD ≤ 5.5V 65.0 2.7 V ≤ VDD < 4.0V 50.0 IOL1 Total of all pins 1.8 V ≤ VDD < 2.7V 29.0 mA Output current, low IOL2 Per pin of P20-P27, P121-P124 Note 1.8V ≤ VDD ≤ 5.5V 0.4 mA Noteç When used as digital input ports, set AVREF = VDD. = EVDD. Caution This specification is Duty = 70% condition of I OH and IOL. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) DC Characteristics (2/4) (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VIH1 P02, P12, P13, P15, P40-P47, P50-P57, P60-P67, P121-P124, P144-P145 0.7VDD V DD V VIH2 P00, P01, P03-P06, P10-P11, P14, P16-P17, P30-P33, P70-P77, P120, P140-P143, RESET 0.8VDD V DD V Input voltage, high VIH3 P20-P27 Note 0.7AVREF AV REF V VIL1 P02, P12, P13, P15, P40-P47, P50-P57, P60-P67, P121-P124, P144-P145 0 0.3V DD V VIL2 P00, P01, P03-P06, P10-P11, P14, P16-P17, P30-P33, P70-P77, P120, P140-P143, RESET 0 0.2V DD V Input voltage, low VIL3 P20-P27 Note 0 0.3AVREF V Noteç When used as digital input ports, set AVREF = VDD = EVDD. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) DC Characteristics (3/4) (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit IOH = -3.0 mA 4.0V ≤ VDD ≤ 5.5V VDD-0.7 V IOH = -2.5 mA 2.7 V ≤ VDD ≤ 5.5V VDD-0.5 V VOH1 IOH = -1.0 mA P00-P06, P10-P17, P30-P33, P40-P47, P50-P57, P64-P67, P70-P77, P120, P130, P140-P145 1.8 V ≤ VDD ≤ 5.5V VDD-0.5 V Output voltage, high VOH2 I OH = -0.1 mA P20-P27 P121-P124 1.8 V ≤ VDD ≤ 5.5 V AVREF = VDD = EVDD VDD-0.5 V IOL = 8.5 mA 4.0V ≤ VDD ≤ 5.5V 0.7 V IOL = 1.0 mA 2.7 V ≤ VDD ≤ 5.5V 0.5 V VOL1 IOL = 0.5 mA P00-P06, P10-P17, P30-P33, P40-P47, P50-P57, P64-P67, P70-P77, P120, P130, P140-P145 1.8 V ≤ VDD ≤ 5.5V 0.4 V VOL2 I OL = 0.4 mA P20-P27 P121-P124 1.8 V ≤ VDD ≤ 5.5 V AVREF = VDD = EVDD 0.4 V IOL = 15.0 mA 2.0 V IOL = 5.0 mA 4.0V ≤ VDD ≤ 5.5V 0.4 V IOL = 3.0 mA 2.7 V ≤ VDD ≤ 5.5V 0.4 V Output voltage, low VOL3 IOL = 2.0 mA P60-P63 1.8 V ≤ VDD ≤ 5.5V 0.4 V ILIH1 V I = VDD = EVDD P00-P06, P10-P17, P30-P33, P40-P47, P50-P57, P64-P67, P70-P77, P120-P124, P130, P140-P145 1 µA ILIH2 V I = AVREF P20-P27 1 µA Input leakage current, high ILIH3 V I = VDD = EVDD X1, X2, XT1, XT2 (When use External oscillator) 20 µA ILIL1 V I = VSS = EVSS P00-P06, P10-P17, P30-P33, P40-P47, P50-P57, P64-P67, P70-P77, P120-P124, P130, P140-P145 -1 µA ILIL2 V I = AVREF P20-P27 -1 µA Input leakage current, low ILIL3 V I = VSS = EVSS X1, X2, XT1, XT2 (When use External oscillator) -20 µA Pull-up resistance value RU V I = VDD = EVDD 10 20 100 k Ω VIL In normal operation mode 0 0.2V DD V FLMD0 supply voltage VIH In flash memory programming mode 0.8V DD V DD V Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) DC Characteristics (4/4) (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD =EVDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit fXH = 20 MHz Note2, VDD = 5.0 V 4.7 5.8 mA fXH = 10 MHz Note2 , VDD = 5.0 V Note3 2.5 3.5 mA fXH = 5 MHz Note2 , VDD = 3.0 V Note3 1.5 2.2 mA fRH = 8 MHz Note2 , VDD = 5.0 V 1.9 2.7 mA IDD1 Operation mode fSUB = 32.768 kHz Note2 , VDD = 5.0 V 17 T.B.D. µ A fXH = 20 MHz Note2 , VDD = 5.0 V 2.2 2.6 mA fXH = 10 MHz Note2 , VDD = 5.0 V Note3 1.0 1.2 mA fXH = 5 MHz Note2, VDD = 3.0 V Note3 0.55 0.65 mA fRH = 8 MHz Note2 , VDD = 5.0 V 0.6 0.65 mA IDD2 HALT mode IDD3 STOP mode V DD = EVDD = 5.0 V 1 20 µ A A/D converter operating 0.57 1.3 mA IADC A/D converter IWDT Watchdog Time operating current 240 kHz Ring-OSC operating 5 10 µ A Supply currentNote1 ILVI LVI operating current 9 T.B.D. µ A Notes 1. Total current flowing through the internal power supply (V DD). 2. Input square-wave 3. When AMPH(OSCCTL.0) = 0. Remark 1. f XH: High-Speed System Clock oscillation fre quency (X1 clock oscillation frequency or External main system clock frequency). çç 2. f RH: High-speed Ring-OSC oscillation frequency. ç 3. f SUB: Subsystem Clock oscillation frequency (XT1 clock oscillation frequency or External subsystem clock frequency).

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) AC Characteristics (1)Basic operation ç (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD =EVDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ VDD ≤5.5 V 0.1 16 µs 2.7 V ≤ VDD < 4.0 V 0.2 16 µs High-speed system clock(f XH) 1.8 V ≤ VDD < 2.7 V 0.4 16 µs 2.7 V ≤ VDD < 5.5 V 0.25 4 µs Main system clock(f XP) operation High-speed Ring-OSC clock(f RH) 1.8 V ≤ VDD < 2.7 V 0.5 4 µs Instruction cycle (minimum instruction execution time) TCY Subsystem clock(fSUB)operation 114 122 125 µs 4.0 V ≤ VDD ≤ 5.5 V 2.0 20.0 MHz 2.7 V ≤ VDD < 4.0 V 2.0 10.0 MHz External main system clock frequency fEXCLK 1.8 V ≤ VDD < 2.7 V 2.0 5.0 MHz External main system clock input high-/low-level width tEXCLKH, tEXCLKL (1/ fEXCLK x 1/2) - 1 ns External subsystem clock frequency f EXCLKS 32 32.768 35 kHz External subsystem clock input high-/low-level width tEXCLKSH, tEXCLKSL (1/ fEXCLKS x 1/2) - 5 ns 4.0 V ≤ VDD ≤ 5.5 V 2/f sam +

0.1 Note1

µs TI000, TI010, TI001, TI011 input high-level width, low-level width t TIH0, tTIL0 2.7 V ≤ VDD < 4.0 V 2/fsam +

0.2 Note1

µs 4.0 V ≤ VDD ≤ 5.5 V 10 MHz 2.7 V ≤ VDD < 4.0 V 10 MHz TI50, TI51 input frequency f TI5 1.8 V ≤ VDD < 2.7 V 5 MHz 4.0 V ≤ VDD ≤ 5.5 V 50 ns 2.7 V ≤ VDD < 4.0 V 50 ns TI50, TI51 input high-level width, low-level width tTIH5, tTIL5 1.8 V ≤ VDD < 2.7 V 100 ns Interrupt input high-level width, low-level width tINTH, tINTL 1 µs Key return input low-level width tKR 250 ns RESET low-level width t RSL 10 Note2 µs Notes 1. Selection of f sam = f PRS, fPRS /4, f PRS /256 or f PRS, fPRS /16, f PRS /64 is possible using bits 0 and 1 (PRM000, PRM001 or PRM010,PRM011) of prescaler mode register 00 and 01 (PRM00,PRM01). Note that when selecting the TI 000 or TI001 valid edge as the count clock, fsam = fPRS. 2. Input low level signal into RESET pin until power supply voltage is stabilized in the case of the power supply voltage rise time is slowly (more than 3.4ms).

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) TCY vs VDD (main system clock operation) Guaranteed operation range Supply voltage VDD [V] Remark The values indicated by the shaded section are only when the High-speed Ring-OSC clock is selected. [µs]

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) AC Timing Test Points (Excluding X1 Input) 0.8VDD 0.2VDD Test points 0.8VDD 0.2VDD Clock Timing X1 input VIH6 (MIN.) VIL6 (MAX.) 1/fXP tXPL tXPH 1/fXT tXTL tXTH XT1 input VIH6 (MIN.) VIL6 (MAX.) TI Timing TI00, TI010, TI001, TI011 tTIL0 tTIH0 TI50, TI51 1/fTI5 tTIL5 tTIH5 Interrupt Request Input Timing INTP0 to INTP7 tINTL tINTH RESET Input Timing RESET tRSL

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) (2) Serial interface ç (TA = -40 to +85°C, 1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD= EVDD, VSS = EVSS = AVSS = 0 V) (a)UART mode (UART6, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 312.5 kbps (b) UART mode (UART0, dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 312.5 kbps (c) IIC0 mode Normal mode High speed mode Parameter Symbol MIN. . MAX MIN. . MAX Unit SCL0 clock frequency f CLK 0 100 0 400 kHz Start/restart condition setup timeNote1 t SU: STA 4.8 - 0.7 - µs hold time t HD: STA 4.1 - 0.7 - µs Hold time in SCL = ”L” t LOW 5.0 - 1.25 - µs Hold time in SCL = ”H” t HIGH 5.0 - 1.25 - µs Data setup time (reception) t SU: DAT 0 - 0 - µs Data hold time (sending)Note2 t HD: DAT 0.47 4.0 0.23 1.00 µs Notes 1. The first clock pulse is generated after this period in the case of the start/restart condition. 2. The MAX of tHD:DAT is normal transition value. Wait is occurred in the term of ACK(acknowledge) . Caution Specification at 1.8 V ≤ VDD < 2.7V is not fixed.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) (d) 3-wire serial I/O mode (CSI10, CSI11 master mode, SCK1n ʜinternal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V 100 ns SCK1n cycle time t KCY1 2.7 V ≤ VDD < 4.0 V 200 ns SCK1n high-/low-level width t KH1, tKL1 tKCY1/2 - 10Not1 ns SI1n setup time (to SCK1n↑) t SIK1 30 ns SI1n hold time (to SCK1n↑) t KSI1 30 ns Delay time from SCK1n↓ to SO1n output tKSO1 C = 50 pF Note2 40 ns Notes 1. This is the value when the high-speed system clock (fXH) is operating. ç 2. C is the load capacitance of the SCK1n and SO1n output lines. (e) 3-wire serial I/O mode (CSI10, CSI11 slave mode, SCK1n ʜexternal clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK1n cycle time t KCY2 400 ns SCK1n high-/low-level width t KH2, tKL2 T.B.D ns SI1n setup time (to SCK1n↑) t SIK2 80 ns SI1n hold time (to SCK1n↑) t KSI2 50 ns Delay time from SCK1n↓ to SO1n output tKSO2 C = 50 pF Note 120 ns Note C is the load capacitance of the SO1n output lines. Remark n = 0, 1 Caution Specification at 1.8 V ≤ VDD < 2.7V is not fixed.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) (f) 3-wire serial I/O mode with automatic transmit/ receive function (AUTOCSI SCKA0 ʜinternal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V 600 ns SCKA0 cycle time t KCY3 2.7 V ≤ VDD < 4.0 V 1200 ns 4.0 V ≤ VDD ≤ 5.5 V tKCY3/2 - 50Not1 ns SCKA0 high-/low-level width t KH3 tKL3 2.7 V ≤ VDD < 4.0 V tKCY3/2 - 100Not1 ns SIA0 setup time (to SCKA0↑)t SIK3 100 ns SIA0 hold time (to SCKA0↑) t KSI3 300 ns 4.0 V ≤ VDD ≤ 5.5 V 200 ns Delay time from SCKA0 ↓ to SOA0 tKSO3 C = 100 pF Note2 2.7 V ≤ VDD < 4.0 V 300 ns Time from SCKA0↑ to STB0↑ tSBD tKCY3/2 - 100Not1 ns 4.0 V ≤ VDD ≤ 5.5 V tKCY3 - 30Not1 ns Strobe signal high level width t SBW 2.7 V ≤ VDD < 4.0 V tKCY3 - 60Not1 ns Busy signal setup time (to busy signal detection timing) tBYS 100 ns 4.0 V ≤ VDD ≤ 5.5 V 100 ns Busy signal hold time (from busy signal detection timing) tBYH 2.7 V ≤ VDD < 4.0 V 150 ns Time from busy inactive to SCKA0↓ tSPS 2 tKCY3 ns Notes 1. This is the value when the high-speed system clock (fXH) is operating. ç 2. C is the load capacitance of the SCKA0 and SOA0 output lines. (g) 3-wire serial I/O mode with automatic transmit/ receive function (AUTOCSI SCKA0 ʜexternal clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V 600 ns SCKA0 cycle time t KCY4 2.7 V ≤ VDD < 4.0 V 1200 ns 4.0 V ≤ VDD ≤ 5.5 V T.B.D ns SCKA0 high-/low-level width t KH4 tKL4 2.7 V ≤ VDD < 4.0 V T.B.D ns SIA0 setup time (to SCKA0↑)t SIK4 100 ns SIA0 hold time (to SCKA0↑) t KSI4 300 ns 4.0 V ≤ VDD ≤ 5.5 V 200 ns Delay time from SCKA0↓ to SOA0 output tKSO4 C = 50 pF Note 2.7 V ≤ VDD < 4.0 V 300 ns Note C is the load capacitance of the SOA0 output lines. Caution Specification at 1.8 V ≤ VDD < 2.7V is not fixed.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) Serial Transfer Timing 3-wire serial I/O mode: SI1n SO1n tKCYm tKLm tKHm tSIKm tKSIm Input data tKSOm Output data SCK1n Remark m = 1, 2 n = 0, 1

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) 3-wire serial I/O mode with automatic transmit/receive function: STB0 SCKA0 SIA0 SOA0 D2 D1 D0 D2 D1 D0 tSIK3, 4 tKSI3, 4 tKSO3, 4 tKH3, 4 tF4 tR4 tKL3, 4 tKCY3, 4 tSBD tSBW 3-wire serial I/O mode with automatic transmit/receive function (busy processing): tBYH tSPS tBYS 78 9 Note 10Note 10+nNote 1SCKA0 BUSY0 (active-high) Note The signal is not actually driven low here; it is shown as such to indicate the timing.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) A/D Converter Characteristics (TA = -40 to +85°Cɼ1.8 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD = EVDD, VSS = EVSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution R ES 10 bit 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Overall error Note1,2 A INL AVREF < 2.7 V T.B.D. %FSR 4.0 V ≤ AVREF ≤ 5.5 V 6.6 30 µs 2.7 V ≤ AVREF ≤ 5.5 V 6.6 30 µs Conversion time t CONV AVREF < 2.7 V 11 T.B.D. µs 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Zero-scale error Note1,2 E ZS AVREF < 2.7 V T.B.D. %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR 2.7 V ≤ AVREF ≤ 5.5 V ±0.6 %FSR Full-scale error Note1,2 E FS AVREF <2.7 V T.B.D. %FSR 4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB 2.7 V ≤ AVREF ≤ 5.5 V ±4.5 LSB Integral linearity error Note1 I LE AVREF < 2.7 V T.B.D. LSB 4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB 2.7 V ≤ AVREF ≤ 5.5 V ±2.0 LSB Differential linearity error Note1 D LE AVREF < 2.7 V T.B.D. %FSR Analog input voltage V AIN AV SS AV REF V Notes 1. Excludes quantization error (±1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. POC Circuit Characteristics (TA = -40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage V POC 1.3 1.5 1.7 V Power supply rise time t PTH V DD : VPOC →1.8 V (MIN. value of VDD) 75 T.B.D mV/ms Minimum pulse width t PW T.B.D. 50 µs Notes 1. When voltage rises, time required from detection to reset release 2. When voltage drops, time required from detection to reset occur. POC Circuit Timing Supply voltage (VDD ) Time Detection voltage (MIN.) Detection voltage (TYP.) Detection voltage (MAX.) tPTH tPTHD tPW tPD

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) LVI Circuit Characteristics (TA = -40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit VLVI0 4.10 4.20 4.30 V VLVI1 3.95 4.05 4.15 V VLVI2 3.81 3.91 4.01 V VLVI3 3.66 3.76 3.86 V VLVI4 3.51 3.61 3.71 V VLVI5 3.37 3.47 3.57 V VLVI6 3.22 3.32 3.42 V VLVI7 3.07 3.17 3.27 V VLVI8 2.93 3.03 3.13 V VLVI9 2.78 2.88 2.98 V VLVI10 2.63 2.73 2.83 V VLVI11 2.49 2.59 2.69 V VLVI12 2.34 2.44 2.54 V VLVI13 2.19 2.29 2.39 V VLVI14 2.05 2.15 2.25 V Supply voltage level VLVI15 1.90 2.00 2.10 V Detection voltage External input pinNote1 EXLVI EXLVI < V DD = EVDD 1.21 V Minimum pulse width t LW T.B.D. 50 µs Operation stabilization wait time Note2 TLWAIT1 10 T.B.D µs Note 1.ç Using EXLVI/P120/INTP0 pin 2 . Time required from setting LVION to 1 to operation stabilization Remark V LVI(n|1) > VLVIn : n = 1-15 LVI Circuit Timing Supply voltage (VDD ) Time Detection voltage (MIN.) Detection voltage (TYP.) Detection voltage (MAX.) tLW tLDtWAIT1 LVION ← 1

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 1.3Note 5.5 V Note Dependence on POC detection voltage. The data is held before POC reset, but is not held after POC reset when voltage drops. STOP instruction STOP mode Data retention mode Standby release signal Operation mode

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) Flash Memory Programming Characteristics (TA = -40 to +85°C, 2.3 V ≤ VDD = EVDD ≤ 5.5 V, 2.3 V ≤ AVREF ≤ VDD = EVDD, VSS = EVSS = AVSS = 0 V) (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD supply voltage I DD f XP = 10 MHz (TYP.), 20 MHz (MAX.) 4.5 11.0 mA Chip unit T eraca 20 T.B.D ms Erase timeNote1 Sector unit T erasa 20 T.B.D ms Write time T wrwa 50. T.B.D. µs Number of rewrites per chip C erwr 1 erase + 1 write after erase = 1 rewriteNote2 100 time Notes 1. The prewrite time before erasure and the erase verify time (writeback time) are not included. 2. When a product is first written after shipment, “erase → write” and “write only” are both taken as one rewrite. (2) Serial write operation characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Time from RESET↑ to FLMD0 count start TRFCF T.B.D 10 T.B.D ms Count execution time T COUNT T.B.D 10 T.B.D ms FLMD0 counter high-/low-level width T CH/TCL Tc x 0.45 µs FLMD0 counter rise/fall time TR/TF 12.5 µs Remark These values may change after evaluation. Serial Write Operation RESET FLMD0 VDD 0 V VDD 0 V TRFCF TCL TF TR TCOUNT TCH TC

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V IL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between V IL (MAX) and VIH (MIN). HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. NOTES FOR CMOS DEVICES Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash ® is a registered trademark of Silic on Storage Technology, Inc. in several countries including the United States and Japan.

©NEC Electronics Corporation 2004 78K0/KF2 ZUD-CC-04-0129-E Data Published Oct 2004 N CP(K) The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. NEC Electronics products are classified into the following three quality grades: "Standard", "Special", and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics products before using it in a particular application. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) M5 02. 11-1 (1) (2) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "Standard": "Special": "Specific": Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.