PD780C

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Technical content

Features

D Powerful, wide-range logic capability requiring minimal support circuitry D Fully Z80® -compatible D Industry-standard 8080A software compatibility D CP/M@ -compatible D Comprehensive, powerful instruction set featuring 158 instruction types D Vectored, multilevel interrupt structure D Highly consistent architectural structure featuring dual register set D Foreground/background programming D Automatic refreshing of external dynamic memory D Signal timing compatible with industry-standard memory and peripheral devices D TTL-compatible signals D Single-phase +5 V clock and +5 V DC power supply ® ZBO is a registered trademark of Zilog, Inc .

• CP/M is a registered trademark of Digital Research Corporation. IJPD780 HIGH·PERFORMANCE CP/M® ·COMPATIBLE NMOS 8·BIT MICROPROCESSOR Pin Configuration A,O A13 As A,. A7 A,. As As O. A4 O. A3 +5V Ao RFSH BUSAK WR iffi 83.()()()8nA

Ordering Information

Number Package of Operation I'P078 0C 40-pin plastic 01 P 2.5 MHz I'P0780C - l 40-pin plastic DIP 4 MHz I'PD780C -2 40-pin plastic DIP 6 MHz 4-3 II

/APD780 Pin Identification No. Symbol Function 1-5. A o-A 15 Three-sta te ad dress bus 30-40 (o utput) 6 + Cl ock input 7-10. Do-D7 Three-sta te. 110 data bus 12-15 11 +5 V Po wer supply

16 INT Interrupt re quest input

17 NMI Non-mas k able interrupt input

18 HALT Halt sta te input

19 MREQ Memor y re quest output

20 10RQ 110 request output

21 RD Rea d output

22 WR Write output

23 BUSAK Bus ac knowledge output

24 WAIT Wait sta te input

25 BUSRQ Bus re quest input

26 RESET Reset input

27 Ml Mach ine cycle 1

28 RFSH Refresh output

29 GND Ground

Ao-A15 (Address Bus) 16-bit, three-state output address bus. During refresh operations, lines Ao-A6 output the external memory address. 00-07 (Data Bus) 8-bit, three-state I/O data bus. NMI (Non-Maskable Interrupt) This active low input line is used for non-maskable interrupts. A non-maskable interrupt is always acknowledged at the end of the current instruction, regardless of whether the interrupt enable flip flop has been turned on, except when the BUSRQ signal is asserted. Because of the higher priority of the BUSRQ signal, it is acknowledged before the NMI signal. When NMI is acknowledged, program execution automatically restarts from location 0066H. 4-4 NEe INT (Interrupt Request) This active low input line is used for interrupt requests by external I/O devices. Interrupts are serviced upon completion of the current instruction if the interrupt enable flip flop has been turned on by the soft ware. There are three interrupt response modes: the mode o response is equivalent to an 8080 interrupt response; mode 1 uses location 0038H as a restart address; and mode 2 is a simple vectoring to an interrupt service routine that can be located anywhere in memory. BUSRQ (Bus Request) This active low input signal is used to place the data bus, address bus, and a" three-state bus control signals (WR, RD, 10RQ, and MREQ) in a high­ impedance state to allow a requesting device to assume bus control. The BUSRQ signal has a higher priority than the NMI signal and is always honored at the end of the current machine cycle. Excessive DMA operations resulting in long periods in which BUSRQ is asserted can impair the CPU's ability to adequately refresh the dynamic RAMs. Also, BUSRQ does not have an internal pull-up resistor. For input signals to this pin in a wire-OR'ed configuration, an external pull-up resistor should be used. BUSAK (Bus Acknowledge) This active low output line is used to inform the device requesting bus control that the data bus, address bus, and a" three-state bus controls (WR, RD, 10RQ, and MREQ) are in a high-impedance state and the re­ questing device can now assume control. WR (Write) This three-state active low output is used to strobe data from the data bus to external memory or I/O devices. WR is asserted to indicate the data bus holds valid dlita. This line is three-stated during halt or reset conditions. 10RQ (1/0 Request) This three-state active low output is used to indicate the lower half of the address bus holds a valid address for an I/O read or write. During interrupt acknowledge cycles, 10RQ and Ml are asserted together to indicate that a vector address can be sent to the data bus.

RD (Read) This three-state active low output is used to strobe data from external memory or 1/0 devices onto the data bus. RD is asserted to indicate the CPU is requesting data from external memory or 1/0 devices. This line is three-stated during halt or reset conditions. MREQ (Memory Request) This three-state active low output is used to indicate that the address specified for the memory read or write is valid. M1 (Machine Cycle 1) This active low output is used to indicate that the cur­ rent machine cycle is the opcode fetch phase of an instruction execution. HALT (Halt State) This active low input is used with the HA LT instruc­ tion to initiate a halt state. When HALT is asserted, pro­ gram execution stops and does not resume until an in­ terrupt is generated. During the halt state, NOPs are executed in order to continue memory refresh operations. WAIT (Wait State) This active low input is used to indicate that the ex­ ternal memory or 1/0 devices addressed by the CPU are not ready to transfer data. When WAIT is asserted, the CPU is placed in a wait condition. PD780 RESET This active low input signal is used to initialize the CPU. When RESET is asserted, the interrupt enable flip flop is reset, the program counter and the I and R registers are cleared, and interrupt response mode 0 is enabled. In a reset condition, the address and data busses are three-stated and all output control signals are inactive, after which program execution begins from address 0000. The pulse width of RESET must be a minimum of 3 clock cycles in length to reinitialize the CPU and stabilize operation. RFSH (Refresh) This active low output is used in conjunction with the MREQ signal to initiate a refresh read of all external dynamic memory. RFSH and MREQ are both asserted II when the least significant 7 bits of the address on the A address bus hold a valid external dynamic memory address. (Clock) This line is an input for external clock sources. +5 V Single +5 V power supply. GND Ground. 4-5

",PD780 Block Diagram Int. Control 4-6 Main General-Purpose Register Set Accumulator Flag A F Alternative General-Purpose Register Set Accumu'ator A' Flag F' NEe A.B. Buffer 8 C 0 E H L 8' c' ---j] General-Purpose Registers H' L' Interrupt Vector ::: A j Index Register IX o.B. Buffer Inst. Decoder AeadlWrile Control Timing ContrOl 1 1 1 ii, +5V GNO

The architecture includes a dual set of six 8-bit general­ purpose registers and two a-bit accumulators and flag registers. A flexible vectored interrupt structure is sup­ ported by an 8-bit interrupt vector register that pro­ vides the most-significant 8 bits of a pointer to a table of vector addresses, while the requesting device generates the least-significant 8 bits of the pointer. Two 16-bit index registers enable the manipulation of tabular data as well as facilitating code relocation. Multilevel interrupts as well as virtually unlimited sub­ routine nesting are supported by a 16-bit stack pointer and complimentary 16-bit program counter, enhanc­ ing the speed and efficiency of a wide variety of data­ handling operations. Processing efficiency is addi­ tionally supported by a special memory refresh regis­ ter that enables automatic refreshing of all external dynamic memory with minimal processor overhead. The dual set of general-purpose registers may be used as individual 8-bit registers or paired as 16-bit regis­ ters. The dual register set (including a dual accumula­ tor and flag register) not only allows more powerful addressing and data transfer operations, but also per­ mits programming in foreground/background mode for vastly improved throughput. Standard Test Conditions The standard test conditions reference all voltages to ground (0 V) and follow the convention that positive current flows into the referenced pin. The listing of AC parameters is based on a load capacitance of 50 pF unless explicitly stated otherwise. For every 50 pF increase in load capacitance there is a 10 ns delay, up to a maximum increase of 200 pF for the data bus and 100 pF for the address bus and the bus control lines. The operating temperature range is: O°C to + 70°C; +4.75 V :s; Vee :s; +5.25 V. Absolute Maximum Ratings TA = 25°C Opera ting temperature Stora ge tempera ture Vo ltag e on any pin Po wer dissipat ion Note: (I) With respect to ground. J.lPD780 DOC to + 70°C -6 5°C to + 150°C -0.3 to +7 V (1 ) 1.5 W Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Capacitance TA = 25°C Limns Test Parameter Symbol Min Max Unn Condnlons Cl ock capac itan ce Cf 35 pF le=1 MHz Input capacita nce CIN 5 pF Unmeas ured pins Output capacitan ce COUT 10 pF returned to ground. DC Characteristics TA = Do C to +70oe; Vcc = +5 V ± 5% unless otherwise specified Parameter Clock input low voltag e Cl ock input high voltag e Input low voltag e I nput high voltag e Output low voltag e Output hi gh voltag e Po wer supply ,..POlSO Cu rrent ,..POlSO-l Input lea kage current Three-sta te output lea kage current in floa t Three-stat e output lea kage current in fl oat Da ta bus lea kage current in input mode Limits Symbol Min "Jyp VILC -0.3 VIHC Vee -0.6 VIL -0.3 VIH 2.0 VOL VOH 2.4 Icc lee 90 'll 'LDH 'LOL ILO Test Max Unn Condnlons 0.45 V Vee V +0.3 O.S V Vee v 0.4 V IOL =1 .S mA V IOH = -250 ,.. A 150 rnA tC=400 ns 200 mA te=250 ns 10 ;tA VIN=O to Vee 10 ;tA VOUT=2.4 to Vee -1 0 ;tA VOUT=O.4 V ±10 ;tA O:sVIN :sVce 4-7 II

I-'PD780 NEe AC Characteristics TA = OOC to +70oC; vee = +5 V ± 5%; unless otherwise specified Limits P07ao (2.5 MHz) 1"0780-1{4 MHz) 1'.0780-2 II MHz) 11151 Parameter Symbol Min Max Min Max Min Max Unit Condlltons Clock period tc 0.4 (1) 0.25 (I ) 0.165 (I ) I's Clock pulse width, clock high tw(+H) 180 (2) 110 (2) 65 (2) ns Clock pulse width, clock low tw(+L) 180 2000 110 2000 72 2000 ns Clock rise and fall time tRf 30 30 20 ns Address output delay tD(AD) 145 110 90 ns Delay to float tF(AD) 110 90 80 ns Address stable prior to MREO (Memory cycle) tACM (3) (3) (3) ns CL = 50 pF Address stable prior to lORa, RD or WR (1/0 cycle) tACI (4) (4) (4) ns Address stable from RD or WR tCA (5) (5) (5) ns Address stable from RD or WR dur ing Float tCAF (6) (6) (6) ns Data output delay tD(D) 230 150 130 ns Delay to float du ring write cycle tF(D) 90 90 80 ns Data setup time to rising edge of clock during Ml cycle ts,(O) 50 35 30 ns Data setup time to falling edge of clock during M2 to M5 cycles ts,(O) 60 50 40 ns CL = 200 pF Data stable prior to WR (Memory cycle) tDCM (7) (7) (7) ns Data stable prior to WR (1/0 cycle) tOCI (8) (8) (8) ns Data stable from WR tCOF (9) (9) (9) ns BUSRO setup time to rising edge of clock tSISQ) 80 50 50 ns BUSAK delay from rising edge of clock to BUSAK low tOL(BA) t20 100 90 ns BUSAK delay from falling edge of clock to BUSAK high to HI BA) 110 100 90 ns CL = 50 pF Delay to float (MREO, lORa , RD and WR) tF(C) 100 80 70 ns Ml stable prior to 10RO (I nterrupt ack.) tMR (10) (10) (10) ns Any hold time for setup time tH a a a ns HALT delay lime from falling edge of clock to(HT) 300 300 260 ns CL = 50 pF 1NT setup time to rising edge of clock tS(IT) 80 80 70 ns 10RO delay from rising edge of clock to 10RO low tOL!(IR) 90 75 65 ns 10RO delay from falling edge of clock to 10RO low tOLt(IR) 110 85 70 ns 10RO delay from rising edge of clock to 10RO high tOHt(IR) 100 85 70 ns 10RO delay from falling edge of clock to lORa high tOH+(IR) 110 85 70 ns CL=50pF Ml delay from rising edge of clock to Ml low tOL(Mll 130 100 80 ns Ml delay from rising edge of clock to Ml high tOH(Mll 130 100 80 ns MREQ delay from falling edge of clock to MREO low tOLf(MR) 100 85 70 ns MREO delay from rising edge of clock to MREO high tDHt(MR) 100 85 70 ns MREO delay from falling edge of clock to MREO high tOHt(MR) 100 85 70 ns Pulse width, MREO low tW(MRL) (11 ) (11 ) (11) ns Pulse width, MREO high tw(MRH) (12) (12) (12) ns Pulse width, N M I low tW(NML) 80 80 70 ns RESET setup time to rising edge of clock IS(RS) 90 60 60 ns RD delay from rising edge of clock to RD low tOL,(RO) 100 85 70 ns RD delay from falling edge of clock to RD low IOLt(RO) 130 95 80 ns RD delay from rising edge of clock 10 RD high IDHt(RO) 100 85 70 ns RiJ delay from falling edge of clock to RD high tOH,(RO) 110 85 70 ns CL = 30 pF 4-8

AC Characteristics (cont) TA = DOC to + 70°C; Vcc = + 5 V ± 5%; unless otherwise specified PD7'O (2.5 MHzI Parameter Symbol Min Max RFSH delay from rising edge of clock to RFSH low tOL(RF) 180 RFSH delay from rising edge of clock to RFSH high tOH(RF) 150 WAIT setup time to falling edge of clock tS(wr) 70 WR delay from rising edge of clock to WR low tOL.,(WR) 80 WR delay from falling edge of clock WR low tOl+(WR) 90 WR delay from falling edge of clock to WR high tOHt(WR) 100 Pulse width to WR low tW(WRL) (13) Notes: (1 ) tc = tw(tH) + tw(,L) + tR + tF (2) Though the structure of the 780 is static, 2OOs is guaranteed maximum. (3) tACM = tw(tH) + tF - 65 (75)' (50)" (6) ICAF = twit L) + tR - 45 (60)' (40)"' (9) tCOF = twltL) + tR - 70 (80)* (55)*' (12) Iw(MRH) = twit H) + IF - 20 (30)' (20)" , These values apply to the flPD780. " These values apply to the flPD780-2. Load Circuit for Output From Output -----t--_t----i " .. ,,-, too .. 10 K 2.2 K 83-OOO884A PD780 Umlls PD71O·1(4 MHzl PD78.2 (6 MHz) Test Min Max Min Max Unit Conditions 130 110 ns CL : 30 pF 120 100 ns 70 60 ns 65 60 ns 80 70 ns 80 70 ns (13 ) (13 ) ns 4-9

J,tPD780 Timing Waveforms Input Cycle Output Cycle 4-10 T, T, RD T, T, J----.J tDIAD) lAC. - tOL<t>(IR) - tOL<1>(WRl lo'O' i tOCI --r---'\\ --- --' \\....-- Tw Port Address Oata Out :T'C=- T. T, r-----f.-Jn I--'CA-j 'OH;;;(IR) I- -toH;i;(WR) .,1, --JtF(D) ttlEC

Timing Waveforms (coni) M, Cycle T, T2 T, I, tWCMRH!1 t r---'-It - tOH<t>{MR t DH4>(MR) MREQ -+---t--.(n I'DL'1MR' J.---.{, t I J1 W(MRL'='1( r---it tOH(M1)l.-...-J M1-- D _L( _ M toH(RF) J-1- Memory Read/Write Cycles T1 T2 T3 T1 T2 T3 T, A,-A .. ::::0 Memory Address X Memory Address f-- tOL:i:(MR)f-- I tOH:i:(MR)f-- tOLJ,(MRlf--L IOH;;;-{MR)r----- jr MREQ !I RD-+ __ t_D_L i"-RD- , -- --+ IDL;j;{WR) tOH;;-;(WRlf.-Ir_I-__ _ It--- tW(WRL)---1 __ I I tOCM-----j ' f-1CDF-:1 Data Out J.lPD780 II 4-11

",PD780 NEe Timing Waveforms (cont) Interrupt Reques t/Acknowledge Cycle LastTState T1 T2 Tw ,', I WAIT I I RD Input and Output Cycles In 110 operations, a single wait state (Tw) is automat­ ically included to provide adequate time for an 110 port to decode the address from the port address lines and initiate a wait condition if needed. Opcode Fetch Instruction Cycle At the beginning of the cycle, the contents of the pro­ gram counter are placed on the address bus. After ap­ proximately one-half cycle, MREQ is asserted and its falling edge can be used directly by the external mem­ ory as a chip enable signal. The data from the exter­ nal memory can be gated onto the data bus when RD is asserted. The CPU reads the data at the rising edge of T3' During T3 and T4, external dynamic memory is refreshed while the instruction is decoded and exe­ cuted. The assertion of RFSH indicates that the ex­ ternal dynamic memory requires a refresh read. 4-12 Memory Read or Write Cycles In read and write operations, the MREQ and RD signals function the same as they do in opcode fetch operations. In a write operation MREQ is asserted and can be used directly by external memory as a chip enable signal when information on the address bus is stable. The WR signal is used as a write strobe to almost any type of semiconductor memory, and is asserted when data on the data bus is stable. Interrupt Request/Acknowledge Cycle The interrupt signal is sampled at the rising edge of the final clock pulse at the end of an instruction. When an interrupt is accepted, an Ml cycle is begun. Instead of MREQ, 10RQ is asserted during this cycle to indicate that an 8-bit vector address can be placed on the data bus by the interrupting device. This cycle includes the automatic addition of two wait states to facilitate the implementation of a daisy-chain priori­ ty i nterru pt protocol.

The instruction set of the IlPD780 consists of 158 types of instructions divided into 16 categories as follows: 8-bit load operations register exchanges memory block searches 16-bit arithmetic operations rotate and shift operations jump operations restart operations miscellaneous operations 16-bit load operations memory block transfers 8-bit arithmetic and logic operations bit set, reset, and test operations 1/0 operations call operations return operations general-purpose accumulator and flag operations This comprehensive instruction set is made more powerful by the array of addressing modes im­ plemented by the architecture, as follows: bit addressing register-indirect addressing immediate addressing extended addressing implied addressing register addressing relative addressing immediate-extended addressing indexed addressing modified page zero addressing J.(PD780 Instruction Set Symbol Definitions Symbol Description

• Flag not affected o Flag set x Flag Flag affected according to result of operation v Overflow set P Parity set IFF I nterrupt flip-flop set C CarrylLink z Zero P/V Parity IOverflow S Sign N Add/Su btract H Half Carry II 4-13

-"" Instruction Set Mnemonic Operation ADC HL. 55 HL - HL + 66 + CV ADC A, r A-A+r +CV ADC A, n A-A+ n+CY ADC A, (HL) A -A + (HL) + CV ADC A, (IX + d) A - A + (IX + d) + CV ADC A, (I V + d) A -A + (IV + d) + CV ADD A, n A -A + n ADD A, r A - A + r ADD A, (HL) A -A + (HL) ADD A, (I X + d) A -A + (IX + d) ADD A. (I V + d) A - A + (IV + d) ADD HL, 56 HL - HL + 66 ADD IX, pp IX - IX + pp ADD IV , rr IV - IV + rr AND r A - A II r AND n A -A /I n AND (HL) A -A II (HL) AND (IX + d) A -A II (I X + d) AND (IV + d) A -A /I (I V + d)

Description

Add with carry re g. pair 56 to H L Add with carry Reg. r to ACC Add with carrry value n to ACC Add with car ry loc. (HL) to ACC Add with car ry lac. (IX + d) to ACC Add with carry lac. (IV + d) to ACC Add va lue n to ACC Add Reg. r to ACC Add locat ion (HL) to ACC Add loca tion (IX + d) to ACC Add loca tion (IV + d) to ACC Add Reg. pair 56 to HL Add Reg. pair pp to IX Add Reg. pair rr to IV Logica l 'AN 0' of Reg. r II ACC Logical 'A ND' of va lue n /I ACC Logical 'AND ' of lac. (HL) II ACC Logica l 'AND ' of lac. (I X + d) /I ACC Logica l 'AND ' of lac. (I V + d) II ACC Operation Code 7 6 5 _ 3 2 1 o o o 6 5 1 0 o 1 1 (A) o o 0 0 r r r (8) o 0 o nnnnnnnn 000 1 1 1 0 11 011101 1 000 1 1 1 0 d d d d d d d d 111 11101 1 000 1 1 1 0 d d d d d d d d o 0 0 0 n n n n n n n n o 0 0 0 r r r (8) o 0 0 0 1 1 0 110 11 10 1 100001 10 d d d d d d d d 1 1 1 1 1 0 0 0 d d d d 1 1 0 1 o 1 1 0 d d d d o 0 5 6 1 0 0 1 (A) 1 1 0 o 0 p p 1 0 o 0 1 (e) 1 1 o 0 r o 1 1 rI O o 0 r o 0 o o 1 (D) r r (8) o nnnnnnnn o 1 0 0 110111 1 0 1 0 0 1 d d d d d d 1 1 1 1 10100 1 d d d d d d o o 1 1 0 d d o 1 1 0 d d No. 01 Clocks No. 01 Bytes C t t Flags Z PlY S v v v v v v v v v v N o o o o o o o o o o * V a H X

• • • 0 X t • • • 0 X t • • • 0 X o P 0 o P 0 o P o o P o o P o 1:: CI .... CO o (')

.j:>. (j1 Instruction Set (cont) Mnemonic CPIR CPL DAA DE C r DEC (HL) DE C (IX + d) DE C IIV + d) DE C IX DE C IV DE C 55 DI DJNZ, e EI EX IS P), HL EX (SP) , IX EX (SP ), IV EX AF, AF ' EX DE, HL EXX HALT Operation A - (HL) HL HL + 1 8C BC - 1 until A = (HL ) or 8C = 0 A A r r - 1 (H L) (HL) - 1 (IX + d) (IX + d) -1 (IV + d) (IV + d) -1 IX IX - 1 IV - IV - 1 ss ss - 1 IFF -0 8+-8- 1iI8=0 continue il 8 '" 0, PC +- PC + e IFF +- 1 H -(SP + 1) , L .. (SP) IXH .. (SP + 1) IXL" (SP) IVH - (SP + 1) IVL - (SP) AF - AF ' DE - HL 8C - 8C' DE - DE ', HL - Hl' Pr ocessor Halted Compar e loca tion (HL) an d AC C, increment HL, decre ment 8C Repea t until 8C = C Complement AC C (1 's comp,) De cima l ad just AC C Decre ment Reg. r De crement loc. (HL) Decrement loc. (IX + d) Decre ment loc. (IV + d) Decre ment IX Decre ment IV Decre ment Reg. pair ss Disa ble interr upts Decre ment 8 an d jump re lative if 8 = 0 Enable interrupts Exchan ge the locat ion (SP) an d HL Exchange the location (SP) an d IX Exchan ge the loca tion (SP) and IV Excha nge the contents of AF , AF ' Exchange the contents 01 DE an d H L Exchange the contents 01 BC, DE , HL with contents 01 BC', DE', Hl', respectively HALT (wai t lor interrupt or reset) Ope ration Code 7 6 5 4 3 2 1 0 1 0 1 1 0 o 1 0 0 0 o 0 1 0 1 o 0 1 0 0 1 1 o 0 r r r OI lS) 001 1010 11 0111 01 001 10 101 d d d d d d d d 11 1111 01 001 1010 1 d d d d d d d d 1 1 0 1 o 0 1 0 1 1 1 00 0 1 0 o 1 1 0 o 1 o 0 s s o 1 1 (A) 1 1 1 o 0 1 o 0 0 o 0 0 0 - e-2- o 1 0 0 0 1 o 1 1 1 0 1 0 0 0 1 o 1 1 o 0 o o 0 0 0 o 0 0 o 1 0 o 1 1 0 0 o o o II No. 01 No. 01 Clocks Bytes 21 il 8C = 0 2 an d M(HL) 16 i1BC=0 orA= (HL) 23 3 23 3 10 2 10 2 8 2 23 2 23 2 Flags C Z P/V 5

• t(2) t(1) t
• • • • P
• V
• V
• V
• V N H 'l::: Sf CD o

.f:> Instruction Set (cont) 1::: I " en OperaUon Code No. 01 No. 01 Flags a Mnemonic Operation Description 7 6 5 4 3 2 1 0 Clocks Bytes C Z PlY S N H BIT b. (HL) Z - (HL) b Test BIT b of location (HL) 1 0 0 1 0 1 (E) 12 2 • X X a CD 0 b b b 1 0 0 BIT b. (IX + d) Z - (IX + d) b Test BIT b at location (IX + d) 1 1 0 1 1 1 0 1 (E) 20 4 • X X 0 1 1 0 0 1 0 1 1 d d d d d d d d 0 1 b b b 1 1 0 BIT b. (IV + d) Z - (IV + di b Test BIT b at location (IV + d) 1 1 1 1 1 0 1 (E) 20 4 • X X 0 1 1 0 0 1 0 1 1 d d d d d d d d 0 1 b b b 1 1 0 BIT b, r Z <- rb Test BIT of Reg, r 1 o 0 1 0 1 1 8 2 • X X 0 0 b b b r r r (8) (E) else same as CALL nn condition cc is true n n n n n n n n n n n n n n n n CALL nn (SP - 1) - PCH Unconditional call subroutine at 0 0 0 17 3 • • • • • • (SP - 2) - PCl location nn n n n n n n n n PC - nn n n n n n n n n CCF CV - CV Complement carry flag o 0 4 • • • 0 X CP r A - r Compare Reg, r with ACC 0 r r r (8) 4 V CP n A - n Compare value n with ACC 1 0 7 2 V n n n n n n n n CP (H L ) A - (HL ) Compare loc, (H L ) with ACC 0 0 7 V CP (IX + d) A - (IX + d) Compare loc, (IX + d) with ACC 1 1 0 1 1 1 0 1 19 4 V 1 0 1 1 1 1 1 0 d d d d d d d d 1 1 1 1 1 1 0 1 CP (IV + d) Compare loc, (IV + d) with ACC 1 0 1 1 1 1 1 0 19 2 V d d d d d d d d CPO A - (HL ) Compare location (HL ) and ACC, 1 0 1 0 1 16 2 • 1(2) 1(1) HL - HL - 1 decrement H La nd BC 0 a 0 0 1 BC - BC - 1 CPDR A - (H L ) Compare location (HL ) and ACC, 0 1 a 21 if BC = 0 2 • 1(2) 1(1) I HL <- HL - 1 decrement H La nd BC, repeat until BC = 0 0 1 0 0 and M(HL) BC <- BC - 1 16 if BC = 0 until A = (HL) or BC = 0 or A=(HL) CPI A - (HL) Compare location (HL ) and ACC, 1 0 1 1 0 16 2 • 1(2) 1(1) 1 HL <- HL + 1, BC - BC - 1 increment HL and decreme nt BC 0 0 000

-I'> Instruction Set (cont) Mnemonic 1M 0 1M 1 1M 2 IN A, (n) IN r, (C) INC (HL) INC IX INC (IX + d) INC IV INC (IV + d) INC r INC 55 INO INOR INI INIR jp (HL) jp (IX) jp (IY) Operation A'" (n) r'" (C) IX'" IX + 1 IV'" IV + 1 r - r + 1 55 ... 55 + 1 (HL) - (C) (HL)'" (C) 8-8- 1 HL - HL - 1 until 8 = 0 (HL) - (C) (HL) '" (C) 8-8-1 HL ... HL + 1 until B = 0 PC - HL PC -I X PC -IV Load ACC with in put from device n Load Reg. r with input from device (C) Increment location (HL) Increment IX Increment location (IX + d) Increment IV Increment location (IV + d) I ncrement Reg. r Increment Reg. pair 55 Load location (HL) with input from port (Cl. decrement H La nd 8 Load location (HL) with input from port (e), decrement H L and decrement 8, repeat until 8 = 0 Load location (HL) with input from port (C), and increment HL and decrement 8 Load location (HL) with input from port (C), increment HL and decrement 8, repeat until 8 = 0 Unconditional jump to (HL) Unconditional jump to (IX) Unconditional jump to (IV) OperaUon Code 7 8 5 4 3 2 1 0 o o o 1 0 1 o 0 0 1 0 1 01 0 1 0 o 1 o o o 1 1 0 o 1 1 0 o 1 1 0 nnn nnnnn o o 0 o 1 0 1 (I) r r rO O 0 o o 0 11 0111 0 o 0 1 000 110 1 1101 001 10100 d d d d d d d d 1 1 o 0 1 1 1 0 o 0 0 1 11 111101 00 110100 d d d d d d d d o 0 r r rI O 0 (8) 00 5 5 0 0 1 1 (A) o o o o o 1 0 1 o 0 1 0 o 1 0 1 1 0 1 0 o 1 1 0 1 o 0 0 1 0 o 1 1 0 1 1 0 0 1 0 o 1 0 0 o 1 1 0 1 0 0 0 1 1 0 o 0 0 II No. of No. of Cloclai Byles 8 2 8 2 8 2 11 2 12 2 10 2 23 3 10 2 23 3 16 2 21 2 16 2 21 2 8 2 8 2 C Flags Z PlY S

• • •
• • • N H
• •
• •
• P o
• v o
• v o
• v
• v
• • •
• :(3) X
• X
• ;(3) X
• X
• • •
• • •
• • • o o
• • • X X X X X X X X
• • •
• • •
• • • o 1:: D .... m o

.j>. OJ Instruction Set (cont) Mnemonic JP cc, nn JP nn JR C, e JR e JR NC, e JR NZ, e JR Z, e LD A, (BC) LD A, (DE) LD A, I LD A, (nn) LD A, R LD (BC), A LD (DE), A LD (HL), n LD 55, nn LD HL, (nn) LD (H L), r LD I, A Operation If cc true PC - nn else continue PC - nn If C = 0 continue If C = 1 PC - PC + e PC - PC + e If C = 1 continue If C = 0 PC - PC + e If Z 1 continue if Z = 0 continue A - (BC) A - (DE) A -I A - (nn) A-R (BC) - A (DE) - A (HL ) - n 55 - nn H - (nn + 1) (HL) - r I-A Jump to location nn if continue cc Unconditional jump to location nn Jump relative to PC + e, if carry = 1 Unconditional jump relative to PC + e Jump relative to PC + e if carry = 0 Jump relative to PC + e if non-zero (Z = 0) Jump relative to PC + e if zero (Z = 1) Load ACC with location (BC) Load ACC with location (DE) Load ACC with I Load ACC with location nn Load ACC with Reg. R Load location (BC) with ACC Load location (DE) with ACC Load location (HL) with value n Load Reg. pair 55 with value nn Load HL with location (nn) Load location (HL) with Reg. r Load I with ACC Operation Code 7 6 5 _ 3 2 1 0 - cc o o (H) n n n n n n n n n n n n n n n n o 0 0 0 nnnnnnnn nnnnnnnn 00111000 - e-2- 000 1 1 0 a 0 - e-2- 001 1 000 0 - e-2- 001 000 0 0 - e-2- 00 101 000 - e-2- o 0 0 0 o a o 0 0 o 1 0 1 1 0 1 o 0 1 0 o 0 o o o nnnnnnnn nnn nnnnn o 1 0 o 1 o 000 0 0 0 o o 0 0 o 0 o o 0 o o nnnnnnnn o 0 s s 0 0 0 1 (AI nnnnnnnn n n n n n n n n o 0 n n n n o o o o o n n n n n n n n n n n n Or r r (B) 1 0 1 0 000 1 No. of No. of Flags ClockS Bytes C Z P/V S N H 10 3 7 if condition 2 met, 12 if not 12 2 7 2 7 2 7 2 9 2 13 3 9 2 10 2 20 4 16 3 9 2

• IFF o o
• IFF o 0 'l: C .... o

"'" CD Instruction Set (cont) Mnemonic LD IX, nn LD IX, (nn) LD (IX + d), n LD (IX + d), r LD IY, nn LD IY, (nn) LD SS, (nn) LD (IY + d), n LD (IY + d), r LD (nn), A LD (nn), SS OperaHon IX - nn IXH - (nn + 1) IXL - (nn) (IX + d) - n (IX + d) - r IY - nn IYH - (nn + 1) IYL - (nn) SSH - (nn + 1) sSL - (nn) (IY + d) - n (IY + d) - r (nn) - A (nn + 1) - sSH (nn) - sSL Dm;rlptlon Load IX with value nn Load IX with location (nn) Load location (IX + d) with value n Load location (IX + d) with Reg. r Load IY with value nn Load IY with location (nn) Load Reg. pair dd with location (nn) Load (IY + d) with value n Load location (IY + d) with Reg. r Load location (nn) with ACC Load location (nn) with Reg. pair dd Operation Code 7 & 5 4 3 2 1 0 1 1 0 1 1 1 0 001 0 0 0 0 nnnnnnnn nnnnnnnn 1 1 0 1 00 1 0 1 0 1 o 0 n n n n n n n n nnnnnnnn 110 1110 1 001 10110 d d d d d d d d nnnnnnnn 1 1 0 1 1 0 1 (8) 01 11 0 rrr d d d d d d d d 11 111 0 o 0 0 0 0 0 n n n n n n n n n n n n n n n n 1 1 o 0 o 1 0 1 o 1 0 n n n n n n n n n n n n n n n n o o S S 1 0 1 (A) o 1 1 n n n n n n n n n n n n n n n n 111111 01 00 11 0110 d d d d d d d d n n n n n n n n 1 1 1 1 1 0 1 (8) 011 10rrr d d d d d d d d o 0 0 0 0 n n n n n n n n n n n n n n n n 1 0 1 1 0 1 (A) o ss 00 11 n n n n n n n n n n n n n n n n II No. of No. of Clocks Bytes 19 4 20 4 19 4 19 3 14 4 20 4 20 4 19 4 19 3 13 3 20 4 c Flags Z P/V S

• • • N H
• • t') 1::: "II D CD o

.j>. Instruction Set (cont) 1;:: I I\\J " a Operation Code No. of No. of Flags C Mnemonic Operation Description 7 & 5 • 3 2 1 0 Clocles Bytes C Z PlY 5 N H .... LD (nn). HL (nn + 1) - H Load location (nn) with HL o 0 0 0 0 0 16 3 • • • • • • CD (nn) +- L n n n n n n n n 0 n n n n n n n n LD (nn). IX (nn +1) - IXH Load location (nn) with IX 1 1 0 1 1 1 0 1 20 4 • • • • • • (nn) - IXL a a 1 a a a 1 0 n n n n n n n n n n n n n n n n LD(nn). IY (nn +1) - IYH Load location (nn) with IY 1 1 1 1 1 a 1 20 4 • • • • • • (nn) +- IYL 0 0 000 1 0 n n n n n n n n n n n n n n n n LD R, A R - A Load R with ACC 1 1 0 0 9 2 • • • • • • a 0 0 1 LD r, (HL) r - (HL) Load Reg. r with location (HL) 0 r r r 1 o (8) 7 • • • • • • LD r, (IX + d) r - (IX + d) Load Reg. r with location (IX + d) 1 1 0 1 0 1 (8) 19 3 • • • • • • 0 1 r r r 1 1 0 d d d d d d d d LD r, (IY +d) r - (IY +d) Load Reg. r with location (IY + d) 1 1 1 0 1 (8) 19 3 • • • • • • 0 1 r r r 1 1 0 d d d d d d d d LD r, n r -n Load Reg. r with value n 0 a r r r 1 o (8) 7 2 • • • • • • n n n n n n n n LD, r, r ' r - r ' Load Reg. r with Reg. r' a r r r r' r' r' (F) 4 • • • • • • LD SP, HL SP - HL Load SP with H L o 0 6 • • • • • • LD SP, IX SP +- IX Load SP with IX 0 1 0 10 2 • • • • • • 1 0 0 LD SP, IY SP -I Y Load SP with IY 1 0 1 10 2 • • • • • • o 0 1 LDD (DE) - (HL) Load location (DE) with location (HL), 1 0 1 0 1 16 2 • • • 0 0 DE +- DE -1 decrement DE, HL and BC 0 a a a 0 HL +- HL -1, BC +- BC -1 LDDR (DE) - (HL) Load location (DE) with location (H L) 1 0 1 0 1 21 2 • • 0 • 0 a DE - DE - 1 0 1 o 0 0 HL - HL -1, BC +- BC -1 until Be = a

Instruction Set (cont) Opel8llon Coda No. of No. of Flags Mnemanle OpBl'llllon DBlCriptlon 7 6 5 .3 2 1 0 Clocks Byles C Z PlY S N H LDI (DE) <- (HL) Load location (DE ) wilh location 1 0 1 1 0 1 16 2 • • ;(T) • 0 0 DE <-DE + 1 (HL), increment DE , HL; decrement 0 o 0 0 0 0 (l HL <-HL + 1 BC BC <- BC - 1 LDIR (DE ) <- (HL) Load location (DE ) with location (HL); 1 0 1 1 0 1 21 if BC ,. 0 2 • • 0 • 0 0 DE <- DE + 1 increment DE, HL, 0 1 o 0 0 0 16 if BC = 0 HL <- HL + 1 decrement BC and repeat until BC = 0 BC <- BC -1 until BC = 0 NEG A - O -A Negate ACC (2's complement) 1 1 a 1 0 1 8 2 V 0 000 o 0 NOP No operation 00000000 4 • • • • • • OR r A <- AV r Logical 'OR' of Reg. ra nd ACC 0 0 r r r (8) 4 0 P 0 ; OR n A <- AV n Logical 'OR' of value n and ACC 0 0 7 2 • P 0 * n n n n n n n n OR (Hl) A <- AV (HL) Logical 'OR' of loc. (HL) and ACC 0 0 0 7 1 • * p * 0 OR (IX + d) A - (IX + d) Logical 'OR' of loc. (IX + d) /I ACC 1 1 a 1 1 1 a 1 19 3 • * p * 0 1 a 1 1 0 1 1 0 ddddd dd d OR (IY +d) A <- AV (IV + d) Logical 'OR' of loc. (IY + d) /I ACC 1 1 1 1 1 1 a 1 19 3 • P a 1 0 1 1 0 1 1 a d d d d d d d d OTDR (C ) -(H L) Load output port (C ) with contents of location 1 0 1 a 21 if B,. 0 2 • X X X B<- B- l (HL), decrement HL and B, repeat until B = 0 0 1 o 1 16 if B = e H L - H L - 1 until B = 0 OTIR (e) <- (HL) Load output port (C ) with location (HL), 0 0 21 if B ,. 0 2 • X X X B- B- l increment HL, decrement B. 16 if B = C HI - HL + 1 until B = 0 repeat until B = 0 OUT (C ), r (C ) <-r Load output port (C ) with Reg. r 1 0 1 0 1 (8) 12 2 • • • • • • 0 r r r o 0 1 OUT (n), A (n) <-A Load output port (n) with AC e 0 o 0 11 2 • • • • • • n n n n n n n n OUTD (e) <- (HL) Load output port (C ) with location (HL), 1 0 1 0 16 2 • 1(3) X X X B- B - l,HL<-HL-l increment HL and decrement B 0 0 0 1 OUTI (e) -(HL) Load output port (e) with location (HL), 1 0 1 1 0 16 2 • 1(3) X X X B - B- 1, HL - HL + 1 increment HL and decrement B 0 000 1 1:: C .j>. CD I r\\) I

.j>. I\\) I\\) Instruction Set (cont, Mnemunlc POP IX POP IV POP qq PUSH IX PUSH IV PUSH qq Operation IXH (SP + 1) IXl (SP) IVH ( SP +l) IVl (SP) qqH (SP + 1) qql (SP) (SP - 2) IXl (SP - 1) IXH (SP - 2) IVl (SP - 1) +- IVH (SP - 2) qql (SP - 1) q qH RES b,r Sb 0 RES b, (HL ) Sb 0, (HL ) RES b, (IX + d) Sb 0 (IX + d) RES b, (IV + d) Sb 0, (IV + d) RET PCl (SP) RET cc RETI RETN RL r RL (HL) PCH (SP + 1) If condition cc is false cont. else (PCl (SP) PCH (SP + 1) Oescrlption load IX with top of stack load IV with top of stack Load Reg. pair qq with top of stack load IX onto stack Load IV onto stack load Reg. pair qq onto stack Reset Bit b of Reg. r Reset Bit b of loe. (HL ) Reset Bit b of loc. (IX + d) Reset Bit b of loc. (IV + d) Return from subroutine Return from subroutine if condition cc is true Return from interrupt Return from non-maskable interrupt Rotate left through carry Reg. r Rotate left through carry loc. (HL) Operation Code 765 • 3 2 1 0 o 1 1 1 0 1 0 0 0 0 1 1 1 a o 0 a a q q a a 0 1 (G) o 1 1 1 0 0 1 1 a a q q 0 o o o o o 1 (G ) 1 0 0 1 0 1 (6) o b b b r r r (E) 10010 1 Obbb l 0 11 01 1 101 11 001 011 d d d d d d d d l Ob b b 1 10 11111 10 1 110 01 01 1 d d d d d d d d 10 bbbll0 o a 1 a a No. of No. of Cloclal Bylas 14 2 14 2 15 2 15 2 8 2 15 2 23 4 23 4 cc - a a a ( H ) 5 if CC false 11 if CC true o o 1 a o 0 1 0 1 o 0 0 o o o o 1 1 0 0 1 0 1 (6) 000 lOr r r 110 010 1 000101 a 14 2 14 2 2 2 4 2 c Flags Z PlY S

• • •
• • •
• • • N H
• •
• •
• • P p o 0 a 0 1:: a .... CD o

Instruction Set (cont) Operation Code No. 01 No. of Flags Mnemonic Opel1ltlon Description 7 & 5 432 1 0 CIocIlS Bylas C Z PlY S N H RL (IX + d) Rotate left through carry loc. (IX + d) 1 1 0 1 1 1 0 1 6 4 P 0 0 1 1 o 0 1 0 1 1 d d d d d d d d m r, (HL ) 000 1 0 1 1 0 RL (IV + d) (IX + d), Rotate left through carry loc. (IV + d) 1 1 1 1 1 1 0 1 6 4 P 0 0 (IV + d), A 1 1 o 0 1 0 1 1 d d d d d d d d 000 1 o 1 1 0 RLA Rotate left ACC through carry 000 o 1 1 4 1 * • • • 0 0 RLC (HL) Rotate location (HL ) left circular 1 1 o 0 1 0 1 15 2 * P 0 0 o 0 0 0 0 1 0 RLC (IX + d) Rotate location (IX + d) left circular 1 1 o 1 1 1 0 1 23 4 P 0 0 1 1 o 0 1 o 1 1 d d d d d d d d 00000 1 1 0 RLC (IV + d) Rotate location (IV + d) left circular 1 1 1 1 1 1 o 1 23 4 * P 0 0 1 1 o 0 1 0 1 1 m = r, (HL), d d d d d d d d (IX + d), (IV + d), A 000001 1 0 RLC r Rotate Reg. r left circular 1 1 o 0 1 0 1 (8) 8 2 * P 0 0 o 0 000 r r r RLCA Rotate left circular ACC 00000 1 4 t • • • 0 0 A 17 413 7ol (HL ) Rotate digit left and right between ACC and 1 0 0 18 2 • P 0 0 RLD location (H L) 0 0 1 RR r Rotate right through carry Reg. r 1 1 o 0 0 1 (8) 2 2 P 0 0 000 1 r r r RR (Hl) Rotate right through carry loc. (Hl) 1 1 o 0 0 1 4 2 P 0 0 000 1 1 0 RR (IX + d) Rotate right through carry loc. (IX + d) 1 1 0 1 1 1 o 1 6 4 t P 0 0 1 1 o 0 1 0 1 1 d d d d d d d d 000 1 1 1 1 0 RR (IV + d) Rotate right through carry loc. (IV + d) 1 1 1 1 1 1 0 1 6 4 P 0 0 1 1 o 0 1 0 1 1 m = r, (HL), d d d d d d d d 1:: (IX + d), (IV + d), A 000 1 1 1 1 0 " RRA Rotate right ACC through carry 000 1 1 4 1 • • • 0 0 a .... , CD I\\J o 0 0 0 r r r 0 (,) II

.j>. Instruction Set (cont) 1:: I I\\) ,. .j>. Operation Code No. of No. of Flags C Mnemonic Operation OescrlpUon 7 6 5 .32 1 0 Clocks Bytes C Z P/V S N H ... RRC (HL) Rotate lac. (HL) right circular 1 1 a a a 1 4 2 P 0 0 CD 000 0 1 0 0 RRC (IX + d) Rotate lac (IX + d) right circular 1 1 0 1 1 1 0 1 6 4 P 0 0 1 1 o 0 1 o 1 1 d d d d d d d d o 0 0 0 1 1 1 0 RRC (IY + d) m : r, (HL), Rotate lac. (IY + d) right circular 1 1 1 1 1 1 o 1 6 4 P 0 0 (IX + d), (IY + d), A 1 1 o 0 1 0 1 1 d d d d d d d d o 0 0 0 1 1 1 0 RRCA Rotate right circular ACC 000 0 1 4 • • • 0 0 A 1 7 4 1 3 cl401(HL) Rotate digit right and then left between 1 0 1 0 18 2 • P 0 0 ACC and location (HL) 0 o 0 1 RRD RST, (SP - 1) - PCH Restart to location T 1 1 t t t 1 1 1 11 • • • • • • (SP - 2) - PCl PCH - 0, PCl - T SBC A, r A - A - r CY Subtr act Reg. r from ACC w/carry o 0 r r r (8) 4 V SBC A, n A - A - n - CY Su btract value n from ACC with carry 0 0 7 2 V n n n n n n n n SBC A, (HL) A - A - (HL) - CY Sub. loc. (HL) from ACC w/carry o 0 0 7 1 V SBC A, (IX + d) A - A - (IX + d) - CY Su btract lac. (IX + d) from ACC with carry 1 1 0 1 1 1 0 1 19 3 V 1 o 0 1 1 1 1 0 d d d d d d d d SBC A, (IY + d) A - A - (IY + d) - CY Su btract lac. (lY + d) from ACC with carry 1 1 1 1 1 1 0 1 19 3 V 1 o 0 1 1 1 1 0 d d d d d d d d SBC HL, 55 HL -HL - 55 - CY Subtract Reg. pair 55 from H L with carry 1 o 1 1 0 1 (AI 15 2 V X 0 5 5 o 0 1 0 SCF CY - 1 Set carry flag (C : 1) o 0 o 1 1 1 4 • • • 0 0 SET b, (HL) (HL)b - 1 Set Bit b of location (HL) 1 o 0 1 0 1 1 (E) 15 2 • • • • • • 1 b b b 1 1 0 SET b, (IX + d) (IX + d)b - 1 Set Bit b of location (IX + d) 1 1 0 1 1 1 0 1 (El 23 4 • • • • • • 1 1 o 0 1 o 1 1 d d d d d d d d 1 1 b b b 1 1 0 n

Instruction Set (cont) Operallon Code No. 01 No. 01 Flags Mnemonic Operation Description 7 6 5 3 2 1 0 Clocks Bytes C Z PlY S N H SET b, (IV + d) (IV + d)b - 1 Set Bit b of location (IV + d) 1 1 1 1 1 1 o 1 ( E) 23 4 • • • • • • 1 1 o 0 1 o 1 1 n d d d d d d d d 1 1 b b b 1 1 0 SET b, r rb - 1 Set Bit b of Reg. r o 0 1 0 1 1 (S) 8 2 • • • • • • b b b r r r SLA r Shill Reg. r lell arithmetic 1 1 o 0 1 0 1 (S) 8 2 P 0 0 o 0 1 o 0 r r r SLA (HL) O Shill lac. (HL) lell arithmetic 1 1 o 0 1 0 1 15 2 P 0 0 o 0 1 o 0 1 0 SLA (IX + d) m = r, (HL). (IX + d), (IV + d) Shill lac. (IX + d) lell arithmetic 1 1 0 1 1 1 0 1 23 4 P 0 0 1 1 o 0 1 o 1 1 d d d d d d d d o 0 1 o 0 1 1 0 SLA (IV + d) Shill lac. (IV + d) lell arithmetic 1 1 1 1 1 1 0 1 23 4 P 0 0 1 1 o 0 1 0 1 1 d d d d d d d d o 0 1 00 1 1 0 SRA r Shill Reg. r right arithmetic 1 1 o 0 0 1 (S) 8 2 P 0 0 o 0 1 0 r r r SRA (HL) Shill loc. (HL) right arithmetic 1 1 o 0 0 1 1 15 2 P 0 0 o 0 1 0 1 1 0 SRA (IX + d) m = r, (HL), (IX + d), (IV + d) Shill lac. (IX + d) right arithmetic 1 1 0 1 1 1 0 23 4 P 0 0 1 1 o 0 1 0 1 d d d d d d d d o 0 1 0 1 1 1 0 SRA (IV + d) Shill loc. (IV + d) right arithmetic 1 1 1 1 1 1 0 1 23 4 P 0 0 1 1 o 0 1 0 1 1 d d d d d d d d o 0 1 0 1 1 1 0 SRL r Shill Reg. r right logical 1 1 o 0 1 0 1 1 (S) 8 2 P 0 0 o 0 1 1 1 r r r SRL (HL) O Shill loc. (HL) right logical 1 1 o 0 1 0 1 15 2 P 0 0 o 0 1 1 1 1 0 SRL (IX + d) m = r, (HL), (IX + d), (IV + d) Shill loc. (IX + d) right logical 1 1 0 1 1 1 0 1 23 4 P 0 0 1 1 o 0 1 0 1 1 1;: d d d d d d d d " o 0 1 1 1 1 1 0 C -.. .I>- CO , I\\) 0 (J1 II

..,. I I\\) O'l Instruction Set (cont) Mnemonic Operation SRL (IV + d) SUB r A .... A - r SUB n A"" A - n SUB (HL) A"" A - (HL) SUB (IX + d) A"" A - (IX + d) SUB (IV + d) A"" A - (IV + d) XOR r A .... AV r XOR n A .... AV n XOR (HL) A .... AV (HL) XOR (IX + d) A .... A V (IX + d) XOR (IY + d) A"" AV (IY + d) Note: (1) P IV flag is a if B ; 0, else P IV ; 1 (2) Z; 1 if A ; (HL), else Z ; a (3) If B ; 0, Z flag set, else reset Shift loc. (IV + d) right logical Su btract Reg. r from ACC Subtract value n from ACC Su btract loc. (HL) from ACC Subtract loc. (IX + d) from ACC Su btract loc. (IV + d) from ACC Exclusive 'OR' Reg. ra nd ACC Exclusive 'OR' value n and ACC Exclusive 'OR' loc. (HL) and ACC Operation Code 7 6 5 4 3 2 1 0 11111 101 11 00101 1 d d d d d d d d 001 11110 1 a a lOr r r (B) a a a n n n n n n n n 001 01 10 11 01 11 01 100 1 a 1 1 a d d d d d d d d 1111 11 01 10 01 01 10 d d d d d d d d a a r r r (B) a a n n n n n n n n o a a No. 01 No. 01 Flags Cloclls Bytes C Z P/V 5 N H 23 4 P a a 4 V 7 2 v 7 v 19 3 v 19 3 v 4 P 7 2 P 7 P Exclusive 'OR' loc. (IX + d) and ACC 11 01 1 101 10 101 110 d d d d d d d d 19 3 P Exclusive 'OR' loc. (IY + d) and ACC 111111 01 10 10 1 110 d d d d d d d d 19 3 p A B Reg 55 Reg r Be 00 A lII DE 01 B 000 HL 10 C OOl SP 11 DO lO E 011 H 10 0 L 101 C Reg pp BC 00 DE 01 IX 10 SP 11 o Reg rr BC 00 a DE 01 IV 10 2 SP 11 3 E F G H BH b Reg r, r ' Reg qq CC Condition

000 A lII

001 B 000

010 C OOl

011 DO lO

100 E 011

101 H 100

110 L 101

111 111 M Sign negative S Al II 1:: C CD o