PD780701Y

PD780701Y_15 RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 2.1 Port Pins
• 2.2 Non-port Pins
• 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
• 4.1 Ports
• 4.2 Clock Generator
• 4.3 Timer/Counter
• 4.4 Clock Output/Buzzer Output Control Circuit
• 4.5 A/D Converter
• 4.6 Serial Interfaces
• 4.7 DCAN Controller (µµµµPD780701Y only)
• 4.8 IEBus Controller (µµµµPD780702Y only)

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µµµµPD780701Y, 780702Y 8-BIT SINGLE-CHIP MICROCONTROLLER Document No. U13920EJ1V0PM00 (1st edition) Date Published March 1999 N CP(K) Printed in Japan PRELIMINARY PRODUCT INFORMATION

DESCRIPTION

The µPD780701Y and 780702Y are the µPD780701Y Subseries products of the 78K/0 Series. These microcontrollers have DCAN controller (µPD780701Y), IEBus TM controller (µPD780702Y), A/D converter, timer, serial interface, interrupt control, and various other peripheral hardware. The µPD78F0701Y which can operate in the same power supply voltage as the mask ROM version, and various development tools are under development. Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before designing. µµµµPD780701Y Subseries User’s Manual: U13781E 78K/0 Series User’s Manual Instructions: U12326E

FEATURES

• DCAN (Direct Storage Controller Area Network) controller (incorporated in µPD780701Y)
• IEBus (Inter Equipment Bus TM ) controller (incorporated in µPD780702Y)
• Internal ROM: 60 Kbytes
• Internal high-speed RAM: 1024 bytes
• Internal expansion RAM: 2048 bytes
• Buffer RAM for DCAN: 288 bytes (µPD780701Y only)
• Minimum instruction execution time can be changed from high-speed (0.32 µs) to low-speed (5.09 µs)
• I/O ports: 67
• 8-bit resolution A/D converter: 16 channels
• Serial interface: 4 channels
• Timer: 7 channels
• Power supply voltage: VDD = 3.5 to 5.5 V

APPLICATIONS

Car audio systems, etc.

ORDERING INFORMATION

µPD780701YGC- ××× -8BT 80-pin plastic QFP (14 × 14 mm) µPD780702YGC- ××× -8BT 80-pin plastic QFP (14 × 14 mm) Remark ××× indicates ROM code suffix. © 1999 The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 78K/0 SERIES LINEUP The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names. PD780955 PD780973 PD780833Y PD78044F PD78044H PD780232 80-pin PD78083 PD780034A PD780024A PD780024AY PD78014H PD78018F PD780308 PD78064B PD78064 PD780308Y PD78064Y 64-pin 64-pin 64-pin 64-pin 42/44-pin 100-pin 100-pin 80-pin 100-pin 100-pin 100-pin 64-pin PD780065 80-pin PD780988 PD780948 PD78098B PD780701Y 100-pin 80-pin 80-pin 80-pin 100-pin 80-pin 80-pin PD78018FY PD780034AY PD780208 PD780228 PD78058F PD78054 80-pin 80-pin 80-pin 80-pin 100-pin 100-pin 100-pin 100-pin PD78054Y PD78058FY PD780058Y PD780018AY PD78070AY PD78078Y PD780058 PD78078 PD78070A PD78075B PD780958 µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ µ Ultra low power consumption, on-chip UART Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 78K/0 Series Inverter control FIPTM drive LCD drive Bus interface supported Meter control EMI-noise reduced version of the PD78078 PD78054 with timer and enhanced external interface function ROM-less version of the PD78078 PD78078Y with enhanced serial I/O, and only selected functions are provided PD78054 with enhanced serial I/O, EMI-noise reduced version EMI-noise reduced version of the PD78054 PD78018F with UART, D/A converter, and enhanced I/O PD780024A with expanded RAM PD780024A with enhanced A/D converter PD78018F with enhanced serial I/O EMI-noise reduced version of the PD78018F Basic subseries for control On-chip UART and capable of low-voltage (1.8 V) operation On-chip inverter control circuit and UART, EMI-noise reduced version PD78044F with enhanced I/O and FIP C/D, Display output total: 53 PD78044H with enhanced I/O and FIP C/D, Display output total: 48 For panel control, on-chip FIP C/D, Display output total: 53 PD78044F with N-ch open-drain input/output, Display output total: 34 Basic subseries for driving FIP, Display output total: 34 PD78064 with enhanced SIO and expanded ROM and RAM EMI-noise reduced version of the PD78064 Basic subseries for driving LCDs, on-chip UART On-chip DCAN controller PD78054 with IEBusTM controller, EMI-noise reduced version On-chip DCAN/IEBus controller On-chip J1850 (CLASS2) controller For controlling industrial meters On-chip controller/driver for driving automobile meters

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 OVERVIEW OF FUNCTIONS Part Number Item µPD780701Y µPD780702Y ROM 60 Kbytes High-speed RAM 1024 bytes Expansion RAM 2048 bytes Internal memory Buffer RAM for DCAN 288 bytes None Minimum instruction execution time On-chip minimum instruction execution time variable function General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Instruction set • 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc. I/O ports Total: 67
• CMOS I/O: 56
• TTL input/CMOS output: 8
• N-ch open-drain I/O: 3 A/D converter • 8-bit resolution × 16 channels
• Power fail detection function Serial interface • 3-wire serial I/O mode: 2 channels
• UART mode: 1 channel
• I C bus mode: 1 channel Timer • 16-bit timer/event counter: 2 channels
• 8-bit timer/event counter: 3 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel Timer output 5 (8-bit PWM output capable: 3) (@ 6.29-MHz operation with system clock) Bus controller DCAN controller IEBus controller Maskable Internal: 20, External: 8 Internal: 19, External: 8 Non-maskable Internal: 1 Vectored interrupt sources Software 1 Power supply voltage V DD = 3.5 to 5.5 V Operating ambient temperature T A = −40 to +85°C Package 80-pin plastic QFP (14 × 14 mm)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 PIN CONFIGURATION (Top View) (1) µµµµPD780701Y Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1 . 2. Connect the AVSS pin to VSS0 . 3. Connect the AVREF pin to VDD0 . Remark When the µPD780701Y and 780702Y are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to V DD0 and V DD1 individually and connecting VSS0 and V SS1 to different ground lines, is recommended. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P90/ANI8 P91/ANI9 P92/ANI10 P93/ANI11 P94/ANI12 P95/ANI13 P96/ANI14 P97/ANI15 P70/TI52/TO52 P71/SDA0 P72/SCL0 P73/TO01 P74/TI001 P75/TI011 P76/TI50/TO50 P77/TI51/TO51 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P66 P65 P64 P27/PCL P26/ASCK0 P25/TxD0 P24/RxD0 P23/BUZ P07/INTP7 P06/INTP6 P05/INTP5 P04/INTP4 P22/SCK31 P21/SO31 P20/SI31 P57 P56 P55 P54 P53 AV SS P87/ANI7 P86/ANI6 P85/ANI5 P84/ANI4 P83/ANI3 P82/ANI2 P81/ANI1 P80/ANI0 AV REF VSS1 VDD1 CPUREG IC RESET CTXD CRXD P67 P40 P41 P42 P43 P44 P45 P46 P47 P30/SI30 P31/SO30 P32/SCK30 V DD0 VSS0 P33 P34/TO00 P35/TI000 P36/TI010 P50 P51 P52

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (2) µµµµPD780702Y Cautions 1. Connect the IC (Internally Connected) pin directly to VSS0 or VSS1 . 2. Connect the AVSS pin to VSS0 . 3. Connect the AVREF pin to VDD0 . Remark When the µPD780701Y and 780702Y are used in applications where the noise generated inside the microcontroller needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to V DD0 and V DD1 individually and connecting VSS0 and V SS1 to different ground lines, is recommended. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P90/ANI8 P91/ANI9 P92/ANI10 P93/ANI11 P94/ANI12 P95/ANI13 P96/ANI14 P97/ANI15 P70/TI52/TO52 P71/SDA0 P72/SCL0 P73/TO01 P74/TI001 P75/TI011 P76/TI50/TO50 P77/TI51/TO51 P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P66 P65 P64 P27/PCL P26/ASCK0 P25/TxD0 P24/RxD0 P23/BUZ P07/INTP7 P06/INTP6 P05/INTP5 P04/INTP4 P22/SCK31 P21/SO31 P20/SI31 P57 P56 P55 P54 P53 AV SS P87/ANI7 P86/ANI6 P85/ANI5 P84/ANI4 P83/ANI3 P82/ANI2 P81/ANI1 P80/ANI0 AV REF VSS1 VDD1 CPUREG IC RESET ITX0 IRX0 P67 P40 P41 P42 P43 P44 P45 P46 P47 P30/SI30 P31/SO30 P32/SCK30 V DD0 VSS0 P33 P34/TO00 P35/TI000 P36/TI010 P50 P51 P52

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 ANI0 to ANI15: Analog Input P80 to P87: Port 8 ASCK0: Asynchronous Serial Clock P90 to P97: Port 9 AV REF : Analog Reference Voltage PCL: Programmable Clock AV SS : Analog Ground RESET: Reset BUZ: Buzzer Output RxD0: Receive Data (for UART0) CPUREG: Regulator for CPU Power Supply SCK30, SCK31: Serial Clock (for SIO30, 31) CRXD: CAN Receive Data SCL0: Serial Clock (for IIC0) CTXD: CAN Transmit Data SDA0: Serial Data IC: Internally Connected SI30, SI31: Serial Input INTP0 to INTP7: Interrupt for Peripherals SO30, SO31: Serial Output IRX0: IEBus Receive Data TI000, TI010, TI001, ITX0: IEBus Transmit Data TI011, TI50, TI51, P00 to P07: Port 0 TI52: Timer Input P20 to P27: Port 2 TO00, TO01, TO50, P30 to P36: Port 3 TO51, TO52: Timer Output P40 to P47: Port 4 TxD0: Transmit Data (for UART0) P50 to P57: Port 5 V DD0 , VDD1 : Power Supply P64 to P67: Port 6 V SS0 , VSS1 : Ground P70 to P77: Port 7 X1, X2: Crystal

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 BLOCK DIAGRAM (1) µµµµPD780701Y 16-bit TIMER/ EVENT COUNTER 00 (TM00) TO00/P34 TI000/P35 TI010/P36 SERIAL INTERFACE 30 (SIO30) SI30/P30 SO30/P31 SCK30/P32 SERIAL INTERFACE 31 (SIO31) SI31/P20 SO31/P21 SCK31/P22 RxD0/P24 TxD0/P25 ASCK0/P26 INTP0/P00 to INTP7/P07 I2C BUS (IIC0) UART (UART0) INTERRUPT CONTROL (INT29) SCL0/P72 SDA0/P71 16-bit TIMER/ EVENT COUNTER 01 (TM01) TO01/P73 TI001/P74 TI011/P75 8-bit TIMER/ EVENT COUNTER 50 (TM50) TI50/TO50/P76 TI51/TO51/P77 TI52/TO52/P70 8-bit TIMER/ EVENT COUNTER 51 (TM51) 8-bit TIMER/ EVENT COUNTER 52 (TM52) WATCH TIMER (WTN0) WATCHDOG TIMER (WDT) PCL/P27 BUZ/P23 CLOCK OUTPUT CONTROL BUZZER OUTPUT 78K/0 CPU CORE INTERNAL HIGH-SPEED RAM

1024 Bytes

2048 Bytes

60 KBytes

(AD3) (ADCTL3) DCAN RAM

288 Bytes

ANI7/P87, ANI8/P90 to ANI15/P97 AV SS AV REF DCAN CONTROLLER (DCAN) CTXD CRXD SYSTEM CONTROL VOLTAGE REGULATOR RESET VDD1 VDD0 VSS0 IC CPUREG VSS1

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (2) µµµµPD780702Y 16-bit TIMER/ EVENT COUNTER 00 (TM00) TO00/P34 TI000/P35 TI010/P36 SERIAL INTERFACE 30 (SIO30) SI30/P30 SO30/P31 SCK30/P32 SERIAL INTERFACE 31 (SIO31) SI31/P20 SO31/P21 SCK31/P22 RxD0/P24 TxD0/P25 ASCK0/P26 INTP0/P00 to INTP7/P07 I2C BUS (IIC0) UART (UART0) INTERRUPT CONTROL (INT29) SCL0/P72 SDA0/P71 16-bit TIMER/ EVENT COUNTER 01 (TM01) TO01/P73 TI001/P74 TI011/P75 8-bit TIMER/ EVENT COUNTER 50 (TM50) TI50/TO50/P76 TI51/TO51/P77 TI52/TO52/P70 8-bit TIMER/ EVENT COUNTER 51 (TM51) 8-bit TIMER/ EVENT COUNTER 52 (TM52) WATCH TIMER (WTN0) WATCHDOG TIMER (WDT) PCL/P27 BUZ/P23 CLOCK OUTPUT CONTROL BUZZER OUTPUT 78K/0 CPU CORE INTERNAL HIGH-SPEED RAM (AD3) (ADCTL3) IEBus CONTROLLER (IEBUS0) P90 to P978 ANI0/P80 to ANI7/P87, ANI8/P90 to ANI15/P97 AV SS AV REF ITX0 IRX0 SYSTEM CONTROL VOLTAGE REGULATOR RESET VDD1 VDD0 VSS0 IC CPUREG VSS1

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 1. DIFFERENCES BETWEEN µµµµPD780701Y AND µµµµPD780702Y The essential difference between these two products is the on-chip bus controller. The main differences between the µPD780701Y and µPD780702Y are outlined in Table 1-1. Table 1-1. Differences between µµµµPD780701Y and µµµµPD780702Y Part Number Item µPD780701Y µPD780702Y On-chip bus controller DCAN controller IEBus controller Buffer RAM for DCAN 288 bytes None RX Pin (Pin No.62) CRXD IRX0 TX Pin (Pin No.63) CTXD ITX0 Internal maskable interrupt Total: 20 sources (3 sources via the DCAN controller) Total: 19 sources (2 sources via the IEBus controller)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 2. PIN FUNCTIONS

2.1 Port Pins (1/2)

Pin Name I/O Function After Reset Alternate Function P00 to P07 Input/output Port 0. 8-bit input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Input INTP0 to INTP7 P20 SI31 P21 SO31 P22 SCK31 P23 BUZ P24 RxD0 P25 TxD0 P26 ASCK0 P27 Input/output Port 2. 8-bit input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Input PCL P30 SI30 P31 SO30 P32 An on-chip pull-up resistor can be specified by means of software. SCK30 P33 N-ch open-drain input/output port (15-V withstand voltage). LEDs can be driven directly. P34 TO00 P35 TI000 P36 Input/output Port 3. 7-bit input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Input TI010 P40 to P47 Input/output Port 4. 8-bit input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Interrupt request flag KRIF is set to 1 by falling edge detection. Input − P50 to P57 Input/output Port 5. 8-bit input/output port. TTL level input/CMOS output. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Input − P60 to P67 Input/output Port 6. 4-bit input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Input −

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

2.1 Port Pins (2/2)

Pin Name I/O Function After Reset Alternate Function P70 TI52/TO52An on-chip pull-up resistor can be specified by means of software. P71 SDA0 P72 N-ch open-drain input/output port (5-V withstand voltage). SCL0 P73 TO01 P74 TI001 P75 TI011 P76 TI50/TO50 P77 Input/output Port 7. 8-bit input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Input TI51/TO51 P80 to P87 Input/output Port 8. 8-bit input/output port. Input/output can be specified in 1-bit units. Input ANI0 to ANI7 P90 to P97 Input/output Port 9. 8-bit input/output port. Input/output can be specified in 1-bit units. Input ANI8 to ANI15

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

2.2 Non-port Pins (1/2)

Pin Name I/O Function After Reset Alternate Function INTP0 to INTP7 Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified Input P00 to P07 SI30 P30 SI31 Input Serial interface serial data input Input P20 SO30 P31 SO31 Output Serial interface serial data output Input P21 SDA0 I/O Serial interface serial data input/output Input P71 SCK30 P32 SCK31 P22 SCL0 I/O Serial interface serial clock input/output Input P72 RxD0 Input Serial data input for asynchronous serial interface Input P24 TxD0 Output Serial data output for asynchronous serial interface Input P25 ASCK0 Input Serial clock input for asynchronous serial interface Input P26 CRXD Note 1 Input Data input of DCAN controller (DCAN) Input − CTXD Note 1 Output Data output of DCAN controller (DCAN) Output − IRX0 Note 2 Input Data input of IEBus controller (IEBUS0) Input − ITX0 Note 2 Output Data output of IEBus controller (IEBUS0) Output − TI000 External count clock input to 16-bit timer (TM00) P35 TI010 External count clock input to 16-bit timer (TM00) P36 TI001 External count clock input to 16-bit timer (TM01) P74 TI011 External count clock input to 16-bit timer (TM01) P75 TI50 External count clock input to 8-bit timer (TM50) P76/TO50 TI51 External count clock input to 8-bit timer (TM51) P77/TO51 TI52 Input External count clock input to 8-bit timer (TM52) Input P70/TO52 TO00 16-bit timer (TM00) output P34 TO01 16-bit timer (TM01) output P73 TO50 8-bit timer (TM50) output P76/TI50 TO51 8-bit timer (TM51) output P77/TI51 TO52 Output 8-bit timer (TM52) output Input P70/TI52 PCL Output Clock output Input P27 BUZ Output Buzzer output Input P23 ANI0 to ANI7 P80 to P87 ANI8 to ANI15 Input A/D converter (AD3) analog input Input P90 to P97 AV REF Input A/D converter (AD3) reference voltage and analog power supply−− AV SS − A/D converter (AD3) ground potential −− X1 Input −− X2 − Connecting crystal resonator for system clock oscillation Notes 1. µPD780701Y only 2. µPD780702Y only

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

2.2 Non-port Pins (2/2)

Pin Name I/O Function After Reset Alternate Function RESET Input System reset input Input − CPUREG − Regulator for CPU power supply. Connect to VSS0 or VSS1 via a 0.1-µF capacitor. VDD0 − Positive power supply for ports −− VDD1 − Positive power supply (except ports and analog section) −− VSS0 − Ground potential for ports −− VSS1 − Ground potential (except ports and analog section) −− IC − Internally connected. Connect directly to VSS0 or VSS1 . −−

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, refer to Figure 2-1. Table 2-1. Types of Pin Input/Output Circuits Pin Name Input/Output Circuit Type I/O Recommended Connection of Unused Pins P00/INTP0 to P07/INTP7 Independently connect to V SS0 via a resistor. P20/SI31 8-C P21/SO31 5-H P22/SCK31 8-C P23/BUZ 5-H P24/RxD0 8-C P25/TxD0 5-H P26/ASCK0 8-C P27/PCL 5-H P30/SI30 8-C P31/SO30 5-H P32/SCK30 8-C Independently connect to VDD0 or VSS0 via a resistor. P33 13-P Connect to V DD0 via a resistor. P34/TO00 5-H P35/TI000 P36/TI010 8-C Independently connect to VDD0 or VSS0 via a resistor. P40 to P47 5-H Independently connect to V DD0 via a resistor. P50 to P57 5-T P64 to P67 P70/TI52/TO52 5-H Independently connect to VDD0 or VSS0 via a resistor. P71/SDA0 P72/SCL0 13-R Independently connect to V DD0 via a resistor. P73/TO01 5-H P74/TI001 P75/TI011 P76/TI50/TO50 P77/TI51/TO51 8-C P80/ANI0 to P87/ANI7 P90/ANI8 to P97/ANI15 11-E Input/output Independently connect to VDD0 or VSS0 via a resistor. CRXD Note 1 2 Input Connect to V DD0 or VSS0 via a resistor. CTXD Note 1 3-B Output Leave open. 2 Input Connect to V DD0 or VSS0 via a resistor. 3-B Output Leave open. 2 − AV REF Input Connect to VDD0 . AV SS Connect to VSS0 . IC Connect directly to VSS0 or VSS1 . Notes 1. µPD780701Y only 2. µPD780702Y only RESET IRX0 Note 2 ITX0 Note 2

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 2-1. Pin Input/Output Circuits IN pullup enable VDD0 P-ch P-ch VDD0 N-ch VSS0 IN/OUT data output disable P-ch VDD0 N-ch N-ch VSS0 IN/OUT data output disable P-ch AV SS VREF input enable P-ch VDD0 N-ch VSS0 OUTdata pullup enable VDD0 P-ch P-ch VDD0 N-ch VSS0 IN/OUT data output disable input enable N-ch VSS0 IN/OUT output data output disable input enable N-ch VSS0 IN/OUT output data output disable pullup enable VDD0 P-ch P-ch VDD0 N-ch VSS0 IN/OUT data output disable input enable Type 13-R Type 2 Schmitt-triggered input with hysteresis characteristics Type 3-B Type 5-H Type 5-T TTL input Type 8-C Type 11-E Comparator (threshold voltage) Type 13-P

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 4. PERIPHERAL HARDWARE FUNCTION FEATURES

4.1 Ports

The following three types of I/O ports are available.

• CMOS input/output (Ports 0, 2 to 4, 7 to 9 (except P33, P71, P72)): 56
• TTL input/CMOS output (Port 5): 8
• N-ch open-drain input/output (P33, P71, P72): 3 Total: 67 Table 4-1. Port Functions Port Name Pin Name Function Port 0 P00 to P07 Input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Port 2 P20 to P27 Input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. P30 to P32, P34 to P36 Input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Port 3 P33 N-ch open-drain input/output port. Input/output can be specified in 1-bit units. LEDs can be driven directly. Port 4 P40 to P47 Input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Interrupt request flag KRIF is set to 1 by falling edge detection. Port 5 P50 to P57 TTL input/CMOS output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Port 6 P64 to P67 Input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. P70, P73 to P77 Input/output port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software. Port 7 P71, P72 N-ch open-drain input/output port. Input/output can be specified in 1-bit units. Port 8 P80 to P87 Input/output port. Input/output can be specified in 1-bit units. Port 9 P90 to P97 Input/output port. Input/output can be specified in 1-bit units.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

4.2 Clock Generator

A system clock generator is incorporated. The minimum instruction execution time can be changed. Figure 4-1. Clock Generator Block Diagram STOP fX fX fX fX fX System clock oscillator Prescaler Prescaler Selector Standby control circuit Clock to peripheral hardware CPU clock CPU )

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

4.3 Timer/Counter

Seven timer/counter channels are incorporated.

• 16-bit timer/event counter: 2 channels
• 8-bit timer/event counter: 3 channels
• Watch timer: 1 channel
• Watchdog timer: 1 channel Table 4-2. Operations of Timer/Event Counters 16-bit timer/event counters TM00, TM01 8-bit timer/event counters TM50, TM51, TM52 Watch timer Watchdog timer Interval timer 2 channels 3 channels 1 channel Note 1 1 channel Note 2 Operation mode External event counter 2 channels 3 channels −− Timer output 2 outputs 3 outputs −− PWM output − 3 outputs −− PPG output 2 outputs −− − Pulse width measurement 4 inputs −− − Square wave output 2 outputs 3 outputs −− One-shot pulse output 2 outputs −− − Function Interrupt source 4 3 2 1 Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or the interval timer function.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 4-2. Block Diagram of 16-Bit Timer/Event Counter TM00 TI010/P36 TI000/P35 TO00/P34 INTTM010 fX/2 fX/22 fX/26 fX/23 INTTM000 Internal bus Internal bus Noise elimination circuit Noise elimination circuit Noise elimination circuit Selector Selector Selector Selector 16-bit capture/compare register 000 (CR000) Match Match 16-bit timer/counter 00 (TM00) Clear Output control circuit 16-bit capture/compare register 010 (CR010)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 4-3. Block Diagram of 16-Bit Timer/Event Counter TM01 TI011/P75 TI001/P74 TO01/P73 INTTM011 fX/2 fX/22 fX/26 fX/23 INTTM001 16-bit capture/compare register 011 (CR011) Internal bus Internal bus Noise elimination circuit Noise elimination circuit Noise elimination circuit Selector Selector Selector Selector 16-bit capture/compare register 001 (CR001) Match Match 16-bit timer/counter 01 (TM01) Clear Output control circuit

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 4-8. Watchdog Timer Block Diagram OSTS2 OSTS1OSTS0 WDCS2 WDCS1 WDCS0 WDTM4RUN WDTM3 RUN fX/28 INTWDT RESET Internal bus Clock input control circuit Frequency divider Divided clock select circuit Output control circuit Division mode select circuit WDT mode signal Oscillation stabilization time select register (OSTS) Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

4.4 Clock Output/Buzzer Output Control Circuit

A clock output/buzzer output control circuit (CKU) is incorporated. Clocks with the following frequencies can be output as clock output. system clock) Clocks with the following frequencies can be output as buzzer output.

• 768 Hz/1.54 kHz/3.07 kHz/6.14 kHz (@ 6.29-MHz operation with system clock) Figure 4-9. Block Diagram of Clock Output/Buzzer Output Control Circuit CKU CLOE BCS0, BCS1 BZOE fX/210 to fX/213 fX to fX/27 fX PCL/P27 BUZ/P23 BZOE BCS1 BCS0 CLOE CCS2 CCS1 CCS0 Internal bus Prescaler Selector Selector Clock control circuit Clock output select register (CKS)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

4.5 A/D Converter

An A/D converter consisting of sixteen 8-bit resolution channels is incorporated. The A/D converter has the following two functions.

• 8-bit resolution A/D conversion
• Power fail detection function Figure 4-10. A/D Converter Block Diagram Figure 4-11. Block Diagram of Power Fail Detection Function ANI0/P80 ANI1/P81 ANI2/P82 ANI3/P83 ANI4/P84 ANI5/P85 ANI6/P86 ANI7/P87 ANI8/P90 ANI9/P91 ANI10/P92 ANI11/P93 ANI12/P94 ANI13/P95 ANI14/P96 ANI15/P97 INTAD AV SS AV REF Internal bus Selector Sample & hold circuit Voltage comparator Series resistor string Tap selector (also used with analog power supply) Successive approximation register (SAR) Control circuit A/D conversion result register (ADCR3) ANI0/P80 ANI1/P81 ANI2/P82 ANI3/P83 ANI4/P84 ANI5/P85 ANI6/P86 ANI7/P87 ANI8/P90 ANI9/P91 ANI10/P92 ANI11/P93 ANI12/P94 ANI13/P95 ANI14/P96 ANI15/P97 INTAD Internal bus Multiplexer A/D converter Comparator Selector Power fail compare threshold register 3 (PFT3)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

4.6 S erial Interfaces

Four serial interface channels are incorporated.

• Serial interface UART0
• Serial interfaces SIO30, SIO31
• Serial interface IIC0 (1) Serial interface UART0 The serial interface UART0 has the asynchronous serial interface (UART) mode.
• ••• Asynchronous serial interface (UART) mode This mode enables full-duplex operation wherein one byte of data is transmitted and received after the start bit. The on-chip dedicated UART baud rate generator enables communication using a wide range of selectable baud rates. In addition, a baud rate can also be defined by dividing the clock input to the ASCK0 pin. The dedicated UART baud rate generator can also be used to generate a MIDI-standard baud rate (31.25 kbps). Figure 4-12. Block Diagram of Serial Interface UART0 RXB0 RxD0/P24 TxD0/P25 PE0 FE0 OVE0 ASIS0 TXS0RX0 INTSER0 INTST0 fX/22 to fX/28 P26/ASCK0 TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0 ASIM0 INTSR0 Baud rate generator Internal bus Receive buffer register 0 Receive shift register 0 Transmit shift register 0 Receive control parity check Transmit control parity addition

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (3) Serial interface IIC0 The serial interface IIC0 has the I C (Inter IC) bus mode (multimaster supported).

• ••• I C bus mode (multimaster supported) This is an 8-bit data transfer mode between multiple devices using two lines: serial clock line (SCL0) and serial data bus line (SDA0). This mode complies with the I C bus format, and can output “start condition”, “data”, and “stop condition” during transmission via the serial data bus. These data are automatically detected by hardware during reception. Since the SCL0 and SDA0 are open-drain outputs in IIC0, pull-up resistors for the serial clock line and the serial data bus line are required. Figure 4-15. Block Diagram of Serial Interface IIC0 MSTS0 ALD0 EXC0 COI0 TRC0 CLD0 DAD0 SMC0 DFC0 CL01 CL00 ACKD0 STD0 SPD0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 D SDA0/P71 SCL0/P72 SET CLEAR CL01, CL00 fX INTIIC0 IIC0 transfer clock select register (IICCL0) Internal bus Internal bus IIC0 status register (IICS0) IIC0 control register (IICC0) Slave address register 0 (SVA0) Noise elimination circuit Match signal IIC0 shift register (IIC0) SO0 latch N-ch open-drain output Data hold time correction circuit Acknowledge detection circuit Wake-up control circuit Acknowledge detection circuit Start condition detection circuit Stop condition detection circuit Serial clock counter Interrupt request signal generator Serial clock control circuit Noise elimination circuit Serial clock wait control circuit Prescaler

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

4.7 DCAN Controller (µµµµPD780701Y only)

The µPD780701Y incorporates a DCAN (Direct storage Control Area Network) controller. Table 4-3. DCAN Controller Functional Outline Function Details Protocol CAN2.0-supported extended frame format (Bosch specification 2.0 part B) Baud rate Maximum of 390 kbps (@ 6.29 MHz) Bus line control CMOS I/O for external transceiver Clock Selectable by register Data storage Capacity of buffer RAM for DCAN: 288 bytes (if not using for DCAN, it can be used for normal RAM) Message configuration Messages received via a message identifier are stored in RAM. Transmit message buffers: 2 Message number Maximum of 16 receive messages, including 2 masks Transmit channels: 2 channels Message sorting Can set a separate identifier for the 16 receive messages Mask identifiers: 2 Can set a global mask for all messages Interrupts Transmit interrupt request: 1 Receive interrupt request: 1 Error interrupt request: 1 Time function A time stamp function is available Other functions A separate transmit/receive error counter is available A flag for checking the bus connection is available A dedicated receive mode is available (use when detecting the baud rate on the bus) Low power consumption mode Sleep mode (can be woken up by the DCAN bus) Stop mode (cannot be woken up by the DCAN bus)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 4-16. DCAN Controller Block Diagram (µµµµPD780701Y only) The DCAN interface section processes all protocol operations by means of the DCAN protocol section hardware. The memory access engine either fetches the DCAN protocol data transmitted from a specific RAM area and transfers it to the DCAN protocol section, or compares and sorts the fetched data and then stores it in a predefined RAM area. The DCAN allows direct interfacing between the DCAN and the accessible CPU area, as well as between the CPU and that area without any effect on the CPU. The DCAN section operates with the external bus transceiver that converts transmit data line and receive data line to the electrical characteristics of DCAN bus. CANL CANH CPU External bus transceiver Memory access Arbitration Receive message Receive message Receive message Receive messageCycle steal DMA control SFR access Interface management (including global register) Memory access engine Buffer RAM for DCAN High-speed RAM DCAN protocol Transmit buffer Transmit buffer Timer Time signal DCAN interface

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

4.8 IEBus Controller (µµµµPD780702Y only)

The µPD780702Y incorporates an IEBus controller. The functions of the IEBus interface are limited compared with those of previous models (i.e., those incorporated in the µPD78098B Subseries). Table 4-4 shows a comparison of the interfaces in the µPD78098B Subseries and the µPD780702Y. Table 4-4. IEBus Interface Comparison (µµµµPD78098B Subseries and µµµµPD780702Y) Item IEBus Incorporated in µPD78098B Subseries IEBus Incorporated in µPD780702Y Communication mode Mode 0, mode 1, mode 2 Fixed at mode 1 Internal system clock f X = 6.0 (6.29) MHz f X = 6.291456 MHz Note Internal buffer size Transmit buffers: 33 bytes (FIFO) Receive buffers: 40 bytes (FIFO) Up to 4 frames receivable Transmit buffers: 1 byte Receive buffers: 1 byte CPU processing Processing before start of communication (data setting) Setting, controlling each communication status Writing data to transmit buffers Reading data from receive buffers Processing before start of communication (data setting) Setting, controlling each communication status Data write processing in one-byte units Data read processing in one-byte units Transmission control of slave status, etc. Multiple-frame control, repeat master- request processing Hard processing Bit processing (modem, error detection) Field processing (generation/control) Arbitration result detection Parity processing (generation/error detection) ACK/NACK automatic response Automatic retransmit-of-data processing Automatic remaster processing Automatic transmission processing of slave status, etc. Multiple-frame reception processing Bit processing (modem, error detection) Field processing (generation/control) Arbitration result detection Parity processing (generation/error detection) ACK/NACK automatic response Automatic retransmit-of-data processing Note The µPD780702Y only supports an IEBus controller that operates at fX = 6.291456 MHz. Remark fX: System clock frequency

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 4-17. IEBus Controller Block Diagram (µµµµPD780702Y only) BCR0 (8) UAR (12) SAR (12) PAR (12) CDR (8) DLR (8) DR (8) USR (8) ISR (8) SSR (8) SCR (8) CCR (8) 8 1 2 1 2 888 1 2 888 888 888 NFIRX0 ITX0 MPX MPX TX/RX CLK Internal bus R/W CPU interface Internal registers Internal bus PSR (8 bits) 12-bit latch Comparator Interrupt control circuit INT request Interrupt control Contention detection Parity generation/ error detection IEBus interface ACK generation Bit processing Field processing

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 The IEBus is broadly configured from the following 6 blocks.

• CPU interface
• Interrupt control
• Internal registers
• Bit processing
• Field processing
• IEBus interface <CPU interface> This is a control block whose purpose is to interface between the CPU (78K/0) and the IEBus main unit. <Interrupt control> This is a control block whose purpose is to pass on interrupt request signals from the IEBus main unit to the CPU. <Internal registers> This block sets the control registers that control the IEBus and the data of each field. <Bit processing> This block performs the bit timing generation and resolution, and is mainly configured from bit sequence ROM, an 8-bit preset timer, and a determiner. <Field processing> This block generates each field in the communication frame, and is mainly configured from field sequence ROM, a 4-bit down counter, and a determiner. <IEBus interface> This is the external driver/receiver interface block, and is mainly configured from a noise filter, a shift register, a contention detector, a parity detector, a parity generation circuit, and an ACK/NACK generation circuit.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 5. INTERRUPT FUNCTIONS A total of 30 interrupt sources are provided in the µPD780701Y, and a total of 29 interrupt sources are provided in the µPD780702Y, divided into the following three types.

• Non-maskable: 1
• Maskable: 28 ( µPD780701Y) 27 (µPD780702Y)
• ••• Software: 1 Table 5-1. Interrupt Source List (1/2) Interrupt Source Interrupt Type Default Priority Note 1 Name Trigger Internal/ External Vector Table Address Basic Configuration Type Note 2 Non-maskable − INTWDT Watchdog timer overflow (with non- maskable interrupt selected) (A)

0 INTWDT Watchdog timer overflow (with interval

timer selected) Internal 0004H (B)

1 INTP0 0006H

2 INTP1 0008H

3 INTP2 000AH

4 INTP3 000CH

5 INTP4 000EH

6 INTP5 0010H

7 INTP6 0012H

Pin input edge detection External 0014H (C)

9 INTSER0 Occurrence of UART0 reception error 0016H

10 INTSR0 End of UART0 reception 0018H

11 INTST0 End of UART0 transmission 001AH

12 INTCSI30 End of SIO30 transfer 001CH

13 INTCSI31 End of SIO31 transfer 001EH

14 INTIIC0 End of IIC0 transfer 0020H

15 INTCE

16 INTCR

17 INTCT

IEBus communication error and start/end of communication 0026H

18 INTWTNI0 Reference time interval signal from

19 INTTM000 Generation of matching signal of TM00

and CR000 (with compare register specified) TI000 valid edge detection (with capture register specified) Internal 002AH (B) Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest order and 28 is the lowest order. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 5-1. 3. µPD780701Y only 4. µPD780702Y only

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Table 5-1. Interrupt Source List (2/2) Interrupt Source Interrupt Type Default Priority Note 1 Name Trigger Internal/ External Vector Table Address Basic Configuration Type Note 2

20 INTTM010 Generation of matching signal of TM00

and CR010 (with compare register specified) TI010 valid edge detection (with capture register specified) 002CH

21 INTTM001 Generation of matching signal of TM01

and CR001 (with compare register specified) TI001 valid edge detection (with capture register specified) 002EH

22 INTTM011 Generation of matching signal of TM01

and CR011 (with compare register specified) TI011 valid edge detection (with capture register specified) 0030H

23 INTTM50 Generation of matching signal of TM50

24 INTTM51 Generation of matching signal of TM51

25 INTTM52 Generation of matching signal of TM52

26 INTAD End of conversion by A/D converter 0038H

27 INTWTN0 Watch timer overflow

(B)Maskable

28 INTKR Port 4 falling edge detection External 003CH (D)

Software − BRK Execution of BRK instruction − 003EH (E) Notes 1. Default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest order and 28 is the lowest order. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 5-1.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 5-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt (B) Internal maskable interrupt (C) External maskable interrupt (INTP0 to INTP7) IF MK IE PR ISP Standby release signal Internal bus Interrupt request Priority control circuit Vector table address generator IF MK IE PR ISP Standby release signal Internal bus External interrupt edge enable register (EGP , EGN) Interrupt request Edge detection circuit Priority control circuit Vector table address generator Standby release signal Internal bus Interrupt request Priority control circuit Vector table address generator

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Figure 5-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (INTKR) (E) Software interrupt IF: Interrupt request flag IE: Interrupt enable flag ISP: In-service priority flag MK: Interrupt mask flag PR: Priority specification flag IF MK IE PR ISP Standby release signal Internal bus Interrupt request Falling edge detection circuit Priority control circuit Vector table address generator Vector table address generator Internal bus Interrupt request Priority control circuit

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 6. STANDBY FUNCTION The following two standby functions are available for further reduction of system current consumption.

• HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode.
• STOP mode: In this mode, oscillation of the system clock is stopped. All the operations performed on the system clock are suspended, resulting in extremely small current consumption. Figure 6-1. Standby Function 7. RESET FUNCTION The following two reset methods are available.
• External reset by RESET signal input
• Internal reset by watchdog timer runaway time detection HALT mode System clock operation Interrupt request Interrupt request STOP instruction STOP mode (System clock oscillation stopped) HALT instruction (Clock supply to CPU halted, oscillation maintained)

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 8. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ 2nd operand 1st operand #byte A r Note sfr saddr !addr16 PSW [DE] [HL] [HL+byte] [HL+B] [HL+C] $addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC rM O V MOV ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B, C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC DEC !addr16 MOV PSW MOV MOV PUSH POP [DE] MOV [HL] MOV ROR4 ROL4 [HL+byte] [HL+B] [HL+C] MOV X MULU C DIVUW Note Except r = A

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd operand 1st operand #word AX rp Note sfrp saddrp !addr16 SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW MOVW MOVW rp MOVW MOVW Note INCW, DECW PUSH, POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 MOVW SP MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR 2nd operand 1st operand A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ 2nd operand 1st operand AX !addr16 !addr11 [addr5] $addr16 Basic instruction BR CALL BR CALLF CALLT BR, BC, BNC BZ, BNZ Compound instruction BT, BF BTCLR, DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°°°C) Parameter Symbol Conditions Ratings Unit VDD AV REF VDD = AVREF −0.3 to +6.5 VPower supply voltage AV SS −0.3 to +0.3 V VI1 P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, CRXD, IRX0, X1, X2, RESET −0.3 to V DD + 0.3 VInput voltage VI2 P33 N-ch open drain −0.3 to +16 V Output voltage V O P00 to P07, P20 to P27, P30 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, CTXD, ITX0 −0.3 to V DD + 0.3 V Analog input voltage VAN P80 to P87, P90 to P97 Analog input pin AV SS − 0.3 to AVREF + 0.3 and −0.3 to VDD + 0.3 V Per pin for P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P77, P80 to P87, P90 to P97, CRXD, IRX0 −10 mA Output current, high IOH Total for all pins −30 mA Peak value 20 mAPer pin for P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, CTXD, ITX0 rms value 10 mA Peak value 30 mAP33 rms value 15 mA Peak value 100 mA Output current, low IOL Note Total for all pins rms value 60 mA Operating ambient temperature TA −40 to +85 °C Storage temperature T stg −65 to +150 °C Note The rms value should be calculated as follows: [rms value] = [Peak value] × √ Duty Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 System Clock Oscillator Characteristics (TA = −−−−40 to +85°°°°C, VDD = 3.5 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Oscillation frequency (fX) Note 1 6.29 Note 2 MHzCrystal resonator Oscillation stabilization time Note 3 30 ms Notes 1. Indicates only oscillator characteristics. 2. 6.29 = 6.291456 (MHz) 3. Time required to stabilize oscillation after reset or STOP mode release. Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance.

• ••• Keep the wiring length as short as possible.
• ••• Do not cross the wiring with the other signal lines.
• ••• Do not route the wiring near a signal line through which a high fluctuating current flows.
• ••• Always make the ground point of the oscillator capacitor the same potential as VSS1 .
• ••• Do not ground the capacitor to a ground pattern through which a high current flows.
• ••• Do not fetch signals from the oscillator. IC X2 X1 C2 C1

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 DC Characteristics (TA = −−−−40 to +85°°°°C, VDD = 3.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VIH1 P21, P23, P25, P27, P31, P34, P40 to P47, P64 to P67, P73, P80 to P87, P90 to P97 0.7VDD VDD V VIH2 P00 to P07, P20, P22, P24, P26, P30, P32, P35, P36, P70 to P72, P74 to P77, CRXD, IRX0, RESET 0.8VDD VDD V VIH3 P50 to P57 2.3 V DD V VIH4 P33 N-ch open drain 0.7V DD 15 V Input voltage, high V IH5 X1, X2 VDD −−−− 0.5 VDD V VIL1 P21, P23, P25, P27, P31, P34, P40 to P47, P64 to P67, P73, P80 to P87, P90 to P97 00 . 3 V DD V VIL2 P00 to P07, P20, P22, P24, P26, P30, P32, P35, P36, P70 to P72, P74 to P77, CRXD, IRX0, RESET 00 . 2 V DD V VIL3 P50 to P57 0 0.75 V VIL4 P33 N-ch open drain 0 0.3V DD V Input voltage, low VIL5 X1, X2 0 0.4 V VOH1 IOH = −1 mA VDD −−−− 1.0 VDD VOutput voltage, high V OH2 IOH = −100 µA P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P77, P80 to P87, P90 to P97, CTXD, ITX0 VDD −−−− 0.5 VDD V VOL1 IOL = 15 mA P33 0.4 2.0 V VOL2 IOL = 1.6 mA P71, P72 0.4 V VOL3 IOL = 1 mA 1.0 V Output voltage, low VOL4 IOL = 100 µA P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P77, P80 to P87, P90 to P97, CTXD, ITX0 0.5 V ILIH1 P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, CRXD, IRX0, RESET µA ILIH2 VIN = VDD X1, X2 20 µA Input leakage current, high I LIH3 VIN = 15 V P33 80 µA ILIL1 P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P80 to P87, P90 to P97, CRXD, IRX0, RESET µA ILIL2 X1, X2 −20 µA Input leakage current, low I LIL3 VIN = 0 V P33 (except executing input instruction Note −3 µA Note During input instruction execution, a low-level input leakage current of −200 µA (MAX.) flows only for 1 clock (without wait). Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 DC Characteristics (TA = −−−−40 to +85°°°°C, VDD = 3.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output leakage current, high ILOH VOUT = VDD P00 to P07, P20 to P27, P30 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, CTXD, ITX0 µA Output leakage current, low ILOL VOUT = 0 V P00 to P07, P20 to P27, P30 to P36, P40 to P47, P50 to P57, P64 to P67, P70 to P77, P80 to P87, P90 to P97, CTXD, ITX0 µA Software pull-up resistor R 1 VIN = 0 V P00 to P07, P20 to P27, P30 to P32, P34 to P36, P40 to P47, P50 to P57, P64 to P67, P70, P73 to P77 15 30 90 k Ω IDD1 6.29-MHz crystal oscillation operating mode 4.0 20 mA IDD2 6.29-MHz crystal oscillation HALT mode Note 2 500 1000 µA Power supply current Note 1 IDD3 STOP mode 0.1 30 µA Notes 1. Refers to the current flowing to the VDD1 pin. The current flowing to the A/D converter and on-chip pull-up resistor is not included. 2. Low-speed mode operation (when processor clock control register (PCC) is set to 04H). The current for peripheral circuit operation is not included. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 AC Characteristics (1) Basic operation (TA = −−−−40 to +85°°°°C, VDD = 3.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Cycle time (Min. instruction execution time) T CY Operating with system clock (fX = 6.291456 MHz) 0.318 5.09 µs TI000, TI010, TI001, TI011 input high-/low- level width t TIH0 tTIL0 4/fsam + 0.25 Note µs TI50, TI51, TI52 input frequency f TI5 2M H z TI50, TI51, TI52 input high-/low-level width tTIH5 tTIL5 200 ns Interrupt request input high-/low-level width tINTH tINTL INTP0 to INTP7, P40 to P47 10 µs RESET low-level width t RSL 10 µs Note Selection of fsam = fX/2, fX/4, fX/64 is possible with bits 0 and 1 (PRM0n0, PRM0n1) of prescaler mode register 0n (PRM0n). However, if the TI00n valid edge is selected as the count clock, the value becomes fsam = fX/8 (n = 0, 1). 5.0 5.09 1.0 2.0 0.5 0.318 0.1 10.0 Power supply voltage VDD [V] TCY vs VDD (At system clock operation) Cycle time TCY [ s]µ Guaranteed operation range

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (2) Serial interface (TA = −−−−40 to +85°°°°C, VDD = 3.5 to 5.5 V) (a) 3-wire serial I/O mode (SCK30 ... Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK30 cycle time t KCY1 1.9 µs SCK30 high-/low-level width tKH1 tKL1 tKCY1 / 2 − 50 ns SI30 setup time (to SCK30 ↑) tSIK1 100 ns SI30 hold time (from SCK30 ↑) tKSI1 400 ns SO30 output delay time from SCK30↓ tKSO1 C = 100 pF Note 300 ns Note C is the load capacitance of the SCK30 and SO30 output lines. (b) 3-wire serial I/O mode (SCK30 ... External clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK30 cycle time t KCY2 800 ns SCK30 high-/low-level width tKH2 tKL2 400 ns SI30 setup time (to SCK30 ↑) tSIK2 100 ns SI30 hold time (from SCK30 ↑) tKSI2 400 ns SO30 output delay time from SCK30↓ tKSO2 C = 100 pF Note 300 ns Note C is the load capacitance of the SO30 output line.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (c) 3-wire serial I/O mode (SCK31 ... Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK31 cycle time t KCY3 1.9 µs SCK31 high-/low-level width tKH3 tKL3 tKCY1 / 2 − 50 ns SI31 setup time (to SCK31 ↑) tSIK3 100 ns SI31 hold time (from SCK31 ↑) tKSI3 400 ns SO31 output delay time from SCK31↓ tKSO3 C = 100 pF Note 300 ns Note C is the load capacitance of the SCK31 and SO31 output lines. (d) 3-wire serial I/O mode (SCK31 ... External clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK31 cycle time t KCY4 800 ns SCK31 high-/low-level width tKH4 tKL4 400 ns SI31 setup time (to SCK31 ↑) tSIK4 100 ns SI31 hold time (from SCK31 ↑) tKSI4 400 ns SO31 output delay time from SCK31↓ tKSO4 C = 100 pF Note 300 ns Note C is the load capacitance of the SO31 output line.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 (e) UART mode (Dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP. MAX. Unit Transfer rate 38836 bps (f) UART mode (External clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit ASCK0 cycle time t KCY3 800 ns ASCK0 high-/low-level width tKH3 , tKL3 400 ns Transfer rate 39063 bps (g) I C bus mode Standard Mode High-speed ModeParameter Symbol MIN. MAX. MIN. MAX. Unit SCL0 clock frequency f SCL 0 100 0 400 kHz Bus free time (between stop and start conditions) t BUF 4.7 − 1.3 − µs Hold time Note 1 tHD :STA 4.0 − 0.6 − µs SCL0 clock low-level width t LOW 4.7 − 1.3 − µs SCL0 clock high-level width t HIGH 4.0 − 0.6 − µs Start/restart condition setup time t SU :STA 4.7 − 0.6 − µs CBUS compatible master 5.0 −−− µsData hold time I C bus tHD :DAT Note 2 − 0 Note 2 0.9 Note 3 µs Data setup time t SU :DAT 250 − 100 Note 4 − ns SDA0 and SCL0 signal rise time t R − 1000 − 300 ns SDA0 and SCL0 signal fall time t F − 300 − 300 ns Stop condition setup time t SU :STO 4.0 − 0.6 − µs Spike pulse width controlled by input filter t SP −− 05 0 n s Capacitive load of each bus line Cb − 400 − 400 pF Notes 1. On start condition, the first clock pulse is generated after this period. 2. To fulfill undefined area of the SCL0 falling edge, it is necessary for the device to provide internally SDA0 signal (on VIHmin. of SCL0 signal) with at least 300 ns of hold time. 3. If the device does not extend the SCL0 signal low hold time (tLOW ), only maximum data hold time tHD:DAT needs to be fulfilled. 4. The high-speed mode I C bus is available in the standard mode I C bus system. At this time, the conditions described below must be satisfied.

• If the device does not extend the SCL0 signal low state hold time tSU :DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax . + tSU:DAT = 1000 + 250 = 1250 ns by standard mode I C bus specification).

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 AC Timing Test Points (excluding X1 input) Clock Timing TI Timing VIH5 (MIN.) VIL5 (MAX.) 1/fX tXL tXH X1 Input TI000, TI010, TI001, TI011 tTIL0 tTIH0 TI50, TI51, TI52 1/fTI5 tTIL5 tTIH5 0.8VDD 0.2VDD Test points 0.8VDD 0.2VDD

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Serial Transfer Timing 3-wire serial I/O mode: n = 1 to 4 UART mode (external clock input): I C bus mode: SI30, SI31 SO30, SO31 tKCYn tKLn tKHn tSIKn tKSIn tKSOn SCK30, SCK31 Output data Input data ASCK0 tKH5tKL5 tKCY5 SCL0 SDA0 tHD : STA tBUF tHD : DAT tHIGH tF tSU : DAT tSU : STA tHD : STA tSP tSU : STO tR tLOW Stop condition Stop condition Start condition Restart condition

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 IEBus0 Controller Characteristics (TA = −−−−40 to +85°°°°C, VDD = 3.5 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit IEBus system clock frequency fS Fixed at mode 1 6.29 MHz Driver delay time (Bus line from ITX0 output) tDTX C = 50 pF Note The µPC2590 is used as a driver/receiver 1.5 µs Receiver delay time (IRX0 input from bus line) t DRX The µPC2590 is used as a driver/receiver 0.7 µs Propagation delay time on bus tDBUS The µPC2590 is used as a driver/receiver 0.85 µs Note C is the load capacitance of the ITX0 output line. Remarks 1. Although the standard system clock frequency for the IEBus is 6.0 MHz, the µPD780702Y guarantees normal operation of the IEBus controller at 6.29 MHz. 2. fS: IEBus controller system clock frequency A/D Converter Characteristics (TA = −−−−40 to +85°°°°C, VDD = AVREF = 3.5 to 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 888 b i t Overall error Note ±0.6 % Conversion time t CONV 14 100 µs Analog input voltage V IAN AV SS AV REF V AV REF resistance R AIREF T.B.D 28 T.B.D k Ω Note Excludes quantization error (±0.2%). It is indicated as a ratio to the full-scale value.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −−−−40 to +85°°°°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention power supply voltage VDDDR 2.0 5.5 V Data retention power supply current IDDDR VDDDR = 2.0 V 0.1 10 µA Release signal set time tSREL 0 µs Release by RESET 2 /fX msOscillation stabilization wait time tWAIT Release by interrupt request Note ms Note Selection of 2 /fX, 2 /fX, 2 /fX, and 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Data Retention Timing (STOP mode release by RESET) Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal) tSREL tWAIT VDDDR VDD RESET STOP mode Internal reset operation HALT mode Operating mode Data retention mode STOP instruction execution tSREL tWAIT VDD VDDDR Standby release signal (interrupt request) STOP mode HALT mode Operating mode Data retention mode STOP instruction execution

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Interrupt Request Input Timing RESET Input Timing INTP0 to INTP7 tINTL tINTH RESET tRSL

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 10. PACKAGE DRAWING

80 PIN PLASTIC QFP (14×14)

ITEM MILLIMETERS INCHESNOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. P80GC-65-8BT F 0.825 0.032 B 14.00±0.20 0.551 +0.009 –0.008 S 1.70 MAX. 0.067 MAX. M 0.17 0.007 +0.001 –0.003 +0.03 –0.07 +0.009 –0.008 C 14.00±0.20 0.551 +0.009 –0.008 A 17.20±0.20 0.677±0.008 G 0.825 0.032 H 0.32±0.06 0.013 +0.002 –0.003 I 0.13 0.005 L 0.80±0.20 0.031 +0.009 –0.008 N 0.10 0.004 Q 0.125±0.075 0.005±0.003 R3 ° 3°+7° –3° +7° –3° D 17.20±0.20 0.677±0.008 4160 4061 2180 201 M S Q R K M L A B C D JH I F G P N detail of lead end

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using the µPD780701Y Subseries. Also refer to (5) Cautions on Using Development Tools. (1) Language Processing Software RA78K/0 Assembler package common to 78K/0 Series CC78K/0 C compiler package common to 78K/0 Series DF780701 Note Device file for µPD780701Y Subseries CC78K/0-L C compiler library source file common to 78K/0 Series Note Under development (2) Flash Memory Writing Tools Flashpro II (Part No. FL- PR2), Flashpro III (Part No. FL-PR3, PG-FP3) Dedicated flash programmer for microcomputers incorporating flash memory FA-80GC Adapter for writing to flash memory for use in an 80-pin plastic QFP (GC-8BT type). An adjusting connection to the target product is necessary. Flashpro II controller, Flashpro III controller Program that is controlled from a PC and comes together with Flashpro II and Flashpro III. It operates in environments such as Windows TM 95. (3) Debugging Tools

• ••• When IE-78K0-NS in-circuit emulator is used IE-78K0-NS In-circuit emulator common to 78K/0 Series IE-70000-MC-PS-B Power supply unit for IE-78K0-NS IE-70000-98-IF-C Interface adapter necessary when using PC-9800 series PC (except notebook type) as host machine (C bus supported) IE-70000-CD-IF-A PC card and interface cable necessary when using notebook PC as host machine (PCMCIA socket supported) IE-70000-PC-IF-C Interface adapter necessary when using IBM PC/AT TM compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter necessary when using personal computer incorporating PCI bus as host machine IE-780701-NS-EM1 Note Emulation board to emulate µPD780701Y Subseries NP-80GC Emulation probe for 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket to connect the NP-80GC and a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted ID78K0-NS Integrated debugger for IE-78K0-NS SM78K0 System simulator common to 78K/0 Series DF780701 Note Device file for µPD780701Y Subseries Note Under development

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

• ••• When IE-78001-R-A in-circuit emulator is used IE-78001-R-A In-circuit emulator common to 78K/0 Series IE-70000-98-IF-C Interface adapter necessary when using PC-9800 series PC (except notebook type) as host machine (C bus supported) IE-70000-PC-IF-C Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus supported) IE-70000-PCI-IF Adapter necessary when using personal computer incorporating PCI bus as host machine IE-78000-R-SV3 Interface adapter and cable necessary when using EWS as host machine IE-780701-NS-EM1 Note Emulation board to emulate µPD780701Y Subseries IE-78K0-R-EX1 Emulation probe conversion board necessary when using IE-780701-NS-EM1 on IE-78001-R-A EP-78230GC-R Emulation probe for 80-pin plastic QFP (GC-8BT type) EV-9200GC-80 Conversion socket to connect the EP-78230GC-R and a target system board on which an 80-pin plastic QFP (GC-8BT type) can be mounted ID78K0 Integrated debugger for IE-78001-R-A SM78K0 System simulator common to 78K/0 Series DF780701 Note Device file for µPD780701Y Subseries Note Under development (4) Real-time OS RX78K/0 Real-time OS for 78K/0 Series MX78K0 OS for 78K/0 Series (5) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780701.
• The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 and DF780701.
• The FL-PR2, FL-PR3, FA-80GC, and NP-80GC are products made by Naitou Densei Machidaseisakusho Co., Ltd. (TEL +81-44-822-3813). Contact an NEC distributor regarding the purchase of these products.
• For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
• The host machine and OS suitable for each software are as follows: PC EWSHost Machine [OS] Software PC-9800 series [Windows TM IBM PC/AT and compatibles [Japanese/English Windows] HP9000 series 700 TM [HP-UX TM SPARCstation TM [SunOS TM , Solaris TM NEWS TM (RISC) [NEWS-OS TM RA78K/0 √ Note CC78K/0 √ Note ID78K0-NS √− ID78K0 √√ SM78K0 √− RX78K/0 √ Note MX78K0 √ Note Note DOS-based software

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 APPENDIX B. RELATED DOCUMENTS

• ••• Documents Related to Devices Document No.Document Name English Japanese µPD780701Y Subseries User’s Manual Under preparation U13781J µPD780701Y, 780702Y Preliminary Product Information This document U13920J µPD78F0701Y Preliminary Product Information U13563E U13563J 78K/0 Series User’s Manual Instructions U12326E U12326J
• ••• Documents Related to Development Tools (User’s Manuals) Document No.Document Name English Japanese Operation U11802E U11802J Language U11801E U11801J RA78K0 Assembler Package Structured Assembly Language U11789E U11789J RA78K Series Structured Assembler Preprocessor EEU-1402 U12323J Operation U11517E U11517JCC78K0 C Compiler Language U11518E U11518J CC78K/0 C Compiler Application Note Programming Know-How U13034E U13034J IE-78K0-NS To be prepared To be prepared IE-78001-R-A To be prepared To be prepared IE-78K0-R-EX1 To be prepared To be prepared IE-780701-NS-EM1 To be prepared To be prepared EP-780230 EEU-1515 EEU-985 SM78K0 System Simulator Windows Based Reference U10181E U10181J SM78K Series System Simulator External Part User Open Interface Specifications U10092E U10092J ID78K0-NS Integrated Debugger Windows Based Reference U12900E U12900J ID78K0 Integrated Debugger EWS Based Reference − U11151J ID78K0 Integrated Debugger Windows Based Guide U11649E U11649J ID78K0 Integrated Debugger PC Based Reference U11539E U11539J

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00

• ••• Documents Related to Embedded Software (User’s Manuals) Document No.Document Name English Japanese Fundamental U11537E U11537J78K/0 Series Real-Time OS Installation U11536E U11536J 78K/0 Series OS MX78K0 Fundamental U12257E U12257J
• ••• Other Related Documents Document No.Document Name English Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)C11892E C11892J Guide to Microcomputer-Related Products by Third Party − U11416J Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips. FIP, IEBus, and Inter Equipment Bus are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µµµµPD780701Y, 780702Y Preliminary Product Information U13920EJ1V0PM00 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1

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