PD77728

Microchip Technology

8-Port PoE PSE Manager Revision E Date 07/2024

Manufacturer: Microchip Technology

Document: 44 Pages / 2Mb

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Technical content

to provide 48 4-pair ports. The device is available in a 56-pin 8 mm × 8 mm QFN package. The following figure shows the typical PoE application of the PD77728 device. Figure 1. Typical PoE Applic ation

Features

The PD77728 device and PD77728 based PSE have the following key features:

Supported Standards – IEEE 802.3bt
Supported PD Types – Type 1, Type 2 PDs (802.3af, 802.3at) – Single-Signature (Type 1–4) PDs – Dual-Signature (Type 3 and 4) PDs – Pre-Standard (Legacy) 4-pair PDs – Supports non-compliant and legacy PDs
Four Operational Modes – Controller mode in conjunction with PD77020 PSE Power Management Controller – Semi-Auto mode – Managed Auto mode – Unmanaged Auto mode
Cascade up to 12 devices to support 96 × 2-pair ports or 48 × 4-pair ports and any 4-pair/2-pair combination
Device Features – Stand-Alone device supports up to 8 × 2-pair ports or 4 × 4-pair ports and any 4-pair/2-pair combination – Per-Port integrated FET, sense resistor, and port diode – Total port resistance of 160 mΩ – Device power dissipation ≤ 2W at full load – Two power rails (55V and 3.3V) for maximum power efficiency – Guaranteed 4-pair output power of > 90W – Over Supply Signal (OSS) support – AutoClass support – Supports Fast and Perpetual PoE – MarkHold function support – Host Interface through I 2C Communication
Real-Time Protection (RTP)
Measurements – Per-Port voltage and current measurement – Accurate main power measurement
Surge – Surge up to 2 kV without additional components per IEC61000-4-5-2014 – Surge compliance, ITU-T K.21, GR1089, IE61000-4-5-2014, EN55024
Up to 10 kV per IEC61000-4-5-2014
Up to 6 kV per ITU-T K.21
Physical Characteristics – Ambient temperature range –40 °C to 85 °C – 56-pin 8 mm × 8 mm QFN package with thermal pad – MSL3, RoHS compliant

Campus switches
Switches and routers for enterprises, small and medium businesses, Small Office Home Office (SOHO), and commercial markets
Switches for lighting markets
PoE injectors

Analog front-end block (x8)
Voltage and temperature measurement module
Digital processing and control block
PoE controller (based on the Cortex -M device) The following figure shows a high-level block diagram of the device. Figure 1-1. Block Diagram PoE ControllerMicrochip Cortex M0+ I2CHost Interrupt Reset Global ThermalShutdown Port 0 Analog Block Port 1 Analog Block Port 7 Analog Block Band Gap CLK VMAIN3.3V IREF Vport analog frontend POR OSS SPI VMAIN_7 VMAIN_36VMAIN VMHVDD VDDA Detection ADC Classification voltage gen. ThermalSensor+_+_ ADC DAC RPORT ILIM and Inrush control RPORT MarkHold LDO 1.8V UVLO CREG1P8 ... Temp0Vport0Temp1Vport1 Vport7 Temp7 Port SCPShort Circuit Port TLIM protection Port OVT protection Port MPS logic TCUT / ICUT INRUSH protection FSD IPORT MeasurementProcessing (8) ILIM / CLASS control (8) VoltagesMeasurementProcessing Detection & RPORTcontrol (8) VMAINVBG ...Digital Domain TBG RTP (8) VMH PORT_NEGx SPI REGSDFTTRIM

1.1 Analog Front-End Block

The analog front-end block of each port contains the following components:

Current limiting block—fast acting current limiting loop
Classification voltage regulation
V PORT measurement analog interface
Detection module
Current measurement module
Proprietary MarkHold analog block This structure allows efficient and flexible port control. It also supports simultaneous power-up/ power-on 8 ports control.

1.2 Voltage and Temperature Measurement Module

The module measures port voltages, VMAIN voltage, and temperature.

1.3 Digital Processing and Control Block

The digital block communicates with the integrated PoE controller and controls the analog front-end block. It consists of the following blocks:

Ports ON/OFF control block
I LIM and ICLASS control blocks
I INRUSH control and protection block
Detection and R PORT control block
Port voltage and temperature measurement post-processing module
Port current post-processing module
RTP module

1.4 PoE Controller

The integrated PoE controller controls both port-level and device-level PoE tasks. The firmware is pre-programmed into the integrated controller with field-upgradable capability through the I2C host interface. The integrated PoE controller provides the following features:

Host communication interface (Fast-Mode Plus I 2C interface, INT_OUT signal)
OSS fast shut-down control
Device-level data processing
Supports PoE firmware download capability from host
Manages one device 2p and 4p ports configuration
Device-Level power budgeting and power assignment

1.5 Power

The PD77728 device is designed for low power consumption and low power dissipation, using cutting-edge process technology and proprietary port’s MOSFET design. The following two parameters allow a total power dissipation of equal to or less than 2W at TJ = 125 °C:

Very low channel (port) resistance (typically, 160 mΩ at 25 °C)
Very low V MAIN quiescent current The PD77728 device supports any power rail sequencing of the VMAIN and VDD rails.

1.6 Real-Time Pr ot ection (RTP)

This section describes the RTP blocks included in the PD77728 device. The device supports multi- level and real-time support mechanisms. All RTP mechanisms are configured by the PoE controller, implemented in the digital domain, and directly control the port analog front-end. Each port has its own RTP protection blocks. This type of design ensures fast-acting protection under all conditions.

1.6.1 Current Overload (TLIM/ILIM) Pr ot ection

The configurable ILIM and TLIM parameters are based on the IEEE 802.3bt standard. TLIM and ILIM threshold levels are selected by firmware based on the assigned class. The port shuts down if it enters current limit (ILIM) and maintains ILIM for a period of TLIM. Current overload RTP also protects against repetitive overload conditions, where the port repetitively enters current limit for a duration less than TLIM, which might result in a device damage due to accumulated overheating. The PD77728 overload protection mechanism disconnects the port if the accumulated power poses danger to the Safe Operating Area (SOA) of the MOSFET.

1.6.2 Short-Circuit Protection

If the port enters the current limit and the port voltage (VPORT) drops below a configurable value, the port is considered to be in a short-circuit condition. In this case, the port is turned off within 100 µs (typical) to minimize the power dissipation on the MOSFET during such a harsh condition. The voltage below which the port is considered to be in a short-circuit condition is also configurable.

1.6.3 Inrush (Power-Up) Pr ot ection

During the port inrush phase, the PD capacitor is charged with a constant current for up to 75 ms. If the PD is not limiting the current, the PSE uses its current limit to limit the capacitor inrush current (for most cases, ILIM is 0.425A). Inrush current is also configurable. A failed PD capacitor, or too large a capacitor value, might result in either a true short-circuit condition on the port during inrush (leads to very high-power dissipation, equal to 0.425A × VMAIN), or a very high-power dissipation due to the slow increase in the capacitor voltage. A dedicated inrush protection mechanism is provided to protect the device from such events, assuring that the port’s MOSFET does not exceed its SOA under any condition.

1.6.4 Over-Temperature (OVT) Pr ot ection

OVT protection adds an additional layer of protection to the device, and protects the device from overheating and damaging in parallel to the other protection mechanisms. An example for OVT protection is a slow increase in ambient temperature (for example, a failed fan), resulting in an elevated junction temperature which exceeds the maximum operating junction temperature. In this case, the OVT real-time protection either limits the number of ports that can be turned on at such temperature, or turns off the port (s) with the highest junction temperature.

1.6.5 TCUT/ICUT Pr ot ection

The firmware selects TCUT and ICUT threshold levels based on the assigned class. The port is turned off if the port current exceeds ICUT for a cumulative time of TCUT (typical 65 ms). Both TCUT and ICUT values are configurable.

1.6.6 Maintain Power Signature (MPS)

Although this condition does not endanger the PSE device, the MPS signature is required to keep a PD powered and to disconnect its power if PD is removed. The PD77728 device incorporates MPS protection, in which the port is turned off if the PD current does not comply with the required hold current and time, as defined in the IEEE 802.3bt standard. Both the hold current (IHOLD/IHOLD-2P) and the duration (TMPS, TMPDO) are configurable parameters.

1.7 Over Supply Shutdown (OSS)

OSS is a control pin required to turn off ports of a certain priority due to failure in one of the power supplies. A dedicated, fast shut-down bus is located between the PoE controller and the digital block to allow fast shut-down response to the OSS signal. Both 1-bit signal priority and 3-bit signal priority are supported.

1.8 VMAIN Under-Voltage Lockout (VMAIN_UVLO)

VMAIN under-voltage lockout (VMAIN_UVLO) turns off ports when VMAIN drops below a set threshold.

1.9 Surge

The PD77728 device supports up to 2 kV per IEC-61000-4-5-2014 without external protection components. For a higher level of surge, request AN4813 Surge Protection for Systems Based on PD777xx 8-Port PSE PoE Manager Application note.

1.10 PSE System Modes of Oper ation

The device supports the following PSE system modes of operation:

Controller mode (with PD77020 PSE Power Management Controller)
Managed Semi-Auto mode
Managed Auto mode
Unmanaged Auto mode For more details, see 5. Application Information.

PD77020 PSE Power Management Controller Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 10 2. PD77020 PSE Power Management Controller The PD77020 PoE Power Management Controller provides multi-port PoE functions, such as port mapping (Port Matrix), port priority, port status, and system power management. The PD77020 device is used in conjunction with the PD77728 PoE Manager. The PD77020 device is based on Microchip SAM D21 and is packaged in a 5 mm × 5 mm 32-pin QFN package. For more details, see the PD77020 Data Sheet and Communications Protocol documents.

Electrical Specific ations Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 11 3. Electrical Specific ations This section describes the electrical specifications of the device.

3.1 Absolute Maximum Ratings

PoE performance is not guaranteed when it exceeds the recommended rating. Exposure to any stress in the range between the recommended rating and the absolute maximum rating must be limited to a short time. Exceeding these ratings might impact long-term operating reliability. The following table lists the absolute maximum ratings. Table 3-1. Absolute Maximum Ratings Parameter Minimum Maximum Unit VDD –0.3 3.8 V VDDA –0.3 3.8 V VDDA to VDD –0.3 0.3 V VMAIN –0.3 80 V VMAIN_7, VMAIN_36 VMAIN 80 V MarkHold FET is OFF 0 VMAIN V PORT_NEGx to AGND –0.3 Lower of VMAIN_x + 0.5 or 80 V DGND to AGND –0.3 0.3 V Digital I/O –0.3 3.6 V AUTO –0.3 Lower of VDDA + 0.3 or 3.8 V Junction Temperature –40 Self Protected °C Storage –55 150 °C Solder 10 Seconds — 260 °C

3.2 Immunity

The following tables list the device immunity. Table 3-2. ESD Model Pins Minimum Rating Test Method Human Body Model (HBM) All ±2000V JS-001-2017 Charge Device Model (CDM) All ±1000V JESD22-C101F Table 3-3. Surge Pr ot ection Standard Application Minimum Rating IEC61000-4-5 Ed3 Common mode 1 kV, 2 kV, 4 kV, 6 kV, and 10 kV ITU-T K.21 2019 Common mode 2.5 kV, 4 kV, and 6 kV Differential mode 2.5 kV and 6 kV EN55024 2010 Common mode 1 kV and 4 kV GR1089 Issue 6 Common mode 1 kV and 2.5 kV Differential mode 1 kV Note: Device meets 2 kV per IEC-61000-4-5 without need for additional surge protection components. Consult Microchip for recommended protection circuitry for enhanced surge capability.

3.3 Recommended Oper ating Conditions

The following table lists the recommended operating conditions. Table 3-4. Recommended Oper ating Conditions Parameter Conditions Min. Typ. Max. Units Junction temperature — –40 — 125 °C Ambient temperature — –40 — 85 °C VMAIN Type 1: Reference to AGND 44 — 57 V Type 2, 3: Reference to AGND 50 — 57 V Type 4: Reference to AGND 52 — 57 V VMAIN_7/VMAIN_36 Reference to AGND — VMAIN — V VMAIN slew rate VMAIN = 0V to 57V VDD may be either present or absent — — 1.0 V/µs VDD Reference to DGND 3.0 3.3 3.6 V VDDA Reference to AGND 3.0 3.3 3.6 V DGND–AGND voltage difference — –0.3 — 0.3 V

3.4 Electrical Char act eristics

If not specified under conditions, the minimum and maximum ratings listed in the following table apply to the entire specified operating ratings of the device. Typical values stated are either by design or by production testing at 25 °C ambient. The following tables list the electrical characteristics of the device. Table 3-5. Current and Power Consumption Parameter Symbol Conditions Min. Typ. Max. Units VMAIN current IMAIN Power on Reset (POR) threshold exceeded. VMAIN > 12V — — 1.5 mA VMAIN< POR threshold 0V < VMAIN ≤ 8V VDD and VDDA not present IC is non-operational — — 100 µA VDD rail + VDDA rail current IVDD + IVDDA VMAIN = 55V, VDD = VDDA = 3.6V — — 30 mA Table 3-6. Port Char act eristics Parameter Symbol Conditions Min. Typ. Max. Units Port supported continuous current IPORT_CONT • Single-Signature PD

V MAIN = 52V, port not in current limit
Class 8 with P CLASS_PD = 99.7W
Maximum unbalance 1.185 — — A Power dissipation PDISS All ports 4P Class 8 power (90W) VMAIN = 52V VDD = VDDA = 3.3V — — 2.0 W Total channel resistance RCH_ON TA = 25 °C, — 0.160 — Ω Port resistance RCH_OFF RPORT connected, TJ = 25 °C VPORT < 30V 50 60 70 kΩ RPORT disconnected, TJ = 25 °C — 1.8 — MΩ VPORT leakage ILEAKAGE VPORT_NEGx to AGND — — 5 µA Port capacitance CPSE Required: External X7R port capacitance (typical capacitor values) 47 100 220 nF CPD Supported PD capacitance for IEEE 802.3bt compliant detection 50 — 150 nF Supported PD capacitance, non-compliant PD detection 0.05 — 12.8 µF Supported PD capacitance, inrush phase, IEEE® 802.3bt compliant 5 — 180 µF Supported PD capacitance, inrush phase, not IEEE® 802.3bt compliant — — 432 µF Supported output power PPORT4P 2 ports power, connected to a single-signature PD, VMAIN = 52V — — 100 W

Electrical Specific ations Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 14 Table 3-7. Current Limit (ILIM) Parameter Symbol Conditions Min. Typ. Max. Units Port current limit ILIM Class 0–Class 3, 2-pair single signature — 0.720 — A Class 4, 2-pair single signature — 0.850 — A Class 4, 4-pair dual signature — 0.850 — A Class 5, 4-pair single signature — 0.850 — A Class 6, 4-pair single signature — 0.890 — A Class 7, 4-pair single signature — 1.000 — A Class 8, 4-pair single signature Class 5, 4-pair dual signature — 1.200 — A Inrush current limit IINRUSH_B ILIM setting ILIM_2P_B 0.400 0.425 0.450 A Table 3-8. Power Accuracy Parameter Conditions Min. Typ. Max. Single port (2 pairs) power accuracy Port power: 5W to 15W −5.0% — 5.0% Port power: 15W to 55W −2.5% — 2.5% 2 ports (4 pairs) power accuracy Total 4-pair power: 5W to 30W −5.0% — 5.0% Total 4-pair power: 30W to 100W −2.5% — 2.5% Table 3-9. De t ection and Connection Check Parameter Symbol Conditions Min. Typ. Max. Units Accept signature resistance RDET — 17 25 29 kΩ Accept signature capacitance CDET — — — 0.15 µF Reject signature resistance (low) RREJ — — — 15 kΩ Reject signature resistance (high) RREJ — 33 — — kΩ Reject signature capacitance CREJ — 10 — — µF Detection open circuit resistance ROC — 0.5 — — MΩ Valid detection test voltage VVALID — 2.8 — 10 V Detection open circuit voltage VOC — — — 30 V Total detection timing TDET — — — 400 ms Table 3-10. Classific ation Parameter Symbol Conditions Min. Typ. Max. Units Measured ICLASS at PSE ICLASS Class Signature 0 0 — 5 mA Class Signature 1 8 — 13 mA Class Signature 2 16 — 21 mA Class Signature 3 25 — 31 mA Class Signature 4 35 — 45 mA Table 3-11. Real-Time Pr ot ection Parameter Symbol Conditions Min. Typ. Max. Units Short Circuit Protection (SCP) disconnection time TSCP Port in current limit, VPORT < 40V, no bouncing — 100 — µs Overload protection (TLIM) TLIM_2P Port in current limit, VPORT ≥ 40V Class 1 to Class 6 — 11 — ms Port in current limit, VPORT ≥ 40V Class 7 and Class 8 — 7 — ms

Electrical Specific ations Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 15 Parameter Symbol Conditions Min. Typ. Max. Units Port MPS current threshold IMPS SSPD, Class 1–4, 4P operation 2.0 3.5 5.0 mA SSPD, Class 1–4, 2P operation 5.0 7.0 9.0 mA SSPD, Class 5–8, 4P operation 2.0 4.5 7.0 mA DSPD 2.0 4.5 7.0 mA MPS on time detection TMPS — — — 6 ms MPS off time TMPDO — 340 356 372 ms Port OVT protection Reference temperature Temperature above which the OVT protection is active — — 150 °C Table 3-12. ICUT and TCUT Specific ations Parameter Symbol Conditions Min. Typ. Max. Units ICUT threshold ICUT_2P 44V < VMAIN < 57V Class 0–3 — 0.375 — A 50V < VMAIN < 57V Class 4 SSPD 2P operation — 0.644 — A 50V < VMAIN < 57V Class 5 SSPD 4P operation — 0.700 — A 52V < VMAIN < 57V Class 6 SSPD 4P operation — 0.800 — A 52V < VMAIN < 57V Class 7 SSPD 4P operation — 0.900 — A 52V < VMAIN < 57V Class 8 SSPD 4P operation Class 5 DSPD 4P operation — 1.090 — A TCUT disconnect time TCUT_2P — — 65 — ms PCUT disconnect time PCUT_2P IPORT ≥ PCUT/VMAIN — 132 — ms Table 3-13. Inrush (Power-Up) Phase Parameter Symbol Conditions Min. Typ. Max. Units Inrush time TINRUSH Per port VMAIN = 57V IINRUSH_2P = 0.425A — 65 — ms Number ports for simultaneous power-up NPORT Power-up to maximum capacitor of 360 µF + 20% — — 8 Ports Table 3-14. UVLO Parameter Symbol Conditions Min. Typ. Max. Unit VMAIN_UVLO Threshold voltage VMAIN_UVLO_F Threshold level below which ports are turned off. VMAIN falling. 29.5 30 30.5 V VMAIN_UVLO_R Threshold level above which ports are operational. VMAIN rising. 39.4 40 40.6 V VMAIN_UVLO ports off response time tVMAIN_UVLO_F Time between VMAIN falling below VMAIN_UVLO_F and ports turned off. VMAIN falling. 8 — 24 ms

Electrical Specific ations Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 16 Table 3-15. I2C Parameter Symbol Conditions Min. Typ. Max. Units I2C SCL clock frequency fSCL Standard, Fast, and Fast Plus modes are supported. — — 1 MHz Table 3-16. External Current Reference Resistor IREF Parameter Symbol Conditions Min. Typ. Max. Units IREF resistor value IREF External 0402 reference resistor value — 10 — kΩ IREF% External 0402 reference resistor accuracy –0.1 — 0.1 % IREF_TEMPCO Resistor temperature coefficient — 25 50 ppm/°C Table 3-17. I/O Char act eristics Symbol Parameter Conditions Min. Typ. Max. Units RPULL Internal Pull-up/Pull-down resistance — 20 40 60 kΩ VIL Input low-level voltage VDD = 3.0V–3.6V — — 0.3 × VDD V VIH Input high-level voltage VDD = 3.0V–3.6V 0.55 × VDD — — VOL Output low-level voltage VDD > 3.0V, IOL maxI — 0.1 × VDD 0.2 × VDD VOH Output high-level voltage VDD > 3.0V, IOH maxII 0.8 × VDD 0.9 × VDD — IOL Output low-level current VDD = 3V–3.63V — — 10 mA IOH Output high-level current VDD = 3V–3.63V — — 7 mA tRISE Rise time1 load = 20 pF, VDD = 3.3V — — 15 ns tFALL Fall time1 load = 20 pF, VDD = 3.3V — — 15 ns ILEAK Input leakage current Pull-up resistors disabled −1 ±0.015 1 μA Note: 1. These values are based on simulation. These values are not covered by test limits in production or characterization. Table 3-18. I2C Pins Char act eristics in I2C Con figur ation Symbol Parameter Condition Min. Typ. Max. Units VIL Input low-level voltage VDD = 3.0V–3.6V — — 0.3 × VDD V VIH Input high-level voltage VDD = 3.0V–3.6V 0.55 × VDD — — VHYS Hysteresis of Schmitt trigger inputs 0.08 × VDD — — VOL Output low-level voltage VDD > 3.0V, IOL = 3 mA — — 0.4 IOL Output low-level current VOL = 0.4V Fast Mode Plus 20 — — mA fSCL SCL clock frequency — — 400 KHz

© 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 18 The following table lists the pin descriptions of the PD77728 device. Table 4-1. Pin Descriptions Pin Designator Type Description 1, 2, 4, 9, 11, 13, 19, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 39, 41, 42, 55 Not Connected (NC) N/A NC. Leave floating.

3 PORT_NEG0 Power Negative port 0 output

5 PORT_NEG1 Power Negative port 1 output

6, 8, 16, 18, 35, 37 N/A N/A Pin removed

7 VMAIN_7 Power Connect to VMAIN through PCB trace or 0Ω resistor

for basic level protection. Leave unconnected for enhanced surge protection. See PD77728 Surge Protection Application Note for more details.

10 PORT_NEG2 Power Negative port 2 output

12 PORT_NEG3 Power Negative port 3 output

14 IREF Analog Input Current reference resistor. Connect through 10K 0.1% to AGND. 15 MarkHold Analog Input MarkHold input. Leave unconnected when not used. 17 VMAIN Power Connect to VMAIN. Connect a 1 µF, 100V, X7R capacitor near each device's VMAIN pin. 20 VREG1P8 Power Internal 1.8V regulator output capacitor connection. Connect a low-ESR, 1 μF capacitor to DGND. 21 AGND GND Analog Ground. Connect to DGND through a single point connection. 22 VDDA Power Analog 3.3V supply. Connect a capacitor to AGND. Connected to main 3.3V supply on the board.

31 PORT_NEG4 Power Negative port 4 output

33 PORT_NEG5 Power Negative port 5 output

36 VMAIN_36 Power Connect to VMAIN through PCB trace or 0Ω resistor

for basic level protection. Leave unconnected for enhanced surge protection. See PD77728 Surge Protection Application Note for more details.

38 PORT_NEG6 Power Negative port 6 output

40 PORT_NEG7 Power Negative port 7 output

43 VDD Power Digital 3.3V supply. Connect a capacitor to DGND. Connected to main 3.3V supply on the board. 44 RESET_IN_N Input Device Reset. Connect a pull-up resistor to VDD. 45 INT_OUT_N Output Interrupt output pin (open drain). Leave open if not used. 46 DGND GND Digital Ground. Connect to AGND through a single point connection. 47 VDDCORE Power Internal 1.2V regulator output capacitor pin. Connect 1.0 μF low ESR capacitor to DGND. 48 A1 Input I2C device address. Connect to VDD or DGND. 49 A2 Input I2C device address. Connect to VDD or DGND. 50 A3 Input I2C device address. Connect to VDD or DGND. 51 A4 Input I2C device address. Connect to VDD or DGND.

52 AUTO Input Connect a resistor divider comprised of a 10 kΩ

resistor from VDD to AUTO pin, and a resistor from AUTO pin to DGND to select the AUTO mode configuration. See Table 5-1 for resistor selection and AUTO mode configurations.

53 SCLIO Bidirectional I2C clock

54 SDIO Bidirectional I2C data input/output

56 OSS Input OSS is used to shut down ports based on priority

settings. Connect to AGND through 10K, if unused. EPAD EPAD Analog Exposed Pad. Connect to AGND through short trace on PCB underneath device. AGND must have enough copper mask to ensure adequate thermal performance.

Applic ation In f ormation Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 20 5. Applic ation In f ormation This section provides practical operation information for the PD77728 device.

5.1 Oper ational Modes

This section provides a high level description of the four available operational modes:

Controller mode
Semi-Auto mode
Managed Auto mode
Unmanaged Auto mode

5.1.1 Controller Mode

This section describes the chipset operation with PD77020 PoE Power Management Controller. The PD77020 device is used in conjunction with the PD77728 device, where the PD77020 PoE Power Management Controller provides multi-port PoE functions, such as port mapping (Port Matrix), port priority, port status, and system power management. The following figure shows the Controller Mode application. Figure 5-1. Controller Mode Applic ation PD77728 PD77728 PD77728 PD77728 OSS RESET_IN_N A1 – A4: Set I2C device address 01234567 port_neg 01234567 port_neg 01234567 port_neg 01234567 port_neg VMAIN VMAINVMAINVMAIN 3.3V 3.3V 3.3V 3.3V 10K10K10K10K RESET_IN_N OSS SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDA SCL INT_OUT_N RESET_IN_N OSS INT_OUT_N RESET_IN_N OSS INT_OUT_N RESET_IN_N OSS INT_OUT_N I2C iso Isolation Barrier dig iso PD77020 I2C_OUT_SDA I2C_OUT_SCL OSS_OUT xRESET_OUT I2C_IN_SDA I2C_IN_SCL xSys_OK xDISABLE_PORTS xINT_OUT xRESET_IN xI2C_MESSAGE_READY Host Processor SDA SCL CONTROL CONTROL CONTROL CONTROL CONTROL LED_SCK xLED_SS LED_DO xLED_OE LED Stream I2C_ADDR_Meas3.3V 10K xINT_IN AUTO AUTO AUTO AUTO

5.1.2 Semi-Auto Mode

In the Semi-Auto mode, the device performs periodic connection check, detection, and classification, but does not power-up the ports without a host command. Each device has initial PSE configuration containing the Port Matrix (2P/4P configuration) and stores the port investigation results in the memory for host control. The host can override these settings. In this mode, the PoE controller is responsible for the periodic or cyclic detection and classification of the ports. The following figure shows the Semi-Auto mode application. Figure 5-2. Semi-Auto Mode Applic ation PD77728 PD77728 PD77728 PD77728 OSS (optional) RESET_IN_N A1 – A4: Set I2C device address 0 1 2 3 4 5 6 7 port_neg 0 1 2 3 4 5 6 7 port_neg 0 1 2 3 4 5 6 7 port_neg 0 1 2 3 4 5 6 7 port_neg VMAIN VMAINVMAINVMAIN 3.3V ... 3.3V 3.3V 3.3V 10K Isolation Barrier I2C iso dig iso 10K10K10K RESET_IN_N OSS RESET_IN_N OSS RESET_IN_N OSS RESET_IN_N OSS SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO I2C_OUT_SDA I2C_OUT_SCL SDA SCL OSS xRESET_OUT Host Processor xINT_IN INT_OUT_N (optional) INT_OUT_N INT_OUT_N INT_OUT_N INT_OUT_N ... AUTO AUTO AUTO AUTO ...

5.1.3 Auto Mode

The Auto mode is an operational mode where PSE can perform the required functionality with predetermined configuration values. In this mode, the device performs connection check, detection, classification, and power-up autonomously following POR, and turning valid PoE ports ON without host intervention. A device supporting the Auto mode might either be connected to a host (Managed Auto mode) or be used as a stand-alone system without any control interface (Unmanaged Auto mode). The following tasks are supported in the Auto mode:

Autonomous detection, classification, power-up, and power-on ports based on configuration pins
Device-Level matrix configuration

5.1.3.1 Managed Auto Mode

In the Managed Auto mode, the device has initial PSE configuration with which the system can be operated without the need for host communication. However, host communication allows subsequent changes to the PSE configuration. The following figure shows the host-controlled Managed Auto mode application. Figure 5-3. Host-Controlled Managed Auto Mode Applic ation AUTO RB PD77728 PD77728 PD77728 PD77728 OSS (optional) RESET_IN_N A1 – A4: Set I2C device address 0 1 2 3 4 5 6 7 port_neg 0 1 2 3 4 5 6 7 port_neg 0 1 2 3 4 5 6 7 port_neg 0 1 2 3 4 5 6 7 port_neg VMAIN VMAINVMAINVMAIN 3.3V 3.3V 3.3V 3.3V 10K Isolation Barrier I2C iso dig iso 10K10K10K RESET_IN_N OSS RESET_IN_N OSS RESET_IN_N OSS RESET_IN_N OSS SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO SDIO SCLIO I2C_OUT_SDA I2C_OUT_SCL SDA SCL OSS xRESET_OUT Host Processor xINT_IN INT_OUT_N (optional) INT_OUT_N INT_OUT_N INT_OUT_N INT_OUT_N ... AUTO RB AUTO RB AUTO RB

5.1.3.2 Unmanaged Auto Mode

In the Unmanaged Auto mode, the device is a stand-alone system. There is no host I2C communication to the device. All PSE configurations are stored within the system and are available to the device (s) without host communication. This is the typical application of a single device system. More than one device may be employed in this type of system, but each device operates interdependently of other devices. The following figure shows the Unmanaged Auto mode application. Figure 5-4. Unmanaged Auto Mode Applic ation 0 1 2 3 4 5 6 7 port_neg VMAIN 3.3V AUTO RESET_IN_N 10K RB 3.3V AA11–– AA4 4:: Set I2C device address PD77728 The following table lists the values of the resistor RB that are used to set the PSE type. Table 5-1. AUTO Pin Con figur ation Level Level Range (V) Mode RB (kΩ) Set Value (V) 0 0–0.278 Class8 0.442 0.140 1 0.279–0.557 Class7 1.47 0.423 2 0.558–0.847 Class6 2.67 0.695 3 0.847–1.115 Class5 4.22 0.979 4 1.115–1.393 Class4–4P 6.19 1.262 5 1.394–1.693 Class4–2P 8.87 1.551 6 1.694–1.951 Class3–2P 12.4 1.827 7 1.951–2.23 AUTO mode disabled > 17.4 or open 2.096 Note: A 10KΩ resistor from 3.3V to AUTO pin is the top resistor value, RTOP, which along with RB creates the required voltage level at AUTO pin input.

5.2 I2C

The port I2C address is programmed through pins A1, A2, A3, and A4 (pins 48–51). Tie each pin to VDD or DGND to set the I2C address, as listed in the following table. Note: The I2C address is a 7-bit address. Table 5-2. I2C Address Select A4 A3 A2 A1 Ports I2C Address 0 0 0 0 0–3 0x20 4–7 0x21 0 0 0 1 0–3 0x22 4–7 0x23 0 0 1 0 0–3 0x24 4–7 0x25 0 0 1 1 0–3 0x26 4–7 0x27 0 1 0 0 0–3 0x28 4–7 0x29 0 1 0 1 0–3 0x2A 4–7 0x2B 0 1 1 0 0–3 0x2C 4–7 0x2D 0 1 1 1 0–3 0x2E 4–7 0x2F 1 0 0 0 0–3 0x30 4–7 0x31 1 0 0 1 0–3 0x32 4–7 0x33 1 0 1 0 0–3 0x34 4–7 0x35 1 0 1 1 0–3 0x36 4–7 0x37 1 1 0 0 0–3 0x38 4–7 0x39 1 1 0 1 0–3 0x3A 4–7 0x3B 1 1 1 0 0–3 0x3C 4–7 0x3D 1 1 1 1 0–3 0x3E 4–7 0x3F

Applic ation In f ormation Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 25 5.3 2-Pair and 4-Pair (2P/4P) Oper ation The IEEE 802.3bt standard introduces the ability to drive a PD (that supports this mode) by using four pairs and allowing higher PD power support. The IEEE 802.3bt standard discusses the 4P definition from a logical port point of view. That is, a port in the IEEE 802.3bt standard can operate either in 2P mode or in 4P mode. A PD that can accept power on both ALT-A and ALT-B at the same time is regarded as a single 4P-capable PD. 5.3.1 2P Oper ation PSE port can operate over two pairs, that is, only two pairs are used to actively deliver power to the PD, either on ALT-A or ALT- B, but not both. This is allowed when the assigned class is 0 to 4. A 2P operation uses a single physical port that is considered as a logical port. 5.3.2 4P Oper ation When the assigned class is 5 to 8, the PSE port must deliver the power over four pairs. When operating in 4P, powered is delivered to the PD on both pairsets (ALT-A and ALT-B), that is, two physical ports are combined to create a single logical 4P port required for the 4P operation. When operating in the 4P mode, the two physical ports that create the one logical four pair port must be chosen from the same physical PD77728 IC. In addition, the logical 4P port must be created from the same physical port group (0, 1, 2, and 3) or (4, 5, 6, and 7). For example, a logical 4P port from physical ports 0 and 3 is allowed, but a logical 4P port from physical ports 0 and 4 is not allowed.

5.4 PD77728 Communic ation Interface

The I2C interface is the communication interface between PD77728 and PD77020. In the Semi-Auto and the Managed Auto modes, communication between PD77728 and the host processor is also through I2C. For more detailed information, see PD77728 Register Map.

5.5 OSS Pin Behavior

The OSS pin can be used to turn off groups of ports based on the signal type received on the pin. The OSS pin has two modes of operation:

Single-Bit Priority Shutdown mode
Multi-Bit Priority Shutdown mode The OSS pin mode of operation is set in register MISC (0x17) bit [4]. The default value of the OSS pin is Single-Bit Priority Shutdown mode.

5.5.1 Single-Bit Priority Shutdown Mode

To enable the Single-Bit Priority Shutdown, bit [4] in register MISC (0x17) must be set to 0 (Default). In this mode of operation, a rising edge of the OSS hardware pin shuts down low priority ports:

Powered ports are turned off
Unpowered ports stop detection
If the OSS bit is asserted, then the low priority ports do not perform detection
Once OSS is back to low level, all low priority ports resume detection Low-priority ports are defined by writing to register PWRPR (0x15) bits [7:4] (Port Power Priority). This register sets the ports to be turned off if OSS is asserted. In the Auto mode, the low priority ports that are turned off are automatically re-enabled after OSS has cleared. In the Controller mode, the low priority ports that are turned off are automatically re-enabled based on the value written in register Detect/Class Enable (0x14) bits [3:0].

Applic ation In f ormation Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 26 In the Semi-Auto mode, the host must re-enable Detection and Classification. Note: Do not clear bits [3:0] of register Detect/Class Enable (0x14) during the assertion of OSS. The following events occur when the OSS pin is set:

OSS event (bit [1]) in register SUPPLY (registers 0x0A, 0x0B) and Supply Event (bit [7]) in Interrupt register (0x00) are set.
Ports that are on and assigned as low-priority ports, are turned off.
Ports that were turned off, set the corresponding Power Good and Power Enable bits in Power register (0x10).
Ports that are not on, but perform detection and class and are assigned as low priority ports, stop detection and classification without reporting any bit. Figure 5-5. OSS Pin Single-Bit Priority Shutdown Mode Timing 3.3V ON OFF TOSS-OFF Low priority group Ports are OFF, detection is disable Low priority group ports are ON Low priority group Ports are OFF, detection is enabled

5.5.2 Multi-Bit Priority Shutdown Mode

The Multi-Bit Priority Shutdown mode has the following characteristics:

3-bit priority for every port
Each bit has a length of T BIT-OSS
Idle state of OSS pin is low level (0)
A start-bit comprising of transition from 0 (IDLE) to 1 back to 0 precedes the data
000 is the highest priority (reducing as the bit value increases) The OSS mode is set to the Multi-Bit Priority mode by setting Multi Bit Priority (bit [4]) in the MISC register (0x17). Multi-bit power priority code is set in Multi-bit Power Priority registers (0x27, 0x28). Port power priority field in register PWRPR (register 0x15 bits [7:4]) are ignored. If the host selects certain priority ports to be turned off, then it sends the relevant shutdown code on the OSS, based on the timing diagram shown in Figure 5-6. The PD77728 device compares the code received on OSS with the power priority of each port (as defined by registers 0x27 and 0x28) and shuts down the ports which are less than or equal to the received priority. Then, the PD77728 device returns to normal operation, that is, ports that were turned off due to OSS shut-down event immediately restart detection. These ports are re-enabled for detection. Ports that are not on, but perform detection/classification, and are assigned to the priority code, are not interrupted. The following events occur when the OSS code is received:

OSS event (bit [1]) in register SUPPLY (registers 0x0A, 0x0B) and Supply Event (bit [7]) in the Interrupt register (0x00) are set.
Ports that are on and assigned as corresponding OSS code, are turned off
Ports that are turned off, set the corresponding Power Good and Power Enable bits in the Power register (0x10).
Ports that are not on and assigned with the corresponding OSS code, continue to perform uninterrupted detection and classification. The following figure shows the OSS pin Multi-Bit Priority Shutdown mode timing. Figure 5-6. OSS Pin Multi-Bit Priority Shutdown Mode Timing TOSS-BIT 25µs TOSS-BIT 25µs defines the start bit 3.3V 3 bits of data (each either “1” or “0”) Priority group ports are ON ON OFF TOSS-BIT 25µs TOSS-BIT 25µs TOSS-OFF TOSS-IDLE TOSS-BIT 25µs Priority group ports are OFF The following table lists the OSS Pin Multi-Bit Priority Shutdown mode parameters. Table 5-3. OSS Pin Multi-Bit Priority Shutdown Mode Parameters Parameter Description Min. Typ. Max. Unit TBIT-OSS OSS bit period 24 25 26 µs TOSS-OFF Time between receiving shutdown code and shutting down of ports. 1 — 50 µs TOSS-IDLE Idle time between consecutive shutdown code transmission in the Multi-Bit mode. — 50 — µs Notes:
If only one of the IC’s addresses is configured to multi-bit, then the configuration is applied on both sub-chips.
There is no support for single bit and multi bit on the same IC.
In the Multi-Bit Priority mode, if OSS I/O has changed but a valid start-bit is not detected, then the OSS event is discarded.
OSS priority table is rebuilt every 3 ms. Therefore, it might take up to 3 ms for a new configuration to take place.
The OSS priority table is locked against changes during an OSS event.

5.6 Compliance to Limited Power Source Requirements

The Microchip PD77728 PoE manager fulfills Limited Power Source (LPS) requirements per IEC/UL/ EN62368-1. In other words, the PD77728 device is an IC current limiter that is used for current limiting the output of the power source in accordance with the requirements of an LPS. As per IEC62368-1 Ed.2, if the system power supply exceeds 250 VA, then the PD77728 device is shorted during compliance testing. Therefore, an external current limiter or per-port fuse is required. If the total system power is less than 250 VA, then the PD77728 device is not shorted during compliance testing and LPS requirements are met by virtue of the PD77728 device being an IC current limiter. As per IEC62368-1 Ed.3, the IC current limiters used for current limiting in power sources are not shorted from input to output if they comply with all of the following:

The IC current limiters limit the current to manufacturer’s defined value which must be less than 5A under normal operating conditions with any specified drift accounted for.
The IC current limiters are entirely electronic and have no means of manual operation or reset.
The IC current limiters output current is limited to 5A or less (specified maximum load). This implies that per port fuses might not be required to meet IEC62368-1 Ed3. The compliance requirements are as follows:
If a system is intended to meet IEC62368-1Ed2: Per port fuse is required if the total system power > 250 VA.
If a system is intended to meet IEC62368-1Ed2: Per port fuse is not required if the total system power is < 250 VA.
If a system is intended to meet IEC62368-1Ed3: Per port fuse may not be required. For additional details, request for Microchip AN3527 Compliance to Limited Power Source Requirements. These statements are Microchip’s good faith interpretation of the IED62368-1 standard. Consult IEC or equivalent agency and the IEC62368-1 Ed2/Ed3 standards for official positions with respect to this topic.

© 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 29 6. Package Specific ations This device is a 56-lead very thin plastic quad flat, no lead package (KDC), 8 mm x 8 mm x 0.9 mm body [VQFN] with depopulated terminals and 5.5 mm2 exposed pad. For latest package drawings, see Microchip Package Drawings. Figure 6-1. Package Outline Drawing (POD) BA 0.10 C 0.10 C

0.10 C A B

0.05 C C 2X TOP VIEW SIDE VIEW BOTTOM VIEW 0.10 C 0.08 C 16X (DATUM B) (DATUM A) SEATING PLANE K D E e e 50X b 0.21 A

© 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 30 Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.50 BSC

0.203 REF

0.30 0.20 0.80 0.00 0.25 0.40 0.85 0.035

8.00 BSC

0.50 0.30 0.90 0.05 MAX K–Terminal-to-Exposed-Pad Overall Length Exposed Pad Length D D2 5.40 5.50 5.60 REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M 5.40 5.50 5.60 0.70 –

6.1 Recommended PCB Layout

The following figures show the recommended PCB layout of the PD77728 device. Note: All figure dimensions are in mm. Figure 6-2. Solder Mask (Component Side) 8.593 6.906 0.406 0.500 0.094 0.864 5.680 5.680 8.000 8.000 Figure 6-3. Solder Mask (Print Side) 5.680 5.680

© 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 33 Figure 6-5. Paste Mask (Component Side) 8.262 6.779 0.278 0.500 0.221 1.5801.930 8.000 8.000 Ø0.050 Minimum Radius All Corners0.140x45° 8.262 6.779 0.278 0.500 0.221 1.5801.930 8.000 8.000 Ø0.050 Minimum Radius All Corners0.140x45° Note: Use a 5 mil stencil.

6.2 Thermal Pr operties

The following table lists the thermal properties of the device. Table 6-1. Thermal Pr operties 1 Parameter Symbol Typical Unit Junction-to-ambient thermal resistance ϴJA 21.03 °C/W Junction-to-case (top) thermal resistance ϴJC(TOP) 10.04 °C/W Junction-to-board thermal resistance ϴJB 4.12 °C/W Junction-to-top characterization parameter ψJT 0.334 °C/W Note: 1. Using the JESD51-7 test board.

6.3 Recommended Solder R e flo w In f ormation

The following list shows the solder reflow information:

RoHS 6/6
Pb-free 100% Matte Tin Finish
Package Peak Temperature for Solder Reflow (40s maximum exposure)—260 °C (0 °C, –5 °C) The following tables list the classification reflow profile and Pb-Free Process—package classification reflow temperature details. Table 6-2. Classific ation R e flo w Pr ofile Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (TSMAX to TP) 3 °C/s maximum 3 °C/s maximum Preheat Temperature min (TSMIN) 100 °C 150 °C Temperature max (TSMAX) 150 °C 200 °C Time (tsMIN to tsMAX) 60s to 120s 60s to 180s Time Maintained Temperature (TL) 183 °C 217 °C Time (tL) 60s to 150s 60s to 150s Peak classification temperature (TP) 210 °C to 235 °C 240 ℃ to 255 °C Time within 5 °C of actual peak temperature (tP) 10s to 30s 20s to 40s Ramp-down rate 6 °C/s maximum 6 °C/s maximum Time 25 °C to peak temperature 6 minutes maximum 8 minutes maximum Table 6-3. Pb-Free Process—Package Classific ation R e flo w Temperatures Package Thickness Volume < 350 mm3 Volume 350–2000 mm3 Volume > 2000 mm3 Less than 1.6 mm 260 + 0 °C 260 + 0 °C 260 + 0 °C 1.6 mm to 2.5 mm 260 + 0 °C 250 + 0 °C 245 + 0 °C The following figure shows the classification reflow profile. Figure 6-7. Classific ation R e flo w Pr ofile

Tape and Reel Specific ations Data Sheet © 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 37 Dimension Value (mm) Width 16.00 ±0.30 The following figure shows the reel specifications of the PD77728 device. Figure 7-3. Reel Specific ation The following table lists the reel mechanical data details of the PD77728 device. Table 7-2. Reel Mechanical Data Dimensions Value (mm) Value (inch) Tape size 16.00 ±0.3 0.630 ±0.012 A maximum 330 13 B maximum 1.5 0.059 C 13.0 ±0.20 0.512 ±0.008 D minimum 20.2 0.795 N minimum 50 1.968 T maximum 29 1.142 Note: Base quantity: 2000 pieces

© 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 38 8. Ordering In f ormation The following table lists the part ordering information of the device. Table 8-1. Ordering In f ormation Part Number Package Packaging Type Temperature Part Marking PD77728ILQ-VVVV1-TR Plastic QFN 8 mm × 8 mm (56 lead) Tape and Reel −40 °C to 85 °C Microchip Logo PD77728 e3 Arm® YYWWNNN2 Notes: 1. VVVV = Firmware version 2. YY = Year, WW = Week, and NNN = Trace code.

PD77020 PoE PSE Power Management Controller Data Sheet
AN4896 Designing an IEEE® 802.3bt/at/af PoE System Based on PD77728
AN4813 Surge Protection for Systems Based on PD777xx 8-Port PSE PoE Manager
PD77728 Auto Mode Register Map
AN4952 PD777xx PSE Firmware Download and Replace Flow
PD77728 Auto Mode Evaluation Board User Guide

Revision History

© 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 40 10. Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Table 10-1. Revision History Revision Date Description E 07/2024 The following is the summary of changes made in this revision:

Updated the following tables: – Table 3-5 – Table 3-6 – Table 3-11
Added the following tables: – Table 3-17 – Table 3-18
Updated Figure 5-1 D 05/2023 The following is the summary of the changes made in this revision:
Updated the following figures: – Figure 5-1 – Figure 5-2 – Figure 5-3 – Figure 5-4
Edited 8. Ordering Information
Edited Table 3-5 C 03/2023 The following is the summary of the changes made in this revision:
Re-defined 5.1. Operational Modes
Added 5.5. OSS Pin Behavior
Updated descriptions of Over voltage and T CUT/ICUT Protection in 1.6.4. Over-Temperature (OVT) Protection and 1.6.5. TCUT/ICUT Protection respectively.
Added additional Surge Protection information in 1.9. Surge
Incorporated minor editorial changes throughout the document. B 08/2022 Added and revised all the sections, and updated information regarding functional descriptions, electrical specifications, and pin descriptions throughout the document to align with device performance. A 05/2021 This is a preliminary version of the data sheet.

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© 2024 Microchip Technology Inc. and its subsidiaries DS00003920E - 43 All other trademarks mentioned herein are property of their respective companies. © 2024, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. ISBN: 978-1-6683-4877-2 Quality Management System For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

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Product Information

PD77728 specifications and overview.

Summary

8-Port PoE PSE Manager Revision E Date 07/2024

Description

8-Port PoE PSE Manager Revision E Date 07/2024

Source title PD77728 Datasheet(PDF) - Microchip Technology

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