PD75104

UPD75104 NEC | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 3.1 PORT PINS
• 3.2 PINS OTHER THAN PORTS
• 3.3 PIN INPUT/OUTPUT CIRCUITS
• 3.4 RECOMMENDED PROCESSING OF UNUSED PINS
• 3.5 NOTES ON USING THE P00/INT4, AND RESET PINS
• 5.1 PORTS
• 5.2 CLOCK GENERATOR CIRCUIT
• 5.3 CLOCK OUTPUT CIRCUIT
• 5.4 BASIC INTERVAL TIMER
• 5.5 TIMER/EVENT COUNTER
• 5.6 SERIAL INTERFACE
• 5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)
• 5.9 POWER-ON FLAG (MASK OPTION)

DESCRIPTION

µPD75108 is a 4-bit single-chip microcomputer integrating timer/event counters, serial interface, and vector interrupt function, in addition to a CPU, ROM, RAM, and I/O ports, on a single chip. Operating at high speeds, the microcomputer allows data to be manipulated in units of 1, 4, or 8 bits. In addition, various bit manipulation instructions are provided to reinforce I/O manipulation capability. Equipped with I/Os for interfacing with peripheral circuits operating on a different supply voltage, outputs that can directly drive LEDs, and analog inputs, µPD75108 is suitable for controlling such systems as VTRs, acoustic products, button telephones, radio communications equipment, and printers. A pin-compatible EPROM model is also available for evaluation of system development and small-scale production of application systems. Detailed functions are described in the following user’s manual. Be sure to read it for designing. µPD751XX Series User’s Manual: IEM-922

FEATURES

• Internal memory
• Program memory (ROM) : 8068 × 8 bits ( µPD75108) : 6016 × 8 bits ( µPD75106) : 4096 × 8 bits ( µPD75104)
• Data memory (RAM) : 512 × 4 bits ( µPD75108) : 320 × 4 bits ( µPD75106, 75104)
• New architecture “75X series” rivaling 8-bit microcomputers
• 43 systematically organized instructions
• A wealth of bit manipulation instructions
• 8-bit data transfer, compare, operation, increment, and decrement instructions
• 1-byte relative branch instructions
• GETI instruction executing 2-/3-byte instruction with one byte
• High speed. Minimum instruction execution time: 0.95 µs (at 4.19 MHz), 5 V
• Power-saving, instruction time change function: 0.95 µs/1.91 µs/15.3 µs (at 4.19 MHz)
• I/O port pins as many as 58
• Three channels of 8-bit timers
• 8-bit serial interface
• Multiplexed vector interrupt function
• Model with PROM is available: µPD75P108B (One-time PROM, EPROM)  NEC Corporation 1989 Document No. IC-2520B (O. D. No. IC-6906B) Date Published January 1994 P Printed in Japan DATA SHEET MOS INTEGRATED CIRCUIT µPD75104, 75106, 75108 4-BIT SINGLE-CHIP MICROCOMPUTER The mark H shows major revised points. The information in this document is subject to change without notice. Unless there are differences among µPD75104, 75106, and 75108 functions, µPD75108 is treated as the representative model throughout this manual.

µPD75104, 75106, 75108

ORDERING INFORMATION

Part Number Package Quality Grade µPD75104CW-xxx 64-pin plastic shrink DIP (750 mil) Standard µPD75104GF-xxx-3BE 64-pin plastic QFP (14 × 20 mm) Standard µPD75106CW-xxx 64-pin plastic shrink DIP (750 mil) Standard µPD75106GF-xxx-3BE 64-pin plastic QFP (14 × 20 mm) Standard µPD75108CW-xxx 64-pin plastic shrink DIP (750 mil) Standard µPD75108GF-xxx-3BE 64-pin plastic QFP (14 × 20 mm) Standard Remarks : xxx is ROM code number. Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

µPD75104, 75106, 75108 FUNCTIONAL OUTLINE Item Specifications Number of Basic Instructions 43 Minimum Instruction Changeable in three steps: 0.95 µs, 1.91 µs, and 15.3 µs at 4.19 MHz Execution Time ROM 8064 × 8 bits (µPD75108), 6016 × 8 bits (µPD75106), 4096 × 8 bits (µPD75104) RAM 512 × 4 bits (µPD75108), 320 × 4 bits (µPD75106, 75104) General-Purpose Register 4 bits × 8 × 4 banks (memory mapped) Three accumulators selectable according to the bit length of manipulated data:

• 1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA) 58 port pins
• CMOS input pins: 10 I/O Port • CMOS I/O pins (can directly drive LEDs): 32
• Medium voltage N-ch open-drain I/O pins: 12 (can directly drive LEDs. Pull-up resistor can be connected to each bit)
• Comparator input pins (4-bit accuracy): 4
• 8-bit timer/event counter × 2Timer/Counter • 8-bit basic interval timer (can be used as watchdog timer)
• 8 bits Serial Interface • LSB first/MSB first mode selectable
• Two transfer modes (transfer/reception and reception only modes) Vector Interrupt External: 3, Internal: 4 Test Input External: 2 Standby • STOP and HALT modes
• Various bit manipulation instructions (set, reset, test, Boolean operation) Instruction Set • 8-bit data transfer, compare, operation, increment, and decrement
• 1-byte relative branch instructions
• GETI instruction constituting 2 or 3-byte instruction with 1 byte
• Power-ON reset circuit (mask option)Others • Bit manipulation memory (bit sequential buffer: 16 bits) Package • 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 20 mm) Internal Memory Accumulator

µPD75104, 75106, 75108

µPD75104, 75106, 75108 1. PIN CONFIGURATION (Top View)

• 64-Pin Plastic Shrink DIP (750 mil) P13/INT3 1 V3 2 V64 SS µPD75104CW- PD75106CW- PD75108CW- ××× P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 PTH01 PTH00 TI0 TI1 P23 P22/PCL P21 PTO1 13 P20 PTO0 14 P9063 P9162 P9261 P9360 P8059 P8158 P8257 P8356 P7055 P7154 P7253 P7352 P6051 P03/SI 15 P61 50 P02/SO 16 P62 49 P01/SCK 17 P63 48 P00/INT4 18 X1 47 P123 19 X2 46 P122 20 RESET 45 P121 21 P50 44 P120 22 P51 43 P133 23 P52 42 P132 24 P53 41 P131 25 P40 40 P130 26 P41 39 P143 27 P42 38 P142 28 P43 37 P141 29 P30 36 P140 30 P31 35 NC 31 P32 34 DD µµ P33

51 P1311P41 64

V NC P140 P141 P142 P143 P130 63 62 61 60 59 58 57 56 55 54 53 52 DD 20 21 22 23 24 25 26 27 28 29 30 31 32 P81 P80 P93 P92 P91 P90 V P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02 SS µPD75104GF- PD75106GF- PD75108GF- ××× µµ -3BE -3BE -3BE

50 P1322P40

49 P1333P53

48 P1204P52

47 P1215P51

46 P1226P50

45 P1237RESET

44 P00/INT48X2

43 P01/SCK9X1

42 P02/SO10P63

41 P03/SI11P62

40 P20/PTO012P61

39 P21/PTO113P60

38 P22/PCL14P73

37 P2315P72

36 TI116P71

35 TI017P70

34 PTH0018P83

33 PTH0119P82

• 64-Pin Plastic QFP (14 × 20 mm)

µPD75104, 75106, 75108 Pin names P00-P03 : Port 0 SCK : Serial Clock Input/Output P10-P13 : Port 1 SO : Serial Output P20-P23 : Port 2 SI : Serial Input P30-P33 : Port 3 PTO0, PTO1 : Timer Output P40-P43 : Port 4 PCL : Clock Output P50-P53 : Port 5 PTH00-PTH03 : Comparator Input P60-P63 : Port 6 INT0, INT1, INT4 : External Vector Interrupt Input P70-P73 : Port 7 INT2, INT3 : External Test Input P80-P83 : Port 8 TI0, TI1 : Timer Input P90-P93 : Port 9 X1, X2 : Clock Oscillation Pin P120-P123 : Port 12 RESET : Reset Input P130-P133 : Port 13 NC : No Connection P140-P143 : Port 14

µPD75104, 75106, 75108 2. BLOCK DIAGRAM TI0 PTO0/P20 BASIC INTERVAL TIMER INTBT PROGRAM COUNTER* ALU CY SP (8) BANK GENERAL REG. DECODE AND CONTROL ROM PROGRAM MEMORY 8064 8BITS : PD75108 6016 8BITS : PD75106 4096 8BITS : PD75104µ µ µ RAM DATA MEMORY 512 4BITS : PD75108 320 4BITS : PD75106, 75104 × × µ µ f /2XX N CPU CLOCK Φ PCL/P22 X1 X2 V DD VSS RESET CLOCK OUTPUT CONTROL CLOCK DIVIDER CLOCK GENERATOR STAND BY CONTROL TIMER/EVENT COUNTER TIMER/EVENT COUNTER SERIAL INTERFACE INTERRUPT CONTROL PROGRAM- MABLE THRESHOLD PORT #0 TI1 PTO1/P21 SI/P03 SO/P02 SCK/P01 INT0/P10 INT1/P11 INT2/P12 INT3/P13 INT4/P00 PTH00-PTH03 4 BIT SEQ. BUFFER (16) PORT 0 P00 - P03 P10 - P13PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 PORT 8 PORT 9 PORT 12 PORT 13 PORT 14 P20 - P23 P30 - P33 P40 - P43 P50 - P53 P60 - P63 P70 - P73 P80 - P83 P90 - P93 P120 - P123 P130 - P133 P140 - P143 *: 13 bits: PD75106, 75108 12 bits: PD75104 µ µ INTT0 INTT1 INTSIO

µPD75104, 75106, 75108 3. PIN FUNCTIONS

3.1 PORT PINS

Pin Name I/O Shared with: Function At Reset Circuit TYPE*1 P00 Input INT4 B P01 I/O SCK F 4-bit input port (PORT 0) Input P02 I/O SO E P03 Input SI B x P10 INT0 P11 INT1 Input 4-bit input port (PORT 1) Input B P12 INT2 P13 INT3 P20*3 PTO0 P21*3 PTO1 I/O 4-bit I/O port (PORT 2) Input E P22*3 PCL x P23*3 — 4-bit programmable I/O port (PORT 3) P30-P33* 3 I/O — Input E Can be specified for input or output bitwise. P40-P43* 3 I/O — 4-bit I/O port (PORT 4) Input E o P50-P53* 3 I/O — 4-bit I/O port (PORT 5) Input E 4-bit programmable I/O port (PORT 6) P60-P63* 3 I/O — Input E Can be specified for input or output bitwise. o P70-P73* 3 I/O 4-bit I/O port (PORT 7) Input E P80-P83* 3 I/O — 4-bit I/O port (PORT 8) Input E o P90-P93* 3 I/O — 4-bit I/O port (PORT 9) Input E 4-bit N-ch open-drain I/O port (PORT 12) Built-in pull-up resistors can be specified in bit P120-P123*

3 I/O —

units by mask option. Open-drain withstanding voltage: 12 V o 4-bit N-ch open-drain I/O port (PORT 13) Built-in pull-up resistors can be specified in bit P130-P133*3 I/O — units by mask option. Open-drain withstanding voltage: 12 V 4-bit N-ch open-drain I/O port (PORT 14) Built-in pull-up resistors can be specified in bit P140-P143*

3 I/O — – Input* 2 M

units by mask option. Open-drain withstanding voltage: 12 V *1: Circles indicate Schmitt trigger input pins. 2: With drain open: high impedance With pull-up resistor connected: high level 3: Can directly drive LEDs. 8-Bit I/O Input*2 M Input*2 M

µPD75104, 75106, 75108

3.2 PINS OTHER THAN PORTS

Pin Name I/O Shared with: Function At Reset Circuit TYPE*1 PTH00-PTH03 Input — 4-bit variable threshold voltage analog input port — N TI0 External event pulse inputs for timer/event counter. Input — Also serves as edge-detected vector interrupt input. — B TI1 1-bit input also possible. PTO0 P20 I/O Outputs for timer/event counter Input E PTO1 P21 SCK I/O P01 Serial clock I/O Input F SO I/O P02 Serial data output Input E SI Input P03 Serial data input Input B Edge-detected vectored interrupt input (both rising and INT4 Input P00 Input B falling edges detected) INT0 P10 Edge-detected vectored interrupt inputs (valid Input Input B INT1 P11 edge selectable) INT2 P12 Input Edge-detected testable inputs (rising edge detected) Input B INT3 P13 PCL I/O P22 Clock output Input E Crystal/ceramic system clock oscillator connections. X1, X2 — — Input external clock to X1, and signal in reverse phase — — with X1 to X2. RESET Input — System reset input (low level active type) — B NC*2 — — No Connection — — VDD — — Positive power supply — — VSS —— G N D —— *1: Circles indicate Schmitt trigger input pins. 2: Connect the NC pin directly to the V DD pin when µPD75P108B and a printed circuit board are shared.

µPD75104, 75106, 75108

3.3 PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the µPD75108. TYPE A TYPE E TYPE B TYPE F IN VDD Input buffer of CMOS standard P–ch N–ch IN Schmitt trigger input with hysteresis characteristics data output disable Type D Type A IN/OUT TYPE D TYPE M data output disable Type D Type B IN/OUT data output disable OUT Push – pull output that can be set in a output high– impedance state (both P–ch and N–ch are off) VDD P-ch N-ch I/O circuit consisting of Type D push-pull output circuit and Type A input buffer I/O circuit consisting of Type D push-pull output and Type B Schmitt trigger input VDD P.U.R. (mask option) IN/OUT data output disable N-ch (+12 V withstand) Medium-voltage input buffer (+12 V withstand) P.U.R.: Pull-Up Resistor

µPD75104, 75106, 75108 TYPE N IN + Comparator V (threshold voltage)REF

3.4 RECOMMENDED PROCESSING OF UNUSED PINS

Pin Recommended connections PTH00-PTH03 TI0 Connect to V SS or V DD TI1 P00 Connect to V SS P01-P03 Connect to V SS or V DD P10-P13 Connect to V SS P20-P23 P30-P33 P40-P43 P50-P53 P60-P63 Input: Connect to V SS or V DD P70-P73 P80-P83 Output: Open P90-P93 P120-P123 P130-P133 P140-P143 RESET* 1 Connect to V DD NC*2 Open *1: Connect this pin to the V DD pin only when a power-ON reset circuit is provided as a mask option. 2: Connect the NC pin to the V DD pin when µPD75P108 and a printed circuit board are shared.

µPD75104, 75106, 75108

3.5 NOTES ON USING THE P00/INT4, AND RESET PINS

In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the µPD75108 are tested (solely used for IC tests), is provided to the P00/INT4 and RESET pins. If a voltage exceeding V DD is applied to either of these pins, the µPD75108 is put into test mode. Therefore, even when the µPD75108 is in normal operation, if noise exceeding the V DD is input into any of these pins, the µPD75108 will enter the test mode, and this will cause problems for normal operation. As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur. Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below.

• Connect a capacitor across P00/INT4 and RESET, and V DD.
• Connect a diode across P00/INT4 and RESET, and V DD. VDD VDD P00/INT4, RESET VDD VDD P00/INT4, RESET

µPD75104, 75106, 75108 4. MEMORY CONFIGURATION

• Program memory (ROM) ... 8064 × 8 bits (0000H-1F7FH) : µPD75108 ... 6016 × 8 bits (0000H-177FH) : µPD75106 ... 4096 × 8 bits (0000H-0FFFH) : µPD75104
• 0000H, 0001H : Vector table to which address from which program is started is written after reset
• 0002H-000BH: Vector table to which address from which program is started is written after interrupt
• 0020H-007FH : Table area referenced by GETI instruction
• Data memory (RAM)
• Data area ....512 × 4 bits (000H–1FFH): µPD75108 320 × 4 bits (000H-13FH) : µPD75106, 75104
• Peripheral hardware area .... 128 × 4 bits (F80H–FFFH)

µPD75104, 75106, 75108 (a) µ PD75108 765 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) INT0/INT1 start address (upper 5 bits) INT0/INT1 start address (lower 8 bits) INTSIO start address (upper 5 bits) INTSIO start address (lower 8 bits) INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) 0000H 0002H 0004H 0006H 0008H 000AH 0020H 007FH 0080H 07FFH 0800H 0FFFH 1000H 1F7FH GETI instruction reference table BRCB ! caddr instruction branch address CALLF ! faddr instruction entry address BR ! addr instruction branch address CALL ! addr instruction subroutine entry address BR $addr instruction relational branch address (–15 to –1, +2 to +16) Branch destination address and subroutine entry address for GETI instruction Address BRCB ! caddr instruction branch address Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. Fig. 4-1 Program Memory Map (1/3)

µPD75104, 75106, 75108 (b) µ PD75106 Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. Fig. 4-1 Program Memory Map (2/3) 765 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 Internal reset start address (upper 5 bits) Internal reset start address (lower 8 bits) INTBT/INT4 start address (upper 5 bits) INTBT/INT4 start address (lower 8 bits) INT0/INT1 start address (upper 5 bits) INT0/INT1 start address (lower 8 bits) INTSIO start address (upper 5 bits) INTSIO start address (lower 8 bits) INTT0 start address (upper 5 bits) INTT0 start address (lower 8 bits) INTT1 start address (upper 5 bits) INTT1 start address (lower 8 bits) 0000H 0002H 0004H 0006H 0008H 000AH 0020H 007FH 0080H 07FFH 0800H 0FFFH 1000H 177FH GETI instruction reference table BRCB ! caddr instruction branch address CALLF ! faddr instruction entry address BR ! addr instruction branch address CALL ! addr instruction subroutine entry address BR $addr instruction relational branch address (–15 to +16) Branch destination address and subroutine entry address for GETI instruction Address BRCB ! caddr instruction branch address

µPD75104, 75106, 75108 (c) µ PD75106 765 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 MBE RBE 0 Internal reset start address (upper 4 bits) Internal reset start address (lower 8 bits) INTBT/INT4 start address (upper 4 bits) INTBT/INT4 start address (lower 8 bits) INT0/INT1 start address (upper 4 bits) INT0/INT1 start address (lower 8 bits) INTSIO start address (upper 4 bits) INTSIO start address (lower 8 bits) INTT0 start address (upper 4 bits) INTT0 start address (lower 8 bits) INTT1 start address (upper 4 bits) INTT1 start address (lower 8 bits) 000H 002H 004H 006H 008H 00AH 020H 07FH 080H 7FFH 800H FFFH GETI instruction reference table CALLF ! faddr instruction entry address BRCB ! caddr instruction branch address CALL ! addr instruction subroutine entry address Address BR $addr instruction relational branch address (–15 to +16) Branch destination address and subroutine entry address for GETI instruction Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction. Fig. 4-1 Program Memory Map (3/3)

µPD75104, 75106, 75108 (a) µ PD75108 000H 01FH 0FFH 100H 1FFH F80H FFFH Data memory Memory bank (32 × 4) 256× 4 Not provided 128× 4 Bank 0 General-purpose register area Stack area Data memory Static RAM (512× 4) Peripheral hardware area 256× 4 Bank 1 Bank 15 Fig. 4-2 Data Memory Map(1/2)

µPD75104, 75106, 75108 (b) µ PD75106, 75104 000H 01FH 0FFH 100H 13FH F80H FFFH Data memory Memory bank (32 × 4) 256× 4 Not provided 128× 4 Bank 0 General-purpose register area Stack area General- purpose Static RAM (320× 4) Peripheral hardware area 64 × 4 Bank 1 Bank 15 Fig. 4-2 Data Memory Map(2/2)

µPD75104, 75106, 75108 5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

I/O ports are classified into the following 3 kinds:

• CMOS input (PORT0, 1) : 8
• CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9) : 32
• N-ch open-drain input/output (PORT12, 13, 14) :1 2 Total : 52 PORT0 PORT1 PORT3 PORT6 PORT2 PORT4 PORT5 PORT7 PORT8 PORT9 PORT12 PORT13 PORT14 Function 4-bit input 4-bit I/O* 4-bit I/O* (N-ch open- drain. 12V) Table 5-1 Port Function Operation and Features Can always be read or tested regardless of opera- tion mode of shared pin Can be set in input or output mode bitwise Can be set in input or output mode in units of 4 bits. Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs to input or output 8-bit data Can be set in input or output mode in units of 4 bits. Ports 12 and 13 can be used in pairs to input or output 8-bit data Port (Symbol) Remarks Shared with SI, SO, SCK, and INT0 to 4 pins Port 2 pins are shared with PTO0, PTO1, and PCL pins Each bit can be connected to pull-up resistor by mask option *: Can directly drive LED.

µPD75104, 75106, 75108

5.2 CLOCK GENERATOR CIRCUIT

The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and peripheral hardware. In addition, this circuit can change the instruction execution time.

• 0.95 µs/1.91 µs/15.3 µs (operating at 4.19 MHz)
• Basic interval timer (BT)
• Clock output circuit
• Timer/event counter
• Serial interface f or XX fX 1/2 1/16 1/8 to 1/4096 Frequency civider System clock generator circuit Oscillation stops Selector Frequency divider
• CPU
• Clock output circuit HALT F/F S RQ PCC PCC0 PCC1 PCC2 PCC3 Internal busHALT* STOP* Clears PCC2, PCC3 STOP F/F Q S R Wait release signal from BT RES (internal reset) signal Standby release signal from interrupt control circuit Φ *: Execution of the instruction Remarks 1: f XX = Crystal/ceramic oscillator 2: f X = External clock frequency 3: PCC: Processor clock control register 4: One clock cycle (t CY) of Φ is one machine cycle of an instruction. For t CY, refer to AC characteristics in 12. ELECTRICAL SPECIFICATIONS. Fig. 5-1 Clock Generator Block Diagram H

µPD75104, 75106, 75108

5.3 CLOCK OUTPUT CIRCUIT

The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output clock pulses to the remote control output, peripheral LSIs, etc.

• Clock output (PCL) : Φ , 524, 262 kHz (operating at 4.19 MHz) Selector Output buffer PCL/P22 Bit 2 of PMGBPORT2.2 Port 2 input/ output mode specification bit P22 output latch Internal bus CLOM3 CLOM2 CLOM1 CLOM0 CLOM Φ f X/23 f X/24 From the clock generator X X Fig. 5-2 Clock Output Circuit Configuration

µPD75104, 75106, 75108

5.4 BASIC INTERVAL TIMER

The basic interval timer has these functions:

• Interval timer operation which generates a reference time interrupt
• Watchdog timer application which detects a program runaway
• Selects the wait time for releasing the standby mode and counts the wait time
• Reads out the count value Remarks : *: Instruction execution Fig. 5-3 Basic Interval Timer Configuration From the clock generator f X/25 f X/27 f X/29 f X/212 MPX Clear Basic interval timer (8-bit frequency divider circuit) 4 8 BT Clear Set signal BT interrupt request flag IRQBT Wait release signal for standby release Vector interrupt request signal Internal bus BTM3 BTM2 BTM1 BTM0 BTM SET1* X X X X

5.5 TIMER/EVENT COUNTER

µPD75108 contains two channels of timer/event counters. These two channels are almost identical in terms of configuration and function except the count pulse (CP) that can be selected and the function to supply clocks to the serial interface. The functions of the timer/event counter include:

• Programmable interval timer operation
• Output of square wave at an arbitrary frequency to PTOn pin
• Event counter operation
• Input of TIn pin signal as external interrupt input signal
• Dividing TIn pin input by N to output to PTOn pin (frequency divider operation)
• Supply of serial shift clock to serial interface circuit (channel 0 only)
• Reading counting status

µPD75104, 75106, 75108 Internal bus 88 8 Modulo register (8)TMn7 TMn6 TMn5 TMn4 TMn3 TMn2 TMn1 TMn0 TIn Input buffer TIn MPX CPFrom clock generator circuit Timer operation start SET1* TMn TMODn Tn Clear RES Remarks: Comparator (8) Count register (8) TOUT F/F Coincidence TOFn To selector TMn1 TMn0 Edge detector circuit To enable flag P2n output latch Port 2 I/O mode TOEn TOn PORT2.n Bit 2 of PGMB To serial interface (channel 0 only) P2n/PTOn Output buffer IRQTn set signal IRQTn clear signal Fig. 5-4 Timer/Event Counter Block Diagram (n = 0, 1) * indicates the instruction execution.

µPD75104, 75106, 75108

5.6 SERIAL INTERFACE

The µPD75108 is equipped with clock 8-bit serial interface that operates in the following two modes:

• Operation stop mode
• Three-line serial I/O mode

µPD75104, 75106, 75108 Internal bus 8 8 P03/SI P02/SO P01/SCK SIO0 Shift register (8) SIO7 SIO QS R Clear Serial clock counter (3) Overflow MPX *: "SET1" indicates execution of the instruction. Φ f /2XX 4 f /2XX 10 TOF0 (from timer channel 0) Serial start SIOM7 SIOM6 SIOM5 SIOM4 SIOM3 SIOM2 SIOM1 SIOM0 SET1* SIOM IRQSIO set signal IRQSIO clear signal Fig. 5-5 Serial Interface Block Diagram

µPD75104, 75106, 75108

5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)

µPD75108 is equipped with a 4-bit analog input port (consisting of PTH00 to PTH03 pins) whose threshold voltage is programmable. This programmable threshold port is configured as shown in Figure 5-6. The threshold voltage (VREF) can be changed in 16 steps (VDD × 0.5/16 – VDD × 15.5/16), and analog signals can be directly input. When VREF is set to VDD × 7.5/16, the programmable threshold port can also be used as a digital signal input port. Input buffer PTH00 PTH01 PTH02 PTH03 VDD Internal bus Programmable threshold port input latch (4) Operates /stops PTH0 MPX PTHM7 PTHM6 PTHM5 PTHM4 PTHM3 PTHM2 PTHM1 PTHM0 PTHM 2 R 2 R R R VREF Fig. 5-6 Programmable Threshold Port Configuration

µPD75104, 75106, 75108 The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer, addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this buffer is very useful for processing long data in bit units. Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register. Fig. 5-7 Bit Sequential Buffer Format

5.9 POWER-ON FLAG (MASK OPTION)

The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal has been generated (see Fig. 8-1). The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation instruction. However, it cannot be set by the SET1 instruction. 6. INTERRUPT FUNCTIONS The µPD75108 has 7 different interrupt sources and can perform multiplexed interrupt processing with priority assigned. In addition to that, the µPD75108 is also provided with two types of edge detection testable inputs. The interrupt control circuit of the µPD75108 has these functions:

• Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by using the interrupt enable flag (IExxx) and interrupt master enable flag (IME).
• The interrupt start address can be arbitrarily set.
• Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS).
• Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of software).
• Standby mode release (Interrupts to be released can be selected by the interrupt enable flag). Address bit Symbol L register 32103210 3210321 0 L = F L = C L = B L = 8 L = 7 L = 4 L = 3 L = 0 BSB3 BSB2 BSB1 BSB0 DECS L INCS L FC3H FC2H FC1H FC0H

µPD75104, 75106, 75108 Internal bus IM1 IM0 IRQBT INT4 /P00 INT0 /P10 INT1 /P11 INT2 /P12 INT BT INTSIO INTT0 Both edge detection circuit Edge detection circuit Edge detection circuit Rising edge detection circuit Falling edge detection circuit IRQ4 IRQ0 IRQ1 IRQSIO IRQT0 IRQT1 IRQ2 Interrupt enable flag (IE )××× IME Decoder IST Priority control circuit Vector table address generator Standby release signal Fig. 6-1 Interrupt Control Block Diagram IRQ3 IPS INTT1 INT3 /P13 Interrupt request flag

µPD75104, 75106, 75108 7. STANDBY FUNCTIONS The µPD75108 has two different standby modes (STOP mode and HALT mode) to reduce the power consumption of the microcomputer chip while waiting for program execution. Table 7-1 Each Status in Standby Mode Setting Instruction STOP instruction HALT instruction Clock Generator circuit Basic Interval Timer Operates (sets IRQBT at reference time intervals) Operates only when input of external SCK or output of TO0 is selected as serial clock (where external TI0 is input to timer/event counter 0) Operates when serial clock other than Φ is specified Operates Stops Serial Interface Clock output STOP Mode HALT Mode Clock oscillation stops Only CPU clock Φ is stopped Operation Status Timer/Event Counter circuit Operates only when TIn pin input signal is specified as count clock Operates when clock other than CPU clock Φ is used Stops CPU Stops Release Signal Interrupt request signal enabled by interrupt enable flag, or RESET input Stops

µPD75104, 75106, 75108 8. RESET FUNCTION The reset ( RES) signal generator circuit is configured as shown in Figure 8-1. RESET SWB SWA Power-ON reset generator circuit Internal reset signal (RES) Power-ON flag (PONF) Execution of bit manipulation instruction* Internal bus *: PONF cannot be set to 1 by SET1 instruction. Fig. 8-1 Reset Signal Generator Circuit The Power-ON reset generator circuit generates an internal reset signal when the supply voltage rises. This pulse can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK OPTION SELECTION.) The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs. 8-2 and 8-3, respectively. Supply voltage 0 V Internal reset signal (RES) Wait* (approx. 31.3 ms: 4.19 MHz) HALT mode Operation mode Internal reset operation *: The wait time does not include the time required after the RES signal has been generated until the oscillation starts. Fig. 8-2 Reset by Power-ON Reset Circuit

µPD75104, 75106, 75108 Wait* (31.3 ms: 4.19 MHz) HALT mode Operation mode Operation mode or standby mode RESET input Internal reset operation *: The wait time does not include the time required after the RES signal has been generated until the oscillation starts. Fig. 8-3 Reset by RESET Signal The status of each internal hardware device after the reset operation has been performed is shown in Table 8-

µPD75104, 75106, 75108 Table 8-1 Hardware Device Status After Reset RESET input during Power-ON Reset or RESET standby mode Input during Operation Lower 4 bits of program Lower 4 bits of program memory address 000H are memory address 000H are Program Counter (PC) set to PC 12-8,*1 and set to PC 12-8,*1 and contents of address 001H contents of address 001H are set to PC 7-0. are set to PC 7-0. Carry Flag (CY) Retained Undefined Skip Flags (SK0-SK2) 0 0 PSW Interrupt Status Flags (IST0, 1) 0 0 Bit 6 of program memory Bit 6 of program memory Bank Enable Flags (MBE, RBE) address 000H is set in address 000H is set in RBE, and bit 7 is set in RBE, and bit 7 is set in MBE. MBE. Stack Pointer (SP) Undefined Undefined Data Memory (RAM) Retained* 2 Undefined General-Purpose Registers (X,A,H,L,D,E,B,C) Retained Undefined Bank Selector Registers (MBS, RBS) 0, 0 0, 0 Counter (BT) Undefined Undefined Mode Register (BTM) 0 0 Counter (Tn) 0 0 Modulo Register (TMODn) FFH FFH Mode Register (TMn) 0 0 TOEn, TOFn 0, 0 0, 0 Serial Interface Shift Register (SIO) Retained Undefined Mode Register (SIOM) 0 0 Processor Clock Control Register 0 0 (PCC) Clock Output Mode Register 0 0 (CLOM) Interrupt Request Rlags Reset (0) Reset (0) (IRQxxx) Interrupt Enable Flags (IExxx) 0 0 Interrupt Priority Selector Register (IPS) 0 0 INT0, 1 Mode Registers 0, 0 0, 0 (IM0, IM1) Output Buffer OFF OFF Digital Port Output Latch Cleared (0) Cleared (0) I/O Mode Registers 0 0 (PMGA, PMGB, PMGC) PTH00-PTH03 Input Latches Undefined Undefined Analog Port Mode Register (PTHM) 0 0 Power-ON Flag (PONF) Retained 1 or undefined* 2 Bit Sequential Buffer (BSB0-BSB3) 0 0 *1: PC 11-8 for µPD75104 2: Power-ON reset: 1 RESET input during operation: undefined Note: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input. Hardware Basic interval timer Timer/Event Counter (n = 0, 1) Clock Generator Circuit, Clock Output Circuit

µPD75104, 75106, 75108 9. INSTRUCTION SET (1) Operand representation and description Describe one or more operands in the operand field of each instruction according to the operand representation and description methods of the instruction (for details, refer to RA75X Assembler Package User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from several operands. The uppercase characters, +, and – are keywords and must be described as is. Describe an appropriate numeric value or label as immediate data. The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem, and bit (for details, refer to µPD751XX Series User‘s Manual (IEM-922)). However, fmem and pmem restricts the label that can be described. Representation Description reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp' XA, BC, DE, HL, XA', BC', DE', HL' rp'1 BC, DE, HL, XA', BC', DE', HL' rpa HL, HL+, HL–, DE, DL rpa1 DE, DL n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label* bit 2-bit immediate data or label fmem FB0H to FBFH,FF0H to FFFH immediate data or label pmem FC0H to FFFH immediate data or label µPD75104 0000H to 0FFFH immediate data or label addr µPD75106 0000H to 177FH immediate data or label µPD75108 0000H to 1F7FH immediate data or label caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H to 7FH immediate data (where bit0 = 0) or label PORTn PORT0 - PORT9, PORT12 - PORT14 IExxx IEBT, IESIO, IET0, IET1, IE0 - IE4 RBn RB0 - RB3 MBn MB0, MB1, MB15 *: Only even address can be described as mem for 8-bit data processing.

µPD75104, 75106, 75108 (2) Legend of operation field A : A register; 4-bit accumulator B : B register; 4-bit accumulator C : C register; 4-bit accumulator D : D register; 4-bit accumulator E : E register; 4-bit accumulator H : H register; 4-bit accumulator L : L register; 4-bit accumulator X : X register; 4-bit accumulator XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC); 8-bit accumulator DE : Register pair (DE); 8-bit accumulator HL : Register pair (HL); 8-bit accumulator XA' : Expansion register pair (XA') BC' : Expansion register pair (BC') DE' : Expansion register pair (DE') HL' : Expansion register pair (HL') PC : Program counter SP : Stack pointer CY : Carry flag; or bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 - 9, 12 - 14) IME : Interrupt mask enable flag IPS : Interrupt priority selection register IExxx : Interrupt enable flag RBS : Register bank selection register MBS : Memory bank selection register PCC : Processor clock control register . : Delimiter of address and bit (xx) : Contents addressed by xx xxH : Hexadecimal data

µPD75104, 75106, 75108 (4) Machine cycle field In this field, S indicates the number of machine cycles required when an instruction having a skip function skips. The value of S varies as follows: Note : The GETI instruction is skipped in one machine cycle. One machine cycle equals to one cycle of the CPU clock Φ , (= tCY), and can be changed in three steps depending on the setting of the processor clock control register (PCC). (3) Symbols in addressing area field *1 MB = MBE . MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (00H-7FH) Data memory MB = 15 (80H-FFH) addressing MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 µPD75104 addr = 0000H-0FFFH µPD75106 addr = 0000H-177FH µPD75108 addr = 0000H-1F7FH *7 addr = (Current PC) – 15 to (Current PC) – 1 (Current PC) + 2 to (Current PC) + 16 Program memory *8 µPD75104 caddr = 0000H-0FFFH (PC 11 = 0) addressing µPD75106 caddr = 0000H-0FFFH (PC 12 = 0) or 1000H-177FH (PC 12 = 1) µPD75108 caddr = 0000H-0FFFH (PC 12 = 0) or 1000H-1F7FH (PC 12 = 1) *9 faddr = 000H-7FFH *10 taddr = 020H-07FH Remarks • MB indicates memory bank that can be accessed.

• In *2, MB = 0 regardless of MBE and MBS.
• In *4 and *5, MB = 15 regardless of MBE and MBS.
• *6 to *10 indicate areas that can be addressed.

µPD75104, 75106, 75108 Ma- Instruc- Mne- Operand Bytes chine Operation Addressing Skip tions monics Cyc- Area Conditions les Transfer MOV A, #n4 1 1 A ← n4 String effect A reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 String effect B rp2, #n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L = 0 A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A* 1 @HL, XA 2 2 (HL) ← XA *1 A,mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A* 3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp' 2 2 XA ← rp' reg1, A 2 2 reg1 ← A rp'1, XA 2 2 rp'1 ← XA XCH A, @HL 1 1 A ↔ (HL) *1 A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L = 0 A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1 XA, rp' 2 2 XA ↔ rp' MOVT XA, @PCDE 1 3 • µPD75104 XA ← (PC11-8+DE)ROM

• µPD75106, 75108 XA ← (PC12-8+DE)ROM XA, @PCXA 1 3 • µPD75104 XA ← (PC11-8+XA)ROM
• µPD75106, 75108 XA ← (PC12-8+XA)ROM Table Refer- ence

µPD75104, 75106, 75108 Ma- Instruc- Mne- Operand Bytes chine Operation Addressing Skip tions monics Cyc- Area Conditions les Bit MOV1 CY,fmem.bit 2 2 CY ← (fmem.bit) *4 transfer CY,pmem.@L 2 2 CY ← (pmem7-2+L3-2.bit(L1-0)) *5 CY,@H+mem. 2 2 CY ← (H+mem 3-0.bit) *1 bit fmem.bit,CY 2 2 (fmem.bit) ← CY *4 pmem.@L,CY 2 2 (pmem 7-2+L3-2.bit(L1-0)) ← CY *5 @H+mem.bit, 2 2 (H+mem 3-0.bit) ← CY *1 CY Arith- ADDS A, #n4 1 1+S A ← A+n4 carry metic XA, #n8 2 2+S XA ← XA+n8 carry opera- A, @HL 1 1+S A ← A+(HL) *1 carry tion XA, rp’ 2 2+S XA ← XA+rp’ carry rp’1, XA 2 2+S rp’1 ← rp’1+XA carry ADDC A, @HL 1 1 A, CY ← A+(HL)+CY *1 XA, rp’ 2 2 XA, CY ← XA+rp’+CY rp’1, XA 2 2 rp’1,CY ← rp’1+XA+CY SUBS A, @HL 1 1+S A ← A-(HL). *1 borrow XA, rp’ 2 2+S XA ← XA-rp’ borrow rp’1, XA 2 2+S rp’1 ← rp’1-XA borrow SUBC A, @HL 1 1 A, CY ← A-(HL)-CY *1 XA, rp’ 2 2 XA, CY ← XA-rp’-CY rp’1, XA 2 2 rp’1,CY ← rp’1-XA-CY AND A, #n4 2 2 A ← A ∧ n4 A, @HL 1 1 A ← A ∧ (HL) *1 XA, rp’ 2 2 XA ← XA ∧ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ∧ XA OR A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) *1 XA, rp’ 2 2 XA ← XA ∨ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ∨ XA XOR A, #n4 2 2 A ← A ∨ n4 A, @HL 1 1 A ← A ∨ (HL) *1 XA, rp’ 2 2 XA ← XA ∨ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ∨ XA RORC A 1 1 CY ← A0, A3 ← CY, A n-1 ← An NOT A 2 2 A ← A Incre- INCS reg 1 1+S reg ← reg+1 reg = 0 ment/ rp1 1 1+S rp1 ← rp1+1 rp1 = 00H decre- @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0 ment mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0 DECS reg 1 1+S reg ← reg-1 reg = FH rp’ 2 2+S rp’ ← rp’-1 rp’ = FFH Accumulator Manipulation

µPD75104, 75106, 75108 Ma- Instruc- Mne- Operand Bytes chine Operation Addressing Skip tions monics Cyc- Area Conditions les Com- SKE reg, #n4 2 2+S Skip if reg = n4 reg = n4 pare @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp’ 2 2+S Skip if XA = rp’ XA = rp’ Carry SET1 CY 1 1 CY ← 1 flag CLR1 CY 1 1 CY ← 0 Manipu- SKT CY 1 1+S Skip if CY = 1 CY = 1 lation NOT1 CY 1 1 CY ← CY Memory/ SET1 mem.bit 2 2 (mem.bit) ← 1 *3 Bit fmem.bit 2 2 (fmem.bit) ← 1 *4 Manipu- pmem.@L 2 2 (pmem 7-2 + L 3-2.bit(L1-0)) ← 1* 5 lation @H+mem.bit 2 2 (H + mem 3-0.bit) ← 1* 1 CLR1 mem.bit 2 2 (mem.bit) ← 0 *3 fmem.bit 2 2 (fmem.bit) ← 0 *4 pmem.@L 2 2 (pmem 7-2 + L3-2.bit(L1-0)) ← 0* 5 @H+mem.bit 2 2 (H+mem 3-0.bit) ← 0* 1 SKT mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L3-2.bit (L 1-0)) = 1 *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 1 *1 (@H+mem.bit) = 1 SKF mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem 7-2 +L3-2.bit (L 1-0)) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H + mem 3-0.bit) = 0 *1 (@H+mem.bit) = 0 SKTCLR fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem 7-2+L3-2.bit *5 (pmem.@L) = 1 (L1-0)) = 1 and clear @H+mem.bit 2 2+S Skip if (H+mem 3-0.bit) = 1 and clear *1 (@H+mem.bit) = 1 AND1 CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∧ (pmem 7-2+L3-2.bit(L 1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∧ (H+mem 3-0.bit) *1 OR1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem7-2+L3-2.bit (L 1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem 3-0.bit) *1 XOR1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4 CY,pmem.@L 2 2 CY ← CY ∨ (pmem 7-2+L3-2.bit (L 1-0)) *5 CY,@H+mem.bit 2 2 CY ← CY ∨ (H+mem 3-0.bit) *1

µPD75104, 75106, 75108 Ma- Instruc- Mne- Operand Bytes chine Operation Addressing Skip tions monics Cyc- Area Conditions les Branch BR addr — — • µPD75104 *6 PC11-0 ← addr The most suitable instruction is selectable from among BRCB ! caddr, and BR $ addr depending on the assembler.

• µPD75106, 75108 PC12-0 ← addr The most suitable instruction is selectable from among BR ! addr, BRCB ! caddr, and BR $ addr depending on the assembler. ! addr 3 3 • µPD75106, 75108 *6 PC12-0 ← addr $ addr 1 2 • µPD75104 *7 PC11-0 ← addr
• µPD75106, 75108 PC12-0 ← addr BRCB ! caddr 2 2 • µPD75104 *8 PC11-0 ← caddr 11-0
• µPD75106, 75108 PC12-0 ← PC12 + caddr 11-0 BR PCDE 2 3 • µPD75104 PC11-0 ← PC11-8 + DE
• µPD75106, 75108 PC12-0 ← PC12-8 + DE PCXA 2 3 • µPD75104 PC11-0 ← PC11-8 + XA
• µPD75106, 75108 PC12-0 ← PC12-8 + XA Subrou- CALL ! addr 3 3 • µPD75104 *6 tine/ (SP-4)(SP-1)(SP-2) ← PC11-0 Stack (SP-3) ← MBE, RBE, 0, 0 Control PC 11-0 ← addr, SP ← SP-4
• µPD75106, 75108 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, PC 12 PC12-0 ← addr, SP ← SP-4

µPD75104, 75106, 75108 Ma- Instruc- Mne- Operand Bytes chine Operation Addressing Skip tions monics Cyc- Area Conditions les CALLF ! faddr 2 2 • µPD75104 *9 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, 0 PC11-0 ←0, faddr, SP ← SP-4

• µPD75106, 75108 (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, PC 12 PC12-0 ← 00, faddr, SP ← SP-4 RET 1 3 • µPD75104 MBE, RBE, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4
• µPD75106, 75108 MBE, RBE, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4 RETS 1 3+S • µPD75104 Unconditioned MBE, RBE, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally
• µPD75106, 75108 MBE, RBE, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) SP ← SP+4, then skip unconditionally RETI 1 3 • µPD75104 MBE, RBE, x, x ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6
• µPD75106, 75108 MBE, RBE, x, PC 12 ← (SP+1) PC11-0 ← (SP)(SP+3)(SP+2) PSW ← (SP+4)(SP+5), SP ← SP+6 PUSH rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2 BS 2 2 (SP-1) ← MBS, (SP-2) ← RBS, SP ← SP-2 POP rp 1 1 rp ← (SP+1)(SP), SP ← SP+2 BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2 Subrou- tine/ Stack Control (Cont‘d)

µPD75104, 75106, 75108 Ma- Instruc- Mne- Operand Bytes chine Operation Addressing Skip tions monics Cyc- Area Conditions les Inter- EI 2 2 IME (IPS.3) ← 1 rupt IExxx 2 2 IExxx ← 1 Control DI 2 2 IME (IPS.3) ← 0 IExxx 2 2 IExxx ← 0 I/O IN* A, PORTn 2 2 A ← PORT n (n = 0-9, 12-14) XA, PORTn 2 2 XA ← PORTn+1,PORTn (n = 4, 6, 8, 12) OUT* PORTn, A 2 2 PORT n ← A (n = 2-9, 12-14) PORTn, XA 2 2 PORTn+1, PORTn ← XA(n = 4, 6, 8, 12) CPU HALT 2 2 Set HALT Mode (PCC.2 ← 1) Control STOP 2 2 Set STOP Mode (PCC.3 ← 1) NOP 1 1 No Operation Special SEL RBn 2 2 RBS ← n (n = 0-3) MBn 2 2 MBS ← n (n = 0, 1, 15) GETI taddr 1 3 • µPD75104 *10

• Where TBR instruction, PC11-0 ← (taddr) 3-0+(taddr+1)
• Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, 0 PC11-0 ← (taddr) 3-0+(taddr+1) SP ← SP-4
• Except for TBR and TCALL Depends on instructions, referenced Instruction execution of instruction (taddr)(taddr+1)
• µPD75106, 75108
• Where TBR instruction, PC12-0 ← (taddr) 4-0+(taddr+1)
• Where TCALL instruction, (SP-4)(SP-1)(SP-2) ← PC11-0 (SP-3) ← MBE, RBE, 0, PC 12 PC12-0 ← (taddr) 4-0+(taddr+1) SP ← SP-4
• Except for TBR and TCALL Depends on instructions, referenced Instruction execution of instruction (taddr)(taddr+1) *: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15. Remarks: TBR and TCALL instructions are assembler instructions for GETI instruction table definition. H

µPD75104, 75106, 75108 10. APPLICATION EXAMPLES

10.1 VTR SYSTEM CONTROLLER

PD75108µRemote controller signal receiver Operation mode LED indicator Servo system control circuit Motor driver circuit, etc. High- current output System controller/ tape counter/ remote controller/ remaining tape computation INT INT Comparator input INT Audio video system control circuit 12 V SIO Key matrix Take-up reel pulse Supply reel pulse Sensor circuit Exposure sensor Tape start/end sensor On-screen display controller PD752 timer/tuner/OSD µ ×× PWM output MNOS PD6252 PD6253 PD6254 µ µ µ TunerFIP

10.2 VTR CAMERA

PD75108µ Operation mode LED indicator Servo system control circuit INT Motor plunger driver circuit, etc. System control/ editing function INT Key matrix (including message input) Reel pulse Battery sensor Sensor circuit Exposure sensor Tape start/end sensor Power- down detector On-screen display controller 12 V Audio video system control circuit Comparator input High- current output

µPD75104, 75106, 75108

10.3 COMPACT DISC PLAYER

PD75108µ SIO INT Servo control IC Loading control circuit Remote controller signal receiver High- current output Key matrix LED indication

10.4 AUTOMOBILE APPLICATIONS (TRIP COMPUTER)

PD75108µ SIO INT0 INT1 TI TO Vehicle speed detection Number of revolutions detection Fuel comsumption Key position Gear position Key input Mode select Numerical input Buzzer Display driver PD6300 PD6323 PD6332 µ µ µ Clock Alarm Average speed Arrival time, etc.

µPD75104, 75106, 75108

10.5 PUSHBUTTON TELEPHONE

PD75108µ Comparator input SIO INT TO Code ROM Piezoelectric buzzer Switch RAM PD4464µ LED indicator Battery check LCD indicator LCD controller/ driver PD7228/7229 µ High- current output Hook switch To main equipment LED indicator Key matrix Data receiver circuit Data transmitter circuit TO PD75108 µ Filter SIO PD7228Gµ LCD controller/ driver LCD indicator Microphone Speaker Transmitter/ receiver MPXHigh- current output Transmitter/ receiver/ speaker selector Communication circuit Speaker amplifier Microphone amplifier Call sound10.6 DISPLAY PAGER

µPD75104, 75106, 75108

10.7 PLAIN PAPER COPIER (PPC)

PD75108µ TO Comparator input Motor/relay driver circuit Switch Piezoelectric buzzer 12 V High- current output LED indicator Key matrix Sensor circuit, heater temperature, toner drum pressure, etc.

10.8 PRINTER CONTROLLER

PD75108µHost machine PD0 to PD7 STRB BUSY TxD INT SI TO 12 V High current Key matrix LED Motor driver control circuit Dot matrix head driver circuit Piezoelectric buzzer

µPD75104, 75106, 75108 11. MASK OPTION SELECTION µPD75108 has the following mask options. Options to be built in can be selected. (1) Pin Pin Mask Option P120 - P123 P130 - P133 Pull-down resistor can be built in bitwise. P140 - P143 (2) Power-ON reset generation circuit, power-ON flag (PONF) One from the following three ways can be selected. Switching Selection Power-On Reset Power-On Flag Internal Reset Signal (Refer to Fig. 8-1.) Generation Circuit (PONF) (RES) SWA SWB ON ON Provided Provided Generates automatically ON OFF Provided Provided Not generates autoamtically OFF OFF Not provided Not provided —

µPD75104, 75106, 75108 12. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C) Parameter Symbol Conditions Ratings Unit Supply Voltage V DD -0.3 to +7.0 V VI1 Other than ports 12, 13, 14 -0.3 to V DD+0.3 V Input Voltage V I2*1 Ports 12 to 14 w/pull-up -0.3 to V DD+0.3 Vresistor Open drain -0.3 to +13 V Output Voltage V O -0.3 to V DD+0.3 V High-Level Output I OH 1 pin -15 mA Current All pins -30 mA Low-Level Output I OL*2 1 pin Peak 30 mA Current rms 15 mA Total of ports 0, 2 to 4, 12 to 14 Peak 100 mA rms 60 mA Total of ports 5 to 9 Peak 100 mA rms 60 mA Operating Temperature T opt -40 to +85 °C Storage Temperature T stg -65 to +150 °C *1: The power supply impedance (pull-up resistance) must be 50 k Ω or higher when a voltage higher than 10 V is applied to ports 12, 13, and 14. 2: rms = Peak value x √Duty

µPD75104, 75106, 75108 OSCILLATOR CIRCUIT CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V) Oscillator Recommended Item Conditions MIN. TYP. MAX. UnitConstants Ceramic Oscillation V DD = Oscillation 2.0 5.0 MHzfrequency(f XX)*1 voltage range Oscillation stabiliza- After V DD come to tion time* 2 MIN. of oscillation voltage range 4m s Crystal Oscillation 2.0 4.19 5.0 MHzfrequency (f XX)*1 Oscillation stabiliza- V DD = 4.5 to 6.0 V 10 ms tion time* 2 30 ms External Clock X1 input frequency 2.0 5.0 MHz(fX)*1 X1 input high-, low-level widths XH, tXL) 100 250 ns *1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC Characteristics. 2: Time required for oscillation to stabilize after V DD has come to MIN. of oscillation volrage range or the STOP mode has been released. 3: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the instruction execution time: otherwise, one machine cycle is set to less than 0.95 µs, falling short of the rated minimum value of 0.95 µs. Note: When using the oscillation circuit of the system clock, wire the portion enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity:

• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines. Also, do not route the wiring in the vicinity of lines through which a high alternating current flows.
• Always keep the ground point of the capacitor of the osccillator circuit at the same potential as VSS. Do not connect the ground pattern through which a high current flows.
• Do not extract signals from the oscillation circuit. X1 X2 C1 C2 X1 X2 C1 C2 X1 X2 PD74HCU04µ H H

µPD75104, 75106, 75108 RECOMMENDED OSCILLATOR CIRCUITS CONSTANTS RECOMMENDED CERAMIC OSCILLATORS External Oscillation Manufacturer Product Name Capacitance (pF) Voltage Range (V) C1 C2 MIN. MAX. CSA 2.00MG 30 30 2.7 6.0 Murata Mfg. CSA 4.19MG 30 30 3.0 6.0 CST 4.19T Provided Provided 3.0 6.0 KBR-2.0MS 100 100 3.0 6.0 Kyoto Ceramic KBR-4.0MS 33 33 3.0 6.0 KBR-4.9152M 33 33 3.0 6.0 RECOMMENDED CRYSTAL OSCILLATOR External Oscillation Manufacturer Product Name Capacitance (pF) Voltage Range (V) C1 C2 MIN. MAX. Kinseki HC-49/U 22 22 2.7 6.0

µPD75104, 75106, 75108 DC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V) Item Symbol Conditions MIN. TYP. MAX. Unit VIH1 Other than below 0.7V DD VDD V High-Level V IH2 Ports 0, 1, TI0, 1, RESET 0.8 V DD VDD V Input Voltage Pull-up resistor 0.7 V DD VDD V Open drain 0.7 V DD 12 V VIH4 X1, X2 V DD-0.5 V DD V VIL1 Other than below 0 0.3 V DD V Low-Level Input Voltage V IL2 Ports 0, 1, TI0, 1, RESET 0 0.2 V DD V VIL3 X1, X2 0 0.4 V VDD = 4.5 to 6.0 V,I OH = -1 mA V DD-1.0 V IOH = -100 µAV DD-0.5 V VDD = Ports 0, 2 to 9, I OL = 15 mA 0.35 2.0 V 4.5 to 6.0 V Ports 12 to 14, I OL = 10 mA 0.35 2.0 V VDD = 4.5 to 6.0 V, I OL = 1.6 mA 0.4 V IOL = 400 µA 0.5 V ILIH1 Other than below 3 µA ILIH2 X1,X2 20 µA ILIH3 VIN = 12 V Ports 12 to 14 (open drain) 20 µA Low-Level I LIL1 Other than X1, X2 –3 µA Input Leakage Current I LIL2 X1, X2 –20 µA High-Level I LOH1 VOUT = V DD Other than below 3 µA Output Leakage Current I LOH2 VOUT = 12 V Ports 12 to 14 (open drain) 20 µA Low-Level Output I LOL VOUT = 0 V –3 µA Leakage Current VDD = 5 V ±10% 15 40 70 k Ω 10 80 k Ω 4.19MHz V DD = 5 V ±10%*2 39 m A crystal V DD = 3 V ±10%*3 0.55 1.5 mA Supply Current* 1 oscillator HALT V DD = 5 V ± 10% 600 1800 µA C1 = C2 = 22pF mode V DD = 3± 10% 200 600 µA IDD3 STOP mode, V DD = 3 V ± 10% 0.1 10 µA *1: The current flowing into the internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included. 2: When the high-speed mode is set by setting the processor clock control register (PCC) to 0011. 3: When the low-speed mode is set by setting the PCC to 0000. Low-Level Output Voltage V OL High-Level Output Voltage VOH VIN = V DD VIN = 0 V High-Level Input Leakage Current Internal Pull-Up Resistor* 1 RL Ports 12 to 14 IDD1 IDD2 VIH3 Ports 12 to 14

µPD75104, 75106, 75108 CAPACITANCE (Ta = 25 °C, V DD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input Capacitance C IN f = 1 MHz 15 pF Output Capacitance C OUT Pins other than thosemeasured are at 0 V 15 pF Input/Output C IO 15 pF Capacitance COMPARATOR CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 4.5 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Comparison Accuracy V ACOMP ±100 mV Threshold Voltage V TH 0V DD V PTH Input voltage V IPTH 0V DD V Comparator circuit PTHM7 is set to “1” 1 mA current dissipation POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = -40 to +85 °C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Power-On Reset High-Level V DDH 4.5 6.0 V Operating Voltage Power-On Reset Low-Level V DDL 0 0.2 V Operating Voltage Supply Voltage t r 10 * 1 µs Rise Time Supply Voltage t off 1s Off Time Power-On Reset Circuit I DDPR VDD = 5 V ±10% 10 100 µA Current Dissipation* 2 VDD = 2.5 V 2 20 µA *1: 2 17/fXX (31.3 ms at f XX = 4.19 MHz) 2: Current flowing when power-ON reset circuit or power-ON Flag is incorporeated. Note: Apply power gradually and smoothly. VDD VDDH VDDL toff tr

µPD75104, 75106, 75108 AC CHARACTERISTICS (T a = -40 to +85 °C, V DD = 2.7 to 6.0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit VDD = 4.5 to 6.0 V 0.95 32 µs 3.8 32 µs VDD = 4.5 to 6.0 V 0 1 MHz 0 275 kHz tTIH,V DD = 4.5 to 6.0 V 0.48 µs tTIL 1.8 µs VDD = 4.5 to 6.0 V Input 0.8 µs Output 0.95 µs Input 3.2 µs Output 3.8 µs VDD = 4.5 to 6.0 V Input 0.4 µs Output tKCY/2-50 ns Input 1.6 µs Output tKCY/2-150 ns SI Setup Time t SIK 100 ns (vs. SCK↑) SI Hold Time t KSI 400 ns (vs. SCK ↑ ) VDD = 4.5 to 6.0 V 300 ns 1000 ns INT0 to 4 t INTH, 5 µs High-/Low-Level Width t INTL RESET Low-Level Width t RSL 5 µs *: The cycle time of the CPU clock ( Φ ) is determined by the input frequency of the ceramic or crystal oscillator circuit and the set value of the processor clock control register. The t CY vs. VDD charac- teristics are as shown on the right. 0123 456 0.5 V DD [V] t CY [ s] tCY vs. VDD µ Operation guaranteed range CPU Clock Cycle Time* (Minimum Instruction Execution Time = 1 Machine Cycle) t CY TI0, TI1 Input Frequency f TI TI0, TI1 Input High-/ Low-Level Width SCK Cycle Time t KCY SCK High-/Low-Level Width tKH, tKL SCK ↓→ SO Output delay Time tKSO

µPD75104, 75106, 75108 AC TIMING MEASURING POINTS (excluding Ports 0, 1, TI0, TI1, X1, X2, and RESET) CLOCK TIMING TI TIMING Measuring points

0.7 VDD

0.3 VDD

X1 input VDD –0.5 0.4 tXL tXH 1/fX

0.8 TI0, TI1

0.2 VDD VDD

µPD75104, 75106, 75108 SERIAL TRANSFER TIMING SCK tKL tKH tKCY Output data tSIK tKSI tKSO Input dataSI SO 0.8 V 0.2 V DD DD

0.8 VDD

0.2 VDD

0.8 V 0.2 V DD DD RESET tRSL

µPD75104, 75106, 75108 LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE (Ta = –40 to +85 °C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data Retention Supply V DDDR 2.0 6.0 VVoltage Data Retention Supply I DDDR VDDDR = 2.0 V 0.1 10 µACurrent* 1 Release Signal Set Time t SREL 0 µs Oscillation Stabilization t WAIT Released by RESET 2 17/fX ms Wait Time* 2 Released by interrupt request * 3 ms *1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and comparator circuit is not included 2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started. 3: Depends on the setting of the basic interval timer mode register (BTM) as follows: BTM3 BTM2 BTM1 BTM0 Wait time ( ): f XX = 4.19 MHz –0 0 0 2 20/fXX (approx. 250 ms) –0 1 1 2 17/fXX (approx. 31.3 ms) –1 0 1 2 15/fXX (approx. 7.82 ms) –1 1 1 2 13/fXX (approx. 1.95 ms) DATA RETENTION TIMING (releasing STOP mode by RESET) STOP mode Data retention mode STOP instruction execution VDD RESET VDDDR tSREL tWAIT Operation mode Internal reset operation HALT mode DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt) STOP mode Data retention mode STOP instruction execution VDD VDDDR tSREL tWAIT Operation mode HALT mode Standby release signal (interrupt request)

µPD75104, 75106, 75108 13. CHARACTERISTIC DATA 5000 1000 500 100 0.5 0123 456 I vs. V Characteristics (crystal oscillation)DD DD Supply voltage V [V]DD Supply current I [ A]DD µ High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100] STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. Figure in [ ] indicate set values of PCC. Crystal oscillation

4.194304 MHz

I vs. f Characteristics (crystal oscillation)DD XX Supply current I [mA]DD f [MHz]XX 0123 5 3.0 2.5 2.0 1.5 1.0 0.5 Figure in [ ] indicate set values of PCC. X1 X2 C1 C2 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100] (V = 5.0 V, T = 25˚C)DD a a(T = 25˚C)

µPD75104, 75106, 75108 DD 5000 1000 500 100 0.5 0123456 I vs. V Characteristics (ceramic oscillation)DD DD High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] STOP mode [1000] When power-ON reset circuit and power-ON flag are incorporated. Figure in [ ] indicate set values of PCC. Ceramic oscillation

4.19 MHz

I vs. f Characteristics (ceramic oscillation)XXDD f [MHz]XX 0123 5 3.0 2.5 2.0 1.5 1.0 0.5 Figure in [ ] indicate set values of PCC. X1 X2 CC High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100] HALT mode [0100] a(T = 25˚C) Supply voltage V [V]DD Supply current I [ A]DD µSupply current I [mA]DD

µPD75104, 75106, 75108 3.0 2.5 2.0 1.5 1.0 0.5 0012345 X1 X2 PD74HCU04 µ Figures in [ ] indicate set values of PCC. I vs. f Characteristics (external clock)DD X f vs. V CharacteristicsDDTI f [MHz]X 1000 TIn input frequency f [kHz]TI 012345 V [V]DD 500 100 High-speed mode [0011] Medium-speed mode [0010] Low-speed mode [0000] HALT mode [0100] Operation guaranteed range (V = 5.0 V, T = 25˚C)DD a Supply current I [ A]DD µ

µPD75104, 75106, 75108 V vs. I (Ports 0 and 2 to 9) CharacteristicsOL OL 01234 V [V]OL Low-level output current of port 0 and 2 to 9 I [mA]OL V vs. I (Ports 12 to 14) CharacteristicsOL OL V = 6 VDD V = 5 VDD 01234 V [V]OL Low-level output current of ports 12 to 14 I [mA]OL V = 4 VDD V = 3 VDD DDV = 4 V V = 3 VDD V = 6 VDD V = 5 VDD

µPD75104, 75106, 75108 V vs. I (Ports 0 and 2 to 9) CharacteristicsOH OH –15 –10 01234 V - V [V]DD OH High-level output current of port 0 and 2 to 9 I [mA]OH V = 6 VDD V = 5 VDD V = 4 VDD V = 3 VDD Remarks: Unless otherwise specified, all the characteristic data shown are reference values.

µPD75104, 75106, 75108 14. PACKAGE DRAWINGS A I J G H F D N M C B M R K L NOTE Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. P64C-70-750A,C-1 ITEM MILLIMETERS INCHES A B C D F G H I J K 58.68 MAX. 1.778 (T.P.) 3.2±0.3 0.51 MIN. 4.31 MAX. 1.78 MAX. L M 0.17 0.25 19.05 (T.P.) 5.08 MAX. 17.0 N 0~15° 0.50±0.10 0.9 MIN. R 2.311 MAX. 0.070 MAX. 0.020 0.035 MIN. 0.126±0.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 0.007 0~15° +0.004 –0.003 0.070 (T.P.) Item "K" to center of leads when formed parallel. +0.10 –0.05 +0.004 –0.005

64 PIN PLASTIC SHRINK DIP (750 mil)

µPD75104, 75106, 75108

64 PIN PLASTIC QFP (14 ×20)

P64GF-100-3B8,3BE,3BR-2 ITEM MILLIMETERS INCHES A B C 23.6±0.4 20.0±0.2 14.0±0.2 0.929±0.016 0.795 0.551 F 1.0 0.039 G 1.0 0.039 H 0.40±0.10 0.016 I 0.20 0.008 K 1.8±0.2 0.071 L 0.8±0.2 0.031 M 0.15 0.006 N 0.10 0.004 P 2.7 0.106 R 5°±5° 5°±5° S 3.0 MAX. 0.119 MAX. +0.008 –0.009 +0.009 –0.008 +0.004 –0.005 +0.008 –0.009 +0.009 –0.008 +0.004 –0.003 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. 5152 32 1 2019 I JM N HG F A S P K L M B C D detail of lead end Q R +0.10 –0.05

µPD75104, 75106, 75108 15. RECOMMENDED SOLDERING CONDITIONS It is recommended that µPD75104, 75106, and 75108 be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-616). For other soldering methods and conditions, please consult NEC. Table 15-1 Soldering Conditions of Surface Mount Type µPD75108GF - xxx - 3BE: 64-pin plastic QFP (14 x 20 mm) Soldering Method Soldering Conditions Infrared Reflow Package peak temperature: 230 °C, time: 30 seconds max. IR30-00-1 (210°C min.), number of times: 1 (200°C min.), number of times: 1 Wave Soldering Soldering bath temperature: 260 °C max., time: 10 seconds WS60-00-1 max., number of times: 1, pre-heating temperature: 120 °C max. (package surface temperature) Pin Partial Heating Pin temperature: 300 °C max., — time: 3 seconds max. (per side) Caution: Do not use two or more soldering methods in combination (except the pin partial heating method). Symbol for Recommended Condition Table 15-2 Soldering Conditions of Through-Hole Type µPD75108CW - xxx : 64-pin plastic shrink DIP (750 mil) Soldering Method Soldering Conditions Wave Soldering Soldering bath temperature: 260 °C max., Time: 10 seconds max. (Only for lead part) Pin Partial Heating Pin temperature: 260 °C max., Time: 10 seconds max. Caution: The wave soldering must be performed at the lead part only. Note that the solder must not be directly contacted to the package body.

µPD75104, 75106, 75108

• CMOS I/O: 32 (pull-up resistor as mask option: 24)
• +12 V open-drain output: 12 (pull-up resistor as mask option) LED direct drive: 44 APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PRODUCTS IN PD751XX SERIES µ Item PD75104 µ PD75106µ PD75108µ PD75112µ PD75116µ PD75104Aµ PD75108Aµ PD75108Fµ PD75112Fµ PD75116Fµ PD75P108Bµ PD75P116µ ROM Configuration Mask ROM PROM ROM (Bits) 000H-FFFH 0000H-177FH 0000H-1F7FH 0000H-2F7FH 0000H-3F7FH 000H-FFFH 0000H-1F7FH 0000H-1F7FH 0000H-2F7FH 0000H-3F7FH 0000H-1F7FH 0000H-3F7FH 4096 × 8 6016 × 8 8064 × 8 12160 × 8 16256 × 8 4096 × 8 8064 × 8 8064 × 8 12160 × 8 16256 × 8 8064 × 8 16256 × 8 320 × 4 (Bank 0: 256 × 4) (Bank 1: 64 × 4) 512 × 4 (Bank 0: 256 × 4) (Bank 1: 256 × 4) 512 × 4 (Bank 0: 256 × 4) (Bank 1: 256 × 4) 320 × 4 (Bank 0: 256 × 4) (Bank 1: 64 × 4) 512 × 4 (Bank 0: 256 × 4) (Bank 1: 256 × 4) RAM (Bits) Instruction Set High-end (Only PD75104 and 75104A are not provided with BR!addr instruction.) High end Total 58 I/O
• CMOS I/O: 32
• +12 V open-drain output: 12 (pull-up resistor as mask option) LED direct drive: 44
• CMOS I/O: 32
• +10 V open-drain output: 12 (pull-up resistor as mask option) LED direct drive: 44
• CMOS I/O: 32
• +12 V open-drain output: LED direct drive: 44
• CMOS input: 10 (pull-up resistor as mask option: 4)
• Comparator input: 44
• CMOS input: 10
• Comparator input: 4
• CMOS input: 10
• Comparator input: 4 Input I/O Lines Power-ON Reset Circuit Power-ON Flag Operating Voltage Range Provided (mask option) µ None 2.7 to 6.0 V 2.7 to 5.0 V (Ta = -40 to +50°C) 2.8 to 5.0 V (Ta = -40 to +60°C) 2.7 to 6.0 V 5 V ± 10% Minimum Instruction Execution Time 0.95 s (at 5 V) µ 3 s (at 3 V)µ 0.95 s (at 4.5 V to 5.0 V) µ 1.91 s (at 3 V) µ 0.95 s (at 5 V) µ 3 s (at 3 V)µ 0.95 s (at 5 V) µ Pin Connections Depends on package Depends on package. Only PD75P108, and 75P116 are provided with VPP pin. µ
• 64-pin plastic shrink DIP (750 mil)
• 64-pin ceramic shrink DIP (w/window)
• 64-pin plastic QFP (14 × 20 mm)
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 20 mm)
• 64-pin plastic QFP (14× 20 mm)• 64-pin plastic QFP (14 × 14 mm)
• 64-pin plastic QFP (14 × 14 mm)
• 64-pin plastic QFP (14 × 14 mm)
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14× 20 mm)
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14× 20 mm) Package

µPD75104, 75106, 75108 APPENDIX B. DEVELOPMENT TOOLS The following development support tools are readily available to support development of systems using µPD75108: Hardware IE-75000-R* 1 In-circuit emulator for 75X series IE-75001-R IE-75000-R-EM* 2 Emulation board for IE-75000-R and IE-75001-R EP-75108CW-R Emulation prove for µPD75108CW EP-75108GF-R Emulation prove for µPD75108GF. It is provided with a 64-pin conversion socket, EV-9200G-64 PG-1500 PROM programmer PA-75P108CW PROM programmer adapter for µPD75P108BCW and 75P108BDW. It is connected to PG-1500. PA-75P116GF Programmer adapter for µPD75P108BGF. It is connected to PG-1500. Software IE Control Program PG-1500 Controller RA75X Relocatable Assembler *1: Maintenance product 2: Not provided with IE-75001-R. 3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function. Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151). EV-9200G-64 Host machine PC-9800 series (MS-DOS TM Ver.3.30 to Ver.5.00A* 3) IBM PC/AT TM (PC DOS TM Ver.3.1)

PD75104, 75106, 75108 APPENDIX C. RELATED DOCUMENTS

µPD75104, 75106, 75108

1 STATIC ELECTRICITY (ALL MOS DEVICES)

Exercise care so that MOS devices are not adversely influenced by static electricity while being handled. The insulation of the gates of the MOS device may be destroyed by a strong static charge. Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case, or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use grounding when assembling the MOS device system. Do not leave the MOS device on a plastic plate and do not touch the pins of the device. Handle boards on which MOS devices are mounted similarly .

2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)

Fix the input level of CMOS devices. Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its input pin, intermediate level input may be generated due to noise, and an inrush current may flow through the device, causing the device to malfunction. Therefore, fix the input level of the device by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an output pin (whose timing is not specified), each pin should be connected to V DD or GND through a resistor. Refer to “Processing of Unused Pins” in the documents of each devices.

3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)

The initial status of MOS devices is undefined upon power application. Since the characteristics of an MOS device are determined by the quantity of injection at the molecular level, the initial status of the device is not controlled during the production process. The output status of pins, I/O setting, and register contents upon power application are not guaranteed. However, the items defined for reset operation and mode setting are subject to guarantee after the respective operations have been executed. When using a device with a reset function, be sure to reset the device after power application. GENERAL NOTES ON CMOS DEVICES

µPD75104, 75106, 75108 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for the applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime system, etc. MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. M4 92.6