PD70211

PD70211 MICROSEMI | Alldatasheet

Document overview

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Technical content

Features

 Supports IEEE802.3af/at, HDBaseT and other 2- pair/4-pair configurations  Wall-adapter support (Rear Aux method)  PD detection & programmable classification  2,3,4, and 6 event classification  Integrated 0.3Ω isolating (series-pass) FET  Inrush current limiting  Less than 10µA offset current during detection  Advanced PWM section  Lead-free MLPQ-36 (6 × 6 mm) package

Applications

 HDBaseT up to 95 Watts  IEEE802.3af and 802.3at  Power Forwarding  Indoor and outdoor PoE 31 VH

32 VAUX_VCC

0.1µF/10V 0.1µF/10V 17 SS0.1µF/10V VCC

18 RCLP

12 ENABLE

0.1µF/ 25V 10µF/ 25V HYST14 562k 18.7k 562k RFREQ1649.9k GND PGND VSN SG CSN 28 Si7852ADP 3A/80V120µH/1.5A 57V/0.6A PD70211 (PWM SECTION) Loop compensation will need to be tweaked PG 30 100 1nF 29CSP BOOST CONVERTER (FOR 0.6A, PoE Applications) VSP SYNC DAO RDET36 24.9k 1% RCLASS5 RREF4 30.9k 243k EPAD (Pin 37) VPN_IN8 , 9 VPP35 VPN_OUT 10 , 11 VAUX_VCC32 WA_EN 33 SUPP_S1 1 AT_FLAG 7 AT_FLAG SUPP_S2 2 VPN 0.1µF/100V SMAJ58A PD70211 (Front-End SECTION) FB 23 COMP 21 4 x ERJ-1TYJ2R4U (Four 2.4Ω/1W) 21.5k 4.99k 237k 2nF 100pF 215k330pF 330µF/63V/ Aluminum STAND-ALONE PD SOLUTION FOR POWER FORWARDING 4P_AT_FLAG 3 4P_AT_FLAG HD_FLAG 6 HD_FLAG 4P_HD_FLAG 34 4P_HD_FLAG SUPP_S1 SUPP_S2 SUPP_S1 VPortN1 VPortP1 VPN VPP SUPP_S2 VPortN2 VPortP2 VPN VPP VPN Figure 1: Typical Applications Diagram (PD70211)

Copyright © 2016 Microsemi Page 2 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Configuration VPN_OUT VPN_OUT ENABLE VINS HYST SYNC RFREQ SS RCLP EPAD (Pin 37) SUPP_S1 SUPP_S2 4P_AT_FLAG RREF RCLASS HD_FLAG AT_FLAG VPN_IN 9VPN_IN 19 VSN VSP COMP DAO FB GND VL SG

27 PGND

VAUX_VCC WA_EN 4P_HD_FLAG VPP RDET 10 11 12 13 14 15 16 17 18 282930313233343536 PD70211 (Top view) Figure 2: Pinout of PD70211 (top view)

Ordering Information

Temperature Type Part Marking Ordering P/N Package Note -40°C to 85°C RoHS compliant, Pb-free MSCC Logo 70211 Assembly site and production revision identifiers Date/Lot Code PD70211ILQ- TR MLPQ-36 (6 mm × 6 mm, 0.5mm pitch)

Copyright © 2016 Microsemi Page 3 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Description (PD70211) Pin Number Designator Description

1 SUPP_S1

Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin along with the SUPP_S2 pin can be used to distinguish between 2 -pair and 4-pair operation. (For PSEs that operate in 4 pairs but do not generate the classification procedure on both pair but one pair only). Signal is referenced to VPN_IN. Place a 10k resistor in the input of this pin.

2 SUPP_S2

Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin along with the SUPP_S1 pin can be used to distinguish between 2 -pair and 4-pair operation. (For PSEs that operate in 4 pairs but do not generate the classification procedure on both pair but one pair only) . Signal is referenced to VPN_IN. Place a 10k resistor in the input of this pin. 3 4P_AT_FLAG Open Drain Output. The pin gets actively pulled low when a 4-pair version of a (non- standard) Type 2 PD-PSE mutually identifies each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT 4 RREF Bias current resistor. A 60.4k, 1% resistor is connected between RREF and IC ground (VPN_IN)

5 RCLASS

Sets the Class of the PD. Connect RCLASS (programming resistor) between this pin and IC ground (VPN_IN). Allowed values are 133 Ω, 69.8 Ω, 45.3 Ω, and 30.9 Ω for Class 1, 2, 3, and 4 respectively. If RCLASS is not present, the PD will draw up to 3 mA during classification, thus indicating Class 0 (default Type 1) to the PSE. Signal is referenced to VPN_IN

6 HD_FLAG

Open Drain Output. The pin gets actively pulled low when a 2-pair HDBaseT PD-PSE mutually identify each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT

7 AT_FLAG

Open Drain Output. This pin gets actively pulled low when a Type 2 PD -PSE mutually identifies each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT 8, 9 VPN_IN Lower rail of the incoming PSE voltage rail – from the negative terminal of the two OR-ed bridge rectifiers (the corresponding upper PoE rail is VPP) 10, 11 VPN_OUT This is in effect, the switched ground for establishing continuity to the PWM section after successful detection, classification, and Power-up. It is connected to the Power ground and PWM controller IC’s ground plane of the DC-DC converter section

Copyright © 2016 Microsemi Page 4 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number Designator Description A logic-level input to enable the converter. We can pull it constantly up, say with a 100k resistor to VDD, to forcibly enable the converter. Provided the input supply has exceeded any applicable UVLO thresholds, of course, as set on the VINS pin or on the VCC pin. Internally, the ENABLE pin actually goes to the input of an OR-gate, the other input terminal of which is tied to “POK” – a signal provided by the front-end. If the ENABLE pin is forced high, the output of the OR-gate goes high and the converter is allowed to start (provided all UVLO’s are past of course). If the ENABLE pin is held low, the internal node “POK” goes active high when the PD’s front end conducts (power OK), so the OR-gate goes high once again. In this case the switching converter turns ON naturally and correctly as required by the PoE standard. However, for supporting wall-adapters, injecting power after the front- end (at the input of the converter), we can forcefully turn the converter ON without the front-end signaling “PGOOD”, by not tying the ENABLE pin low, but by tying it high (to VDD). That will turn ON the converter irrespective of the state of the front-end (conducting or not), and whether there is any incoming PoE power or not.

13 VINS

The VINS pin is a programmable UVLO pin. The converter will turn ON provided the voltage on the VINS pin is above 1.2V (and VCC is not in UVLO, and ENABLE pin is also high – connected to VDD for example). The converter will stop switching (turn OFF) when the voltage on the VINS pin falls below 1.2V (or if ENABLE is taken low, or if VCC falls outside its operating range). Thus by connecting a voltage divider between input rail and IC ground, we can set the UVLO threshold to enable switching. However, to have a smooth startup, it is advisable to have some hysteresis too, by means of a resistor between VINS and HYST as explained below.

14 HYST

This is the output of the UVLO comparator as shown in the Block Diagram. We connect a “hysteresis resistor” from HYST pin to VINS pin to create positive feedback (and hysteresis). Initially, as the input voltage is rising, the VINS pin voltage is below 1.2V and so the output of the UVLO comparator is low, and the hysteresis resistor falls in parallel to the lower resistor of the UVLO divider placed at the VINS pin, assisting it by pulling down the VINS pin voltage further. As soon as the rising UVLO threshold is exceeded (VINS > 1.2V), the output of the UVLO comparator suddenly goes high (up to VDD) and the hysteresis resistor, effectivel y comes partially across the upper resistor of the UVLO divider, assisting it in the act of pulling up on the VINS pin. This feedback therefore increases the voltage on the VINS pin. And so, now the input rail has to fall to a much lower level to allow the VINS pin voltage to fall below 1.2V. That is how hysteresis is created by positive feedback action through the hysteresis resistor. The exact math is in the applications information of this datasheet. Note that HYST pin always toggles high or low depending on whether the voltage on the VINS pin is above or below 1.2V respectively. This can always be used to simultaneously drive an opto, to indicate when the input rail is above the programmed rising threshold and when it falls below the programmed falling threshold.

15 SYNC

Used to synchronize the LX7309 to a frequency higher than its default value as set on RFREQ pin. The synchronizing clock must be 2x the desired sync frequency, with a maximum synchronizing clock frequency of 1MHz (for 500kHz PWM frequency). The PG pin’s rising edge will occur at the same instant as the rising edge of the clock being applied on the SYNC pin.

Copyright © 2016 Microsemi Page 5 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number Designator Description

16 RFREQ

Connect a programming resistor from this pin to IC ground (pin GND) to set the switching frequency. A typical value of the programming resistor is 49.9k, and this value will provide a frequency between 215kHz. Halving it will roughly double the frequency, whereas doubling it will halve the frequency. Note that the converter is designed to operate from 100 to 500 kHz based on this pin. Switching Frequency Equation: 𝐹𝑟𝑒𝑞 = (90𝑝𝐹 ×𝑅𝐹𝑅𝐸𝑄)+ 150𝑛𝑠 where Freq is [Hz] and RFREQ in [Ω] For further information refer to Setting Switching Frequency. 17 SS This is the soft-start pin. Typically a 0.1µF cap, the “soft-start capacitor”, is connected between this pin and IC ground (pin GND). The capacitor gets charged up to 1.2V by an internal resistor, and the voltage on the cap in effect forms the input voltage referen ce VREF of the error amplifier. But note that this capacitor serves other functions too; for example, it controls the rate of hiccupping under overcurrent fault conditions. So even if the internal reference is not being used (as in isolated topologies with a TL431 on the Secondary side), the soft-stat cap is always recommended to be in place. The actual capacitor used will be determined by the application. For further information refer to Setting Soft-Start. Low power clamp resistor. We can connect a resistor from this pin to IC ground (pin GND) to set the exact level at which pulse-skipping mode is entered at light loads. However, the usual default is to connect this pin directly to IC ground, in which case pulse -skipping mode is disabled. The method to select the threshold (and RCLP resistor value) is described in the Applications Information section of this datasheet.

19 VSN

The negative input of the internal differential-sense voltage amplifier. Note that the common-mode range of the differential voltage amplifier is 3.5V and its gain is 7. We can use this differential amplifier for implementing topologies where the “system (output) ground” is different from the IC ground. We can then step-down both output rails (output rail and its return), by equal amounts, using identical voltage dividers, to bring the voltage below 3.5V, then use differential sensing, and finally connect the output of the differential voltage amplifier (pin DAO) to FB pin.

20 VSP

The positive input of the internal differential-sense voltage amplifier. Note that it must always be connected in such a way that VSP is at a higher voltage than VSN. Also keep in mind that since the differential voltage amplifier has a gain of 7 and the output of that amp is connected to the feedback pin which compares that against a 1.2V reference, in effect, the difference between VSP and VSN stabilizes to 1.2V/7 = 0.171V in steady state. That is how we design the (identical) voltage dividers present on VSP and VSN.

Copyright © 2016 Microsemi Page 6 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number Designator Description

21 COMP

This is the output of the internal error amplifier, and the input of the PWM comparator. It is brought out to support isolated topologies because in such cases, there is an error amplifier already present on the Secondary side (for example a TL431 or equivalent). Therefore we want to bypass the error amplifier of the converter section. On the other hand, in non- isolated topologies, we want to use the error amplifier of the converter. We can do that directly, or through the differential voltage amplifier stage.

22 DAO

This is the output of the internal differential voltage amplifier (gain = 7). When this amplifier is used, we connect DAO to the feedback pin (FB). We have part of the compensation network between the two pins, and this network is typical of any Type 3 error amplifier input, with or without a differential amplifier present. 23 FB This is the feedback pin of the IC. It is internally compared to a 1.2V reference. If the internal error amplifier is not used and the COMP pin is being used to inject the error signal (as in isolated topologies), the FB pin can be either tied high (to VDD), or connected to COMP.

24 GND

This is the IC ground. In more detail this is the analog (quiet) ground of the IC. Pin 20 is th e Power ground (PGND). Typically, we can connect the analog ground and PGND together on a copper island on the component side, and then connect that through several vias very close to the chip on to a large ground plane which extends up to the lower side of the current sense resistor. All chip decoupling can then be very simply with respect to the copper island on the component side. 25 VL This is created by an internal LDO and basically provides a housekeeping rail for the IC itself, which is 5V with respect to the IC ground. A 1µF ceramic cap placed close to this pin, connected to IC ground is recommended for proper decoupling. This pin can also provide up to 5mA for external circuitry if required, thermal aspects (IC dissipation) being considered. 26 SG Secondary Gate driver. We can use this to drive a synchronous FET or an active clamp FET. It is derived from VCC (~ 12V), and has a 10Ω limiting resistor. So it can be used to drive a Gate-drive transformer directly. It is usually complementary to the Primary Gate driver pin (PG). But there is a typical 110ns blanking time between the two to prevent cross - conduction. SG is held firmly low in pulse-skip mode (if allowed). It is also low during soft- start. It allows forced PWM (continuous conduction) mode by allowing negative inductor currents. It does not support diode-emulation mode (discontinuous conduction mode). However, in pulse-skip mode, since SG stays OFF, the converter automatically lapses into discontinuous conduction mode through the body-diode of the synchronous FET. We can leave this pin floating if unused. Power ground (for internal SG and PG drivers). This is also best for VCC decoupling, and the Primary-side current sense resistor’s lower terminal. We can also combine GND an PGND on to a single large ground plane. Note that Power ground plane is firmly connected to VPN_OUT, which is the Drain side of the PD’s low-side pass-FET (it stands for Negative Port Voltage Out).

Copyright © 2016 Microsemi Page 7 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Pin Number Designator Description

28 CSN

The negative input of the internal current-sense voltage amplifier. Note that the common- mode range of the differential current-sense amplifier is 2V and its gain is 5. We can use this for high-side current sensing up to 2V. It is then placed on the (steady) output side of a Buck inductor, and the max output voltage is 1.8V for using this type of sensing. Ensure that CSN is at a lower voltage compared to the positive input of the current-sense amplifier (CSP). Current sensing can also be implemented in a more basic fashion for “low -side” sensing, with a resistor in the return (ground) of the Buck. In that case CSN is shown connected to IC ground. However, to avoid noise from ground bounce, it is best to route this on the PCB in Kelvin manner to the lower end of the sense resistor. This is important because the peak operating voltage on the sense resistor is only 200mV and PCB-related noise can cause jitter in the switching waveform in current-mode control.

29 CSP

The positive input of the internal current-sense voltage amplifier. See discussion for Pin 28 (CSN) above. Note that the output of the current-sense amplifier is amplified 5 times. So a 0.2V current-sense voltage translates to a 1V swing at the input of the PWM comparator. Higher voltages lead to hiccup mode protection. 30 PG This stands for Primary Gate driver. We can use this to drive the main FET, and it has a 5 or 10Ω limiting drive resistor switched between a voltage close to VCC rail and the IC ground. For guaranteeing proper shutdown during OFF time, it is necessary to add a 470k resistor from PG to VINS, as shown in Figure 1. 31 VH Internal rail of -5V with respect to VCC, brought out only for decoupling purposes. Connect a 0.1µF ceramic cap very close, from this pin to VAUX_VCC pin. Auxiliary voltage rail from front-end to the VCC (supply) input of the PWM section. The front-end provides a few mA of startup current for the PWM controller (at typically 10.5V). Signal is referenced to VPN_OUT and is activated once front end power up sequence is end . After initial startup of PWM section, a bias winding can be connected to this pin through a diode, to sustain the PWM section.

33 WA_EN

While this input is low (referenced to VPN_IN) the chip work according to internal flow diagram. When this input is high, it enable wall adapter feature. Place 100nF/10V capacitor from WA_EN to VPN_IN pins, locate it close to device. When WA_EN is not used, connect it to VPN_IN. For further information, refer to External source connected to PD device output. 34 4P_HD_FLAG Open Drain Output. The pin gets actively pulled low when a 4 -pair HDBaseT PD-PSE mutually identify each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT

35 VPP Upper rail of the incoming PSE voltage rail – from the positive terminal of the two OR-ed

bridge rectifiers (the corresponding lower PoE rail is VPN_IN) 36 RDET Internally connects to VPN_IN during detection phase and disengages after it is over. A 25KΩ (or 24.9K), 1% resistor is connected between this pin and VPP

37 EPAD Connected on PCB plane to VPN_IN

Copyright © 2016 Microsemi Page 8 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Functional Block Diagram RDET RCLS VPP SUPP_S1 SUPP_S2 VPN_IN WA_EN 4P_AT_FLAG HD_FLAG AT_FLAG 4P_HD_FLAG VPN_OUT Enhanced Classification Block Startup/ Inrush control VAUX_VCC10.5V regulator 4.8V regulator Vdd45mA 1.2V Bandgap Bleeder control Detection control RREF Iclass Class control Temp Temp +48V 48VRTN Rsense RCLASS RDET RREF 80ms delay timerVPP UVLO Figure 3: Block Diagram (PD70211 front-end section)

Copyright © 2016 Microsemi Page 9 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications VCC VCC Dead time Blanking and Limiting offset CLK Clock SYNC RFREQ offset × 7 × 5 Differential Current sense amplifier Differential Voltage sense amplifierPulse skip Mode Rskip RCLP Soft-start / Logic Csoftstart Enable ENABLE SS FB DAO Differential amp output Vout_high Vout_low COMP Rsense Rupper Rlower Rupper Rlower PWM logic VREF Vin UVLO/PFW select SYNC DAO VDD VIN VIN Rfreq VINS 13 HYST 14 VSN VSP CSP CSN SG PG Chip Supply VAUX_VCC 32 5V drop “High” Internal Rail VH 315V LDO “Low” Internal Rail (VDD) VL VREF (1.2V) Decoupling for VH rail Decoupling for VL (VDD) rail PD70211 (PWM section) GND 24 PGND 27 POK Figure 4: Block Diagram (PD70211 PWM section)

Copyright © 2016 Microsemi Page 10 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Absolute Maximum Ratings Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability. Voltages are with respect to IC ground (VPN_IN). Min Max Units VPP, VPN_OUT, RDET -0.3 74 V AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG -0.3 20 V SUPP_S1, SUPP_S2 0 VVPP + 1.5 V RREF, RCLS, WA_EN -0.3 5 V VAUX_VCC -0.3 20 V PG, SG -0.3 20 V VL -0.3 6 V VH (with respect to VAUX_VCC) 0.3 -6 V ENABLE All other pins -0.3 VL+0.3 V Junction Temperature -40 150 °C Lead Soldering Temperature (40s, reflow) 260 °C Storage Temperature, MSL3 -65 150 °C ESD rating HBM ±1.5* kV MM ±50 V CDM ±500 V *Pins VPP, VAUX/VCC , RREF pass ±1kV HBM only. Operating Ratings (Front-End Section) Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. voltages are with respect to IC ground (VPN_IN). Min Max Units VPP 0 57 V Ambient Temperature* -40 85 °C Detection Range 1.1 10.1 V Mark event range 4.9 10.1 V Class event range 13.7 20.9 V * Corresponding Max Operating Junction Temperature is 125°C.

Copyright © 2016 Microsemi Page 11 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Operating Ratings (PWM Section) Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. Voltages are with respect to IC ground. Min Max Units VCC 7.8 20 V Fsw (adjustable frequency range) 100 500 kHz Max Duty Cycle 44.5 % fsw_synch (synchronization frequency range) 200 1000 kHz Thermal Properties Thermal Resistance Min Typ Max Units θJA 22.3 °C/W θJP 3 °C/W θJC 4 °C/W Note: The Jx numbers assume no forced airflow. Junction Temperature is calculated using T J = TA + (PD x JA). In particular, θJA is a function of the PCB construction. The stated number above is for a four -layer board in accordance with JESD-51 (JEDEC). Electrical Characteristics (Front-End Section) Unless otherwise specified under conditions, the Min and Max ratings stated below apply over the entire specified operating ratings of the device. Typ values stated, are either by design or by production testing at 25°C ambient. Voltages are with respect to IC ground (VPN_IN). Symbol Parameter Conditions Min Typ Max Units Input Voltage IIN IC input current with ICLASS off VPP=55V 1 3 mA Detection phase VDET Detection range 1.1 10.1 V RDET_TH RDET disconnect threshold 10.1 12.8 V RDS_DET_ON On-resistance of internal FET during detection 50 Ω

Copyright © 2016 Microsemi Page 12 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter Conditions Min Typ Max Units RDS_DET_OFF Off-resistance of internal FET after detection 2 MΩ IOFFSET_DET Input offset current 1.1V ≤ VPP ≤ 10.1V, TJ ≤ 85°C 5 μA VR_DET_ON RDET reconnection threshold when VPP goes low 2.8 3.0 4.85 V Classification phase VCLS_ON Classification sink turn- on threshold 11.4 13.7 V VCLS_OFF Classification sink turn- off threshold 20.9 23.9 V VHYS_CLS_ON Hysteresis of VCLS_ON threshold 1 V VMARK_TH Mark detection threshold (VPP falling) 10.1 11.4 V IMARK Current sink in Mark event region 0.25 4 mA ICLASS_CLIM Current limit of class current 50 68 80 mA ICLASS Classification current sink RCLASS = not present (Class 0) 3 mA RCLASS = 133 Ω (Class 1) 9.5 10.5 11.5 RCLASS = 69.8 Ω (Class 2) 17.5 18.5 19.5 RCLASS = 45.3 Ω (Class 3) 26.5 28.0 29.5 RCLASS = 30.9 Ω (Class 4) 38.0 40.0 42.0 Isolation FET RDSON On resistance Total resistance between VPN_IN to VPN_OUT; ILOAD < 600mA, -40oC <TA < 85oC 0.3 Ω ICLIM_INRUSH Inrush current limit 105 240 325 mA OCP Overcurrent protection 2.2 A

Copyright © 2016 Microsemi Page 13 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter Conditions Min Typ Max Units ILOAD Continuous operation load 2 A Undervoltage Lockout UVLOON Threshold that marks start of Inrush phase 36 42 V UVLOOFF Threshold where pass- FET turns off as VPP collapses 30.5 34.5 V DC-DC Input Cap Discharger ICAP_DIS Discharge current 7V ≤ VPP ≤ 30V 22.8 60 mA tdis Discharge time CDC_DC ≤ 264 μF (by design, not tested) 500 ms timerdis Discharge timer Time for which discharge circuit is activated 430 ms References, Rails and Logic VAUX Auxiliary voltage 0mA < IAUX < 4mA 9.8 10.5 12.0 V IAUX Max continuous current from VAUX 4 mA IAUX_CLIM Aux current limit 10 32 mA VREF Bandgap reference voltage 1.17 1.2 1.23 V tFLAG_LO Low level flag For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG, IFLAG= 3mA 0.4 V IFLAG Flag Current driving capability For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG 5 mA tFLAG Delay timer between start of inrush and flags declared For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG 80 ms VSUPP_HI SUPP_Sx high voltage threshold For SUPP_S1 and SUPP_S2 25 35 V

Copyright © 2016 Microsemi Page 14 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Wall Adapter Min Typ Max Units VIH Input high logic 2.4 V VIL Input low logic 0.8 V Truth Table for Status of Flags Number of Fingers “N” (N-Event classification) SUPP_S1 SUPP_S2 AT_FLAG HD_FLAG 4P_AT_FLAG 4P_HD_FLAG

1 X X Hi Z Hi Z Hi Z Hi Z

2 H L 0V Hi Z Hi Z Hi Z

2 L H 0V Hi Z Hi Z Hi Z

2 H H 0V Hi Z 0V Hi Z

3 L H 0V 0V Hi Z Hi Z

3 H L 0V 0V Hi Z

3 H H 0V 0V 0V Hi Z

4 X X 0V 0V 0V Hi Z

5 RESERVED FOR FUTURE

6 X X 0V 0V 0V 0V

Electrical Characteristics (PWM Section) Unless otherwise specified under conditions, the Min and Max ratings stated below apply over the entire specified operating ratings of the device. Typ values stated, are either by design or by production testing at 25°C ambient. Voltages are with respect to IC ground (VPN_IN). Symbol Parameter Conditions Min Typ Max Units Input Voltage Current VCC_UVLO_UP UVLO threshold with input rising VCC rise time > 0.5 ms 8.85 9.15 9.5 V VCC_UVLO_DN UVLO threshold with input falling VCC rise time > 0.5 ms 7 7.3 7.6 V IVCC_SD IC input current (no switching) VENABLE = Low, or VVCC < VCC_UVLO_UP 1 2000 µA

Copyright © 2016 Microsemi Page 15 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter Conditions Min Typ Max Units IVCC_Q IC input current (switching, no load on SG, PG, VDD) VENABLE = High, and VVCC > VCC_UVLO_UP, fsw = 500kHz 3 mA Input UVLO/PFW VINS_TH Threshold on VINS pin Rising or falling 1.171 1.200 1.229 V VHYST_HIGH Hysteresis pin high voltage IHYST_SOURCING = 1mA 2.8 V VHYST_LOW Hysteresis pin low voltage IHYST_SINKING = 3mA 0.4 V LDOs VL IVDD_EXT < 5mA (current out of pin) 4.75 5 5.25 V VH VH rail (with respect to VCC) -5V V Soft Start ISS_CH Current out of SS pin during charging phase RFREQ=33.3k, VSS=0.5V 32 36 40 µA ISS_DISCH Current into SS pin during discharging phase RFREQ=33.3k, VSS=0.5V 10 % of ISS_CH VSS_CH Soft start charge completed threshold By design only 90 95 % of VREF VSS_DISCH Soft start discharge completed threshold 50 mV RSS_DISCH Soft-start pin discharge FET resistance 50 Ω

Copyright © 2016 Microsemi Page 16 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter Conditions Min Typ Max Units tDISCH Soft-start discharge FET on-time 32 Switch cycles Switching Frequency and Synchronization fsw_range Switching frequency accuracy RFREQ=33.2k 285 315 345 kHz fsync_max Max synchronization frequency 1 MHz VSYNC_HI SYNC pin high threshold 2.4 V VSYNC_LO SYNC pin low threshold 0.8 V tsync Minimum pulse width of SYNC pulse 100 ns Dsync_max Max SYNC pulse duty cycle 90 % Error Amplifier VREF Reference voltage 1.171 1.200 1.229 V GainDC_OPL DC Open-loop gain Rload=100k 70 100 dB AVUGBW Unity Gain Bandwidth Cload=10pF (By design only) 2 5 MHz ICOMP_OUT Output sourcing current 0.2V< VCOMP < 1.3V 110 620 µA ICOMP_IN Output sinking current 0.2V< VCOMP < 1.3V 145 495 µA VEA_CMR_MAX Max of input common- mode range 2 V VCLAMP COMP pin high clamp 1.8 2.1 2.6 V

Copyright © 2016 Microsemi Page 17 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter Conditions Min Typ Max Units PWM Comparator VOFFSET Inserted offset in inverted input 200 300 mV VRCLP Voltage set on RCLP pin by external resistor to GND 0 1 V Current Sense Amplifier GainCSA DC Gain 4.75 5 5.25 V IAUX Max continuous current from VAUX 4 mA VCSA_CMR_MAX Max input common- mode range 2 V tBLANK Blanking time 50 100 ns VILIM Current limit threshold on output of current sense amplifier Where PWM pulses start to get truncated 1.1 1.2 1.3 V VILIMHICCUP Current Limit threshold on output of current sense amplifier capability Where PWM pulses start to get omotted in hiccup mode 1.7 1.8 1.9 V Differential Voltage Amplifier GainDA DC gain of differential voltage amp 6.68 7.0 7.14 AVUGBW_DA Unity Gain Bandwidth of differential voltage amp

5 MHz

VDA_CMR_MAX Max of input common- mode range 3.5 V Drivers RPG_HI Drive resistance when PG is high 10 Ω RPG_LO Drive resistance when PG is low 5 Ω tPG_MIN Minimum on-time of PG 120 ns DMAX PG max duty cycle 44.5 50 %

Copyright © 2016 Microsemi Page 18 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Symbol Parameter Conditions Min Typ Max Units RSG_HI Drive resistance when SG is high 10 Ω RSG_LO Drive resistance when SG is low 10 Ω tDEAD Deadtime PG low to SG high or PG high to SG low 60 110 190 ns Logic Levels on VINS and ENABLE VHI Input high threshold 2 V VLO Input low threshold 0.8 V Thermal Protection TSD Thermal shutdown (rising) 157 °C THYST Thermal shutdown hysteresis 15 30 °C Thermal Protection PD70211 is protected from excessive internal temperatures that may occur during various operating procedures. Two temperature sensors are located on the chip, monitoring the temperatures of the following:  Isolating Switch (pass-FET)  Classification Current Sink Each of the over temperature sensor activates a protection mechanism that will disconnect the Isolation (pass) FET or the classification circuit respectively. This protects the device from being permanently damaged or even from long-term degradation.

Copyright © 2016 Microsemi Page 19 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Truth Table for Status of Flags Number of Fingers “N” (N-Event Classification) SUPP_S1 SUPP_S2 AT_FLAG HD_FLAG 4P_AT_FLAG 4P_HD_FLAG PD70211 support wall adapter functionality, i.e. by setting WA_EN pin high it will give priority to the wall adapter jack to supply the load. WA_EN pin is used while connecting a wall-adapter voltage between VPP and VPN_OUT by means of an OR- ing diode. While WA_EN, Wall-adapter enable pin, is held low (referenced to VPN_IN), the front-end works as a normal PD. When WA_EN is raised high (referenced to VPN_IN) three internal operations are forced:  The Isolation FET is turned OFF.  All output flags AT_FLAG, HD_FLAG, 4P_AT_FLAG and 4P_HD_FLAG are activated (low state).  Vaux output voltage is turned ON. While activating WA_EN pin, the wall-adapter will supply input voltage for the DC-DC converter. Having WA_EN at high state does not disable detection and classification modes.

Copyright © 2016 Microsemi Page 20 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Applications Information Peripheral devices  An 100nF/100V capacitor should be placed between device VPP and VPNI pins, and located as close as possible to the device.  An 58V TVS should be placed between device VPP and VPNI pins.  An 10K ohm resistor should be placed on SUPP_S1 and SUPP_S2 lines between diode bridge and PD70211 device.  When WA_EN is used, an 100nF/10V Capacitor should be placed between WA_EN and VPNI pin close to PD70211 device.  When not used, WA_EN should be connected to VPNI pin. Setting Switching Frequency A resistor, RFREQ, is connected from RFREQ pin to IC ground. Based on that, we get the following frequency 𝐹𝑟𝑒𝑞 = 1 (90𝑝𝐹 × 𝑅𝐹𝑅𝐸𝑄) + 150𝑛𝑠 where Freq is [Hz] and Rfreq in Ω For example, by setting RFREQ=49900Ω, we get 𝐹𝑟𝑒𝑞 = 1 (90𝑝𝐹 × 49900Ω) + 150𝑛𝑠 = ~215000𝐻𝑧 We can set any frequency between 100 to 500 kHz. Note that when synchronizing, the default frequency (as set by RFREQ) must be lower than the synchronization clock. In case the synchronization breaks, the converter will lapse back to the default value. When synchronizing, we can increase the frequency to 1MHz.

Copyright © 2016 Microsemi Page 21 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Setting Soft-Start A capacitor is connected between SS pin and IC ground. The current charging the capacitor is SS_CHG 1.2VI (in seconds)RFREQ For example, if RFREQ=49.9k, we get SS_CHG 3 1.2VI (in Amperes) = 2.4 10 24 A 49.9 10 So, charging a 0.1µF ceramic cap on the soft-start pin from 0 to 1.2V will take SS SS_CHG C V 0.1 1.2 0.12t (in seconds) = (in seconds) = (in sec onds) = 5 10 (in seconds) 5ms24 24I This is the soft-start time in this case. Setting Pulse-skip Mode threshold If a programming resistor RCLP is placed between RCLP pin and IC ground, the clamping voltage level is given by CLP

0.3 RCLPV (in Volts)RFREQ

For example, if RCLP = RFREQ, say both are 49.9k, then the converter will enter pulse skipping when the output of the current sense amplifier drops to 0.3V. Note that the gain with this current amplifier is 5, so in terms of the voltage on the sense resistor (input of the current amp), we get 0.3V/5 = 0.06V. Since we usually design the converter so that its peak is around 0.2V (the peak of Rsense voltage before it starts to current limit), we are getting a ratio of 0.06V/0.2V = 0.3. In other wor ds, the converter will enter pulse -skipping when the output current is 30% of the max designed output current. Setting UVLO/Hysteresis thresholds Note: A 470k resistor from PG pin to VINS pin is required for guaranteeing proper termination of Gate drive pulse during UVLO. Suppose we have a divider connected to input at the VINS pin. Suppose we call the resistors R UPPER and RLOWER. We also have a hysteresis resistor, R HYST, from the output of the UVLO comparator, which provides positive feedback on to t he VINS pin, as explained in the Pin Description section. So, when the input voltage is rising, in

Copyright © 2016 Microsemi Page 22 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications effect the hysteresis resistor is in parallel to the lower resistor R LOWER. When the voltage on the VINS pin rises above 1.2V, the UVLO comparator flips and the hysteresis resistor appears connected to 5V (output of the UVLO comparator). The equivalent configurations are shown in Figure 5. After solving the equations, the following example indicates the set thresholds. The values are as used in Figure 3.    UPPER LOWER HYST LOWER HYST LOWER HYST LOWER _ EQUIV LOWER HYST R 270k; R 8.66k; R 270k Part 1: (VINS less than 1.2V) Equivalent lower resistor is a parallel combination of R and R RR 8.66k 270kR 8.391 R R 8.66k 270k UVLO_ UP LOWER _ EQUIV k The rising voltage threshold is RR 270k 8.391kV VREF 1.2V 39.8V R 8.391k     UPPER UPPER UVLO_ DN LOWER HYST Part 2: (VINS greater than 1.2V) RRV VREF VDD VREF VREFRR So with the selected resistors, we get a rising threshold of 39.8V, and a falling threshold of 34.8V. VIN RUPPER RLOWER RHYST VVINS < 1.2V Rising Input VIN RUPPER RLOWER RHYST VVINS > 1.2V Falling Input Figure 5: Equivalent Diagrams for UVLO and Hysteresis

Copyright © 2016 Microsemi Page 23 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Setting the Voltage Divider for Output Rails Generically, we can state the equation to be  UP LOW OUT X LOW RRVV R Where RUP is the name we have given to the u pper resistor (connected to output rail) and R LOW is the name we have given here to the resistor connected to lower rail (usually IC ground). However, there are so many topologies, we have in effect thress cases in all the typical schematics presented so far. a) Non-isolated topologies with simple divider connected directly to FB pin. For this use VX = 1.2V. b) Isolated topologies with divider to another reference (such as TL431 with an internal reference of 2.5V). For this use VX = 2.5V. c) Non-isolated topologies with a differential divider connected to differential voltage amplifier of the LX7309 . Here we use the same divider equation provided above, but using V X = 0.171V (that is 1.2V divided down by the gain of the diff-amp, i.e. by 7). We need two identical dividers. Selecting the Sense Resistor In a Buck topology, the center of the switch current ramp equals the output current. To that we need to add about 30% for the peak current “IPEAK+” because of the rising ramp caused by the inductor. That is a factor of 1.3. We also need to include some headroom for proper transient response at max load. Since the peak voltage on the sense resistor is 0.2V, to leave headroom, we should plan that the switch current peak stays at around 0.18V max at max load. This means that:   PEAK O SENSE OO I 1.3 I , So 0.18 0.138 R = 1.3 I I SENSE O

0.138 R = (Buck) I

Assuming we have designed the converter to operate up to 44% max duty cycle, we can quickly estimate the peak current as follows.

Copyright © 2016 Microsemi Page 24 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications For example, if we have a Buck application for 5A output, irrespective of the input and output voltage conditions (as long as they are not violating the min and max duty cycle limits of the converter), and assuming we have selected inductance appropriately, we should pick a sense resistor of SENSE 0.138R =0.028 5A We may need to put an adjust resistor in parallel (such as the “22Ω” placeholder) we have shown in all the typical application schematics. For a Forward converter (Buck with a transformer), instead of the load current IOR in the above equation, use the reflected load current of I O/n, where n is the turns ratio (number of Primary -side turns divided by number of Secondary-side turns). You will also need to lower the sense resistance further (by means of the adjust resistor), to account for the magnetization current component on the switch side. So roughly:  P SENSE OS N0.138R (Forward) IN For a Boost or Buck-Boost, we have to account for the fact that the peak current is not just 1.3 times max load current, but is actually   O PEAK II 1.3 (where D can be as high as 44%) 1D So we should use the following equation for sense resistor O O O 0.18 1 D 0.101 1R = = 1.3 I 1.3 I 13 I SENSE O 0.077R (Boost, Buck-Boost) I For example, if the max load current is 5A, the sense resistor value to use is SENSE 0.077R =0.015 5A As we can see, this is roughly half of what we got for the Buck (same load current). For a Flyback topology (Buck-Boost with a transformer), we have to use the reflected output current. So we get:  P SENSE OS N0.077R (Flyback) IN

Copyright © 2016 Microsemi Page 27 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications R3 and R4 are set to the range of few kΩ- 10’s of kΩ using the equation below: (I) 𝑃𝐷70211_𝑊𝑎_𝑒𝑛 = 𝑉𝑒𝑥𝑡_𝑎𝑑𝑎𝑝𝑡𝑒𝑟_𝑃𝐷70211 x (𝑅3+𝑅4) Using R3=15kΩ, Vext_adapter=33.7V and from data sheet we use PD70211_WA_EN=2.4V as turn Off min threshold. Solving the equation , we get the valid resistors values for an adapter of 36V and above. 𝑅3 = 15𝑘Ω 𝑅4 = 1.15𝑘Ω

Copyright © 2016 Microsemi Page 28 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications Package Dimensions LQ 36-Pin QFN 6x6mm Dim MILLIMETERS INCHES MIN MAX MIN MAX A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0 0.002 A3 0.20 REF 0.008 REF e 0.50 BSC 0.019 BSC L 0.45 0.65 0.018 0.026 b 0.18 0.30 0.007 0.011 D2 4.00 4.25 0.157 0.167 E2 4.00 4.25 0.157 0.167 D 6.00 BSC 0.236 BSC E 6.00 BSC 0.236 BSC Note: 1. Dimensions do not include protrusions; these shall not exceed 0.155mm (.006”) on any side. Lead dimension shall not include solder coverage. 2. Dimensions are in millimeters, inches for reference only. e D E A A1 A3 K b L

Copyright © 2016 Microsemi Page 30 Rev. 1.4, July 2017 CPG – PoE BU One Enterprise Aliso Viejo, CA 92656 USA PD70211 PD Controller with Switching Regulator for AF/AT/UPOE/HDBaseT/4-pair PoE Applications The information contained in the document (unless it is publicly available on the Web without access restrictions) is PROPRIETARY AND CONFIDENTIAL information of Microsemi and cannot be copied, published, uploaded, posted, transmitted, distributed or disclosed or used without the express duly signed written consent of Microsemi. If the recipient of this document has entered into a disclosure agreement with Microsemi, then the terms of such Agreement will also apply. This document and the information contained herein may not be modified, by any person other than authorized personnel of Microsemi. No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the information, either expressly, by implication, inducement, estoppel s or otherwise. Any license under such intellectual property rights must be approved by Microsemi in writing signed by an officer of Microsemi. Microsemi reserves the right to change the configuration, functionality and performance of its products at anytime without any notice. This product has been subject to limited testing and should not be used in conjunction with life -support or other mission-critical equipment or applications. Microsemi assumes no liability whatsoever, and Microsemi disclaims any express or implied warranty, r elating to sale and/or use of Microsemi products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property ri ght. Any performance specifications believed to be reliable but are not verified and customer or user must conduct and complete all performance and other testing of this product as well as any user or customers final application. User or customer shall not rely on any data and performance sp ecifications or parameters provided by Microsemi. It is the customer’s and user’s responsibility to independently determine suitability of any Microsemi product and to test and verify the same. The information contained herein is provided “AS IS, WHERE IS” and with all faults, and the entire risk associated with such information is entirely with the User. Microsemi specifically disclaims any liability of any kind including for consequential , incidental and punitive damages as well as lost profit. The produc t is subject to other terms and conditions which can be located on the web at http://www.microsemi.com/company/terms-and-conditions

Revision History

Revision Level / Date Para. Affected Description 0.1 / Feb 2, 2012 - Initial Release 0.2 / March 2012 - Class Values – Typo’s Editing 0.3 -0.5/ March 2013 - General update 0.6/ July 2014 - Reduce flags maximum voltage, Add WA_EN information 1.0/ August 2014 - Add freq setting information 1.1/ Jan 2015 - Add PCB footprint recommendation 1.2 / June 2015 - Updating typo in part marking definition 1.3 / Oct 2015 Page 7 Page 13 Page 31 Fix Vaux pin description. Add UVLO_ON missing information. Fidure 9, 10, 11 Typo (cnage PD70224 to PD70211) 1.31 / July 2016 Page 2 Clarified Ordering Information table Fix typo descibing the IC marking (remove the initial “PD”) Page 8 Remove the name of the front end die in functional block diagram (Remove PD70210A) All Pages Update Rev number and date in the footer. 1.4 / July 2017 Page 2, 10 Updated marking and MSL3 per PCN 157021 © 2016 Microsemi Corp. All rights reserved. For support contact: PoEsupport@microsemi.com Visit our web site at: www.microsemi.com Catalog Number: DS_PD70211