PD70210A

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Technical content

Features

The PD70211 device has the following key features.

Supports IEEE 802.3af/at, HDBaseT, and other 2-pair/4-pair configurations
Wall adapter support (Rear Aux method)
PD detection and programmable classification
2, 3, 4, and 6 event classification
Integrated 0.3Ω isolating (series-pass) FET
Inrush current limiting
Less than 10 µA offset current during detection
Advanced PWM section
Lead-free QFN-36 (6 mm × 6 mm) package © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 1

The following table lists the Microchip PD products offerings. Table 1. Microchip Powered Device Products Offerings

Applications

The following are the applications of the PD70211 device.

HDBaseT up to 95W
IEEE 802.3af and IEEE 802at
Power forwarding
Indoor and outdoor PoE PD70211 © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 2

The following figure shows a basic PD block diagram using PD70211. Figure 1. Basic PD Block Diagram see our MPLAB Analog Designer (MAD) tool at www.microchip.com/mad-poe.

Functional Descriptions The following figures show the functional blocks of the PD70211 device. Figure 1-1. PD70211 Block Diagram (Front-End Section) PD70211 Functional Descriptions © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 5

Electrical Specifications The following sections describe the electrical specifications of the PD70211 device.

2.1 Absolute Maximum Ratings

Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage or negatively impact long-term operating reliability. Voltages are with respect to IC ground (VPN_IN). Table 2-1. Absolute Maximum Ratings Parameter Min Max Units VPP, VPN_OUT, RDET –0.3 74 V AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG –0.3 20 V SUPP_S1, SUPP_S2 0 VVPP + 1.5 V RREF, RCLS, WA_EN –0.3 5 V VAUX_VCC –0.3 20 V PG, SG –0.3 20 V VL –0.3 6 V VH (with respect to VAUX_VCC) 0.3 –6 V ENABLE All other pins –0.3 VL + 0.3 V Junction temperature –40 150 °C Lead soldering temperature (40 s, reflow) — 260 °C Storage temperature, MSL3 –65 150 °C ESD rating HBM — ±1.51 kV MM — ±50 V CDM — ±500 V Note: 1. The VPP, VAUX/VCC, and RREF pins pass ±1 kV HBM only. PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 7

2.2 Operating Ratings

Performance is generally guaranteed over this range, as detailed in the 2.4.1 Electrical Characteristics of Front-End Section. Voltages are with respect to IC ground (VPN_IN). Table 2-2. Operating Ratings of Front-End Section Parameter Min Max Units VPP 0 57 V Ambient temperature1 –40 85 °C Detection range 1.1 10.1 V Mark event range 4.9 10.1 V Class event range 13.7 20.9 V Note: 1. The corresponding maximum operating junction temperature is 125 °C. Performance is generally guaranteed over the range, as detailed in the 2.4.2 Electrical Characteristics of PWM Section. Voltages are with respect to IC ground. Table 2-3. Operating Ratings of PWM Section Parameter Min Max Units VCC 7.8 20 V FSW (Adjustable Frequency Range) 100 500 kHz Maximum duty cycle — 44.5 % fsw_synch (Synchronization Frequency Range) 200 1000 kHz

2.3 Thermal Properties

The following table lists the thermal specifications of the PD70211 device. Table 2-4. Thermal Properties Thermal Resistance Min Typ Max Units θJA — 22.3 — °C/W θJP — 3 — °C/W θJC — 4 — °C/W Note: The θJx numbers assume no forced airflow. Junction temperature is calculated using TJ = TA + (PD x qjA). In particular, θJA is a function of the PCB construction. Published thermal resistance is for a four-layer board in accordance with the JESD-51 (JEDEC) standards. PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 8

2.4 Electrical Characteristics

This section describes the electrical characteristics of the front-end and PWM sections, thermal protection mechanism against excessive internal temperature, and wall adapter mode functionality.

2.4.1 Electrical Characteristics of Front-End Section

Unless otherwise specified under conditions, the minimum and maximum ratings stated in the following table apply over the entire specified operating ratings of the PD70211 device. Typical values are determined either by design or by production testing at 25 °C ambient temperature. Voltages are with respect to IC ground (VPN_IN). Table 2-5. Typical Electrical Performance Symbol Parameter Conditions Min Typ Max Units Input Voltage IIN IC input current with ICLASS off VPP = 55V — 1 3 mA Detection Phase VDET Detection range — 1.1 — 10.1 V RDET_TH RDET disconnect threshold — 10.1 — 12.8 V RDS_DET_ON ON-Resistance of internal FET during detection — — — 50 Ω RDS_DET_OFF OFF-Resistance of internal FET after detection — 2 — — MΩ IOFFSET_DET Input offset current 1.1V ≤ VPP ≤ 10.1V, TJ ≤ 85 °C — — 5 μA VR_DET_ON Threshold when VPP goes low — 2.8 3.0 4.85 V Classification Phase VCLS_ON Classification sink turn-ON threshold — 11.4 — 13.7 V VCLS_OFF Classification sink turn-OFF threshold — 20.9 — 23.9 V VHYS_CLS_ON Hysteresis of VCLS_ON threshold — — 1 — V VMARK_TH Mark detection threshold (VPP falling) — 10.1 — 11.4 V IMARK Current sink in the mark event region — 0.25 — 4 mA ICLASS_CLIM Current limit of class current — 50 68 80 mA PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 9

Symbol Parameter Conditions Min Typ Max Units ICLASS Classification current sink RCLASS = not present (class 0) — — 3 mA RCLASS = 133Ω (class 1) 9.5 10.5 11.5 mA RCLASS = 69.8Ω (class 2) 17.5 18.5 19.5 mA RCLASS = 45.3Ω (class 3) 26.5 28.0 29.5 mA RCLASS = 30.9Ω (class 4) 38.0 40.0 42.0 mA Isolation FET RDSON ON resistence Total resistance between VPN_IN to VPN_OUT; ILOAD < 600 mA, –40 oC < TA < 85 oC — — 0.3 Ω ICLIM_INRUSH Inrush current limit — 105 240 325 mA OCP Overcurrent protection — 2.2 — — A ILOAD Continuous operation load — — — 2 A Undervoltage Lockout UVLOON Threshold that marks start of inrush phase — 36 — 42 V UVLOOFF Threshold where pass- FET turns OFF as VPP collapses — 30.5 — 34.5 V DC-DC Input Cap Discharger ICAP_DIS Discharge current 7V ≤ VPP ≤ 30V 22.8 — 60 mA tdis Discharge time CDC_DC ≤ 264 μF (by design, not tested) — — 500 ms timerdis Discharge timer Time for which discharge circuit is activated 430 — — ms References, Rails, and Logic VAUX Auxiliary voltage 0 mA < IAUX < 4 mA 9.8 10.5 12.0 V IAUX Maximum continuous current from VAUX — 4 — — mA IAUX Auxiliary current limit — 10 — 32 mA VREF Bandgap reference voltage — 1.17 1.2 1.23 V tFLAG_LO Low level flag For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG, IFLAG = 3 mA — — 0.4 V IFLAG Flag current driving capability For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG 5 — — mA PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 10

Symbol Parameter Conditions Min Typ Max Units tFLAG Delay timer between start of inrush and flags declared For AT_FLAG, HD_FLAG, 4P_AT_FLAG, 4P_HD_FLAG 80 — — ms VSUPP_HI SUPP_Sx high voltage threshold For SUPP_S1 and SUPP_S2 25 — 35 V Wall Adapter VIH Input high logic — 2.4 — — V VIL Input low logic — — — 0.8 V Table 2-6. Truth Table for Status of Flags Number of Fingers “N” (N-Event classification) SUPP_S1 SUPP_S2 AT_FLAG HD_FLAG 4P_AT_FLAG 4P_HD_FLAG

1 X X Hi-Z Hi-Z Hi-Z Hi-Z

2 H L 0V Hi-Z Hi-Z Hi-Z

2 L H 0V Hi-Z Hi-Z Hi-Z

2 H H 0V Hi-Z 0V Hi-Z

3 L H 0V 0V Hi Z Hi-Z

3 H L 0V 0V Hi Z Hi-Z

3 H H 0V 0V 0V Hi-Z

4 X X 0V 0V 0V Hi-Z

5 Reserved for future

6 X X 0V 0V 0V 0V

2.4.2 Electrical Characteristics of PWM Section

Unless otherwise specified under conditions, the minimum and maximum ratings listed in the following table apply over the entire specified operating ratings of the PD70211 device. Typical values stated, are determined either by design or by production testing at 25 °C ambient. Voltages are with respect to IC ground (VPN_IN). Table 2-7. Typical Electrical Performance Symbol Parameter Conditions Min Typ Max Units Input Voltage Current VCC_UVLO_UP UVLO threshold with input rising VCC rise time ≥ 0.5 ms 8.85 9.15 9.5 V VCC_UVLO_DN UVLO threshold with input falling VCC rise time ≥ 0.5 ms 7 7.3 7.6 V IVCC_SD IC input current (no switching) VENABLE = Low, or VVCC < VCC_UVLO_UP — 1 2000 µA IVCC_Q IC input current (switching, no load on SG, PG, VDD) VENABLE = High, and VVCC > VCC_UVLO_UP, fSW = 500 kHz — — 3 mA Input UVLO/PFW VINS_TH Threshold on VINS pin Rising or falling 1.171 1.200 1.229 V VHYST_HIGH Hysteresis pin high voltage IHYST_SOURCING = 1 mA 2.8 — — V VHYST_LOW Hysteresis pin low voltage IHYST_SINKING = 3 mA — — 0.4 V LDOs VL — IVDD_EXT < 5 mA (current out of pin) 4.75 5 5.25 V VH VH rail (with respect to VCC) — — –5 — V Soft Start ISS_CH Current out of SS pin during charging phase RFREQ = 33.3k, VSS = 0.5V 32 36 40 µA ISS_DISCH Current into SS pin during discharging phase RFREQ = 33.3k, VSS = 0.5V — 10 — % of ISS_CH VSS_CH Soft start charge completed threshold By design only 90 — 95 % of VREF VSS_DISCH Soft start discharge completed threshold — — 50 — mV RSS_DISCH Soft-start pin discharge FET resistance — — 50 — Ω PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 12

Symbol Parameter Conditions Min Typ Max Units tDISCH Soft-start discharge FET on-time — — 32 — Switch cycles Switching Frequency and Synchronization fsw_range Switching frequency accuracy RFREQ = 33.2k 285 315 345 kHz fsync_max Maximum synchronization frequency — 1 — — MHz VSYNC_HI SYNC pin high threshold — 2.4 — — V VSYNC_LO SYNC pin low threshold — — — 0.8 V tsync Minimum pulse width of SYNC pulse — 100 — — ns Dsync_max Maximum SYNC pulse duty cycle — — — 90 % Error Amplifier VREF Reference voltage — 1.171 1.200 1.229 V GainDC_OPL DC open-loop gain Rload = 100k 70 100 — dB AVUGBW Unity gain bandwidth Cload = 10 pF (By design only) 2 5 — MHz ICOMP_OUT Output sourcing current 0.2V ≤ VCOMP ≤ 1.3V 110 — 620 µA ICOMP_IN Output sinking current 0.2V ≤ VCOMP ≤ 1.3V 145 — 495 µA VEA_CMR_MAX Maximum of input common-mode range — 2 — — V VCLAMP COMP pin high clamp — 1.8 2.1 2.6 V PWM Comparator VOFFSET Inserted offset in inverted input — 200 — 300 mV VRCLP Voltage set on RCLP pin by external resistor to GND — 0 — 1 V Current Sense Amplifier GainCSA DC Gain 0 mA < IAUX < 4 mA 4.75 5 5.25 V IAUX Maximum continuous current from VAUX — 4 — — mA VCSA_CMR_MAX Maximum input common- mode range — 2 — — V PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 13

Symbol Parameter Conditions Min Typ Max Units tBLANK Blanking time — 50 — 100 ns VILIM Current limit threshold on output of current sense amplifier Where PWM pulses start to get truncated 1.1 1.2 1.3 V VILIMHICCUP Current limit threshold on output of current sense amplifier capability Where PWM pulses start to get omitted in hiccup mode 1.7 1.8 1.9 V Differential Voltage Amplifier GainDA DC gain of differential voltage amplifier — 6.68 7.0 7.14 V AVUGBW_DA Unity gain bandwidth of differential voltage amplifier — — 5 — MHz VDA_CMR_MAX Maximum of input common-mode range — 3.5 — — V Drivers RPG_HI Drive resistance when PG is high — — 10 — Ω RPG_LO Drive resistance when PG is low — — 5 — Ω tPG_MIN Minimum on-time of PG — — — 120 ns DMAX PG maximum duty cycle — 44.5 — 50 % RSG_HI Drive resistance when SG is high — — 10 — Ω RSG_LO Drive resistance when SG is low — — 10 — Ω tDEAD Deadtime — 60 110 190 ns Logic Levels on VINS and ENABLE VHI Input high threshold — 2 — — V VLO Input low threshold — — — 0.8 V Thermal Protection TSD Thermal shutdown (rising) — — 157 — °C THYST Thermal shutdown hysteresis — — 15 30 °C PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 14

2.4.3 Thermal Protection

The PD70211 device is protected from the excessive internal temperatures that might occur during various operating procedures. The following two temperature sensors are located on the chip monitor temperatures.

Isolating switch (pass-FET)
Classification current sink Each of the given temperature sensors activates a protection mechanism that disconnects the Isolation (pass) FET or the classification circuit, respectively. This action protects the device from being permanently damaged or even from long-term degradation.

2.4.4 Wall Adapter Mode

The PD70211 device supports wall adapter functionality. That is, by setting WA_EN pin high, it gives priority to the wall adapter jack to supply the load. The WA_EN pin is used while connecting a wall adapter voltage between VPP and VPN_OUT by means of an OR- ing diode. While WA_EN, the wall adapter enable pin, is held low (referenced to VPN_IN), the front-end works as a normal PD. When WA_EN pin is raised high (referenced to VPN_IN), the following three internal operations are forced:

The Isolation FET is turned OFF.
All output flags, like AT_FLAG, HD_FLAG, 4P_AT_FLAG, and 4P_HD_FLAG are activated (low state).
V AUX output voltage is turned ON. While activating the WA_EN pin, the wall adapter supplies the input voltage for the DC-DC converter. Having WA_EN pin at high state does not disable detection and classification modes. PD70211 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 15

Pin Configuration The following figure shows the device pin diagram from the top-view. Figure 3-1. PD70211 Pinout The following table lists the pin descriptions of the PD70211 device. Table 3-1. Pin Descriptions Pin Number Designator Description 1 SUPP_S1 Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin along with the SUPP_S2 pin can be used to distinguish between 2-pair and 4-pair operation. (For PSEs that operate in 4 pairs but generates the classification procedure on only one pair and not on both pairs). Signal is referenced to VPN_IN. Place a 10k resistor in the input of this pin. 2 SUPP_S2 Input pin for sensing the voltage on the diode bridge connected to the data pairs. This pin along with the SUPP_S1 pin can be used to distinguish between 2-pair and 4-pair operation. (For PSEs that operate in 4 pairs but generates the classification procedure on only one pair and not on both pairs). Signal is referenced to VPN_IN. Place a 10k resistor in the input of this pin. PD70211 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 16

3 4P_AT_FLAG Open drain output. The pin gets actively pulled low when a 4-pair version of a (non- standard) Type 2 PD-PSE mutually identify each other via classification. There is a minimum 80 ms delay from the moment when the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT. 4 RREF Bias current resistor. A 60.4k, 1% resistor is connected between RREF and IC ground (VPN_IN). 5 RCLASS Sets the Class of the PD. Connect RCLASS (programming resistor) between this pin and IC ground (VPN_IN). Allowed values are 133Ω, 69.8Ω, 45.3Ω, and 30.9Ω for Class 1, 2, 3, and 4 respectively. If RCLASS is not present, the PD draws up to 3 mA during classification, therefore, indicating Class 0 (default Type 1) to the PSE. Signal is referenced to VPN_IN. 6 HD_FLAG Open drain output. The pin gets actively pulled low when a 2-pair HDBaseT PD- PSE mutually identify each other through classification. There is a minimum of 80 ms delay from the moment when the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT. 7 AT_FLAG Open drain output. This pin gets actively pulled low when a Type 2 PD-PSE mutually identifies each other through classification. There is a minimum of 80 ms delay from the moment when the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT. 8, 9 VPN_IN Lower rail of the incoming PSE voltage rail—from the negative terminal of the two OR-ed bridge rectifiers (the corresponding upper PoE rail is VPP). 10, 11 VPN_OUT This is in effect, the switched ground for establishing continuity to the PWM section after successful detection, classification, and power-up. It is connected to the power ground and PWM controller IC’s ground plane of the DC-DC converter section. 12 ENABLE A logic-level input to enable the converter. It can be pulled up constantly, for example, with a 100k resistor to VDD, to forcibly enable the converter, provided the input supply has exceeded any applicable UVLO thresholds as set on the VINS pin or on the VCC pin. Internally, the ENABLE pin goes to the input of an OR-gate, the other input terminal of which is tied to “POK”—a signal provided by the front-end. If the ENABLE pin is forced high, the output of the OR-gate goes high and the converter is allowed to start (provided all UVLO’s are past). If the ENABLE pin is held low, the internal node “POK” goes active/high when the PD’s front-end conducts (power OK), so the OR-gate goes high once again. In this case, the switching converter turns ON as required by the PoE standard. However, for supporting wall adapters, injecting power after the front-end (at the input of the converter), the converter can be turned ON forcefully, without the front-end signaling “PGOOD”, by not tying the ENABLE pin low, but by tying it high (to VDD). That turns ON the converter irrespective of the state of the front-end (conducting or not), and whether there is any incoming PoE power or not. 13 VINS The VINS pin is a programmable UVLO pin. The converter turns ON provided the voltage on the VINS pin is above 1.2V (and VCC is not in UVLO, and ENABLE pin is also high—connected to VDD, for example). The converter stops switching (turns OFF) when the voltage on the VINS pin falls below 1.2V (or if ENABLE is taken low, or if VCC falls outside its operating range). Thus, by connecting a voltage divider between input rail and IC ground, the UVLO threshold to enable switching can be set. However, to have a smooth startup, it is advisable to have some hysteresis too, by means of a resistor between VINS and HYST as explained in pin-14. PD70211 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 17

14 HYST This is the output of the UVLO comparator as shown in the Figure 1-2. “hysteresis resistor” from HYST pin must be connected to VINS pin to create positive feedback (and hysteresis). Initially, as the input voltage is rising, the VINS pin voltage is below 1.2V and so the output of the UVLO comparator is low, leading the hysteresis resistor to fall in parallel to the lower resistor of the UVLO divider placed at the VINS pin, assisting it to pull down the VINS pin voltage further. As soon as the rising UVLO threshold is exceeded (VINS > 1.2V), the output of the UVLO comparator suddenly goes high (up to VDD) and the hysteresis resistor, effectively comes partially across the upper resistor of the UVLO divider, assisting it in to pull up the voltage on the VINS pin. This feedback, therefore, increases the voltage on the VINS pin. Now, the input rail has to fall to a much lower level to allow the VINS pin voltage to fall below 1.2V. That is how hysteresis is created by positive feedback action through the hysteresis resistor. The exact math is shown in the 5. Applications Information section. Note that the HYST pin always toggles between high or low depending on whether the voltage on the VINS pin is above or below 1.2V, respectively. This can always be used to indicate when the input rail is above the programmed rising threshold and when it falls below the programmed falling threshold.

15 SYNC Synchronizes the LX7309 to a frequency higher than its default value as set on

RFREQ pin. The synchronizing clock must be 2x the desired sync frequency, with a maximum synchronizing clock frequency of 1 MHz (for 500 kHz PWM frequency). The PG pin’s rising edge occurs at the same instant as the rising edge of the clock being applied on the SYNC pin.

16 RFREQ Connect a programming resistor from this pin to IC ground (pin GND) to set the

switching frequency. A typical value of the programming resistor is 49.9k, and this value provides a frequency of 215 kHz. Halving it roughly doubles the frequency, whereas doubling it halves the frequency. Note that the converter is designed to operate from 100 kHz to 500 kHz based on this pin. Switching frequency equation: where Freq is [Hz] and RFREQ is in [Ω] For more information, see the 5.2 Setting Switching Frequency section. 17 SS This is the soft-start pin. Typically, a 0.1 µF capacitor, the “soft-start capacitor”, is connected between this pin and IC ground (pin GND). The capacitor gets charged up to 1.2V by an internal resistor, and the voltage on the capacitor, in effect, forms the input voltage reference VREF of the error amplifier. But, note that this capacitor serves other functions too; for example, it controls the rate of hiccupping under overcurrent fault conditions. Therefore, even if the internal reference is not being used (as in isolated topologies with a TL431 on the secondary side), the soft-start capacitor is recommended to be in place always. The actual capacitor used is determined by the application. For more information, see the 5.3 Setting Soft-Start section. 18 RCLP Low power clamp resistor. A resistor can be connected from this pin to IC ground (pin GND) to set the exact level at which pulse-skipping mode is entered at light loads. However, the usual default is to connect this pin directly to IC ground, in which case pulse-skipping mode is disabled. The method to select the threshold (and RCLP resistor value) is described in the 5. Applications Information section. PD70211 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 18

19 VSN The negative input of the internal differential-sense voltage amplifier. Note that the common-mode range of the differential voltage amplifier is 3.5V and its gain is 7. This differential amplifier can be used for implementing topologies where the “system (output) ground” is different from the IC ground. Both output rails (output rail and its return) can then be step-downed, by equal amounts, using identical voltage dividers, to bring the voltage below 3.5V. Then, differential sensing can be used, and finally the output of the differential voltage amplifier (pin DAO) can be connected to the FB pin. 20 VSP The positive input of the internal differential-sense voltage amplifier. Note that it must always be connected in such a way that VSP is at a higher voltage than VSN. Also, keep in mind that since the differential voltage amplifier has a gain of 7 and the output of that amplifier is connected to the feedback pin, which compares that against a 1.2V reference, in effect, the difference between VSP and VSN stabilizes to 1.2V/7 = 0.171V in steady state. That is how the (identical) voltage dividers present on VSP and VSN are designed.

21 COMP This is the output of the internal error amplifier, and the input of the PWM

comparator. It is brought out to support isolated topologies because in such cases, there is an error amplifier already present on the secondary side (for example, a TL431 or equivalent). Therefore, the error amplifier of the converter section can be passed. On the other hand, in non-isolated topologies, the error amplifier of the converter can be used directly or through the differential voltage amplifier stage. 22 DAO This is the output of the internal differential voltage amplifier (gain = 7). When this amplifier is used, DAO is connected to the feedback pin (FB). Part of the compensation network is between the two pins, and this network is typical of any Type 3 error amplifier input, with or without a differential amplifier. 23 FB This is the feedback pin of the IC. It is internally compared to a 1.2V reference. If the internal error amplifier is not used and the COMP pin is being used to inject the error signal (as in isolated topologies), the FB pin can be either tied high (to VDD), or connected to COMP. 24 GND This is the IC ground or the analog (quiet) ground of the IC. Pin 20 is the Power Ground (PGND). Typically, the analog ground and PGND can be connected on a copper island on the component side, and then connect that through several vias very close to the chip on to a large ground plane which extends up to the lower side of the current sense resistor. All chip decoupling can then be very simple with respect to the copper island on the component side.

25 VL This is created by an internal LDO and basically provides a housekeeping rail for

the IC itself, which is 5V with respect to the IC ground. A 1 µF ceramic cap placed close to this pin, connected to IC ground is recommended for proper decoupling. This pin can also provide up to 5 mA for external circuitry if required, thermal aspects (IC dissipation) being considered. PD70211 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 19

26 SG Secondary gate driver. It drives a synchronous FET or an active clamp FET. It is derived from VCC (~ 12 V), and has a 10Ω limiting resistor. Therefore, it can be used to drive a gate-drive transformer directly. It is usually complementary to the primary gate driver pin (PG). But, there is a typical 110 ns blanking time between the two to prevent cross-conduction. SG is held firmly low in pulse-skip mode (if allowed). It is also low during soft-start. It allows forced PWM (continuous conduction) mode by allowing negative inductor currents. It does not support diode- emulation mode (discontinuous conduction mode). However, in pulse-skip mode, as the SG stays OFF, the converter automatically lapses into discontinuous conduction mode through the body-diode of the synchronous FET. This pin can be left floating, if unused. 27 PGND Power ground (for internal SG and PG drivers). This is ideal for VCC decoupling and the Primary-side current sense resistor’s lower terminal. GND and PGND can be combined into a single large ground plane. Note that the power ground plane is firmly connected to VPN_OUT, which is the drain side of the PD’s low-side pass- FET (it stands for Negative Port Voltage Out). 28 CSN The negative input of the internal current-sense voltage amplifier. Note that the common-mode range of the differential current-sense amplifier is 2V and its gain is 5. This is used for high-side current sensing up to 2V. It is then placed on the (steady) output side of a Buck inductor, and the maximum output voltage is 1.8V for using this type of sensing. Ensure that CSN is at a lower voltage compared to the positive input of the current-sense amplifier (CSP). Current sensing can also be implemented in a more basic fashion for “low-side” sensing, with a resistor in the return (ground) of the Buck. In that case, CSN is shown connected to IC ground. However, to avoid noise from ground bounce, it is best to route this on the PCB in Kelvin manner to the lower end of the sense resistor. This is important because the peak operating voltage on the sense resistor is only 200 mV and PCB-related noise can cause jitter in the switching waveform in current-mode control. 29 CSP The positive input of the internal current-sense voltage amplifier. See description of pin 28 (CSN). Note that the output of the current-sense amplifier is amplified five times. Therefore, a 0.2V current-sense voltage translates to a 1V swing at the input of the PWM comparator. Higher voltages lead to hiccup mode protection. 30 PG This stands for primary gate driver. It drives the main FET, and has a 5Ω or 10Ω limiting drive resistor switched between a voltage close to VCC rail and the IC ground. For guaranteeing proper shutdown during OFF time, it is necessary to add a 470k resistor from PG to VINS, as shown in Figure 1. 31 VH Internal rail of –5V with respect to VCC, brought out only for decoupling purposes. Connect a 0.1 µF ceramic cap very close, from this pin to VAUX_VCC pin. 32 VAUX_VCC Auxiliary voltage rail from front-end to the VCC (supply) input of the PWM section. The front-end provides a few mA of startup current for the PWM controller (at typically 10.5V). Signal is referenced to VPN_OUT and is activated once front-end power up sequence ends. After initial startup of PWM section, a bias winding can be connected to this pin through a diode, to sustain the PWM section.

33 WA_EN While this input is low (referenced to VPN_IN) the chip work according to internal

flow diagram. When this input is high, it enable wall adapter feature. Place 100 nF to 1 uF/10V capacitor from WA_EN to VPN_IN pins, locate it close to device. When WA_EN is no tused, connect it to VPN_IN. For further information, see the Operation with an External DC Source section. PD70211 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 20

34 4P_HD_FLAG Open drain output. The pin gets actively pulled low when a 4-pair HDBaseT PD- PSE mutually identify each other via classification. There is a minimum 80 ms delay from the moment that the input capacitor is fully charged to this signal activity. Signal is referenced to VPN_OUT.

35 VPP Upper rail of the incoming PSE voltage rail—from the positive terminal of the two

OR-ed bridge rectifiers (the corresponding lower PoE rail is VPN_IN).

36 RDET Internally connects to VPN_IN during detection phase and disengages after it is

over. A 25 KΩ (or 24.9K), 1% resistor is connected between this pin and VPP. 37 EPAD Connected on PCB plane to VPN_IN. PD70211 Pin Configuration © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 21

Package Specifications The following figure shows a 6 mm × 6 mm, 36-pin QFN PD70211 package. Figure 4-1. QFN Package EŽƚĞ͗ ŝŵĞŶƐŝŽŶ DŝůůŝŵĞƚĞƌƐ /ŶĐŚĞƐ DŝŶ DĂǆ DŝŶ DĂǆ Note: Dimensions do not include protrusions; they must not exceed 0.155 mm (0.006″) on any side. Lead dimension does not include solder coverage. Table 4-1. Package Dimensions Dimension Millimeters Inches Min Max Min Max A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0 0.002 A3 0.20 REF 0.008 REF e 0.50 BSC 0.019 BSC L 0.45 0.65 0.018 0.026 b 0.18 0.30 0.007 0.011 D2 4.00 4.25 0.157 0.167 E2 4.00 4.25 0.157 0.167 D 6.00 BSC 0.236 BSC E 6.00 BSC 0.236 BSC K 0.25 — 0.0098 — PD70211 Package Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 22

4.1 Recommended PCB Layout

The following figures show the recommended PCB layout pattern for the PD70211 device. Figure 4-2. Top Layer Copper Recommended PCB Layout (mm) Figure 4-3. Top Layer Solder Mask, Solder Paste and Vias Recommended PCB Layout (mm) Figure 4-4. Bottom Layer Copper and Solder Paste Recommended PCB Layout for Thermal Pad Array (mm) PD70211 Package Specifications © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 23

Applications Information The following sections describe the PD70211 application.

5.1 Peripheral Devices

An 82 nF to 100 nF/100 V capacitor must be placed between device VPP and VPN_IN pins, and located as close as possible to the device. A 58V TVS must be placed between device VPP and VPN_IN pins for protection against voltage transients. For complete surge protection, see www.microchip.com/DS00003410B. A 10 KΩ resistor must be placed on SUPP_S1 and SUPP_S2 lines between diode bridge and PD70211 device. When WA_EN is used, a 100 nF to 1 uF/10V capacitor must be placed between WA_EN and VPN_IN pins close to PD70211 device. Consult Microchip Technology for optimized recommendation. When not used, WA_EN must be connected to VPN_IN pin.

5.2 Setting Switching Frequency

The RFREQ resistor is connected from RFREQ pin to IC ground. Based on that, the following frequency is obtained: where, Freq is [Hz] and RFREQ is Ω. For example, by setting RFREQ = 49900Ω: Any frequency between 100 kHz to 500 kHz can be set. Note: When synchronizing, the default frequency (as set by RFREQ) must be lower than the synchronization clock. If the synchronization breaks, the converter lapses back to the default value. When synchronizing, the frequency can be increased to 1 MHz.

5.3 Setting Soft-Start

A capacitor is connected between SS pin and IC ground. The current charging of the capacitor is: For example, if RFREQ = 49.9k, then: Therefore, charging a 0.1 µF ceramic cap on the SS pin from 0V to 1.2V takes: This is the soft-start time in this case. PD70211 Applications Information © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 24

5.4 Setting Pulse-skip Mode Threshold

If an RCLP programming resistor is placed between RCLP pin and IC ground, the clamping voltage level is given by: For example, if RCLP = RFREQ, assuming that both are 49.9k, then the converter enters pulse skipping when the output of the current sense amplifier drops to 0.3V. Note: The gain with this current amplifier is 5. Therefore, in terms of the voltage on the sense resistor (input of the current amplifier), 0.3V/5 = 0.06V. As the converter is usually designed in such a way that its peak is around 0.2V (the peak of Rsense voltage before it starts to current limit), ratio of 0.06V/0.2V = 0.3 is obtained. In other words, the converter enters pulse-skipping when the output current is 30% of the maximum designed output current.

5.5 Setting UVLO/Hysteresis Thresholds

Note: A 470k resistor from PG pin to VINS pin is required for guaranteeing proper termination of gate drive pulse during UVLO. For example, a divider is connected to input at the VINS pin, and resistors are called RUPPER and RLOWER. RHYST, a hysteresis resistor from the output of the UVLO comparator, which provides positive feedback on to the VINS pin, is also present, as explained in the 3. Pin Configuration section. When the input voltage is rising, in effect, the hysteresis resistor is in parallel to the lower resistor RLOWER. When the voltage on the VINS pin rises above 1.2V, the UVLO comparator flips and the hysteresis resistor appears connected to 5V (output of the UVLO comparator). The equivalent configurations are shown in Figure 5-1. After solving the equations, the following example indicates the set thresholds. The values are as used in Figure 1-2. Therefore, with the selected resistors, a rising threshold of 39.8V and a falling threshold of 34.8V is achieved. PD70211 Applications Information © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 25

Figure 5-1. Equivalent Diagrams for UVLO and Hysteresis

5.6 Setting the Voltage Divider for Output Rails

Generically, the equation is stated as: Where, RUP is the name given to the upper resistor (connected to output rail) and RLOW is the name given to the resistor connected to lower rail (usually IC ground). However, with so many topologies, in effect the following three cases in all the typical schematics presented so far are present.

Non-isolated topologies with simple divider connected directly to FB pin. For this, V X = 1.2V is used.
Isolated topologies with divider to another reference (such as TL431 with an internal reference of 2.5V). For this, VX = 2.5V is used.
Non-isolated topologies with a differential divider connected to differential voltage amplifier of the LX7309. The same preceeding divider equation is used, but with VX = 0.171V (that is, 1.2V divided by the gain of the differential amplifier 7). Two identical dividers are required.

5.7 Selecting the Sense Resistor

In a Buck topology, the center of the switch current ramp equals the output current. To that, about 30% for the “IPEAK +” peak current must be added because of the rising ramp caused by the inductor. That is a factor of 1.3. Some headroom for proper transient response at maximum load must also be included. As the peak voltage on the sense resistor is 0.2V, to leave headroom, it must be planned in such a way that the switch current peak stays at around 0.18V at the most, at maximum load. This means the following: An adjust resistor must be placed in parallel (for example, the 22Ω placeholder). For a Forward converter (Buck with a transformer), instead of the IOR load current as shown in the preceeding equation, the reflected load current of IO/n can be used, where n is the turns ratio (number of primary-side turns divided by number of secondary-side turns). The sense resistance must also be lowered further (by means of the adjust resistor), to account for the magnetization current component on the switch side. PD70211 Applications Information © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 26

Therefore, roughly: For a Boost or Buck-Boost, account for the fact must be made that the peak current is not just 1.3 times of maximum load current, but it is actually: Therefore, the following equation for sense resistor must be used. For example, if the maximum load current is 5A, the sense resistor value to use is: This is roughly half of the Buck (same load current). For a Flyback topology (Buck-Boost with a transformer), the reflected output current is used:

5.8 Operation with an External DC Source

PD applications utilizing PD70211 IC might be operated with an external power source (DC wall adaptor). Figure 5-2 and Figure 5-3 show the two cases of providing power with an external source.

External source connected to application’s low voltage supply rails. External source voltage level is dependent on DC-DC output characteristics. See Figure 5-2 for more details.
External source connected to PD device output connection towards the application (VPP to VPNOUT). External source voltage level is dependent on DC-DC input requirements. See Figure 5-3 for more details. PD70211 Applications Information © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 27

Figure 5-4. External Power Input Resistors Dividers R1 and R2 set a rough threshold for PFET Q1 enable, to detect whether the external adapter exists or not. It must be set at a lower threshold than the PD70211 disable levels. R3 and R4 set the PD70211 disable threshold. Therefore, in case of 36V–57V external adapter, the disable setting can be selected as follows: PFET enable threshold = 30V. R1 and R2 setting must be such that the value of Q1 VGS is less than 20V at maximum voltage condition of the external adapter. While external adapter voltage is more than 30 V, Q1 is above its VGSth value. R1 is selected as 2 kΩ. Using R1 = 2 kΩ, Vext_adapter = 30V, and VGS = maximum VGSth = 3.5V, the R2 value is obtained: R3 and R4 are set to the range of few kΩ (10’s of kΩ) using the following equation: Using R3 = 15 kΩ, Vext_adapter = 33.7V, and from this data sheet PD70211_WA_EN = 2.4V as the turn OFF minimum threshold. Solving the equation, the valid resistor's values for an adapter of 36V and above are achieved. For complete information and details of various connection methods, see www.microchip.com/DS00003472A. PD70211 Applications Information © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 29

Ordering Information The following table lists the ordering information of the PD70211 device. Table 6-1. Ordering Information Ambient Temperature Type Part Marking Ordering P/N Package –40 °C to 85 °C RoHS compliant, Pb-free MSCC Logo 70211 Z Z e41 YYWWNNN2 PD70211ILQ-TR QFN-36 (6 mm × 6 mm, 0.5 mm pitch) Notes: 1. ZZ e4: ZZ = Random character with no meaning, e4 = Second level interconnect. 2. YY = Year, WW = Week, NNN = Trace code. PD70211

Ordering Information

Reference Documents 1. AN3533 PD70210(A) PD70211 System Layout Guidelines. 2. AN3471 Designing a Type 1/2 802.3 or HDBaseT Type 3 Powered Device Using PD702x1 and PD701x1 ICs. 3. AN3472 Implementing Auxiliary Power in PoE. PD70211 Reference Documents © 2020 Microchip Technology Inc. Datasheet DS00003672A-page 31

Revision History Revision Date Description A 10/2020 Following is the summary of changes:

The document was updated as per the Microchip standards.
Document ID PD-000390461 was changed to DS00003672A.
Added Table 1 to the Features section.
Added new Figure 1 and note in the 2 Applications section.
Updated units column of Table 2-5.
Updated units column of Table 2-7.
Edited the note in the 2.3 Thermal Properties section.
Updated Figure 3-1 and Table 3-1 in the Pin Configuration section.
Added K dimension values in Table 4-1 in the Package Specifications section.
Changed Figure 4-4 in the Recommended PCB Layout section.
Updated the 5.1 Peripheral Devices section.
Edited the 5.7 Selecting the Sense Resistor section.
Added the 7. Reference Documents section.
Updated package specifications in Table 6-1 and notes in the 6. Ordering Information section. 2.0 09/2019 Following is the summary of changes:
Re-drew the QFN package diagram.
Corrected a typo in pin name in the Applications Information section.
Removed the column 'note' was from the Ordering Information table.
Converted the document to Microsemi formatting standards. 1.4 07/2017 Updated the marking and MSL3 information 1.31 07/2016 Following is the summary of changes:
Removed 'PD' in IC marking description
Removed name of the front-end die (PD70210A) in functional block diagram
Updated revision number and date in the footer 1.3 10/2015 Following is the summary of changes:
Fixed Vaux pin description
Added UVLO_ON missing information
PD70224 was changed to PD70211 in figures 9, 10, and 11. 1.2 Updated a typo in part marking definition. 1.1 01/2015 Added a PCB footprint recommendation. 1.0 08/2014 Added frequency setting information. 0.6 07/2014 Flags maximum voltage was reduced and WA_EN information was added. 0.3 03/2013 General updates were made. 0.2 03/2012 Minor edits were made to the class values. 0.1 02/2012 It was the first publication of this document. PD70211

Revision History

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Summary

PD Controller with Switching Regulator for AF/AT/UPOE/ HDBaseT/4-pair PoE Applications 2020

Description