PD69208T4

Microchip Technology

PoE PSE Manager 2020

Manufacturer: Microchip Technology

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Technical content

802.3af/at/bt or Power over HDBase (PoH) Power Sourcing Equipment (PSE) solution. The following figure shows the typical PoE application of Microchip Generation 6 devices. Figure 1. Typical PoE Application with Microchip Controller Consult Microchip AN3361 Designing an IEEE 802.3af/at/bt PoE System Based on PD692x0/PD69208.

Drives 2-pair or 4-pair power ports
Single DC voltage input
Built-in 3.3 V and 5 V regulators
Over-temperature protection and thermal monitoring
Low-power dissipation
Industrial temperature range: –40 °C to 85 °C
MSL3, RoHS compliant

Table 1. Device-Specific Features

Complies with IEEE 802.3af/at/bt
Supports Power over HDBaseT (POH)
Cascade up to 12 PoE devices for 48 logical ports
Advance system power management
Emergency power management supporting 16 configurable power banks
Continuous port monitoring and status
Supports Fast and Perpetual PoE
Supports pre-standard PD detection
LED stream support
Configurable load current setting
Field upgradable
Any combination of PD69208T4, PD69204T4, and PD69208M, and any combination of 2-pair and 4- pair in the same system is possible and supported.

Applications

PoE switches/routers/midspans
Industrial automation
PoE for LED lighting
Video recorders (NVR/DVR) PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 2

Functional Descriptions The following figure shows the functional blocks of the PD69208T4, PD69204T4, and PD69208M. Figure 1-1. PSE Manager Block Diagram

1.1 Digital Block Module

The logic main control block includes digital timing mechanisms and state machines that synchronize and activate PoE functions.

Real-Time Protection
Start-Up Macro
Load Signature Detection
Classification
Voltage and Current Monitoring
ADC interfacing
Direct digital signals with analog block
SPI communication block
Registers

1.2 PD Detection Generator

On request from the controller to the main control module, the PD detection generator generates four different voltage levels to ensure a robust AF/AT/BT PD detection functionality.

1.3 Classification Generator

On request from the PD692x0 controller to the main control module, state machine applies a regulated class event and mark event voltage to ports, as required by IEEE standards. PD69208T4/PD69204T4/PD69208M Functional Descriptions © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 5

1.4 Current Limiter

This circuit continuously monitors the current of powered ports and limits the current to a pre-defined value set by AF/AT/BT/PoH. When the current value exceeds this specific value, the system starts measuring the elapsed timing. If this interval is greater than a preset threshold, the port is disconnected.

1.5 Main Power MOSFET

The main power switching FET is used to control PoE current into the load. 1.6 10-Bit ADC A 10-bit analog to digital converter (ADC) is used to convert analog signals into digital registers for the logic control module.

1.7 Power on Reset

Power on Reset (PoR) monitors the internal 3.3 V and 5 V DC levels. If this voltage drops below the specific thresholds, a reset signal is generated and the manager is reset.

1.8 Voltage Regulator

The voltage regulator generates 3.3 V and 5 V for internal circuitry.

1.9 Oscillator

The manager’s clock (CLK) is an internal 8 MHz clock oscillator.

1.10 SPI Communication

The managers use SPI communication in SPI slave mode to communicate with the MCU. Each manager has an address determined by ADDR0-ADDR3 pins. Addresses 0–11 are supported. The frequency between controller and manager ICs is 1 MHz. PD69208T4/PD69204T4/PD69208M Functional Descriptions © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 6

Electrical Specifications This section describes the electrical specifications of the PD69208T4, PD69204T4, and PD69208M devices.

2.1 Absolute Maximum Ratings

PoE performance is not guaranteed when exceeding the recommended rating. Exposure to any stress in the range between the recommended rating, as listed in the following table, and the absolute maximum rating should be limited to a short time. Exceeding these ratings may impact long-term operating reliability. Table 2-1. Absolute Maximum Ratings Parameters Min Max Units Supply input voltage (VMAIN)1,2 –0.3 72 V PORT_NEG[0.7]pins –0.3 VMAIN +0.5 V VAUX5 –0.3 6 V VAUX3P3,DVDD –0.3 4 V Digital pins: MISO, MOSI, SCK, CS_N, ADDR[3:0], PGD[3:0], RESET_N, TRIM –0.3 DVDD+0.3 and <4.0 V Absolute maximum junction temperature 150 °C Lead soldering temperature (40 s, reflow) 260 °C Storage temperature –65 150 °C 1. Power sequence requirement: V MAIN > VAUX5 > VAUX3P3 = TRIM, DVDD. 2. EPAD is connected by copper plane on PCB to AGND. AGND is ground for IC. Note: DRV_VAUX5 and IREF are output pins and should not apply voltage or current. DRV_VAUX5 can be left open when not used.

2.2 Recommended Operating Conditions

Table 2-2. Operating Conditions Symbol Parameter Conditions Min Typ Max Units Maximum junction operating temperature 125 °C VMAIN Main supply voltage Supports full IEEE 802.3af/at/bt functionality 44 57 V

2.3 Immunity

Table 2-3. Immunity Symbol Parameter Conditions Min Typ Max Units ESD ESD rating HBM1 –2000 +2000 V CDM2 –500 +500 V Surge Lightning surge3 EN61000 4-5 –1 1 kV PD69208T4/PD69204T4/PD69208M Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 7

ESD HBM complies with JESD22 Class 2 standard. 2. ESD CDM complies with JESD22 Class 1 standard. 3. System-level common mode 10/700 µs according to IEC61000-4-5.

2.4 Device Electrical Specifications

If not specified under conditions, the Min and Max ratings stated in the following table apply to the entire specified operating ratings of the device. Typ values stated are either by design or by production testing at 25 °C ambient. Table 2-4. Electrical Specifications Symbol Parameter Conditions Min Typ Max Units VPORT Port output VMAIN–VPORT_NEGx 0 57 V VTH POR threshold Internal or external 3.3 V supply 8 V IMAIN Main power supply current at operating mode. VMAIN = 55 V 14 mA VAUX5 5 V output voltage VAUX5–AGND 4.5 5 5.5 V VAUX3P3 Internal 3.3 V output voltage VAUX3P3–AGND 3 3.3 3.6 V IAUX3P3 3.3 V output current for application use Without external NPN 5 mA With external NPN transistor on VAUX5 30 mA VAUX3P3_IN 3.3 V input voltage VAUX3P3–AGND 3 3.3 3.6 V DVDD Digital 3.3 V input voltage DVDD–DGND 3 3.3 3.6 V PORTP Power-on reset DVDD trip point DVDD–DGND 2.575 2.775 2.975 V PORHYS Power-on reset DVDD hysteresis PORTP–DGND 0.2 0.25 0.3 V RCH_ON Total channel resistance Rds_on + Rsense + Rbonding 0.34 Ω PPWR Port power accuracy >90 W 2 %

2.5 Port Real-Time Protection

Table 2-5. Port Real-Time Protection Symbol Parameter Conditions Min Typ Max Units TRISE Turn-on rise time From 10% to 90% of the voltage difference at the VPORT_NEGx in POWER_ON state from the beginning of POWER_UP 15 µs IINRUSH Output current in POWER_UP state CLOAD ≤ 180 µF1 400 425 450 mA TINRUSH Inrush time 65 ms PD69208T4/PD69204T4/PD69208M Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 8

Symbol Parameter Conditions Min Typ Max Units IPORT Output operating current 802.3af 10 360 mA 802.3at 10 620 mA 802.3bt class 5 10 560 mA 802.3bt class 6 10 692 mA 802.3bt class 7 10 794 mA 802.3bt class 8 10 948 mA ICUT Overload current 802.3af 375 mA 802.3at 645 mA 802.3bt class 5 589 mA 802.3bt class 6 709 mA 802.3bt class 7 825 mA 802.3bt class 8/PoH2 980 mA TCUT Overload time limit 62 64 66 ms ILIM Port current limit 802.3af 400 425 450 mA 802.3bt class 1–3 670 720 770 mA 802.3at, 802.3bt class 4–6 790 850 892 mA 802.3bt class 7–8/PoH 1020 1150 1300 mA TLIM Port current limit time VMAIN–VPORT_NEGx <30 V 1 2 3 ms IUDL DC disconnect under-load current 2 pairs 6 7.5 9 mA 4 pairs IEEE 802.3bt (for each pair-set) 2 2.5 3 mA TMPDO PD maintain power signature dropout time limit 322 324 326 ms TMPS PD maintain power 802.3bt PSE Type 1, 2 46 48 50 ms Signature time for validity 802.3bt PSE Type 3, 4 3 4 5 ms TOFF Turn off time From VMAIN to 2.8 V 500 ms 1. Can be overridden by communication command. 2. The power port is limited to the maximum of 100 W according to UL’s LPS requirements (Port Power = I PORT × VMAIN).

2.6 Port Current Monitoring

Table 2-6. Port Current Monitoring Symbol Conditions Typ Max Units Resolution Reported as 14 bits 10 Bits LSB 122.07 µA Measurement period 16 mS PD69208T4/PD69204T4/PD69208M Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 9

Symbol Conditions Typ Max Units Accuracy 50 mA < IPORT < 150 mA 9 % 150 mA < IPORT < 350 mA 4.5 % IPORT > 350 mA (PD69208M) 3.5 % 350 mA < IPORT < 600 mA (PD6920xT4) 3.5 % 600 mA < IPORT < 800 mA (PD6920xT4) 3.0 % IPORT > 800 mA (PD6920xT4) 1.5 %

2.7 Port Voltage Monitoring

Table 2-7. Port Voltage Monitoring Symbol Conditions Typ Max Units Resolution 10 Bits LSB 58.6 mV Measurement period 3 ms Accuracy 3.3 %

2.8 Main Voltage Monitoring

Table 2-8. Main Voltage Monitoring Symbol Conditions Typ Max Units Resolution 10 Bits LSB 58.6 mV Measurement period 3 ms Accuracy (PD69208T4-PD69204T4) 42 V < VMAIN < 50 V 2.1 % 50 V < VMAIN < 57 V 1.5 % 50 V < VMAIN < 57 V1 0.6 % Accuracy (PD69208M) 42 V < VMAIN < 50 V 3.0 % 50 V < VMAIN < 57 V 2.2 % 1. 0 °C–70 °C

2.9 Temperature Monitoring

Table 2-9. Temperature Monitoring Symbol Conditions Min Typ Max Units Resolution 8 Bits LSB Temperature = (DATA x 1.9384)–277 1.9384 °C PD69208T4/PD69204T4/PD69208M Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 10

Symbol Conditions Min Typ Max Units Measurement period 3 ms Accuracy –3 3 °C

2.10 Digital Interface

Table 2-10. Digital Interface Symbol Parameter Conditions Min Typ Max Units VIH Input logic high voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] 2.2 V VIL Input logic low voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] 0.8 V Hyst Input logic hysteresis voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] 0.4 0.6 0.8 V IIH Input logic high current RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] –10 10 µA IIL Input logic low current RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] –10 10 µA VOH Output logic high voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] IOH = –1 mA 2.4 V VOL Output logic low voltage RESET_N, MOSI, MISO, SCK, CS_N, PGD[0..3], ADDR[0..3] IOH = 1 mA 0.4 V

2.11 Detection

Table 2-11. Detection Symbol Parameter Conditions Min Typ Max Units VOC Pre-detection voltage, open-circuit voltage VMAIN–VPORT_NEGx, open port 7.8 V VVALID Detection voltage VMAIN–VPORT_NEGx, for IEEE 802.3 compliant signature resistance (RSIG <33 K) 9.3 V ISC Short circuit current VMAIN–VPORT_NEGx = 0 V 388 408 µA RSIG_LOW Minimum valid detection resistance 15 19 kΩ RSIG_HIGH Maximum valid detection resistance 26.5 33 kΩ PD69208T4/PD69204T4/PD69208M Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 11

2.12 Classification

Table 2-12. Classification Symbol Parameter Conditions Min Typ Max Units VCLASS Class event output voltage VMAIN–VPORT_NEGx; 0 mA ≤ IPORT ≤ 50 mA 15.5 18 20.5 V VMARK Mark event output voltage VMAIN–VPORT_NEGx; 0.1 mA ≤ IPORT ≤ 5 mA 7 8.5 10 V ICLASS_LIM Class event current limitation VMAIN–VPORT_NEGx = 0 V 51 70 100 mA IMARK_ LIM Mark event current limitation VMAIN–VPORT_NEGx = 0 V 51 70 100 mA Classification current thresholds Class 0 0 5 mA Class 1 8 13 mA Class 2 16 21 mA Class 3 25 31 mA Class 4 35 45 mA Class Error 51 100 mA PD69208T4/PD69204T4/PD69208M Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 12

Pins This section provides pin diagrams and pin descriptions for the PD69208T4, PD69204T4, and PD69208M devices.

3.1 Pin Diagrams

3.2 Pin Descriptions

The following table describes the functional pins of the PD69208T4, PD69208M, and PD69204T4 Managers. Table 3-1. Pin Descriptions Pin Designator Type Description EPAD Exposed PAD. Connect to analog ground. GND must have sufficient copper mass on bottom or top layer to ensure adequate thermal performance. 1,18,45 N.C. N/A Not connected. Leave floating. 2 TST Digital input Test pin for production use only. Connect to DGND. 3,4 VPORT_NEG0 Analog I/O Negative port 0 output. 5,8,11, 14,16, 26,27, 29,32, 35,38 RESERVED N/A Reserved pin. Do not connect externally. 6,7 VPORT_NEG1 Analog I/O Negative port 1 output. 9,10 VPORT_NEG2 Analog I/O Negative port 2 output. 12,13 VPORT_NEG3 Analog I/O Negative port 3 output. 15,21,28 AGND Power Analog ground. 17 VMAIN Power Main high voltage supply voltage. A low ESR 1 µF (or higher) bypass capacitor, connected to AGND, should be placed as close as possible to this pin through low resistance traces.

19 DRV_VAUX5 Power Driven outputs for 5 V external regulation; if

internal regulation is used, connect to pin 20. If an external NPN is used to regulate the voltage, connect this pin to Base and connect 4.7 µF capacitor between this pin and AGND. 20 VAUX5 Power Powered by regulated 5 V. Connect 4.7 µF or higher capacitor between this pin and AGND. If an external NPN is used to regulate the voltage, connect this pin to the emitter. The collector should be connected to VMAIN. 22 VAUX3P3 Power Powered by regulated 3.3 V. A 4.7 µF or higher filtering capacitor should be connected between this pin and AGND. When an external 3.3 V regulator is used, connect it to this pin to supply the chip. 23 VAUX3P3_INT Power Connected to VAUX3P3 (pin 22) if internal 3.3 V regulator is used. Leave unconnected (Floating) if external 3.3 V regulator is used. PD69208T4/PD69204T4/PD69208M Pins © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 14

Pin Designator Type Description 24 IREF Analog input Reference resistor pin. Connect a 28.7 kΩ 1% resistor to AGND. Use 0.1% resistor in BT/PoH applications. 25 TRIM Test input Test input pin. Keep connected to VAUX3P3. 30,31 VPORT_NEG4 Analog I/O PD69208M/T4: Negative port 4 output. PD69204T4: Not connected, leave floating. 33,34 VPORT_NEG5 Analog I/O PD69208M/T4: Negative port 5 output. PD69204T4: Not connected, leave floating. 36,37 VPORT_NEG6 Analog I/O PD69208M/T4: Negative port 6 output. PD69204T4: Not connected, leave floating. 39,40 VPORT_NEG7 Analog I/O PD69208M/T4: Negative port 7 output. PD69204T4: Not connected, leave floating. 41 PGD1 Digital input Power good input from the system power supply. 42 DGND Power Digital ground. 43 DVDD Power in Regulated 3.3 V for digital circuitry. Connect voltage from pin VAUX3P3 or from external power supply source if used. A 1 µF or higher filtering capacitor should be connected between this pin and DGND. 44 RESET_N Digital input Reset input - active low (0 = reset). An external 10 kΩ pull-up resistor should be connected between this pin and DVDD. 46 PGD2 Digital input Power good input from the system power supply. 47 PGD3 Digital input Power good input from the system power supply. 48 ADDR0 Digital input SPI address bit 0 to set chip address. 49 ADDR1 Digital input SPI address bit 1 to set chip address. 50 ADDR2 Digital input SPI address bit 2 to set chip address. 51 ADDR3 Digital input SPI address bit 3 to set chip address. 52 CS_N Digital input SPI bus, chip select. 53 SCK Digital input SPI bus, serial clock input. 54 MOSI Digital input SPI bus, master data out/slave in. 55 MISO Digital output SPI bus, master data in/slave out. 56 PGD0 Digital input Power good input from the system power supply. An adequate ground plane on a bottom or top layer is required for adequate thermal performance. See AN3361 Designing an IEEE 802.3af/802.3at/802.3bt-Compliant PD69208 48-Port PoE System for additional details. PD69208T4/PD69204T4/PD69208M Pins © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 15

Application Information This section describes the application information of the PD69208T4, PD69204T4, and PD69208M devices.

4.1 Connection Check

An additional PD construction detection phase named, connection check, is done to detect which PD configuration is connected (single-signature or dual-signature) per the IEEE 802.3bt standard.

4.2 PD Detection

The PD detection feature detects a valid IEEE 802.3af, IEEE 802.3at, or IEEE802.3bt. The PD detection is done based on four different voltage levels to ensure robust detection, as shown in the Typical IEEE 802.3bt Port PoE Voltage Diagram.

4.3 Legacy Detection

When legacy detection is enabled, the PD detection mechanism detects and powers up the legacy and pre-standard PDs as well as IEEE 802.3af, IEEE 802.3at and IEEE 802.3bt standard compliant PDs (Classes 0–8).

4.4 Classification

The classification process takes place immediately after PD detection is successfully completed. The goal of the classification process is to detect PD class as specified in IEEE 802.3 standards. In IEEE 802.3af mode, the classification mechanism is based on a single voltage level (single event). In IEEE 802.3at and IEEE 802.3bt modes, the classification mechanism is based on two voltage levels (multiple events) as defined in IEEE 802.3-2015 Clause 33 and IEEE 802.3bt. In PoH mode, the classification mechanism is based on three events classification as defined in HDBaseT standard. Figure 4-1. Typical IEEE 802.3bt Port PoE Voltage Diagram

4.5 Port Start-Up

Upon a successful detection and classification process, power is applied to the load through a controlled start-up mechanism. PD69208T4/PD69204T4/PD69208M

Application Information

During this period, inrush current is limited to ILIM for a duration of TLIM (as specified in the table Port Real-Time Protection), which allows PD load to charge and allows a steady state of power condition.

4.6 Over-Load Detection and Port Shut-Down

After power-up, the PSE manager automatically initializes its internal protection mechanisms. These mechanisms are used to monitor and disconnect power from the PD when extreme conditions occur. These conditions include over- current or short ports terminals scenarios.

4.7 Disconnect Detection

The managers support the DC disconnect function as per IEEE 802.3 standards. This mechanism continuously monitors load current and disconnects power according to IUDL, TMPDO, and TMPS parameters as specified in Port Real-Time Protection.

4.8 IC Thermal Monitoring

The managers contains a thermal sensor that is sampled by the controller so that the manager die temperature is monitored at all times. To protect the PSE manager from damage, the system ports are disconnected before damage can occur. A temperature alarm threshold can be set by the controller to send interrupt indication by the xINT_OUT pin before ports are disconnected. The temperature can be read and monitored by the host as well if required.

4.9 Over-Temperature Protection

In addition to the die thermal sensor, there are thermal sensors on each MOSFET that continuously monitors each port main MOSFETs junction temperature, and shuts down the port load power when the temperature exceeds the threshold.

4.10 VMAIN Out-of-Range Protection

The system automatically disconnects ports power when VMAIN exceeds the pre-configured over-voltage and under- voltage thresholds. 4.11 2-Pair and 4-Pair Ports Operation modes include the following:

PoE Type 1/2 class 0–4 (up to 30 W)
PoE Type 3 class 0–4 2-Pair and class 5–6 4-Pair (up to 60 W)
PoE Type 4 class 7/8 4-Pair (75 W/90 W)
POH Mode: 4-Pair (up to 95 W) Note: For more information about 4-Pair operation modes and power, see Microchip AN3361.

4.12 Port Power Limit

Port power limit (PPL) is used to configure port power limit. When a port exceeds the power limit, it gets disconnected automatically. PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 17

4.13 Port Matrix Control

Port matrix control enables layout designers to ascribe each physical port in the system to a logical port if required.

4.14 Power Good Interrupt

Interrupt from power supply directly to the manager. For systems comprising more than a single power supply, in case one power supply fails, a port shutdown mechanism is executed to maintain operation and prevent the collapse of other power supplies. When a function is used, PGD0, PGD1, PGD2, and PGD3 should be connected to the main power supplies status indication pin. Any change of at least 1 µs on these lines triggers a pre-defined disconnection matrix. This matrix is defined by the PSE controller system power parameters. The port shutdown function reacts within 2 µs to any power good event.

4.15 Power Sequencing

Figure 4-2. Power Sequencing For proper operation, ensure that VMAIN is always the highest voltage connected to the IC. With an external 5 V and/or 3.3 V supply:

V aux5 pin voltage should never be above VMAIN pin voltage.
V aux3p3 pin voltage should never be above Vaux5 pin voltage.
The maximum 3.3 V slew rate is 100 ms.
Td1: V MAIN should be raised before or at the same time as 5 V.
Td2: 5 V should be raised before or at the same time as 3.3 V.
Td3: 3.3 V should be dropped before or at the same time as 5 V.
Td4: 5 V should be dropped before or at the same time as V MAIN. For details about PD69208 5 V and 3.3 V power supply connection options, see AN3361 Designing an IEEE 802.3af/at/bt PoE System Based on PD692x0/PD69208.

4.16 Ground

4.17 Voltage Regulator

The voltage regulator generates 3.3 V and 5 V for internal circuitry. These voltages are derived from VMAIN supply. To use the internal voltage regulator connect:

V AUX5 to DRV_VAUX5
V AUX3P3 to VAUX3P3_INT There are three options to reduce the managers’ power dissipation by regulating voltage outside the chip.
Use an external NPN transistor to regulate the 5 V. In this setup, the configuration of regulators pins should be as follows. – DRV_VAUX5 is connected to NPN BASE – V AUX5 is connected to NPN EMITTER (Connect Collector to VMAIN) – V AUX3P3 is connected to VAUX3P3_INT
Supply the manager with an external 5 V voltage regulator. In this setup, regulators pins configuration should be as follows. – V AUX3P3 is connected to VAUX3P3_INT – DRV_VAUX5 is not connected (left open) – V AUX5 is connected to external 5 V
Supply the manager with an external 3.3 V voltage regulator. In this setup, regulators pins configuration should be as follows. – V AUX5 is connected to DRV_VAUX5 – VAUX3P3_INT is not connected (left open) – V AUX3P3 is connected to external 3.3 V

4.18 SPI Communication

The following table lists the SPI communication packet structure. Table 4-1. SPI Communication—Packet Structure Control Byte Selects Manager According to Address R/W Bit Internal Register Address Number of Words (Read Access Only) Data Written to IC (Write Access Only) Read from IC (Read Access Only) 8 bits R(0)/W(1) 8 bits 8 bits 16 bits

4.18.1 SPI Addressing

The manager operates in the 8-bit address and 16-bit data. It responds to SPI transaction if the first SPI byte (IC address byte bits[7:1]) complies with the following. Table 4-2. Manager SPI Addressing

3 Bits (bit 7:5) 4 Bits (bit 4:1) 1 Bit (bit 0)

000 Address Input Pin Read/Write

4.18.2 Broadcast

A broadcast command is intended to instruct all connected manager ICs to perform a specific operation. The broadcast command is a write command with the standard packet structure. In a broadcast read operation, the read data is not valid and the read operation has no impact. PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 19

Table 4-3. Manager Broadcast Figure 4-3. SPI Timing Diagram Table 4-4. SPI Timing Diagram Description Name Min Delay Max Delay Description D1 910 ns SPI clock period D2 45% 55% SPI duty cycle D3 340 ns SPI_CS setup to SPI clock positive edge (delay after SPI_CS active signal) D4 340 ns SPI_CS hold to SPI clock positive edge (delay before SPI_CS inactive signal) D5 2 SPI clock cycles Delay between last SCK in SPI1 frame and first SCK at adjacent SPI1 frame D6 1 SPI clock cycle Between byte 0 (IC address) and byte 1 (address) D7 1 SPI clock cycle Between byte 1 (address) and byte 2 (data) D8 1 SPI clock cycle Between byte 2 (MS data byte) and byte 3 (LS data byte) D9 340 ns MOSI setup time D10 340 ns MOSI hold time D11 700 ns MISO tri-state to valid data from clock positive edge D12 700 ns MISO valid data to tri-state from SPI_CS positive edge D13 1 SPI clock cycle SPI_CS width (Delay SPI1 frame to adjacent SPI1 frame) D14 60 ns Filtered glitch width D15 D3 + D11 + 24 SPI clock cycles MISO tri-state from SPI_CS negative edge to valid data D16 200 ns MISO setup to SCK positive edge D17 200 ns MISO hold to SCK positive edge PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 20

Package Information This section describes the package of the PD69208T4, PD69204T4, and PD69208M devices.

5.1 Package Outline Drawing

The following figure shows the package drawing of the PD69208T4, PD69204T4, and PD69208M package. Figure 5-1. PD69208T4 Package Drawing (56 Pin QFN 8 mm × 8 mm) The following table lists the dimensions and measurements of the PD69208T4 package. Table 5-1. Package Outline Dimensions and Measurements Dimension Millimeters Inches Min Max Min Max A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0 0.002 A3 0.20 REF 0.008 REF K 0.20 MIN 0.008 MIN e 0.50 BSC 0.02 BSC L 0.30 0.50 0.012 0.02 b 0.18 0.30 0.007 0.012 D2 6.50 6.75 0.256 0.267 E2 6.50 6.75 0.256 0.267 D 8.00 BSC 0.315 BSC E 8.00 BSC 0.315 BSC Note: Dimensions do not include protrusions; they should not exceed 0.155 mm (0.006 in.) on any side. Lead dimension should not include solder coverage. Dimensions are in millimeters and inches for reference. PD69208T4/PD69204T4/PD69208M

Package Information

5.2 Thermal Specifications

The following tables list the thermal specifications the PD69208T4, PD69204T4, and PD69208M. Table 5-2. Thermal Specifications Thermal Resistance Typ Units Notes θJA 19.0 °C/W Junction-to-ambient thermal resistance. ΨJT 0.05 °C/W Junction-to-top thermal characterization parameter. A thermal metric derived from the difference in junction temperature (TJ) and package top temperature (TT) divided by total heating power (PH). θJC(top) 4.9 °C/W Junction-to-case thermal resistance with heat flow through package top. θJB 15.2 °C/W Junction-to-board thermal resistance. Note: All parameters are as per JEDEC JESD-51. PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 22

5.3 Recommended PCB Layout

The following figures show the recommended PCB layout for a PD69208T4, PD69204T4, and PD69208M 56-pin QFN 8 mm × 8 mm package. Units are in mm (mils). Figure 5-2. Top-Copper Layer PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 23

Figure 5-3. Top-Solder Paste Layer 8.2797[325.5906] 7.0203[276.3898] 6.1800[243.3071] 4.2300[166.5354] 3.8800[152.7559] 2.2900[90.1575] 1.9700[77.5591] 8.2797[325.5906] 7.0203[276.3898] 6.1300[241.3386] 4.2100[165.7480] 3.8900[153.1496] 2.2700[89.3701] 1.9200[75.5906] 0.2797[11.0118] 0.6209[24.4449] PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 24

Figure 5-6. Top-Layer Pin Geometry 0.8048[31.6850] Paste Metal Mask 0.2797[11.0118] 0.3000[11.8110] 0.3508[13.8110] 0.0254[1.0000] 0.0356[1.4016] 0.7523[29.6181] 0.0254[1.0000] 0.0356[1.4016] Note: The contract manufacturer has latitude to modify the solder paste stencil for manufacturability reasons. The solder paste stencil covers 65% to 80% of the thermal pad and should not allow solder to be applied to the thermal vias under the QFN package using any method they deem appropriate. Any design should be subject to system validation and qualification prior to commitment to mass production of field deployment. Use a 5 mil stencil.

5.4 Recommended Solder Reflow Information

Pb-free 100% Matte Tin Finish Package Peak Temperature for Solder Reflow (40 s maximum exposure)—260 °C (0 °C, –5 °C) PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 26

Table 5-3. Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (TSmax to Tp) 3 °C/second max 3 °C/second max Preheat Temperature min (TSmin) 100 °C 150 °C Temperature max (TSmax) 150 °C 200 °C Time (tsmin to tsmax) 60 s to 120 s 60 s to 180 s Time Maintained Temperature (TL) 183 °C 217 °C Time (tL) 60 s to 150 s 60 s to 150 s Peak classification temperature (TP) 210 °C to 235 °C 240 °C to 255 °C Time within 5 °C of actual peak temperature (tp) 10 s to 30 s 20 s to 40 s Ramp-down rate 6 °C/second max 6 °C/second max Time 25 °C to peak temperature 6 minutes max 8 minutes max Figure 5-7. Classification Reflow Profiles Table 5-4. Pb-Free Process—Package Classification Reflow Temperatures Package Thickness Volume <350 mm3 Volume 350–2000 mm3 Volume >2000 mm3 Less than 1.6 mm1 260 + 0 °C 260 + 0 °C 260 + 0 °C 1.6 mm to 2.5 mm1 260 + 0 °C 250 + 0 °C 245 + 0 °C Greater than or equal to 2.5 mm1 250 + 0 °C 245 + 0 °C 245 + 0 °C 1. Tolerance: The device manufacturer or supplier should assure process compatibility up to and including the stated classification temperature, meaning that the Peak reflow temperature is +0 °C. For example, 260 °C to 0 °C, at the rated MSL value. Note: Exceeding the ratings that are mentioned in the preceding table might cause damage to the device. PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 27

5.5 Tape and Reel Specification

This section provides the tape and reel specifications. Figure 5-8. Tape and Reel Pin-1 Orientation Figure 5-9. Tape Specifications Table 5-5. Tape Mechanical Data Dimension Value (mm) A0 8.35 ±0.10 B0 8.35 ±0.10 K0 1.40 ±0.10 K1 N/A Pitch 12.00 ±0.10 Width 16.00 ±0.30 PD69208T4/PD69204T4/PD69208M © 2020 Microchip Technology Inc. Datasheet DS00003428C-page 28

Figure 5-10. Reel Specifications Table 5-6. Reel Mechanical Data Dimensions Value (mm) Value (inch) Tape size 16.00 ±0.3 0.630 ±0.012 A max. 330 13 B max. 1.5 0.059 C 13.0 ±0.20 0.512 ±0.008 D min. 20.2 0.795 N min. 50 1.968 T max. 29 1.142 Base quantity: 2000 pieces

5.6 Reference Documents

IEEE Std 802.3-2018 Clause 33 Power over Ethernet over 2-Pair and Clause 145 Power over Ethernet
PD692x0_Serial Communication Protocol User Guide
Microchip AN3361 Designing an IEEE 802.3af/802.3at/802.3bt-Compliant PD69208 48-Port PoE System
AN3378 Surge Protection Application Note 8-Port PSE PoE Manager PD69208T4/M/4T4
PD692x0+PD69208M/208T4/204T4 Implementing Perpetual PoE (PPoE) and Fast PoE
PD69210, PD69220 & PD39210 PoE PSE Controller Data Sheet
PD69200 PoE PSE Controller Data Sheet PD69208T4/PD69204T4/PD69208M

Ordering Information The following table lists the part ordering information for the manager ICs. Table 6-1. Ordering Information Part Number Package Packaging Type Temperature Part Marking PD69208T4ILQ-TR-LE Plastic QFN 8 mm × 8 mm (56 lead) Tape and Reel –40 °C to 85 °C Microsemi Logo PD69208T4 L E e41 YYWWNNN2 PD69204T4ILQ-TR-LE Plastic QFN 8 mm × 8 mm (56 lead) Tape and Reel –40 °C to 85 °C Microsemi Logo PD69204T4 L E e41 YYWWNNN2 PD69208MILQ-TR-LE Plastic QFN 8 mm × 8 mm (56 lead) Tape and Reel –40 °C to 85 °C Microsemi Logo PD69208M L E e41 YYWWNNN2 1. L= FAB code; E= V2R4; and e4= second-level interconnect. 2. YY= Year; WW= Week; and NNN= Trace code. Note: The package meets RoHS, Pb-free of the European Council to minimize the environmental impact of electrical equipment. The following table lists the manufacturing and ordering part numbers of the manager devices. Table 6-2. Manufacturing and Ordering Part Numbers Ordering Part Number Manufacturing Part Number PD69208T4ILQ-TR-LE PD69208T4ILQ-TR-LE PD69204T4ILQ-TR-LE PD69204T4ILQ-TR-LE PD69208MILQ-TR-LE PD69208MILQ-TR-LE PD69208T4/PD69204T4/PD69208M

Ordering Information

Revision History Revision Date Section Description C 11/2020 Power Sequencing • Updated text. Ordering Information • Updated "5 mm x 5 mm" to "8 mm x 8 mm". B 7/2020 Typical PoE Application • Updated block diagram. Recommended PCB Layout

Updated all five diagrams. Main Voltage Monitoring • Corrected error to align with actual system performance. Port Current Monitoring • Indicated which conditions are for PD69208M or PD6920xT4. A 4/2020 This is the initial issue of this document. The PD69208T4, PD69204T4, and PD69208M PoE PSE managers were previously described in the following documents:
PD69208T4 and PD69210 Datasheet (Revision 3 September 2019 Document Number PD-000357193)
PD69204T4 and PD69210 Datasheet (Revision 3 September 2019 Document Number PD-000359832)
PD69208M and PD69210 Datasheet (Revision 3 September 2019 Document Number PD-000359833)
PD69208T4 and PD69200 Datasheet (Revision 6 September 2019 Document Number PD-000303603)
PD69204T4 and PD69200 Datasheet (Revision 6 September 2019 Document Number PD-000303601)
PD69208M and PD69200 Datasheet (Revision 6 September 2019 Document Number PD-000303451) PD69208T4/PD69204T4/PD69208M

Revision History

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Product Information

PD69208T4 specifications and overview.

Summary

PoE PSE Manager 2020

Description

PoE PSE Manager 2020

Source title PD69208T4 Datasheet(PDF) - Microchip Technology

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