PD69200 | DigiCamel IC Datasheet

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Technical content

PD69200 is available for existing designs. The PD69210 and PS69220 are recommended for all new designs. enhanced mode PoE capabilities, as specified in IEEE 802.3af, IEEE 802.3at, IEEE 802.3bt, and PoH standards. The PD69200 is available in a 32-pin, 5 mm x 5 mm QFN package. The following figure shows the typical PoE application of PD69208T4 and PD69200 devices. Figure 1. Typical PoE Application

Features

The following is the list of feature details of PSE Controller devices.

Complies with IEEE 802.3 af/at, IEEE 802.3 bt, and HDBaseT (POH) standards
Port matrix and priority
Cascade up to 12 PoE devices for 48 logical ports
45 W maximum two pair power and capable of 90 W per four pair port (.bt)
Supports three power management modes: Class (LLDP), Dynamic, and Static
Supports 16 power banks based on four power supplies
Port power limit setting
Interrupt from power supply to PoE drivers
Interrupt out pin for system and port events
System OK indication
Disable ports input pin
System and port status and port measurements
Legacy detection support
LED stream support
Fast and perpetual PoE support
Software download through I 2C or UART communication interface
32-pin, 5 mm x 5 mm QFN package
Pin compatible with PD69220
MSL3 and RoHS compliant PD69200 © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 2

Architecture The following figures shows the simplified hardware and the firmware architecture of the PoE system based on the PD69200 controller and the PD69208T4, PD69204T4, and PD69208M managers. Figure 1-1. Simplified Hardware Architecture PoE Manager PD69208T4 PD69204T4 PD69208M PoE Controller PD69200 Host Microprocessor SPII2C UART Figure 1-2. Simplified Firmware Architecture PoE Manager PoE Controller P3.xx Firmware Supports 802.3bt and PoH P2.xx Firmware Supports 802.3af/at and PoH Host Microprocessor GUI Customer Application APISystem Services Serial Communication Protocol I2C or UART

Dark grey boxes indicate Microchip supplied firmware
Light grey boxes indicate Microchip provided documentation
White boxes are user supplied

1.1 Firmware

Firmware is pre-programmed in PD69200 controller. The firmware version is identifiable via the IC ordering part number.
Firmware is vendor agnostic with regards to the choice of the host controller.
May operated “stand alone” or with I 2C or UART communication to host.
The default profiles are coded into the firmware. Microchip offers a configuration tool for profile modification.
Firmware is field-upgradeable via the I 2C or UART link.

1.2 Communication

Communication between the host application and the controller’s firmware may be done via a 15 byte protocol. Customers may use a Microchip provided API. Microchip provides a Serial Communication Protocol guide.

1.3 GUI

1.4 Software Library

The firmware (without the boot section), GUI, and API is available on Microchip’s software library https:// www.microchip.com/doclisting/SoftwareLib.aspx.

1.5 SPI Communication

The PD69208T4, PD69204T4, and PD69208M managers use SPI communication in SPI slave mode to communicate with the various controllers. Each manager has an address determined by ADDR0-ADDR3 pins. Each controller can support up to 12 ICs at addresses 0–11. The actual frequency between PD69200 and PD6920x ICs is 1 MHz. The following table lists the SPI communication packet structure. Table 1-1. SPI Communication – Packet Structure Control Byte Selects PD69208T4 According to Address R/W Bit Internal Register Address Number of Words (Read Access Only) Data Written to IC (Write Access Only) Read from IC (Read Access Only) 8 bits R(0)/W(1) 8 bits 8 bits 16 bits See the PD69208T4, PD69204T4, and PD69208M Manager datasheet for additional details on the SPI interface.

1.6 UART

A pull-up resistor is required on the UART communication line. For more information, see AN3361 Designing an IEEE802.3af/at/bt PoE System Based on PD692x0/PD69208. Following is the UART communications configuration setting details:

Bits per second: 19,200 bps
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None

1.7 I2C

The PD69200 requires the host to support I2C clock stretch. Following is the I2C communication configuration setting details:

Address: 7 bits
Clockstretch: host should support
Transaction: 15 bytes or 1 byte PD69200 Architecture © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 5

1.8 UART - I2C Address Selection

The choice of UART or I2C interface between the host CPU is made by applying a specific voltage level to pin #22 (I2C_ADDR_MEAS) on the PD69200. Additionally, the specific I2C address is also set by this voltage level. The voltage is set via an external resistor as shown in the following figure. Figure 1-3. I2C Address Selection 3.3V PD69200 22 10K The following table shows the specific values of R to choose UART or I2C and to set the address. Table 1-2. I2C Address Selection for PD69200 I2C_ADDR Voltage Low Level (V) I2C_ADDR Voltage High Level (V) I2C Address (Hexadecimal) R1- KΩ (1%) 0 0.21 UART N.C. 0.21 0.41 0x4 97.6 0.41 0.62 0x8 53.6 0.62 0.83 0xC 35.7 0.83 1.03 0x10 25.5 1.03 1.24 0x14 19.1 1.24 1.44 0x18 14.7 1.44 1.65 0x1C 11.3 1.65 1.86 0x20 8.87 1.86 2.06 0x24 6.81 2.06 2.27 0x28 5.23 2.27 2.48 0x2C 3.92 2.48 2.68 0x30 2.80 2.68 2.89 0x34 1.87 2.89 3.09 0x38 1.02 3.09 3.30 0x3C 0.324 PD69200 Architecture © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 6

Electrical Specifications For a complete list of electrical ratings and characteristics, see NXP KL15P80M48SF0 KL15 Sub-Family Data Sheet.

2.1 Electrical Characteristics

The following table list typical value conditions of PD69200. Table 2-1. Typical Value Conditions Symbol Parameter Min Typ Value Max Units TA Ambient temperature -40 25 85 °C VDD 3.3 V supply voltage 3.0 3.3 3.63 V

2.2 Immunity

The following table lists the immunity conditions of PD69200. Table 2-2. PD69200 Immunity Symbol Parameter Conditions Min Max Units ESD ESD rating HBM1 -2000 2000 V ESD rating CDM2 -500 500 V Note: 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. PD69200 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 7

2.3 Absolute Maximum Ratings

Stresses beyond those listed in this section may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability. Table 2-3. Absolute Maximum Ratings Symbol Parameter Minimum Maximum Units VDD Digital supply voltage -0.3 3.8 V VDDA Analog supply voltage VDD-0.3 VDD+0.3 V VDIO Digital pin input voltage (Except RESET) -0.3 3.6 V VAIO Analog pins1 and RESET pin input voltage -0.3 VDD+0.3 V Lead Soldering Temperature (40 s, reflow) 260 °C Storage Temperature -55 150 °C Note: 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. PD69200 Electrical Specifications © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 8

Pin Descriptions The following section describes the 32 pins of PD69200.

3.1 Pin Configuration and Pinout

The following figure shows the top view of PD69200. Figure 3-1. PD69200 Pin Diagram Top View xSys_OK/ LEDSystem OK M15M7V XXXX YYYYY UART0_TX UART0_RX RESERVED SWD_DIO VDD SWD_CLK RESERVED 5 76 832 41 EPSI_MOSIRESERVEDRESERVED ESPI_xCSESPI_SCKESPI_MISO VSSAVDDA 20 1819 172223 2124 I2C0_SCLxI2C_MESSAGE_READYRESERVEDI2C0_SDAI2C_ADDR_MEASxRESET RESERVEDRESERVED RESERVED FAN_CONTROL xLED_LATCH xLED_OE xINT_OUT xLED_CS xDISABLE_PORTS VSSD GGG ZZZ 69200 Note: For definitions about markings in the pinout diagram, see Ordering Information. PD69200 Pin Descriptions © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 9

3.2 Pin Details

The following tables describe the functional pin descriptions of the PD69200 device. Table 3-1. PD69200 Pin Description Number Designation Type Description

1 Reserved OUT Reserved UART - Leave Open

2 Reserved IN Reserved UART - Pull up to 3.3 V via 10K 3 ESPI_xCS OUT ESPI Bus to PoE Manager. SPI chip select. Pull-up required. See AN3361 for pin connection requirements. (Active Low) 4 ESPI_SCK OUT ESPI Bus to PoE Manager. SPI clock output to PD6920x, and LED stream clock output, set to 1 MHz. 5 ESPI_MOSI OUT ESPI Bus to PoE Manager. SPI Master Out Slave In. SPI packets are transmitted on this line. 6 ESPI_MISO IN ESPI Bus to PoE Manager. SPI Master In Slave Out. SPI packets are received on this line. 7 VDDA Supply Main Supply 3.3 V

8 VSSA GND Ground

9 Reserved Analog_IN Reserved Analog_IN. Connect to 3.3 V.

10 SWD_CLK Leave Open

11 UART0_RXx IN UART receive from host. 15-byte protocol commands are received on this line. The baud rate is set to 19,200 bps. A pull up is required. See AN3361 for details. 12 UART0_TX OUT UART transmit to host. 15-byte protocol reply/ telemetry is transmitted on this line. The baud rate is set to 19,200 bps.

13 SWD_DIO Leave Open

14 Reserved Analog_IN Reserved Analog_IN. Connect to 3.3 V or GND through 10 kΩ. 15 VDD Supply Main Supply 3.3 V

16 VSSD GND Ground

17 Reserved Oscillator Reserved – Oscillator input – Leave open

18 Reserved Oscillator Reserved – Oscillator output – Leave open

19 xRESET IN/OUT Host Reset input. This pin is active low. The controller can generate self-reset. In this case, the xRESET pin is driven low by the controller for about 100 μs. See AN3361 for pin connection requirements. PD69200 Pin Descriptions © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 10

Number Designation Type Description 20 I2C0_SCL IN/OUT I2C clock from the host master. Speed is limited to 400 KHz. Clock stretch required. Pull-up required, see AN3361 for details. 21 I2C0_SDA IN/OUT I2C bidirectional data. 15-byte protocol messages are transmitted on this line. A pull up is required. See AN3361 for more details.

22 I2C_ADDR_MEAS Analog_IN Analog input to determine I2C address or UART

operation.

23 Reserved Connect to GND

24 xI2C_MESSAGE_READY OUT I2C message ready for reading by the host. The controller asserts this line low when it has an answer to the host. Therefore, the host can poll this line and initiate an I2C read cycle only when the message is ready. This pin is active low. After the host reads the data from the controller, this pin is asserted to high. 25 xINT_OUT OUT Interrupt output indication. This line is asserted low when a pre-configured event is in progress. This pin is active low. 26 xLED_CS OUT Chip select signal for LED stream. This pin is active low. 27 xLED_LATCH OUT Latch signal for LED stream. This pin is active low. 28 xLED_OE OUT Output enable signal for LED stream. This pin is active low. 29 Reserved Analog_IN Reserved Analog_IN. Connect to 3.3 V.

30 FAN_CONTROL OUT Logic out that may be used to control a fan

driver. This pin is active high. 31 xDISABLE_PORTS IN Disable all PoE ports. When this input is asserted low, the controller shuts down all of the PoE ports in the system. See AN3361 for pin connection requirements. (Active Low) 32 xSys_OK/LED System OK OUT System validity indication. The behavior of this output is controlled by individual software mask. (Active Low) ePAD ePAD Connect to VSSA. Sufficient copper mass is needed to ensure adequate thermal performance. PD69200 Pin Descriptions © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 11

3.3 Recommended PCB Layouts

3.3.1 Recommended PCB Layout for 32-Pin QFN 5 mm x 5 mm

The following figures show the PCB layout pattern for PD69200. The units are in mm. Figure 3-2. Top Layer Copper PCB Layout 0.96 0.370.50 3.50 3.87 5.85 Figure 3-3. PD69200 Top-Layer Solder Paste and Vias PCB Layout for Thermal Pad Array 1.45 3.30 1.45 0.66 0.230.50 3.73 5.38 4.06 The contract manufacturer has latitude to modify the solder paste stencil for manufacturability reasons. The solder paste stencil covers 65% to 80% of the thermal pad and must not allow solder to be applied to the thermal vias under the QFN package using any method they deem appropriate. Any design should be subject to system validation and qualification prior to commitment to mass production of field deployment. Use a 5 mil stencil. PD69200 Pin Descriptions © 2020 Microchip Technology Inc. Datasheet DS00003460A-page 12

Package Information This section describes the package drawings of PD69200 device.

4.1 PD69200 Package Outline Drawing

The following figure shows the package drawing (32 Pin QFN 5 mm x 5 mm) of the PD69200 device. Figure 4-1. PD69200 Package Outline Drawing The following table lists the dimensions and measurements of the PD69200 package. Table 4-1. PD69200 Package Outline Dimensions and Measurements Dimension Millimeters Inches Min Max Min Max A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0 0.002 e 0.50 BSC 0.02 BSC L 0.30 0.50 0.012 0.02 b 0.18 0.30 0.007 0.012 D2 3.50 3.70 0.138 0.147 E2 3.50 3.70 0.138 0.147 D 5.00 BSC 0.197 BSC E 5.00 BSC 0.197 BSC Note: Dimensions do not include protrusions. They should not exceed 0.155 mm (.006 in) on any side. Lead dimension should not include solder coverage. The dimensions are in millimeters and inches for reference. PD69200

Package Information

4.2 Thermal Specifications

The following table list the thermal specifications of the PD69200. Table 4-2. Thermal Specifications Thermal Resistance Typ Units Notes θJA 33 °C/W Junction-to-ambient thermal resistance θJC 1.8 °C/W Junction-to-case thermal resistance

4.3 Recommended Solder Reflow Information

Following list shows the recommended solder reflow information details.

RoHS 6/6
Pb-free 100%
Matte Tin Finish
Package Peak Temperature for Solder Reflow (40 s maximum exposure)—260 °C (0 °C, –5 °C) Table 4-3. Classification Reflow Profiles Profile Feature Sn-PbEutectic Assembly Pb-Free Assembly Average Ramp-up Rate (TSmax to Tp) 3 °C/second max 3 °C/second max Preheat Temperature Min (TSmin) 100 °C 150 °C Temperature Max (TSmax) 150 °C 200 °C Time (tsmin to tsmax) 60 s to 120 s 60 s to 180 s Time Maintained Time Maintained Temperature (TL) 183 °C 217 °C Time (tL) 60 s to 150 s 60 s to 150 s Peak Classification Temperature (TP) 210 °C to 235 °C 240 °C to 255 °C Time within 5 °C of Actual Peak Temperature (tp) 10 s to 30 s 20 s to 40 s Ramp-down Rate 6 °C/second max 6 °C/second max Time 25 °C to Peak Temperature 6 minutes max 8 minutes max PD69200

Figure 4-2. Classification Reflow Profiles Table 4-4. Pb-Free Process—Package Classification Reflow Temperatures Package Thickness Volume mm3 < 350 Volume mm3 350– 2000 Volume mm3 > 2000 Less than 1.6 mm1 260 + 0 °C 260 + 0 °C 260 + 0 °C 1.6 mm to 2.5 mm1 260 + 0 °C 250 + 0 °C 245 + 0 °C Greater than or equal to 2.5 mm1 250 + 0 °C 245 + 0 °C 245 + 0 °C Note: 1. Tolerance: The device manufacturer or supplier should assure process compatibility up to and including the stated classification temperature, meaning that the peak reflow temperature is 0 °C. For example, 260 °C to 0 °C, at the rated MSL value. Note: Exceeding the ratings that are mentioned in the preceding table might cause damage to the device.

4.4 Reference Documents

IEEE Std 802.3-2018 Clause 33 Power over Ethernet over 2-Pair and Clause 145 Power over Ethernet
PD692x0 Communication Protocol User Guide
AN3361 Designing an IEEE802.3af/at/bt PoE System Based on PD692x0/PD69208
PD69208T4, PD69204T4, and PD69208M PoE PSE Manager Data Sheet
PD69210 and PD69220 PoE PSE Controller Data Sheet PD69200

Ordering Information The following table lists the part ordering information for PD69200 devices. Table 5-1. Ordering Information Part Number Package Packaging Type Temperature Part Marking Tray Marking PD69200D1- VVVV2SS3 Plastic QFN 5 mm × 5 mm (32 lead) Tray –40 °C to 85 °C Microsemi Logo NXP Logo 69200 M15M7V4 XXXX5 YYYY6 PD69200- VVVVSS PD-OOOOGabb7 YYWW PD69200D1- VVVV2SS3-TR Plastic QFN 5 mm × 5 mm (32 lead) Tape and Reel –40 °C to 85 °C Microsemi Logo NXP Logo 69200 M15M7V4 XXXX5 YYYY6 Note: 1. D stands for the detection method set as: – C = IEEE802.3 and pre-standard – R = IEEE802.3 only 2. VVVV is firmware revision. 3. SS stands for firmware parameters options. 4. Short part number 5. Mask set 6. Date code 7. Operational part number The firmware release note has all required information about how to specify the choice of VVVV and SS. Find the Firmware Release Notes in the Microchip Software Libraries, and register to My Microchip account to access the release notes. Note: The package meets RoHS, Pb-free of the European Council to minimize the environmental impact of electrical equipment. Note: Initial burning of controller's firmware is performed in the factory. Firmware upgrades can be performed by users using the communication interface. For more information, see TN-140 (Catalog Number: 06-0024-081). PD69200

Ordering Information

Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. 6.1 Revision 1.0 The PD69200 PoE PSE Controller was previously described in the following documents:

PD69208T4 and PD69200 Datasheet - Revision 6, September 2019, Document Number PD-000303603
PD69204T4 and PD69200 Datasheet - Revision 6, September 2019, Document Number PD-000303601
PD69208M and PD69200 Datasheet - Revision 6, September 2019, Document Number PD-000303451 Table 6-1. PD69200 Revision History Doc Rev. Date Comments A March 2020 This is the initial issue of this document. PD69200

Revision History

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Product Information

PD69200 specifications and overview.

Summary

PoE PSE Controller A March 2020

Description

PoE PSE Controller A March 2020

Source title PD69200 Datasheet(PDF) - Microchip Technology

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