PD69108FILQ

Microsemi Corporation

8 PORTS PSE POE MANAGER

Manufacturer: Microsemi Corporation

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8 PORTS PSE POE MANAGER

WWW.Microsemi .COM PD69108/F

DESCRIPTION

Microsemi’s PD69108 Power over Ethernet (PoE) Manager integrates power, analog and state of the art logic into a single 48 pin, plastic QFN package. The device is used in Ethernet switches and Midspans, enabling network devices to share power and data over the same cable. The PD69108 device is an 8 ports, mixed-signal, high-voltage PoE driver. It enables detection of IEEE802.3at-2009 compliant Type 1 and Type 2 PDs (Powered Devices), ensuring safe power feeding and disconnection of ports with full digital control and a minimum of external components. The PD69108 executes all real time functions as specified in the IEEE802.3af-2003 (“AF”) and IEEE802.3at-2009 High Power (“AT”) standards, including load detection and “AF” and “AT” classification. In addition, the PD69108 features Multiple Classification Attempts (MCA) port status monitoring, and provides system level activities such as power manag ement and MIB support for system management. The PoE device is designed to detect and disable disconnected ports utilizing DC disconnection methods, as specified in the IEEE 802.3af-2003 and IEEE802.3at-2009 standards. The unit provides PD protection such as over-load, under -load, over-voltage and short -circuiting. It supports supply voltages ranging from 44 to 57 VDC with no need for additional power supply sources. The chip includes built-in internal thermal protection. Optionally, t he PD69108 can detect legacy/pre- standard PD devices. The PD69108 is a low power device using an internal MOSFET and an external 0.36 Ω sense resistor.  IEEE802.3af-2003 compliant  IEEE802.3at-2009 compliant, including two-event classification  Supports pre-standard PD detection  Supports Cisco devices detection  Single DC voltage input (44 to 57 VDC)  Input voltage out of range protection  Wide temperature range: -10°C to +85°C  PD69108F version covering -40°C to +85°C  Over-temperature protection  Low power dissipation (0.36 Ω sense resistor and 0.3Ω MOSFET Rdson)  Includes Reset command pin  4 x direct address configuration pins  Continuous port monitoring and system data  Configurable load current setting  Configurable AT/AF modes  Configurable standard and legacy detection mode  Power soft start mechanism  On-chip thermal protection  Voltage monitoring/protection  Built in 3.3 VDC and 5 VDC regulators  Internal power on reset  RoHS compliant  Emergency power management supporting four configurable power bank I/Os  Can be cascaded to up to 12 PoE devices (96 ports) IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F ABSOLUTE MAXIMUM RAT INGS PACKAGE PIN OUT Supply Input Voltage (VMAIN) -0.3 to 74 VDC Port_Neg[0..7] Pins -0.3 to 74 VDC Port_Sense[0..7] Pins -0.3 to 3.6 VDC QGND, GND Pins -0.3 to 0.3 VDC All Other Pins -0.3 to 3.6 VDC PD69108 Operating Ambient Temperature Range -10° to +85° C PD69108F Operating Ambient Temperature Range -40° to +85° C Maximum Operating Junction Temperature +150° C ESD Protection at all I/O Pins ± 2 KV HBM Storage Temperature Range -65° to +150° C Notes: Exceeding these ratings can cause damage to the device. All voltages are with respect to ground. Currents are marked positive when flowing into specified terminals and marked negative when flowing out of a specified terminal. MOSI IREF AGND VMAIN PORT_SENSE3 VPORT_NEG3 PORT_SENSE4 VPORT_NEG4 PORT_SENSE5 VPORT_NEG6 SCK44 Microsemi LOGO MSC PD69108/F Date Code PG0 PORT_SENSE6 QGND DGND VAUX5 PG1 PG2 PG3 TRIM DGND SPI_CS MISO PORT_SENSE2 VPORT_NEG2 N/C DRV_VAUX5 VPORT_NEG0 PORT_SENSE0 PORT_SENSE7 VPORT_NEG7 VPORT_NEG1 PORT_SENSE1 VPORT_NEG5 VAUX3P3 N/C VAUX3P3_INT AGND DVDD ADDR0 ADDR1 ADDR2 ADDR3 RESET_N N/C N/C AGND REG_EN_N (Top View) RoHS / Pb-free 100% Matte Tin Finish PACKAGE ORDER INFO THERMAL DATA TA (°C) Plastic 48 pin QFN 8 mm x 8 mm TYPICAL THERMAL RESISTANCE-JUNCTION TO AMBIENT 25° C/W RoHS compliant / Pb-free/MSL1 TYPICAL THERMAL RESISTANCE-JUNCTION TO CASE 4° C/W -10 to +85 PD69108ILQ Junction Temperature Calculation: TJ = TA + (PD x θJA). The θJA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. -40 to +85 PD69108FILQ Note: Available in Tape and Reel. Append the letters “TR” to the part number. POWER DISSIPATION Rsense Power Dissipation: 0.36 Ω x Iport2 Rds_ON Power Dissipation: 0.3Ω x Iport2

Pport_AF = 15.4 W ==> PRsense = 28.2mW PRds_ON = 23.4mW
Pport_AT = 30 W ==> PRsense = 107 mW ** Calculated for Supply input Voltage of 55V PRds_ON = 88.5mW INTERNAL 3.3V VOLTAG E REGULATOR IS USED EXTERNAL 3.3V VOLTAG E REGULATOR IS USED PD69108 self power dissipation: 1.1 W PD69108 8 ports AF Application Power dissipation = 1.1 W + PD69108 8 ports AT Application Power dissipation = 1.1 W + [ 8 x (107 mW + 88.5mW) ] = 2.66W PD69108 self power dissipation: 0.5 W PD69108 AF 8 ports Application Power dissipation = PD69108 8 ports AT Application Power dissipation = 0.5 W + [ 8 x (107 mW + 88.5mW) ] = 2.06W

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F ROHS AND SOLDER REFL OW INFORMATION RoHS 6/6 Pb-free 100% Matte Tin Finish Package Peak Temperature for Solder Reflow (40 seconds maximum exposure) 260°C (+0°C, -5°C) Notes: Exceeding these ratings can cause damage to the device.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, the following specifications apply to the operating ambient temperature. PARAMETER SYMBOL TEST CONDITIONS / COMMENT PD6 91 08 POE MANAGER UNITS MIN TYP MAX POWER SUPPLY Input Voltage VMAIN Supports Full IEEE802.3 functionality 44 55 57 V Power Supply Current @ Operating Mode VMAIN = 55 VDC 20 mA 5V Output Voltage VAUX5 4.5 5 5.5 VDC 3.3V Output Voltage VAUX3P3 2.97 3.3 3.63 VDC 3.3V Output Current Without external NPN 5 mA With external NPN transistor on VAUX5 30 mA 3.3V Input Voltage VAUX3P3 REG_EN_N pin = 3.3V (internal reg. is disabled) VAUX3P3_INT=5V 3 3.3 3.6 VDC DIGITAL I/O ( ( RESET_N, MISO, MOSI, SCK, CS, PG[0..3], A DD[0..3]) Input Logic High Threshold VIH 2.2 V Input Logic Low Threshold VIL 0.8 V Input Hysteresis Voltage 0.4 0.6 0.8 V Input High Current IIH -10 10 uA Input Low Current IIL -10 10 uA Output High Voltage VOH For IOH = -1 mA 2.4 V Output Low Voltage VOL IOH = 1 mA 0.4 V POE LOAD CURRENTS AF Limit Mode AF_LIM 400 425 450 mA AT Limit AT_LIM 775 850 925 mA AT Limit Dynamic Range Configurable by communication RSENSE = 0.36 Ω 1% connected at Port_Sense pin 540 1200 mA MAIN POWER SWITCHING FET On Resistance RDSON 0.3 Ω Internal Thermal Protection Threshold 200 °C

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F Dynamic Characteristics The PD69108 utilizes three current level thresholds (Imin, Icut, Ilim) and three timers (Tmin, Tcut, Tlim).  Loads that consume Ilim current for more than Tlim are classified as being in 'short circuit state' and are shutdown.  Loads that dissipate more than Icut for longer than Tcut are classified as ‘overloads’ and are automatically shutdown.  If output power is below Imin for more than Tmin, the PD is classified as ‘no-load’ and is shutdown. Automatic recovery from over-load condition is attempted every TOVLREC periods (typically 1 second). Output power is limited to Ilim, which is a maximum peak current allowed at the port. IEEE802.3 AF Mode Parameters PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Automatic recovery from no- load shutdown TUDLREC value, measured from port shutdown point (can be modified through control port) 1 Sec Cutoff timers accuracy Typical accuracy of Tcut 2 ms Inrush current IInrsh For t = 50 ms, Cload= 180 uF max. 400 450 mA Output current operating range Iport Continuous operation after startup period. 10 350 mA Output power available operating range Pport Continuous operation after startup period, at port output. 0.57 15.4 W Off mode current Imin1 Must disconnect for T greater than TUVL 0 5 mA Imin2 May or may not disconnect where T is greater than TUVL 5 7.5 10 mA PD power maintenance request drop-out time limit TPMDO Buffer period to handle transitions 300 400 ms Over-load current detection range Icut Time limited to TOVL 350 400 mA Over load time limit TOVL 50 75 ms Turn on rise time Trise From 10% to 90% of Vport (Specified for PD load consisting of 100 uF capacitor in parallel to 200 Ω). 15 us Turn off time Toff From Vport to 2.8 VDC 500 ms Time maintain power signature TMPS DC modulation time for DC disconnect 49 ms

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F IEEE802.3 AT Mode Parameters PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Automatic recovery from no-load shutdown TUDLREC value, measured from port shutdown point (can be modified through control port) 1 s Cutoff timers accuracy Typical accuracy of Tcut 2 ms Inrush current IInrsh For t = 50 ms, Cload = 180 uF max. 400 450 mA Output current operating range Iport Continuous operation after startup period 10 600 mA Output power available, operating range Pport Continuous operation after startup period at port output 0.57 36 W Off mode current Imin1 Must disconnect where T is greater than TUVL 0 5 mA Imin2 May or may not disconnect where T is greater than TUVL 5 7.5 10 mA PD power maintenance request drop-out time limit TPMDO Buffer period to handle transitions 300 400 ms Over-load current detection range Icut Time limited to TOVL 600 775 mA Over-load time limit TOVL 50 75 ms Turn on rise time Trise From 10% to 90% of Vport (Specified for PD load consisting of 100 uF capacitor in parallel to 200 Ω). 15 us Turn off time Toff From Vport to 2.8 VDC 500 ms Time maintain power signature TMPS DC modulation time for DC disconnect 49 ms

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F Package Pinout MOSI IREF AGND VMAIN PORT_SENSE3 VPORT_NEG3 PORT_SENSE4 VPORT_NEG4 PORT_SENSE5 VPORT_NEG6 SCK44 Microsemi LOGO MSC PD69108/F Date Code PG0 PORT_SENSE6 QGND DGND VAUX5 PG1 PG2 PG3 TRIM DGND SPI_CS MISO PORT_SENSE2 VPORT_NEG2 N/C DRV_VAUX5 VPORT_NEG0 PORT_SENSE0 PORT_SENSE7 VPORT_NEG7 VPORT_NEG1 PORT_SENSE1 VPORT_NEG5 VAUX3P3 N/C VAUX3P3_INT AGND DVDD ADDR0 ADDR1 ADDR2 ADDR3 RESET_N N/C N/C AGND REG_EN_N PD69108 for -10° to +85°C Operating Ambient Temperature Range PD69108F for -40° to +85°C Operating Ambient Temperature Range Detailed Pinout Description PIN PIN NAME PIN TYPE DESCRIPTION

0 Exposed PAD Analog Gnd

Exposed PAD: Metal plate on the IC bottom side connected to analog ground. A decent ground plane (about 500 mil inch over 500 mil inch) should be deployed around this pin whenever possible

1 PG0 Digital Input Power supply monitoring

2 PG1 Digital Input Power supply monitoring

PORT_SENSE0 Analog Input Sense resistor port input (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy).

4 VPORT_NEG0 Analog I/O Negative port output

PORT_SENSE1 Analog Input Sense resistor port input (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy).

6 VPORT_NEG1 Analog I/O Negative port output

7 AGND Power Analog ground

8 N/C Not Connected

PORT_SENSE2 Analog Input Sense resistor port input (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy).

10 VPORT_NEG2 Analog I/O Negative port output

PORT_SENSE3 Analog Input Sense resistor port input (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy).

12 VPORT_NEG3 Analog I/O Negative port output

13 N/C Analog I/O Test pin for production use only

Keep open, not connected 14 N/C Analog I/O VMAIN Power Supplies voltage for the internal analog circuitry. A low ESR 1 uF (or higher) bypass capacitor, connected to AGND should be placed as close as possible to this pin through low resistance traces. VAUX5 Power Regulated 5 VDC output voltage source; it needs to be connected to a filtering capacitor of 4.7 uF or higher. If an external NPN is used to regulate the voltage, connect this pin to the "Emitter" (the "collector" should be connected to Vmain) DRV_VAUX5 Power Driven outputs for 5 VDC external regulation; if internal regulation is used, connect to pin 16. If an external NPN is used to regulate the voltage, connect this pin to the "Base".

18 AGND Power Analog ground

19 VAUX3P3_INT Power Connected to VAX3P3 (pin 20) if internal 3.3 VDC regulator is used. Connect to VAUX5 (pin 16) if external 3.3 VDC regulator is used VAUX3P3 Power Regulated 3.3v output voltage source. A 4.7 μF or higher filtering capacitor should be connected between this pin and AGND. When an external 3.3 VDC regulator is used, connect it to this pin to supply the chip. 21 QGND Power Quiet analog ground. 22 IREF Analog Input Reference resistor pin. Connect a 30.1 kΩ 1% resistor to QGND. 23 TRIM Analog Input Trimming Input for IC production. Should be connected to VAUX3P3. REG_EN_N REG_EN_N Enable/Disable the internal 3.3 VDC regulator in case an external 3.3 VDC is used to supply the chip.

GND: Internal regulator enabled
3.3 VDC: Internal regulator disabled 25 VPORT_NEG4 Analog I/O Negative port output. PORT_SENSE4 Analog Input Sense resistor port input (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy). 27 VPORT_NEG5 Analog I/O Negative port output. PORT_SENSE5 Analog Input Sense resistor port input. (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy).

29 N/C Not Connected

30 AGND Power Analog ground. 31 VPORT_NEG6 Analog I/O Negative port output.

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F PIN PIN NAME PIN TYPE DESCRIPTION PORT_SENSE6 Analog Input Sense resistor port input. (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy). 33 VPORT_NEG7 Analog I/O Negative port output. PORT_SENSE7 Analog Input Sense resistor port input. (Connected to 0.36 Ω, 1% resistor to QGND with ~12 mΩ trace for measurements accuracy). 35 PG2 Digital Input Power supply monitoring. 36 PG3 Digital Input Power supply monitoring. 37 TST Digital I/O Test pin for production use only. Keep connected to DGND. RESET_N Digital Input Reset input; active low ('0' = reset) An external 10K pull-up resistor should be connected between this pin and DVDD.

39 MOSI Digital Input SPI bus, Master Data out/slave in

40 MISO Digital Output SPI bus, Master Data in/slave out

41 SPI_CS Digital Input SPI bus, Chip Select

42 DVDD Power Digital 3.3 V input. It needs to be connected to filtering capacitor of 1 uF.

43 DGND Digital I/O Digital GND

44 SCK Digital Input SPI bus, Serial clock input

45 ADDR3 Digital Input Address bus to set SPI address

46 ADDR2 Digital Input Address bus to set SPI address

47 ADDR1 Digital Input Address bus to set SPI address

48 ADDR0 Digital Input Address bus to set SPI address

Address Pin Description (ADDR<3:0>) ADDR3 ADDR2 ADDR1 ADDR0 SPI ADDRESS [HEX] 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 A 1 0 1 1 B 1 1 0 0 C 1 1 0 1 D 1 1 1 0 E – Broadcast (See note) 1 1 1 1 F

'1' = DVDD (3.3 V)
'0' = DGND (digital ground) Note: This address is used for Broadcast. Do not set any PD69108s in the system to this address.

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F SPI Detailed Timing Information Name Min Delay Max Delay Description D1 714ns SPI clock period D2 45 55 SPI duty cycle D3 340 ns SPI_CS setup to SPI clock Positive Edge (delay after SPI_CS active signal) D4 340 ns SPI_CS hold to SPI clock Positive Edge (delay before SPI_CS inactive Signal) D5 2 spi clock cycles Delay between last SCK in eSPI1 frame and first SCK at adjacent eSPI1 frame D6 1 spi clock cycles Between byte 0 (IC addr) and byte 1(addr) D7 1 spi clock cycles Between byte 1 (addr) and byte 2(data). D8 1 SPI clock cycles Between byte 2 (MS data byte) and byte 3(LS data byte). D9 340 ns MOSI setup time D10 210 ns MOSI hold time D11 140ns MISO tri-state to valid data from clock positive edge D12 300ns MISO valid data to tri-state from SPI_CS positive edge D13 1 SPI clock cycles SPI_CS width (Delay eSPI1 frame to adjacent eSPI1 frame) D14 60ns Filtered Glitch Width D15 D3 + 15.5 SPI clock cycles D3+23.75 SPI clock cycles MISO tri-state from SPI_CS Negative Edge to valid data D1 D2D7D6 D8 D10 CS_N SCK MOSI MISO D11 D12 SPI1 frame

8 SCK clock cycles 8 SCK clock cycles 8 SCK clock cycles

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F PACKAGE DESCRIPTION 48-Pin 8x8mm QFN DIM MILLIMETERS INCHES MIN MAX MIN MAX A 0.80 1.00 0.031 0.039 A1 0.00 0.05 0 0.002 A3 0.20 REF 0.008 REF K 0.20 MIN 0.008 MIN e 0.50 BSC 0.02 BSC L 0.30 0.50 0.012 0.02 b 0.18 0.30 0.007 0.012 D2 6.35 6.60 0.250 0.260 E2 6.35 6.60 0.250 0.260 D 8.00 BSC 0.315 BSC E 8.00 BSC 0.315 BSC Note: Dimensions do not include protrusions; these do not exceed 0.155 mm (.006”) on any side. Lead dimension do not include solder coverage. e b L K D E A

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F PD69108 Internal Block Diagram The PD69108 is based on two major sections:  A Digital section which controls and monitors the logical PoE functions (state machines, timings etc.)  An Analog section which performs the Front End analog PoE functionality. Figure 1 illustrates both functions. PORT 8 Tool Box PORT 7 Tool Box PORT 6 Tool Box PORT 5 Tool Box PORT 4 Tool Box PORT 3 Toool Box PORT 2 Tool Box CLK A/D Voltage Regulator Analog Mesurment Thermal Protection Controlled Reference Voltage Generator for Line Detection & Classification Current Limiter AGND Vmain POR Sense Resistor Main MOSFET SPI (SPI Control, Watch Dog) CRG (CPU/Control Registers) MSC (Miscellaneous , Power bank, General counter, IC ctrl) sck cs_n mosi miso PG[3:0] sync sync sync VCM (Voltage Current Measurement) ADC Full RTP AIR (Analog Interface) ADDR[3:0] Reg Table DGND Digital Analog Figure 1: PD69108 Internal Block Diagram

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F Logic Main Control Module The Logic Main Control Block includes the Digital Timing Mechanisms and State Machines synchronizing and activating PoE functions according to MCU control commands such as:  Real Time Protection (RTP)  Start Up Macro (DVDT)  Load Signature Detection (RES DET)  Classification Macro (CLASS)  Voltage and Current Monitoring Registers (VMC)  ADC Interfacing  Direct Digital Signals with Analog Block Line Detection Generator Upon request from the MCU to the Main Control Module, four different voltage levels are generated by the Line Detection Generator to ensure a robust AF / AT Line Detection functionality. Classification Generator Upon request from the MCU to the Main Control Module, the State Machine applies a regulated Class Event and Mark Event voltage to the ports, as required by the IEEE standard. Current Limiter This circuit continuously monitors the current of powered ports and limits the current to a specific value, according to pre-defined limits as set by AF/AT and Current_Set pins. In cases where the current exceeds this specific level, the system starts measuring the elapsed time. If this time period is greater than a preset threshold, the port is disconnected. Main MOSFET Main power switching FET, used to control PoE current into the load. ADC A 10-Bit Analog to Digital converter, used to convert analog signals into digital registers for the Logic Control module. Power on Reset (POR) Monitors the internal 3.3 V voltage DC levels; if this voltage drops below specific thresholds, a reset signal is generated and the PD69108 is reset. Voltage Regulator The voltage regulator generates 3.3 VDC and 5 VDC for the internal circuitry. These voltages are derived from the Vmain supply. To use the internal voltage regulator connect:  VAUX5 to DRV_VAUX5  VAUX3P3 to VAUX3P3_INT  REG_EN_N to AGND. There are two options to reduce the PD69108 power dissipation by regulating the voltage outside the chip:  Use an external NPN transistor to regulate the 5 VDC. In this setup, the configuration of the regulators pins should be:

DRV_VAUX5 is connected to the NPN BASE
VAUX5 is connected to the NPN EMITTER (Connect the Collector to VMAIN)
VAUX3P3 is connected to VAUX3P3_INT
REG_EN_N is connected to AGND  Supply the PD69108 with an external 3.3 V voltage regulator. In this setup, the configuration of the regulators pins should be:
VAUX5 is connected to DRV_VAUX5
VAUX3P3_INT is connected to VAUX5
VAUX3P3 is connected to the external 3.3 V
REG_EN_N is connected to VAUX3P3 The above two options can be implemented simultaneously. CLK CLK is an internal 8 MHz clock oscillator.

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F Theory of Operation The PD69108 performs IEEE802.3af and IEEE802.3at functionality as well as legacy (capacitor) and Cisco’s PDs detection and additional protections such as short circuit and dV/dT protection upon startup. Line Detection The Line Detection feature detects a valid AF or AT load, as specified in the AF / AT standard. The resistor value should go from 19 kΩ to 26.5 kΩ. Line detection is based on four different voltage levels generated over the PD (the load) as illustrated in Figure 2. v t

2 Events

(Inrush) Power “ON” Power “OFF” Figure 2: Typical PoE Voltage Time Diagram Legacy (Cap) Detection In cases where legacy is set, the PD69108's Detection mechanism detects and powers up legacy PDs as well as AF/AT compliant PDs. This mechanism is designed to detect and power up CISCO legacy PDs as well. Classification The classification process takes place immediately after resistor detection has successfully completed. The goal of the classification process is to detect PD class, as specified in the IEEE802.3AF and AT standards. In the AF mode, classification mechanism is based on a single voltage level (single finger). In the AT mode, classification mechanism is based on two voltage levels (dual finger) as defined in IEEE802.3at-2009. Port Start Up Upon a successful detection and classification process, power is applied to the load via a controlled Start Up mechanism. During this period current is limited to 425 mA for a typical duration of 65 mS, which allows the PD load to charge and allow steady state power condition. Over-Load Detection and Port Shut Down After power up, the PD69108 automatically initializes its internal protection mechanisms utilized to monitor and disconnect power from the load in cases where extreme conditions such as over-current or short ports terminals scenario occur, as specified in the IEEE802.3AF/AT standard. Disconnect Detection The PD69108 supports DC Disconnect Function as per the IEEE802.3AF/AT standard. This mechanism continuously monitors load current and disconnects power in cases where load current is below 7.5 mA (typical) for more than 322 mS. Over-Temperature Protection The PD69108 has internal temperature sensors that continuously monitor the main MOSFET junction temperature and disconnect load power in cases where

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F junction temperature exceeds 200° C. This mechanism protects the device from extreme events, such as high ambient temperature or other thermo-mechanical failures that could damage the PD69108. VMAIN Out of Range Protection The PD69108 automatically disconnects port power in cases where Vmain exceeds 60 VDC. This valuable mechanism protects the load in cases where main power source is faulty or damaged. TYPICAL APPLICATION This typical application illustrates a simple Power Over Ethernet system Solution for an 8 Ethernet Ports Switch or Hub. “POS” and “NEG” Signals should be connected to the Switch RJ45 Jack To Opto MISO SCK xCS MOSI Vmain DRV_VAUX5 Addr0 Addr1 VAUX5 47nF 0.36? Vport_Pos0 Vport_Neg0 Vport_Sense0 Vport_Neg7 Vport_Sense7 Vport_Neg7 Vmain VAUX5 QGND SPI Communication Bus Vport_Neg0 To Power Supply PG0 PG1 PG2 Iref Addr2 Addr3 PG3 MCU MISO SCK xCS MOSI Isolated SPI Communication Bus VAUX3P3 VAUX3P3_INT Connected to DVDD or DGND according to desired address QGND QGND 30.1K? Figure 3: Typical Application * For detailed application's schematics and layout recommendations, contact: sales_AMSG@microsemi.com

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F Tape and Reel – Packaging Information REEL MECHANICAL DATA mm. inch Tape size 16.00 ±0.3 0.630 ±0.012 A max. 330 13” B max. 1.5 0.059 C 13.0 ±0.20 0.512 ±0.008 D min. 20.2 0.795 N min. 50 1.968 T max. 29 1.142 BASE QUANTITY 2000 pcs.

Copyright © 2013 Microsemi Rev. 1.6 Analog Mixed Signal Group 1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308 WWW.Microsemi .COM PD69108/F The information contained in the document (unless it is publicly available on the Web without access restrictions) is PROPRIETARY AND CONFIDENTIAL information of Microsemi and cannot be copied, published, uploaded, posted, transmitted, distributed or disclosed or used without the express duly signed written consent of Microsemi. If the recipient of this document has entered into a disclosure agreement with Microsemi, then the terms of such Agreement will also apply . This document and the information contained herein may not be modified, by any person other than authorized personnel of Microsemi. No license under any patent, copyright, trade secret or other intellectual property right is granted to or conferred upon you by disclosure or delivery of the information, either expressly, by implication, inducement, estoppels or otherwise. Any license under such intellectual property rights must be approved by Microsemi in writing signed by an officer of Microsemi. Microsemi reserves the right to change the configuration, functionality and performance of its products at anytime without any notice. This product has been subject to limited testing and should not be used in conjunction with life- support or other mission-critical equipment or applications. Microsemi assumes no liability whatsoever, and Microsemi disclaims any express or implied warranty, relating to sale and/or use of Microsemi products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or oth er intellectual property right. Any performance specifications believed to be reliable but are not verified and customer or user must conduct and complete all performance and other testing of this product as well as any user or customers final application. User or customer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the customer’s and user’s responsibility to independently determine suitability of any Microsemi product and to test and verify the same. The information contained herein is provided “AS IS, WHERE IS” and with all faults, and the entire risk associated with such information is entirely with the User. Microsemi specifically disclaims any liability of any kind including for consequential, incidental and punitive damages as well as lost profit. The product is subject to other terms and conditions which can be located on the web at http://www.microsemi.com/legal/tnc.asp

Revision History

Para. Affected Description 0.1 / 3-Nov-09 - Initial Release 0.2 / 10-Jan-10 Power Dissipation 0.3 / 12-Apr-10 Update 0.4 / 12-May-10 Ordering information update 0.4/ 27-Jul-10 Changing catalog numbers metrology 0.5/10-Apr-11 Update/corrections 0.6/1-Aug-11 Add SPI Timing Data 1.2/Oct 2011 Add Theta JC 1.3/Jan 2012 Remove “Confidential” header and updating Footer address 1.4/Feb 2012 Updating I lim according to UL and IEEE 1.5/Dec 2012 Adding Tape & Reel Data 1.6/March 2013 Adding full temperature rang P/N © 2013 Microsemi Corp. All rights reserved. For support contact: sales_AMSG@microsemi.com Visit our web site at: www.microsemi.com Catalogue Number DS_PD69108

Product Information

PD69108FILQ specifications and overview.

Summary

8 PORTS PSE POE MANAGER

Description

8 PORTS PSE POE MANAGER

Source title PD69108FILQ Datasheet(PDF) - Microsemi Corporation

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