PD557

PCA9557 TI | Alldatasheet

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RGV□PACKAGE (TOP VIEW) 5 6 7 8 13141516 SCLSDA V CC RESET GND P3P2 D,□DB,□DGV,□OR□PW□PACKAGE (TOP VIEW) 8 9 161 GND SCL SDA VCC RESET RGY□PACKAGE (TOP VIEW) 7 10 151612 SDA SCL V CC 8 9 GND RESET DESCRIPTION/ORDERING INFORMATION PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 REMOTE 8-BIT I C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS Low Standby Current Consumption of Internal Power-On Reset µ A Max High-Impedance Open Drain on I C to Parallel Port Expander Power Up With All Channels Configured as Operating Power-Supply Voltage Range of Inputs 2.3 V to 5.5 V No Glitch on Power Up 5-V Tolerant I/O Ports Noise Filter on SCL/SDA Inputs 400-kHz Fast I C Bus Latched Outputs With High Current Drive Three Hardware Address Pins Allow for Use of Maximum Capability for Directly Driving LEDs up to Eight Devices on I C/SMBus Latch-Up Performance Exceeds 100 mA Per Lower-Voltage Higher-Performance Migration JESD 78, Class II Path for PCA9556 ESD Protection Exceeds JESD Input/Output Configuration Register 2000-V Human-Body Model (A114-A) Polarity Inversion Register 200-V Machine Model (A115-A) Active-Low Reset Input 1000-V Charged-Device Model (C101) This 8-bit I/O expander for the two-line bidirectional bus is designed for 2.3-V to 5.5-V V CC operation. The device provides general-purpose remote I/O expansion for most microcontroller families via the I C interface [serial clock (SCL) and serial data (SDA)]. The PCA9557 consists of one 8-bit configuration (input or output selection), input port, output port, and polarity inversion (active-high) registers. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master. The device outputs (latched) have high-current drive capability for directly driving LEDs. The device has low current consumption. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. PRODUCTION DATA information is current as of publication date. Copyright 2005 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(CONTINUED) PCA9557 SCPS133I DECEMBER 2005 REVISED JUNE 2008 www.ti.com The system master can reset the PCA9557 in the event of a timeout or other improper operation by asserting a low in the active-low reset RESET input. The power-on reset puts the registers in their default state and initializes the I C/SMBus state machine. Asserting RESET causes the same reset/initialization to occur without depowering the part. Three hardware pins (A0, A1, and A2) are used to program and vary the fixed I C address, allowing up to eight devices to share the same I C bus or SMBus. ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN RGV Reel of 2000 PCA9557RGVR PD557 QFN RGY Reel of 1000 PCA9557RGYR PD557 Reel of 2500 PCA9557DR SOIC D Reel of 250 PCA9557DT PCA9557 Tube of PCA9557D C to C Reel of 2000 PCA9557DBR SSOP DB PD557 Tube of PCA9557DB Reel of 2000 PCA9557PWR TSSOP PW Reel of 250 PCA9557PWT PD557 Tube of PCA9557PW TVSOP DGV Reel of 2000 PCA9557DGVR PD557 (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com TERMINAL FUNCTIONS NO. QFN (RGY) SOIC (D), NAME

DESCRIPTION

(DB), QFN (RGV) TSSOP (PW), AND TVSOP (DGV) SCL Serial clock bus. Connect to V CC through a pullup resistor. SDA Serial data bus. Connect to V CC through a pullup resistor. Address input. Connect directly to V CC or ground. Address input. Connect directly to V CC or ground. Address input. Connect directly to V CC or ground. P-port input/output. High impedance open-drain design structure. Connect to V CC through a pullup resistor. P-port input/output. Push-pull design structure. GND Ground P-port input/output. Push-pull design structure. P-port input/output. Push-pull design structure. P-port input/output. Push-pull design structure. P-port input/output. Push-pull design structure. P-port input/output. Push-pull design structure. P-port input/output. Push-pull design structure. Active-low reset input. Connect to V CC through a pullup resistor if no active RESET connection is used. V CC Supply voltage Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

P7−P0 RESET 15 PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 LOGIC DIAGRAM (POSITIVE LOGIC) Pin numbers shown are for the DB, DGV, PW, and RGY packages. All I/Os are set to inputs at reset. Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

D FF Q D Q FF D Q FF D Q FF Data From Shift Register Data From Shift Register W rite Configuration Pulse W rite Pulse Read Pulse Data From Shift Register W rite Polarity Pulse C K Q C K Q C K Q C K Q Polarity Inversion Register Input Port Register Output Port Register Configuration Register VCC GND Input Port Register Data Polarity Register Data ESD Protection Diode P7−P1 Output Port Register Data I C Interface PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 SIMPLIFIED SCHEMATIC DIAGRAM OF On power up or reset, all registers return to default values. The bidirectional I C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure After the start condition, the device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/ W After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address (A2 A0) inputs of the slave device must not be changed between the start and the stop conditions. On the I C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (start or stop) (see Figure A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

Start Condition Stop Condition SDA SCL Data Line Change Data Output by Transmitter SCL From Master Start Condition S 1 2 8 9 Data Output by Receiver Clock Pulse for Acknowledgment NACK ACK PCA9557 SCPS133I DECEMBER 2005 REVISED JUNE 2008 www.ti.com A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a stop condition. Figure Definition of Start and Stop Conditions Figure Bit Transfer Figure Acknowledgment on the I C Bus Interface Definition BIT BYTE (MSB) (LSB) I C slave address L L H H W Px I/O data bus Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 The address of the PCA9557 is shown in Figure Figure PCA9557 Address Address Reference INPUTS I C BUS SLAVE ADDRESS L L L (decimal), (hexadecimal) L L H (decimal), (hexadecimal) L H L (decimal), (hexadecimal) L H H (decimal), (hexadecimal) H L L (decimal), (hexadecimal) H L H (decimal), (hexadecimal) H H L (decimal), (hexadecimal) H H H (decimal), (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation. Following the successful acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the PCA9557. Two bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be written or read through the I C bus. The command byte is sent only during a write transmission. Once a new command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent. Figure Control Register Bits Command Byte CONTROL REGISTER BITS COMMAND BYTE POWER-UP REGISTER PROTOCOL (HEX) DEFAULT 0x00 Input Port Read byte xxxx xxxx 0x01 Output Port Read/write byte 0000 0000 0x02 Polarity Inversion Read/write byte 1111 0000 0x03 Configuration Read/write byte 1111 1111 Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

www.ti.com The input port register (register reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to signal the I C device that the input port register will be accessed next. Register (Input Port Register) BIT DEFAULT X X X X X X X X The output port register (register shows the outgoing logic levels of the pins defined as outputs by the configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Register (Output Port Register) BIT DEFAULT The polarity inversion register (register allows polarity inversion of pins defined as inputs by the configuration register. If a bit in this register is set (written with 1), the corresponding port pin s polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin s original polarity is retained. Register (Polarity Inversion Register) BIT DEFAULT The configuration register (register configures the directions of the I/O pins. If a bit in this register is set to the corresponding port pin is enabled as an input with high impedance output driver. If a bit in this register is cleared to the corresponding port pin is enabled as an output. Register (Configuration Register) BIT DEFAULT When power (from is applied to V CC an internal power-on reset holds the PCA9557 in a reset condition until V CC has reached V POR At that time, the reset condition is released, and the PCA9557 registers and I C/SMBus state machine initialize to their default states. After that, V CC must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. The RESET input can be asserted to reset the system, while keeping the V CC at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of t W The PCA9557 registers and I C/SMBus state machine are held in their default states until RESET again is high. This input requires a pullup resistor to V CC if no active connection is used. Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

R/W ACK From Slave ACK From Slave ACK From Slave 1 9 8765432 Data 11A20 0S 1 1 A1 A0 0 A 0 000000 A A P tpv Data to PortCommand ByteSlave Address 1/0A20 0S 1 1 A1 A0 0 A 0 000000 A A P SCL SDA Start Condition R/W ACK From Slave ACK From Slave ACK From Slave 1 98765432 Data to RegisterCommand ByteSlave Address Data PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 Data is exchanged between the master and PCA9557 through write and read commands. Data is transmitted to the PCA9557 by sending the device address and setting the least-significant bit (LSB) to a logic (see Figure for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission (see Figure and Figure Figure Write to Output Port Register br/ Figure Write to Configuration or Polarity Inversion Registers Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

Data from RegisterSlave AddressSlave Address R/W ACK From Slave Command Byte S A20 0 1 1 A1 A0 R/W

1 A Data A

At this moment, master-transmitter becomes master-receiver, and slave-receiver becomes slave-transmitter ACK From Slave ACK From Slave ACK From Master NACK From Master First Byte SCL SDA Start Condition R/W Read From Port Data Into Port Stop Condition ACK From Master NACK From Master ACK From Slave Data From PortSlave Address Data From Port 1 9 8765432 A20 0S 1 1 A1 A0 1 A Data 1 Data 4A NA P Data 2 Data 3 Data 4 tph tps Data 5 PCA9557 SCPS133I DECEMBER 2005 REVISED JUNE 2008 www.ti.com The bus master first must send the PCA9557 address with the LSB set to a logic (see Figure for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic Data from the register defined by the command byte then is sent by the PCA9557 (see Figure and Figure After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. Figure Read From Register br/ This figure assumes the command byte has been previously programmed with 00h. Transfer of data can be stopped at any moment by a stop condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure Figure Read Input Port Register Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

(1) RECOMMENDED OPERATING CONDITIONS PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 V V I Input voltage range (2) 0.5 V V O Output voltage range (2) 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O mA I IOK Input/output clamp current V O or V O V CC µ A I OL Continuous output low current V O to V CC mA I OH Continuous output high current V O to V CC mA Continuous current through GND 250 I CC mA Continuous current through V CC 160 D package DB package DGV package 120 θ JA Package thermal impedance (3) C/W PW package 108 RGV package RGY package T stg Storage temperature range 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 2.3 5.5 V SCL, SDA 0.7 V CC 5.5 V IH High-level input voltage V A0, P0, RESET 5.5 SCL, SDA 0.5 0.3 V CC V IL Low-level input voltage V A0, P0, RESET 0.5 0.8 I OH High-level output current mA I OL Low-level output current mA T A Operating free-air temperature C Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

www.ti.com over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT V IK Input diode clamp voltage I I mA 2.3 V to 5.5 V 1.2 V V POR Power-on reset voltage V I V CC or GND, I O V POR 1.65 2.1 V 2.3 V 1.8 V 2.6 I OH mA 4.5 V 4.75 V 4.1 V OH P-port high-level output voltage (2) V 2.3 V 1.5 V 2.5 I OH mA 4.5 V 4.75 V SDA V OL 0.4 V 2.3 V to 5.5 V V OL 0.5 V I OL mA P port (3) V OL 0.55 V 2.3 V to 5.5 V V OL 0.7 V P port, except for (3) V OH 2.3 V 2.3 V to 5.5 V mA I OH V OH 4.6 V 4.6 V to 5.5 V (3) µ A V OH 3.3 V 3.3 V to 5.5 V SCL, SDA I I V I V CC or GND 2.3 V to 5.5 V µ A A0, RESET I IH P port V I V CC 2.3 V to 5.5 V µ A I IL P port V I GND 2.3 V to 5.5 V µ A 5.5 V V I V CC or GND, I O 3.6 V I/O inputs, f SCL 400 kHz 2.7 V Operating mode 5.5 V 1.5 V I V CC or GND, I O I CC 3.6 V µ A I/O inputs, f SCL 100 kHz 2.7 V 0.6 5.5 V 0.25 V I V CC or GND, I O Standby mode 3.6 V 0.25 0.9 I/O inputs, f SCL kHz 2.7 V 0.2 0.8 One input at V CC 0.6 2.3 V to 5.5 V 0.2 Other inputs at V CC or GND Δ I CC Additional current in Standby mode mA Every LED I/O at V I 4.3 5.5 V 0.4 f SCL kHz C I SCL V I V CC or GND 2.3 V to 5.5 V pF SDA 5.5 C io V IO V CC or GND 2.3 V to 5.5 V pF P port 7.5 9.5 (1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V V CC and T A (2) The total current sourced by all I/Os must be limited to mA per bit. (3) Each I/O must be externally limited to a maximum of mA, and the P port (P7 P0) must be limited to a maximum current of 200 mA. Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

I C INTERFACE TIMING REQUIREMENTS RESET TIMING REQUIREMENTS SWITCHING CHARACTERISTICS PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 over recommended operating free-air temperature range (unless otherwise noted) (see Figure STANDARD MODE FAST MODE I C BUS I C BUS UNIT MIN MAX MIN MAX f scl I C clock frequency 100 400 kHz t sch I C clock high time 0.6 µ s t scl I C clock low time 4.7 1.3 µ s t sp I C spike time ns t sds I C serial data setup time 250 100 ns t sdh I C serial data hold time ns t icr I C input rise time 1000 0.1C b (1) 300 ns t icf I C input fall time 300 0.1C b (1) 300 ns t ocf I C output fall time, 10-pF to 400-pF bus 300 0.1C b (1) 300 ns t buf I C bus free time between Stop and Start 4.7 1.3 µ s t sts I C Start or repeated Start condition setup time 4.7 0.6 µ s t sth I C Start or repeated Start condition hold time 0.6 µ s t sps I C Stop condition setup time 0.6 µ s t vd(data) Valid data time, SCL low to SDA output valid 0.9 µ s Valid data time of ACK condition, ACK signal from SCL low to t vd(ack) 0.9 µ s SDA (out) low C b I C bus capacitive load 400 400 pF (1) C b total capacitance of one bus line in pF over recommended operating free-air temperature range (unless otherwise noted) (see Figure STANDARD MODE FAST MODE I C BUS I C BUS UNIT MIN MAX MIN MAX t W Reset pulse duration (1) ns t REC Reset recovery time ns t RESET Time to reset (2) 400 400 ns (1) A pulse duration of ns minimum must be applied to RESET to return the PCA9557 to its default state. (2) The PCA9557 requires a minimum of 400 ns to be reset. over recommended operating free-air temperature range (unless otherwise noted) (see Figure STANDARD MODE FAST MODE I C BUS I C BUS PARAMETER FROM TO UNIT MIN MAX MIN MAX SCL 250 250 t pv Output data valid ns SCL 200 200 t ps Input data setup time P port SCL ns t ph Input data hold time P port SCL 200 200 ns Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

-50 -25 0 25 50 75 100 TA - Free-Air Temperature - °C ICC - Supply Current - µA VCC = 2.5 V VCC = 3.3 V VCC = 5 V fSCL = 400 kHz I/Os unloaded -50 -25 0 25 50 75 100 TA - Free-Air Temperature - °C ICC - Standby Supply Current - nAVCC = 2.5 V VCC = 3.3 V VCC = 5 V SCL = VCC VCC – Supply Voltage – V ICC – Supply Current – µA fSCL = 400 kHz I/Os unloaded VOL – Output Low Voltage – V ISINK – I/O Sink Current – mA TA = –40°C VCC = 2.5 V TA = 25°C TA = 85°C VOL – Output Low Voltage – V ISINK – I/O Sink Current – mA TA = –40°C VCC = 5 V TA = 25°C TA = 85°C VOL – Output Low Voltage – V ISINK – I/O Sink Current – mA TA = –40°C VCC = 3.3 V TA = 25°C TA = 85°C (VCC – V OH) – Output High Voltage – V ISOURCE – I/O Source Current – mA TA = –40°C VCC = 2.5 V TA = 25°C TA = 85°C (VCC – V OH) – Output High Voltage – V ISOURCE – I/O Source Current – mA TA = –40°C VCC = 5 V TA = 25°C TA = 85°C (VCC – V OH) – Output High Voltage – V ISOURCE – I/O Source Current – mA TA = –40°C VCC = 3.3 V TA = 25°C TA = 85°C PCA9557 SCPS133I DECEMBER 2005 REVISED JUNE 2008 www.ti.com SUPPLY CURRENT STANDBY SUPPLY CURRENT SUPPLY CURRENT vs vs vs TEMPERATURE TEMPERATURE SUPPLY VOLTAGE I/O SINK CURRENT I/O SINK CURRENT I/O SINK CURRENT vs vs vs OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE I/O SOURCE CURRENT I/O SOURCE CURRENT I/O SOURCE CURRENT vs vs vs OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE (P7 P1) (P7 P1) (P7 P1) Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

-50 -25 0 25 50 75 100 TA – Free-Air Temperature – °C (V CC – V OH ) – Output High Voltage – mV VCC = 5 V, ISOURCE = 10 VCC = 2.5 V, ISOURCE = 10 VCC = 2.5 V, ISOURCE = 1 mA VCC = 5 V, ISOURCE = 1 mA VCC – Supply Voltage – V VOH – Output High Voltage – VIOH = –10 mA IOH = –8 mA TA = 25°C IOH = –4 mA 100 125 150 175 200 225 250 275 300 -50 -25 0 25 50 75 100 TA – Free-Air Temperature – °C VOL – Output Low Voltage – mV VCC = 5 V, ISINK = 10 mA VCC = 2.5 V, ISINK = 10 mA VCC = 2.5 V, ISINK = 1 mA VCC = 5 V, ISINK = 1 mA PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE vs vs OUTPUT LOW VOLTAGE SUPPLY VOLTAGE TEMPERATURE vs (P7 P1) (P7 P1) TEMPERATURE Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

R L = 1 kW VCC C L = 50 pF (see Note A) tbuf ticr tsth tsds tsdh ticf ticr tscl tsch tststPHL tPLH 0.3 × VCC Stop Condition tsps Repeat Start ConditionStart or Repeat Start Condition SCL SDA Start Condition (S) Address Bit 7 (MSB) Data Bit 10 (LSB) Stop Condition (P) Three Bytes for Complete Device Programming SDA LOAD CONFIGURA TION VOLT AGE W AVEFORMS ticf Stop Condition (P) tsp DUT SDA 0.7 × VCC 0.3 × VCC 0.7 × VCC R/W Bit 0 (LSB) ACK (A) Data Bit 07 (MSB) Address Bit 1 Address Bit 6 BYTE DESCRIPTION

1 I 2C address

2, 3 P-port data PCA9557 SCPS133I DECEMBER 2005 REVISED JUNE 2008 www.ti.com C L includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. All parameters and waveforms are not applicable to all devices. Figure 10. I C Interface Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

A A A A S 0 0 1 1 A1 A2 A0 1 Data 1 1 PData 2 Start Condition 8 Bits (One Data Bytes) From Port Data From PortSlave Address R/W 87654321 tir tir tsps tiv Address Data 1 Data 2 INT Data Into Port B B A A Pn INT R/W A tir 0.7 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.3 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.7 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.3 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.7 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.3 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.7 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.3 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC INT SCL View B−BView A−A tiv R L = 4.7 kW VCC C L = 100 pF (see Note A) INTERRUPT LOAD CONFIGURA TION DUT INT ACK From Slave ACK From Slave 1.5 V PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) C L includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. All parameters and waveforms are not applicable to all devices. Figure 11. Interrupt Load Circuit and Voltage Waveforms Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

0.7 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.3 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC SCL P7 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ tpv (see Note B) Slave ACK Unstable Data Last Stable Bit SDA Pn Pn WRITE MODE (R/W = 0) P0 A 0.7 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.3 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC SCL P7 0.7 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 0.3 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC tps tph READ MODE (R/W = 1) P-PORT LOAD CONFIGURA TION DUT C L = 50 pF (see Note A) Pn 2 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 500 /C0087 500 /C0087 1.5 V PCA9557 SCPS133I DECEMBER 2005 REVISED JUNE 2008 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) C L includes probe and jig capacitance. t pv is measured from 0.7 V CC on SCL to 50% I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. Figure 12. P-Port Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

0.3 /C0121 VCC VCC /2 tRESET Pn R L = 1 kW VCC C L = 50 pF (see Note A) SDA LOAD CONFIGURA TION DUT SDA P-PORT LOAD CONFIGURA TION VCC /2 tRESET DUT C L = 50 pF (see Note A) Pn 2 ×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrVCC 500 /C0087 500 /C0087 PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 PARAMETER MEASUREMENT INFORMATION (continued) C L includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. Figure 13. Reset Load Circuits and Voltage Waveforms Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

(5 V) SCL SDA GND SCL SDA PCA9557 GND INT ALARM Controlled Switch (e.g., CBT Device) ENABLE 1.8 kΩ 1.8 kΩ 620 Ω A B 2 kΩ 10 kΩ 100 k ( 5)XΩ RESET VCC VCC VCC GND RESET RESET Subsystem 1 2 kΩ Subsystem 2 (e.g., Counter) Subsystem 3 (e.g., Alarm System) Master Controller PCA9557 SCPS133I DECEMBER 2005 REVISED JUNE 2008 www.ti.com Figure shows an application in which the PCA9557 can be used. Device address is configured as 0011100 for this example. P1, P4, and are configured as inputs. P0, P2, and are configured as outputs. and are not used and must be configured as outputs. Figure 14. Typical Application Submit Documentation Feedback Copyright 2005 2008, Texas Instruments Incorporated Product Folder Link(s): PCA9557

I CC When I/O Is Used to Control LED LED 100 k/C0087 VCC VCC Pn 3.3 V LED 5 V VCC Pn PCA9557 www.ti.com SCPS133I DECEMBER 2005 REVISED JUNE 2008 When an I/O is used to control an LED, normally it is connected to V CC through a resistor as shown in Figure The LED acts as a diode so, when the LED is off, the I/O V IN is about 1.2 V less than V CC The Δ I CC parameter in Electrical Characteristics shows how I CC increases as V IN becomes lower than V CC Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V CC when the LED is off. Figure shows a high-value resistor in parallel with the LED. Figure shows V CC less than the LED supply voltage by at least 1.2 Both of these methods maintain the I/O V IN at or above V CC and prevent additional supply-current consumption when the LED is off. Figure 15. High-Value Resistor in Parallel With the LED Figure 16. Device Supplied by a Low Voltage Copyright 2005 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCA9557

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PCA9557D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DB ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DBG4 ACTIVE SSOP DB 16 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DGVRG4G4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557DTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9557RGVR ACTIVE QFN RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PCA9557RGVRG4 ACTIVE QFN RGV 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PCA9557RGYR ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR PCA9557RGYRG4 ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. PACKAGE OPTION ADDENDUM www.ti.com 4-Jan-2008 Addendum-Page 1

OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 4-Jan-2008 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCA9557DBR SSOP DB 16 2000 346.0 346.0 33.0 PCA9557DGVR TVSOP DGV 16 2000 346.0 346.0 29.0 PCA9557DR SOIC D 16 2500 346.0 346.0 33.0 PCA9557PWR TSSOP PW 16 2000 346.0 346.0 29.0 PCA9557RGVR QFN RGV 16 2500 346.0 346.0 29.0 PCA9557RGYR QFN RGY 16 1000 190.5 212.7 31.8 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony RF/IF and ZigBee Solutions www.ti.com/lprf Video Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated

Summary

REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS

Description