PD168807

PD168807_15 RENESAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 32

Technical content

Features

• Uses a synchronous rectification type step-down circuit (ch1, ch2)
• Uses a synchronous rectification type step-up/down circuit (ch3)
• Uses a switching circuit to switch between step-down (using synchronous rectification) and inverting (using asynchronous rectification) (ch4)
• Incorporates a power MOSFET (ch1 to ch3)
• Incorporates a phase compensator (ch1 to ch4)
• Operating frequency: 300 kHz to 1500 kHz
• Can use an external clock (to improve the oscillating frequency accuracy)
• Incorporates a timer-latch-type short-circuit protector
• Incorporates a timer-latch-type overheat protector (shutdown temperature: 150ºC or higher)
• Incorporates a recovery-type undervoltage lockout circuit
• Housed in a 48-pin VQFN package

Ordering Information

Part No. Package Packing style μ PD168807K9-4EG-E1-A 48-pin plastic VQFN Embossed taping R03DS0001EJ0200 Rev.2.00 Mar 18, 2011

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 2 of 30 Mar 18, 2011 1. Block Diagram SCP VREG AGND SHDNB1 SHDNB2 SHDNB3 CT RT AVDD TSD ON/OFF Controller Circuit SHDNB4 II4 E/A4 VPIN1 E/A2 II2 0.8V II3 E/A3 II1 0.8V E/A1 Phase Compensator LOUT1 PGND1 Current Mode Current-limit Controller CTL SS1 SS3 SS4 LOUT21 PGND21 VPIN22 LOUTA31 PGNDA31 VPIN31 CLK Undervoltage Lockout Circuit VREF Soft Start Circuit RSTB VPIN21 PGND22 LOUT22 LOUTB31 PGNDB31 DOUT32 OUTA4 OUTB4 PVDD PGND4 PGNDB32 LOUTB32 DOUT31 PGNDA32 LOUTA32 VPIN32 CSL Internal Power Supply VREG SS2 VREF SCP UVLO CLK ++- OSC Oscillator Short-circuit protection circuit Overheat Protection Circuit Reference Voltage Current Mode Current-limit Controller Current Mode Current-limit Controller Current Mode Current-limit Switching Controller to Switch between Step-down and Inverting Phase Compensator Phase Compensator Phase CompensatorThreshold Voltage Switching Circuit

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 3 of 30 Mar 18, 2011 2. Pin Configuration (Top View) SS1 VREF CT SS4 1 2 3 4 5 6 7 8 9 10 11 12 34 35 36 31 3233 282930 25 2627 OUTA4 PVDD LOUT1 PGND1 PGND21 VPIN21 DOUT32 DOUT31 LOUTB31 LOUTB32 PGNDB32 VPIN31 PGNDB31 PGNDA32 PGNDA31 LOUTA32 LOUTA31 VPIN32 II1 II2 II4 AGND RSTB CLK CTL SHDNB4 SHDNB3 SHDNB1 OUTB4 PGND4 AVDD VREG SS2 SS3 SCP RT II3 SHDNB2 CSL VPIN1 PGND22 LOUT21 LOUT22 VPIN22

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 4 of 30 Mar 18, 2011 3. Pin Function Pin No. Symbol I/O Function

1 II1 Input Inverted input for error amplifier of ch1

2 II2 Input Inverted input for error amplifier of ch2

3 II3 Input Inverted input for error amplifier of ch3

4 II4 Input Inverted input for error amplifier of ch4

5 AGND Ground Analog ground

6 RSTB Output Short-circuit detec tion signal pin (open-drain output)

7 CLK Input Clock signal Input

8 CTL Input Step-down circuit / inverti ng circuit operation setting mode of ch4

9 SHDNB4 Input Output ON/OFF of ch4

10 SHDNB3 Input Output ON/OFF of ch3

11 SHDNB2 Input Output ON/OFF of ch2

12 SHDNB1 Input Output ON/OFF of ch1

13 VPIN31 Power Supply Output stage power input 1 of ch3

14 VPIN32 Power Supply Output stage power input 2 of ch3

15 LOUTA31 Output Inductor connection 1 for ch3A

16 LOUTA32 Output Inductor connection 2 for ch3A

17 PGNDA31 Ground Power ground

18 PGNDA32 Ground Power ground

19 PGNDB31 Ground Power ground

20 PGNDB32 Ground Power ground

21 LOUTB31 Output Inductor connection 1 for ch3B

22 LOUTB32 Output Inductor connection 2 for ch3B

23 DOUT31 Output Ou tput 1 of ch3

24 DOUT32 Output Ou tput 2 of ch3

25 RT − Resistance connection for triangular wave generation

26 CT − Capacitor connection for triangular wave generation

27 SCP − Capacitor connection pin for timer latch

28 VREF Output Reference voltage output

29 SS4 − Capacitor connection for soft start of ch4

30 SS3 − Capacitor connection for soft start of ch3

31 SS2 − Capacitor connection for soft start of ch2

32 SS1 − Capacitor connection for soft start of ch1

33 VREG Output Inter nal power supply output

34 AVDD Power Supply Analog block power supply

35 PGND4 Ground Power ground

36 OUTB4 Output Output of ch4B

37 OUTA4 Output Output of ch4A

38 CSL Input Load current detecti on of ch4 (Low-voltage side)

39 PVDD Power Supply

Power supply for output buffer stage, load current detection of ch4 (high-voltage side)

40 VPIN1 Power Supply Output stage power input of ch1

41 LOUT1 Output Inductor connection for ch1

42 PGND1 Ground Power ground

43 PGND21 Ground Power ground

44 PGND22 Ground Power ground

45 LOUT21 Output Inductor connection 1 for ch2

46 LOUT22 Output Inductor connection 2 for ch2

47 VPIN21 Power Supply Output stage power input 1 of ch2

48 VPIN22 Power Supply Output stage power input 2 of ch2

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 5 of 30 Mar 18, 2011 4. Electrical Specifications Absolute Maximum Ratings (Unless otherwise specified, TA = 25°C, glass epoxy four layer substrate, 100 mm x 100 mm x 1.0 mmt, Copper film: 50%) Parameter Symbol Condition Parameter Unit Analog power supply voltage (AVDD pin) AV DD −0.5 to +15 V Buffer stage power supply voltage (PVDD pin) PV DD −0.5 to +15 V CSL pin applied voltage V CSL CSL −0.5 to +15 V VPIN pin applied voltage V PIN VPIN1 to VPIN32 −0.5 to +15 V II pin applied voltage V II II1 to II4 −0.5 to +4.0 V SHDNB pin applied voltage V SHDNB SHDNB1 to SHDNB4 −0.5 to +15 V CTL pin applied voltage V CTL CTL −0.5 to +15 V CLK pin applied voltage V CLK CLK −0.5 to +15 V RSTB pin applied voltage V RSTB RSTB −0.5 to +15 V VPIN1 pin sink current (DC) I PIN1(DC)− 1200 mA VPIN1 pin sink current (pulse) I PIN1(pulse)− 1600 mA VPIN21 + VPIN22 pin sink current (DC) I PIN2(DC)− VPIN21 + VPIN22 1500 mA VPIN21 + VPIN22 sink current (pulse) I PIN2(pulse)− VPIN21 + VPIN22 1900 mA VPIN31 + VPIN32 pin sink current (DC) I PIN3(DC)− VPIN31 + VPIN32 1200 mA VPIN31 + VPIN32 sink current (pulse) I PIN3 (pulse)− VPIN31 + VPIN32 1600 mA LOUT1 output source current (DC) I LO1(DC)+ 1200 mA LOUT1 output source current (pulse) I LO1(pulse)+ 1600 mA LOUT21 + LOUT22 output source current (DC) I LO2(DC)+ LOUT21 + LOUT22 1500 mA LOUT21 + LOUT22 output source current (pulse) ILO2(pulse)+ LOUT21 + LOUT22 1900 mA LOUTA31 + LOUTA32, DOUT31 + DOUT32 output source current (DC) ILOA3, DO3(DC)+ LOUTA31 + LOUTA32 DOUT31 + DOUT32 1200 mA LOUTA31 + LOUTA32, DOUT31 + DOUT32 output source current (pulse) ILOA3, DO3 (pulse)+ LOUTA31 + LOUTA32 DOUT31 + DOUT32 1600 mA LOUTB31 + LOUTB32 output sink current (DC) ILOB3(DC)− LOUTB31 + LOUTB32 1200 mA LOUTB31 + LOUTB32 output sink current (pulse) ILOB3(pulse)− LOUTB31 + LOUTB32 1600 mA OUTA4, OUTB4 output source current (DC) I OA4, B4(DC)+ 30 mA OUTA4, OUTB4 output source current (pulse) I OA4, B4(pulse)+ 400 mA OUTA4, OUTB4 output sink current (DC) I OA4, B4(DC)− 30 mA OUTA4, OUTB4 output sink current (pulse) I OA4, B4(pulse)− 400 mA Total power dissipation P T T A ≤ +25°C 1700 ∗1 mW Operating ambient temperature T A −20 to +85 °C Operating junction temperature T J −20 to +150 °C Storage temperature T stg −55 to +150 °C Note: ∗1. This is the value at TA ≤ +25°C. Where TA > +25°C, perform derating at −13.6 mW/°C. Caution: Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 6 of 30 Mar 18, 2011 Recommended Operating Conditions (Unless otherwise specified, TA = 25°C, glass epoxy four layer substrate, 100 mm x 100 mm x 1.0 mmt, Copper film: 50%) Parameter Symbol Condition MIN. TYP. MAX. Unit Analog power supply voltage (AVDD pin) AVDD 4.0 7.4 14.5 V Buffer stage power supply voltage (PVDD pin) PVDD AV DD V CSL pin applied voltage V CSL CSL AV DD V VPIN pin applied voltage V PIN VPIN1 to VPIN32 4.0 7.4 14.5 V II pin applied voltage V II II1 to II4 0 V REG V SHDNB pin applied voltage V SHDNB SHDNB1 to SHDNB4 0 AV DD V CTL pin applied voltage V CTL CTL 0 AV DD V CLK pin applied voltage V CLK CLK 0 AV DD V RSTB pin applied voltage V RSTB RSTB 0 AV DD V CLK input frequency f CLK CLK 300 750 1500 kHz Oscillation frequency f OSC 300 750 1500 kHz Oscillator timing resistance R T RT 1.2 k Ω Oscillator timing capacitance C T CT 220 pF Soft start capacitance C SS SS1 to SS4 0.01 μ F SCP pin capacitor capacitance C SCP SCP 0.1 μ F VREF pin capacitor capacitance C REF V REF 0.1 μ F VREG pin capacitor capacitance C REG V REG 1.0 μ F

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 7 of 30 Mar 18, 2011 Electrical Specifications (Unless otherwise specified, TA = 25°C, AVDD = PVDD = VPIN1 to 32 = DOUT31 to 32 = 7.4 V, fOSC = 750 kHz) Total Parameter Symbol Condition MIN. TYP. MAX. Unit Standby current I DD(SHDN) AIDD+PIDD+IPIN1+IPIN21+IPIN22+IPIN31+IPIN32 SHDNB1 to SHDNB4 = AGND 1 3 μA Circuit operation current 1 AI DD AI DD, CTL= AVDD (at ch4 inverting) ch1 to ch4 = ”ON”, II1 = II2 = II3 = VREG II4 = AGND 4 8 mA Circuit operation current 2 PI DD PI DD, CTL = AVDD (at ch4 inverting) ch1 to ch4 = ”ON”, II1 = II2 = II3 = II4 = VREG, no load 4 8 mA Reference voltage block Parameter Symbol Condition MIN. TYP. MAX. Unit Reference voltage V REF I REF = 0 mA 1.98 2.00 2.02 V Input regulation VREF(REGIN) AVDD = PVDD = 4.0 V to 14.5 V 10 20 mV Load regulation V REF(REGL) I REF = 0 to 1.0 mA 20 40 mV Temperature characteristic 0.5 % Internal power supply block Parameter Symbol Condition MIN. TYP. MAX. Unit Internal power supply voltage VREG I REG = 0 mA 3.0 3.3 3.6 V Low-voltage malfunctioning prevention circuit Parameter Symbol Condition MIN. TYP. MAX. Unit Operation start voltage during rise time AVDD(L-H) AVDD pin voltage det ected 2.50 3.15 3.80 V Operation stop voltage AV DD(H-L) AVDD pin voltage det ected 2.30 2.95 3.60 V Short-circuit protection circuit Parameter Symbol Condition MIN. TYP. MAX. Unit II1 input detection voltage (ch1) VTH(II)1 II1 pin 0.5 0.6 0.7 V II2 input detection voltage (ch2) VTH(II)2 II2 pin 0.5 0.6 0.7 V II3 input detection voltage (ch3) VTH(II)3 II3 pin 0.7 0.8 0.9 V II4 input detection voltage 1 (ch4 step-down) VTH(II)41 II4 pin, when step-down 0.5 0.6 0.7 V II4 input detection voltage 2 (ch4 inverting) VTH(II)42 II4 pin, when inverting 0.5 0.6 0.7 V DLY detection voltage V TH(DLY) SCP pin 0.6 0.9 1.2 V Short-circuit source current I OUT 0.60 0.85 1.20 μA RSTB pin output voltage V RSTB I RSTB− = 0.1 mA 0.1 V RSTB pin leakage voltage I LEAK-RSTB SHDNB1 to SHDNB4 = AGND 1 μA Oscillation block Parameter Symbol Condition MIN. TYP. MAX. Unit Low-level threshold voltage V TH(L) 0.3 0.4 0.5 V High-level threshold voltage V TH(H) 0.7 0.8 0.9 V Frequency setting accuracy f OSC C T = 220 pF, RT = 1.2 kΩ −10 +10 % Input stability ΔfOSC AV DD = PVDD = 4.0 V to 14.5 V −3 +3 %

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 8 of 30 Mar 18, 2011 Electrical Specifications (Unless otherwise specified, TA = 25°C, AVDD = PVDD = VPIN1 to 32 = DOUT31 to 32 = 7.4 V, fOSC = 750 kHz) Soft start block Parameter Symbol Condition MIN. TYP. MAX. Unit Charging current I SS1 SS1 to SS4 = 0 V, ch4 (when step- down) 2.8 4.0 5.6 μA Discharging current I SS2 SS4 = 2 V, ch4 (when inverting) 2.8 4.0 5.6 μA PWM block Parameter Symbol Condition MIN. TYP. MAX. Unit Maximum duty 1 DMAX.1 ch1, ch2, ch3 step-down, ch4 step- down 100 % Maximum duty 2 D MAX.2 ch3 step-up, ch4 inverting 85 % E/A block (ch1 to ch7) Parameter Symbol Condition MIN. TYP. MAX. Unit E/A 1 input threshold voltage VITH1 Including input offset 0.78 0.80 0.82 V E/A 2 input threshold voltage VITH2 Including input offset 0.78 0.80 0.82 V E/A 3 input threshold voltage VITH3 Including input offset 0.98 1.00 1.02 V E/A 4 input threshold voltage 1 VITH4-1 Including input offset, when step- down 0.78 0.80 0.82 V E/A 4 input threshold voltage 2 VITH4-2 Including input offset, when inverting 0.38 0.40 0.42 V Output block (ch1) Parameter Symbol Condition MIN. TYP. MAX. Unit P-ch output ON resistance R on-p1 I O = 100 mA 0.40 0.60 Ω N-ch output ON resistance R on-n1 I O = −100 mA 0.30 0.50 Ω Output block (ch2) Parameter Symbol Condition MIN. TYP. MAX. Unit P-ch output ON resistance R on-p2 I O = 100 mA 0.35 0.55 Ω N-ch output ON resistance R on-n2 I O = −100 mA 0.25 0.40 Ω Output block (ch3) Parameter Symbol Condition MIN. TYP. MAX. Unit P-ch output ON resistance R on-p3 I O = 100 mA 0.25 0.40 Ω N-ch output ON resistance R on-n3 I O = −100 mA 0.25 0.40 Ω Output block (ch4) Parameter Symbol Condition MIN. TYP. MAX. Unit P-ch output ON resistance R on-p4 I O = 20 mA 30 60 Ω N-ch output ON resistance R on-n4 I O = −20 mA 10 20 Ω ON/OFF controller block Parameter Symbol Condition MIN. TYP. MAX. Unit Threshold voltage VTH(SHDNB) SHDNB1 to SHDNB4, CTL, CLK 0.8 2.0 V Input pull-down resistance R IND SHDNB1 to SHDNB4, CLK 200 400 700 k Ω

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 9 of 30 Mar 18, 2011 5. Output Control Block

• CTL: ch4 Operation setting mode Signal ch4 step-down circuit / in verting circuit operation setting L Step-down H Inverting Remark L: Low level, H: High level Caution Fix the CTL pin during at circuit operation. The pull-down resistor is not connected with the CTL pin. Be sure to externally fix the pin to L or H.  SHDNB1 to SHDNB4: ON/OFF Setting Mode SHDNB1 SHDNB2 SHDNB3 SHDNB4 Common Circuit ch1 ch2 ch3 ch4 L L L L OFF OFF OFF OFF OFF H L L L ON ON OFF OFF OFF L H L L ON OFF ON OFF OFF L L H L ON OFF OFF ON OFF L L L H ON OFF OFF OFF ON H H H H ON ON ON ON ON Remark L: Low level, H: High level Common Circuit: Reference voltage block, internal power supply block, oscillator block and so forth OFF: circuit stand-by, ON: circuit operation status  ch1 to ch4 output mode ch4 ch1 ch2 ch3 (Step-down CTL = L) (Inverting CTL = H) SHDNB1 to SHDNB4 VREG VREF LOUT1 LOUT21 LOUT22 LOUTA31 LOUTA32 LOUTB31 LOUTB32 DOUT31 DOUT32 OUTA4 OUTB4 OUTA4 OUTB4 L AGND AGND HiZ PVDD PGND PVDD PGND H V REG V REF VPIN1 or PGND VPIN21,22 or PGND VPIN31,32 or PGND VOUT3 or PGND VOUT3 PVDD or PGND PVDD or PGND PVDD or PGND PGND Remark L: Low level, H: High level, HiZ: High impedance V OUT3: ch3 output voltage  RSTB: Circuit Protection operation identification mode IC Operation Status RSTB Output Status Stand-by and normal operation HiZ Short-circuit protection operation and overheat protection operation (All channel are latched to OFF.) L Remark L: Low level, HiZ: High impedance

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 10 of 30 Mar 18, 2011 6. Timing Chart VREF AVDD CT SHDNB1 ch1 OUT SHDNB2 ch2 OUT SHDNB3 ch3 OUT SHDNB4 Input Output VREG 2.0V 3.3V ch4 OUT (Step-down CT = 1) ch4 OUT (Inverting CTL = H)

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 11 of 30 Mar 18, 2011 7. Operation of Each Block (Overview) Reference Voltage Block The reference voltage block outputs a reference voltage (2.0 V TYP) that has been temperature-compensated by the voltage supplied from the internal power supply block (3.3 V TYP). This reference voltage is used as the reference voltage for all the internal circuits and a current of up to 1 mA can be output to an external circuit from the VREF pin (pin 28). Internal power supply block The internal power supply block generates 3.3 V (TYP.) from analog power supply through AVDD pin (34 pin). This block provides internal circuits with electric sources; however, not supposed to be used externally. Oscillator block The oscillator block spontaneously oscillates when a timing capacitance and a timing resistance are respectively connected to the CT pin (pin 26) and RT pin (pin 25), and outputs a symmetrical triangular wave with an amplitude of 0.4 to 0.8 V (TYP.) to the CT pin. E/A block (error amplifier) The circuit configuration of all error amplifiers E/A1, E/A2, E/A3 and E/A4 is identical. All E/As have an internal phase compensator. Pin II inputs an inverted signal to the E/A block. The input threshold voltages of the E/A block are (CTL = H, when inverting). Output control block The output control block controls the output ON duty by using the E/A output signal and the signal output from the current detection amplifier. The maximum duty is 100% (TYP) when ch1 and ch2 operate, and ch3 (step-down) and ch4 (step-down, CTL = L) operate, and 85% (TYP) when ch3 (step-up) operates and ch4 operates as the inverting circuit (CTL = H). Output circuit block The output circuit block of ch1 to ch3 includes a power MOSFET. The output current capacity of ch1 is 1.6 A (MAX) when a switching pulse is output and 1.2 A (MAX) when DC is output. The output current capacity of ch2 is 1.9 A (MAX) when a switching pulse is output and 1.5 A (MAX) when DC is output. The output current capacity of ch3 is 1.6 A (MAX) when a switching pulse is output and 1.2 A (MAX) when DC is output. The output circuit block of ch4 has a push-pull configuration and can directly drive the power MOSFET. The output current capacity of ch4 is 400 mA (MAX) when a pulse is output and 30 mA (MAX) when DC is output. ON/OFF control block This circuit can turn on/off the output voltage of each channel by using the SHDNB1 pin to SHDNB4 pin and an external signal. When the SHDNB1 to SHDNB4 pins are made low, a shut-down circuit operates, shutting down the output of each channel. When the SHDNB1 to SHDNB4 pins are made high, the shut-down circuit stops, ch1 to ch4 are soft-started and their output voltage rises.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 12 of 30 Mar 18, 2011 Soft start circuit block (1) Soft start operation when ch1 to ch3 start and ch4 (step-down, CTL = L) start A soft start is triggered by charging the capacitors connected to the SS1 to SS4 pins and slowly increasing the E/A threshold voltage level. When a soft start is triggered, the SS pin voltage is connected to the E/A non-inverted input and the E/A non-inverted input voltage rises from 0 V. The output ON duty then slowly increases, executing the soft start. Timing chart (when ch1 to ch3 start and ch4 (step-down, CTL = L) start SHDNB1 to SHDNB4 (1) (2) (3) 1.2 V VREG (3.3V) VITH (4) VREG (3.3 V) VITH 1.2V SS1 to SS4 ch1 to ch4 OUT VITH: E/A Input threshold voltage <1> Soft start triggered

• When the level of the SHDNB pin for each channel is changed from low to high, the external soft start capacitors for each channel (connected to the SS pins) start charging and voltage output begins.
• Charge current for external soft start capacitors = 4 μA (TYP) <2> End of soft start
• When the voltage of each channel's SS pin reaches the E/A input threshold voltage level, the soft start of each channel ends.
• Even after the soft start ends, the SS pin voltage continues to rise until it reaches at least 1.2 V, at which point the SS pin voltage is pulled up to VREG (3.3 V). <3> Stopping output
• When the level of the SHDNB pin for each channel is changed from high to low, output from each channel stops and the external soft start capacitors discharge. <4> Resuming output
• After output has been stopped (after the SHDNB pin level has been changed from high to low), it takes at least 100 μs before output can be restarted. Caution: This IC does not include an output capacitor discharge circuit. Therefore, be careful about the output capacitor discharge time.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 13 of 30 Mar 18, 2011 (2) Soft start operation when ch4 is operating as the inverting circuit (CTL = H) A soft start of the inverting circuit is triggered by discharging the capacitor connected to the SS4 pin and slowly decreasing the E/A4 threshold voltage level. The capacitor connected to the SS4 pin charges rapidly by means of the reference voltage VREF (2 V) when the level of any of the SHDNB1 to 4 pins is changed from low to high while ch4 is not operating. When a soft start is triggered, the SS4 pin voltage is connected to the E/A4 non-inverted input and the E/A4 non-inverted input voltage falls from 2 V. The output ON duty then slowly increases, executing the soft start. Timing chart (when ch4 is operating as the inverting circuit (CTL = H)) SHDNB4 ch4 OUT (1) (2) (4) SS4 VREF (2.0 V) VITH4-2 (0.4 V) (5) VREF(2.0V) VREF (2.0 V) VITH4-2 (0.4 V) VREF (2.0 V) (6) (3) SHDNB1 to SHDNB3 VITH4-2: E/A4 input threshold voltage (when inverting) <1> Soft start triggered

• When the level of any of the SHDNB1 to 4 pins is changed from low to high while the circuit is on standby (all channels are stopped), the external soft start capacitor (connected to the SS4 pin) starts charging.
• After the external soft start capacitor is finished charging, if the level of the SHDNB4 pin is high, the external soft start capacitor starts discharging and ch4 output starts.
• Discharge current for external soft start capacitors = 4 μA (TYP)
• After the level of the SHDNB4 pin has changed from low to high while the circuit is on standby (all channels are stopped), the time between the start of charging and the start of discharging depends on the circuit conditions (but is no more than 100 μs). <2> End of soft start
• When the voltage of the SS4 pin falls to the E/A4 input threshold voltage level (0.4 V TYP), ch4 ends the startup.
• Once the voltage of the SS4 pin reaches 0.4 V, the SS4 pin voltage is pulled down to ground level. <3> While ch4 is operating
• Even if the level of any of the SHDNB1 to 3 pins is changed from low to high, if ch4 is operating, the soft start capacitor connected to the SS4 pin is not charged and the SS4 pin voltage remains at the GND level. <4> Stopping output
• When the level of the SHDNB4 pin is changed from high to low, ch4 output stops.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 14 of 30 Mar 18, 2011 <5> Resuming output

• After the SHDNB4 pin level has been changed from high to low, it takes at least 100 μs (provisional value) before output can be restarted. <6> When ch4 operation is stopped
• If the level of any of the SHDNB1 to 3 pins is high while ch4 is stopped (by changing the level of the SHDNB4 pin from high to low), the external soft start capacitor starts charging.
• Once the capacitor has finished charging and all the SHDNB pins are low level, the external soft start capacitor will discharge. Caution: This IC does not include an output capacitor discharge circuit. Therefore, be careful about the output capacitor discharge time. External clock The IC can be run on a clock frequency by inputting a clock pulse to the CLK pin (pin 7). The accuracy of the oscillating frequency at this time will depend on the accuracy of the clock frequency.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 15 of 30 Mar 18, 2011 Short-circuit protection circuit (Timer latch type) When the voltage of ch1 to ch3 and ch4 operating as a step-down circuit (CTL = L) drops (or when the voltage of ch4 rises if ch4 is operating as inverting circuit), the voltage of the E/A inverted input pin to which the output is being fed back also drops (or rises in the case of ch4 if ch4 is operating as inverting circuit). If this inverted input pin voltage falls below the input detection voltage of the short-circuit protection circuit (E/A1 = VTH1 = 0.6 V, E/A2 = VTH2 = 0.6 V, E/A3 = VTH3 = 0.8 V, E/A4 = VTH4 = 0.6 V) (or rises above the input detection voltage (E/A4 = VTH4 = 0.6 V) if ch4 is operating as inverting circuit), the timer circuit starts operating and the capacitor connected to the SCP pin (pin 27) (CSCP) starts charging. When the voltage of the capacitor connected to the SCP pin reaches 0.9 V (TYP), all the outputs of the IC are latched to OFF. At this time, the level of the RSTB pin (pin 6) is GND. As long as the voltage of any of the E/A inverted input pins of ch1 to ch4 is below the input detection voltage of the short-circuit protection circuit (or is above the input detection voltage if ch4 is operating as inverting circuit), the capacitor connected to the SCP pin continues charging. When the short-circuit protection circuit is operating, to reset the latch circuit, either drop the level of the power supply voltage (AV DD) to GND or change the level of all the SHDNB1 to SHDNB4 pins from high to low. After the latch status is reset, it takes at least 100 μs before output can be restarted. Timing chart (when ch1 is short circuited) 0.9 V SCP RSTB SHDNB1 ch1 OUT HiZ HiZ (1) (3) II1 VTH(II)1=0.6 V V ITH1 =0.8 V (3.3 V) (4) (2) VREG SHDNB2 to SHDNB4 VITH1: E/A1 input threshold voltage VTH(II): Short-curcuit protection circuit II1 input detection voltage <1> Soft start triggered

• The soft start operation is asynchronous to the short-circuit protection operation. <2> Short-circuit protection operation
• After a short circuit has been detected (when the SCP pin voltage rises to 0.9 V), output from all channels stops (the outputs are latched to OFF). Common circuits (such as the reference voltage block, internal power supply block, and oscillator) continue operating.
• The short detection pin (RSTB) operates when the short-circuit protection circuit operates. During normal operation: high impedance; when the short-circuit protection circuit is operating: low level <3> Cancelling short-circuit protection
• The latch status is reset when the level of all the SHDNB pins is changed from high to low.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 16 of 30 Mar 18, 2011 <4> Resuming output

• After the latch status is reset, it takes at least 100 μs before output can be restarted. Overheat protection circuit (timer latch type) After overheating has been detected (shutdown temperature: 150ºC or higher), output from all channels stops (the outputs are latched to OFF). Common circuits (such as the reference voltage block, internal power supply block, and oscillator) continue operating. When the overheat protection circuit is operating, to reset the latch circuit, either drop the level of the power supply voltage (AV DD) to GND or change the level of all the SHDNB1 to SHDNB4 pins from high to low. After the latch status is reset, it takes at least 100 us before output can be restarted. Undervoltage lockout circuit (auto recovery type) If an undervoltage is detected (if the power supply voltage (AVDD) is too low), output from all channels and common circuits (such as the reference voltage block, internal power supply block, and oscillator) stop and the IC is put on standby. Once the AV DD voltage is recovered, output automatically resumes. While the undervoltage lockout circuit is operating, the output voltage will not recover even if the SHDNB pins are manipulated (the IC remains on standby). Current limiting If an overcurrent occurs, the current is limited on a pulse-by-pulse basis. If the current sensor detects an overcurrent, the current is limited and the switching operation of the PoMOS in the output stage stops until the next cycle. When the current is limited, the output voltage of the channel on which the overcurrent occurred drops. If the II pin voltage falls below the II input detection voltage (or rises above the II input detection voltage in the case of ch4 if ch4 is operating as inverting circuit), the short-circuit protection circuit starts operating.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 17 of 30 Mar 18, 2011 8. Advance on Designing Setting Output Voltage The output voltage settings are shown in the figures below. The output voltage can be calculated by using the equations shown in these figures. The input threshold voltage of the error amplifier is 0.8 V (TYP) for E/A1, E/A2, and E/A4 when ch4 is operating as a step-down circuit, and 1.0 V (TYP) for E/A3 and 0.4 V (TYP) for E/A4 when ch4 is operating as inverting circuit. 0.8 V (TYP.) VOUT (Output voltage VOUT = (1+R1/R2)˜0.8 E/A1㧘E/A2㧘E/A4 (Operating as a step-down circuit) 1.0 V (TYP.) 0.4 V (TYP.) VOUT (Output voltage Setting output voltage of ch3 VOUT = (1+R1/R2)˜1.0 E/A3 VOUT (Output voltage) VOUT = VREF − (VREF - 0.4) ˜(1+R2/R1) VREF (Reference voltage 2.0 V) + R2 E/A4 (Operating as inverting circuit) Setting output voltage of ch1, ch2, and ch4 (operating as a step-down circuit) Setting output voltage of ch4 (operating as inverting circuit)

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 18 of 30 Mar 18, 2011 Setting Oscillation Frequency The oscillation frequency can be arbitrarily set by the timing resistance connected to the RT pin and timing capacitance connected to the CT pin. An approximate expression of the oscillation frequency (fOSC) is shown below. However, because this expression is for approximation, mount the IC on the actual system and check the values of the parameters especially when the IC is used at a high frequency. f OSC = 0.175/(CT x RT) [Hz] (Conditions: AVDD = 7.4 V, TA = 25°C) Example CT = 220 pF, RT = 1.2 kΩ fOSC = 0.175/(220 x 10-12 x 1200) ≅ 663 kHz The following graph shows f OSC vs. RT characteristics with CT as a parameter. 200 400 600 800 1000 1200 1400 1600 1800 2000 0 500 1000 1500 2000 2500 3000 RT ( ) f OSC (kHz ) 110 pF 220 pF 470 p F Ω Calculating the soft start time An approximate equation for calculating the soft start time (tSS) is shown below. (1) Soft start time of ch1, ch2, and ch4 when ch4 is operating as a step-down circuit: tSS [S] = 0.20 x CSS [μF] (2) Soft start time of ch3: tSS [S] = 0.25 x CSS [μF] (3) Soft start time of ch4 when ch4 is operating as inverting circuit: tSS [S] = 0.40 x CSS [μF]

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 19 of 30 Mar 18, 2011 Calculating Delay Time of Short-circuit Protection Circuit The following approximate expression is for calculating the delay time tDLY of the short-circuit protection circuit. tDLY [s] = 1.06 x CSCP [μF] If the delay time of the short-circuit protection circuit is set to be shorter than the internally fixed soft start time, or if the load transient response of the DC-DC converter output is dull, the short-circuit protection may operate before the output voltage of a ch rises. Check the delay time of the short-circuit protection circuit by mounting the IC on an actual system. Pin Processing When Short-circuit Protection Circuit is not used When the short-circuit protection circuit is not used, connect the SCP pin to the AGND pin. At this time, closely monitor heating because the overheat protection circuit does not operate.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 20 of 30 Mar 18, 2011 Process of I/O pin when not used Connect the I/O pins of each ch that are not used to the pins listed below. (Be sure to connect the pins that are necessary to the operations of power supply and GND.) ch1 when not used ch2 when not used PIN NO. Symbol Connect pin PIN NO. Symbol Connect pin

40 VPIN1 AVDD

47 VPIN21 AVDD

41 LOUT1 OPEN 48 VPIN22 AVDD

42 PGND1 PGND

45 LOUT21 OPEN

1 II1 VREG 46 LOUT22 OPEN

32 SS1 AGND 43 PGND21 PGND

12 SHDNB1 OPEN or AGND 44 PGND22 PGND

2 II2 VREG

31 SS2 AGND

11 SHDNB2 OPEN or AGND

ch3 when not used ch4 when not used (CTL = L) PIN NO. Symbol Connect pin PIN NO. Symbol Connect pin

13 VPIN31 AVDD 37 OUTA4 PVDD

14 VPIN32 AVDD 36 OUTB4 OPEN or PGND

15 LOUTA31 OPEN 38 CSL PVDD

16 LOUTA32 OPEN 4 II4 VREG

17 PGNDA31 PGND 29 SS4 AGND

18 PGNDA32 PGND 9 SHDNB4 OPEN or AGND

21 LOUTB31 OPEN 8 CTL AGND

22 LOUTB32 OPEN Remark L: Low level

23 DOUT31 PGND

24 DOUT32 PGND

ch4 when not used (CTL = H) 19 PGNDB31 PGND PIN NO. Symbol Connect pin

20 PGNDB32 PGND 37 OUTA4 PVDD

3 II3 VREG 36 OUTB4 OPEN or PGND

30 SS3 AGND 38 CSL PVDD

10 SHDNB3 OPEN or AGND 4 II4 AGND

29 SS4 AGND

9 SHDNB4 OPEN or AGND

8 CTL AVDD

Remark H: High level When external clock function is not used When ch4 diode rectification step-down circuit and inverting circuit operate PIN NO. Symbol Connect pin PIN NO. Symbol Connect pin

7 CLK OPEN or AGND 36 OUTB4 OPEN or PGND

When short-circuit detection signal pin (RSTB pin) is not used PIN NO. Symbol Connect pin

6 RSTB OPEN or AGND

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 21 of 30 Mar 18, 2011 About ch3 (step-up/down circuit) When using ch3 with an output voltage of 5.5 V or higher, operating noise as high as 60 mV (p-p) might occur. To suppress this noise, connect a Schottky barrier diode between the LOUTB3 and DOUT3 pins. /K50/K6F/K77/K65/K72 /K73/K75/K70/K70/K6C/K79 /K56/K50/K49/K4E/K33 /K4C/K4F/K55/K54/K41/K33 μ/K50/K44/K31/K36/K38/K38/K30/K37 /K63/K68/K33 /K57/K69/K74/K68/K6F/K75/K74 /K53/K42/K44/K69 /K56/K50/K49/K4E/K33 /K4C/K4F/K55/K54/K41/K33 /K43/K6F/K6E/K74/K72/K6F/K6C /K63/K69/K72/K73/K75/K69/K74 μ/K50/K44/K31/K36/K38/K38/K30/K37 /K63/K68/K33 /K41/K64/K64 /K53/K42/K44/K69 /K57/K69/K74/K68 /K53/K42/K44/K69 /K50/K6F/K77/K65/K72 /K73/K75/K70/K70/K6C/K79 /K43/K6F/K6E/K74/K72/K6F/K6C /K63/K69/K72/K73/K75/K69/K74 /K4C/K4F/K55/K54/K42/K33 /K44/K4F/K55/K54/K33 /K4C/K4F/K55/K54/K42/K33 /K44/K4F/K55/K54/K33 Suggestion for improving the efficiency of ch4 (step-down circuit) when the load is light Ch4 (step-down circuit) is a synchronous rectification type step-down circuit that is used to drive an external MOSFET (Pch + Nch). However, because the load connected to ch4 is often light, ch4 can be made to operate more efficiently under a light load by changing to the diode rectification. Synchronous rectification OUTB4 Power supply OUTA4 μPD168807 ch4 Diode rectification OUTB4 OUTA4 μPD168807 ch4 Synchronous rectification → Diode rectification PVDD CSL PVDD CSL Power supply

• IC pin processing during diode rectification OUTB4: OPEN or PGND connection

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 22 of 30 Mar 18, 2011 External clock function Configure the circuit as follows when using an external clock: /K49/K43/K31 /K56/K52/K45/K47 /K52/K54 /K43/K54 /K43/K4C/K4B /K49/K43/K32 /K56/K52/K45/K47 /K52/K54 /K43/K54 /K43/K4C/K4B /K56/K52/K45/K47 /K43/K54 /K52/K54 /K43/K4C/K4B /K45/K78/K74/K65/K72/K6E/K61/K6C /K63/K6C/K6F/K63/K6B /K57/K68/K65/K6E /K74/K68/K65/K72/K65 /K69/K73 /K6D/K6F/K72/K65 /K74/K68/K61/K6E /K6F/K6E/K65 /K49/K43/K57/K68/K65/K6E /K74/K68/K65/K72/K65 /K69/K73 /K6F/K6E/K65 /K49/K43 /K43/K6F/K6E/K66/K69/K67/K75/K72/K65 μ/K50/K44/K31/K36/K38/K38/K30/K37 μ/K50/K44/K31/K36/K38/K38/K30/K37 μ/K50/K44/K31/K36/K38/K38/K30/K37 /K45/K78/K74/K65/K72/K6E/K61/K6C /K63/K6C/K6F/K63/K6B

• IC pin processing RT, CT: Short with VREG External Clock Specifications 0 V Duty Cycle = 50% Duty cycle: 50% Input frequency: 0.3 MHz to 1.5 MHz Input high level voltage: Frequency = 0.3 MHz to 1.5 MHz

14.5 V or less

Input low level voltage: 0 V <R>

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 23 of 30 Mar 18, 2011 Master-slave operation Configure the circuit as follows when using multiple μ PD168807 ICs in a master-slave configuration: (1) Example of usual configuration Master IC VREG RT CT VREF Slave IC SHDNB1 to 4 ON/OFF signal Configuration Diagram μPD168807 μPD168807 VREF SHDNB1 to 4 VREG RT CT Caution Be sure to input the signal that turns the channel started up first to the SHDNB pin of one of the channels on the slave side as well as to the SHDNB pin of the relevant channel on the master side. (The status of the VREF pin when the IC stops operating becomes AGND, so when the master IC is operating, make sure that VREF is not applied to the slave ICs that are stopped.)

• IC pin handling <1> Master side No change. <2> Slave side CT: Short with CT on the master side RT: Short with VREG on the slave side VREF: Short with VREF on the master side (2) Example of configuration when external comparator is used Master IC VREG RT CT VREF Slave IC SHDNB1 to 4 ON/OFF signal Configurationi Diagram μPD168807 μPD168807 VREF SHDNB1 to 4 VREG RT CT

0.8 V 0.4 V Comparator 2.0 V 0.6 V CLK Duty: 50% CLK Caution The triangular wave is 0.8 V ±0.1 V when CLK is high level and 0.4 V ±0.1 V when CLK is low level, so make sure that the 0.6 V constant voltage input to the comparator has an error of no more than ±0.1 V.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 24 of 30 Mar 18, 2011

• IC pin handling <1> Master side CLK: OPEN or AGND connection <2> Slave side CT, RT: Short with VREG on the slave side VREF: Input the external co mparator's output signal

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 25 of 30 Mar 18, 2011 9. Notes on Use Prohibited mode Always fix the CTL pin to high or low during a circuit operation. Condition where protection circuits do not operate When the SCP pin is connected to the AGND pin, the overheat protection circuit and short-circuit protection circuit do not operate. Pin connection Be sure to apply the same potential to the power supply AVDD pin and PVDD pin. Connect all pins if there are two or more pins. About the pull-down resistors connected to the input pins 400 kΩ (TYP) pull-down resistors are connected to the SHDNB1 to SHDNB4 pins and the CLK pin. However, in order to reduce the current consumption when the CTL pin is high level while the IC is on standby, a pull-down resistor is not connected to the CTL pin. The level of the CTL pin must therefore be fixed to either low or high externally. Actual pattern wiring To actually perform pattern wiring, separate the ground of the control signals from the ground of the power signals, so that these signals do not have a common impedance as much as possible. In addition, lower the high-frequency impedance by using a capacitor, so that noise is not superimposed on the VREF pin, VREG pin. Fixed usage of control input pin When using fixed input pins SHDNB1 to SHDNB4 and CTL input pins, connect each input to the pins listed below. Connect pin Input pin Fixed to low level Fixed to high level SHDNB1 AGND AVDD SHDNB2 AGND AVDD SHDNB3 AGND AVDD SHDNB4 AGND AVDD CTL AGND AVDD

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 26 of 30 Mar 18, 2011 10. Application Circuit Example Example 1: (ch4: Step-down operation, CTL = L) ch1OUT ch1OUT 1.2 V ch2OUT 1.8 V 5 V 3.3 V ch4OUT ch3OUT Input Voltage 4.0 V to 14.5 V ch4OUT VPIN1 PGND1 ch2OUT ch3OUT SCP VREF VREG AGND SHDNB1 SHDNB2 SHDNB3 CT RT AVDD Overheat Protection Circuit TSD SHDNB4 II4 E/A4 Phase Compensator E/A2 II2 0.8 V II3 E/A3 II1 0.8 V E/A1 LOUT1 PGND21 CTL SS1 SS2 SS3 SS4 LOUT21 VPIN22 LOUTA31 PGNDA31 VPIN31 CLK Oscillator OSC RSTB VPIN21 PGND22 LOUT22 LOUTB31 PGNDB31 DOUT32 OU TA4 OUTB4 PVDD PGND4 PGNDB32 LOUTB32 DOUT31 PGNDA32 LOUTA32 VPIN32 Threshold Voltage Switching Circuit CLK Short-circuit protection circuit SCP CSL Reference Voltage VREF Internal Power Supply VREG ON/OFF Controller Circuit Current Mode Current-limit Controller ++-

1 V ++

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 27 of 30 Mar 18, 2011 Example 2: (ch4: inverting operation, CTL = H) ch1OUT ch1OUT 1.2 V ch2OUT 1.8 V 5 V -3 V ch4OUT ch3OUT Input Voltage 4.0 V to 14.5 V VPIN1 PGND1 ch2OUT ch3OUT SCP VREF VREG AGND SHDNB1 SHDNB2 SHDNB3 CT RT AVDD SHDNB4 E/A4 Phase Compensator E/A2 II2 0.8 V II3 E/A3 II1 0.8 V E/A1 LOUT1 PGND21 CTL SS1 SS2 SS3 SS4 LOUT21 VPIN22 LOUTA31 PGNDA31 VPIN31 CLK OSC RSTB VPIN21 PGND22 LOUT22 LOUTB31 PGNDB31 DOUT32 OU TA4 OUTB4 PVDD PGND4 PGNDB32 LOUTB32 DOUT31 PGNDA32 LOUTA32 VPIN32 Threshold Voltage CLK Short-circuit protection circui SCP CSL Soft Start Circuit Reference Voltage VREF Internal Power Supply VREG ON/OFF Current Mode Current-limit Controller ++- VREF (2 V) Switching Circuit Phase Compensator Phase Compensator Phase Compensator Controller Circuit Oscillator Overheat Protection Circuit TSD Current Mode Current-limit Controller Current Mode Current-limit Switching Controller to Switch between Step-down and Inverting Undervoltage Lockout Circuit UVLO

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 28 of 30 Mar 18, 2011 11. Package Drawing 48-PIN PLASTIC VQFN (6 mm×6 mm) Punch Type/0.4 mm pitch/Exposed PAD DETAIL OF PART Sy eLp SxbA B M A ITEM DIMENSIONS D E HD HE A b c e Lp x y ZD ZE 6.00 0.05± 6.00 0.05± 6.20 0.10± 6.20 0.10± 0.85 0.83 0.05± 0.18 0.05± 0.22 0.40 0.05 0.05 0.90 0.90 0.05± 0.45 0.10± 0.02 0.02+ 0.015 (UNIT:mm) 48-PIN PLASTIC VQFN (6x6) D E 1 12 2536 AA2 c HE HD S B A 4xC0.5 ZE ZD 45° P48K9-40-4EG 0.20± 0.05 4x0.2824 A

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 29 of 30 Mar 18, 2011 12. Recommended Soldering Conditions The μPD168807 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact our sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www2.renesas.com/pkg/en/mount/index.html) μPD168807: 48-pin plastic VQFN Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher), Count: Three times. Exposure limit: 7 days *1 (after that, prebake at 125°C for 10 hours). Flux: Rosin flux with few chlorine (less than 0.2 Wt%) recommended. <Precaution> Cannot be baked in their taping package. IR60-107-3 Note: ∗1. After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together.

μPD168807 Chapter Title R03DS0001EJ0200 Rev.2.00 Page 30 of 30 Mar 18, 2011 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

μPD168807 Chapter Title All trademarks and registered trademarks are the property of their respective owners. C - 1 Revision History μPD168807 Data Sheet

Description

Rev. Date Page Summary

1.00 Aug 31, 2010 − First Edition Issued

2.00 Mar 18, 2011 p.22 External clock function Modification of Configure

1. All information included in this document is current as of the date this document is issued. Such information, however, is s ubject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part . 4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", an d "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compati bility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renes as Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this doc ument or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-o wned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Renesas Electronics Canada Limited

1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada

Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K Tel: +44-1628-585-100, Fax: +44-1628-585-900 Renesas Electronics Europe GmbH Arcadiastrasse 10, 40472 Düsseldorf, Germany Tel: +49-211-65030, Fax: +49-211-6503-1327 Renesas Electronics (China) Co., Ltd. 7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: +86-10-8235-1155, Fax: +86-10-8235-7679 Renesas Electronics (Shanghai) Co., Ltd. Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898 Renesas Electronics Hong Kong Limited Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong Tel: +852-2886-9318, Fax: +852 2886-9022/9044 Renesas Electronics Taiwan Co., Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan Tel: +886-2-8175-9600, Fax: +886 2-8175-9670 Renesas Electronics Singapore Pte. Ltd. 1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632 Tel: +65-6213-0200, Fax: +65-6278-8001 Renesas Electronics Malaysia Sdn.Bhd. Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea SALES OFFICES © 2011 Renesas Electronics Corporation. All rights reserved. Colophon 1.0