PD16732D

PD16732D_15 RENESAS | Alldatasheet

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. © 2001,2002 MOS INTEGRATED CIRCUIT µµµµ PD16732D 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DATA SHEET Document No. S15022EJ1V0DS00 (1st edition) Date Published June 2002 NS CP (K) Printed in Japan

DESCRIPTION

The µPD16732D is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as V SS2 + 0.1 V to V DD2 – 0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 65 MHz when driving at 3.0 V, 45 MHz when driving at 2.3 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels.

FEATURES

• CMOS level input (2.3 to 3.6 V)
• 384 outputs
• Input of 6 bits (gray-scale data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
• Logic power supply voltage (VDD1): 2.3 to 3.6 V
• Driver power supply voltage (VDD2): 8.0 to 9.0 V
• High-speed data transfer: fCLK = 65 MHz (internal data transfer speed when operating at VDD1 = 3.0 V)
• Output dynamic range: VSS2 + 0.1 V to VDD2 – 0.1 V
• Apply for dot-line inversion, n-line inversion and column line inversion
• Output voltage polarity inversion function (POL)
• Display data inversion function (capable of controlling by each input port) (POL21,POL22)
• Current consumption control function (LPC, Bcont)
• Succession of µPD16732A driver

ORDERING INFORMATION

µPD16732DN-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives. The mark # shows major revised points.

µµµµPD16732D 1. BLOCK DIAGRAM STHL VDD1 VSS1 VDD2 VSS2 S2S1 V0 - V9 POL D 00 - D 05 C 1 C 2 C 63 C 64 STB CLK 64-bit bidirectional shift register Data register Latch Level shifter D/A converter Voltage follower output R,/L STHR D 10 - D 15 D 20 - D 25 S3 S384 POL21,POL22 D 30 - D 35 D 40 - D 45 D 50 - D 55 Bcont LPC Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 S2 S383 6-bit D/A converter S384 POL Multi- plexer

Data Sheet S15022EJ1V0DS 3 µµµµPD16732D 3. PIN CONFIGURATION (Top of copper foil surface, face-up) µµµµPD16732DN-xxx: TCP (TAB package) S384 S383 STHL S382 D55 S381 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L VDD2 VSS2 Bcont VSS1 LPC CLK STB POL POL21 POL22 D D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 S4 D03 S3 D02 S2 D01 S1 D00 STHR Copper foil surface Remark This figure does not specify the TCP package.

µµµµPD16732D 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name I/O Description S1 to S384 Driver Output The D/A converted 64-gray-scale analog voltage is output. D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 Display data Input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). D X0: LSB, DX5: MSB R,/L Shift direction control Input The shift direction control pin of the shift register. The shift directions of the shift registers are as follows. R,/L = H (right shift): STHR (input), S 1 → S384, STHL (output) R,/L = L (left shift) : STHL (input), S384 → S1, STHR (output) STHR Right shift start pulse I/O STHL Left shift start pulse I/O These refer to the start pulse I/O pins when the IC is connected in cascade. Loading of display data starts when a high level is read at the rising edge of CLK. A high level should be input as the pulse of one cycle of the clock signal. If the start pulse input is more than 2CLKs, the first 1CLK of the high-level input is valid. R,/L = H (right shift): STHR input, STHL output R,/L = L (left shift): STHL input, STHR output CLK Shift clock Input This pin refers to the shift clock input of the shift register. The display data is loaded into the data register at the rising edge. At the rising edge of the 64th after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. When the 66 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch Input The contents of the data register are transferred to the latch circuit at the rising edge. In addition, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input Input POL = L: The S 2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL21, POL22 Data inversion Input Select of inversion or no inversion for input data. POL21: D 00-D05, D10-D15, D20-D25 Data inversion or no inversion of Port1 POL22: D30-D35, D40-D45, D50-D55 Data inversion or no inversion of Port2 POL21,POL22 = H: Data are inverted in the IC. POL21,POL22 = L: Data are not inverted in the IC. LPC Low power control Input The current consumption is lowered by controlling the constant current source of the output amplifier. In low power mode (LPC = L), the VDD2 of static current consumption can be reduced to two thirds of the normal current consumption. This pin is pulled up to the V DD1 power supply inside the IC. LPC = H or open: Normal power mode LPC = L: Low power mode Bcont Bias control Input This pin can be used to finely control the bias current inside the output amplifier. In cases when fine-control is necessary, connect this pin to the stabilized ground potential (V SS2) via an external resistor of 10 to 100 kΩ (per IC). When this fine-control function is not required, leave this pin open. Refer to 9. CURRENT CONSUMPTION REDUCTION FUNCTION

Data Sheet S15022EJ1V0DS 5 µµµµPD16732D (2/2) Pin Symbol Pin Name I/O Description V0 to V9 γ -corrected power supplies − Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. V DD2 − 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 8.0 to 9.0 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be V DD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down (Simultaneous power application to V DD2 and V0 to V9 is possible.). 2. To stabilize the supply voltage, please be sure to insert a 0.1 µµµµF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µµµµF is also recommended between the γγγγ -corrected power

µµµµPD16732D 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µPD16732D incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r 0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V 0’ to V63’ and V0” to V63” is almost equivalent as shown in Figure 5-2. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine-gray scale voltage precision is not necessary, there is no need to connect voltage follower circuit to the γ –corrected power supplies V1 to V3 and V6 to V8. Figure 5–1 shows the relationship between the driving voltages such as liquid-crystal driving voltages V DD2 and VSS2, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships as follows. VDD2 – 0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 + 0.1 V Figures 5–2 indicates γ -corrected voltages and ladder resistors ratio. Figures 5–3 indicates the relationship between the input data and output voltage and the resistance values of the resistor string. Figure 5–1. Relationship between Input Data and γγγγ-corrected Power Supplies 0.1 V 0.1 V VDD2

0.5 VDD2

Input Data (HEX) Split interval

Data Sheet S15022EJ1V0DS 7 µµµµPD16732D Figure 5–2. γγγγ -corrected Voltages and Ladder Resistor’s Ratio V0' V17' V1' V47' V2' V48' V3' V49' V15' V16' V63' V61' V62' r17 r47 r46 r48 r49 r14 r15 r16 r60 r61 r62 V17'' V0'' V16'' V15'' V2'' V1'' V63'' V62'' V61'' V49'' V48'' V47'' r61 r60 r59 r49 r48 r47 r46 r62 r17 r16 r15 r14 V60'' rn Ratio1 Ratio2 Value( Ω ) r0 8.0 0.050 800 r1 7.5 0.047 750 r2 7.0 0.044 700 r3 6.5 0.041 650 r4 6.0 0.038 600 r5 5.5 0.035 550 r6 5.5 0.035 550 r7 5.0 0.032 500 r8 5.0 0.032 500 r9 4.0 0.025 400 r10 4.0 0.025 400 r11 3.5 0.022 350 r12 3.5 0.022 350 r13 3.5 0.022 350 r14 3.0 0.019 300 r15 3.0 0.019 300 r16 3.0 0.019 300 r17 2.5 0.016 250 r18 2.5 0.016 250 r19 2.5 0.016 250 r20 2.0 0.013 200 r21 2.0 0.013 200 r22 2.0 0.013 200 r23 1.5 0.009 150 r24 1.5 0.009 150 r25 1.5 0.009 150 r26 1.5 0.009 150 r27 1.0 0.006 100 r28 1.0 0.006 100 r29 1.0 0.006 100 r30 1.0 0.006 100 r31 1.0 0.006 100 r32 1.0 0.006 100 r33 1.0 0.006 100 r34 1.0 0.006 100 r35 1.0 0.006 100 r36 1.0 0.006 100 r37 1.0 0.006 100 r38 1.0 0.006 100 r39 1.0 0.006 100 r40 1.0 0.006 100 r41 1.0 0.006 100 r42 1.0 0.006 100 r43 1.0 0.006 100 r44 1.0 0.006 100 r45 1.0 0.006 100 r46 1.0 0.006 100 r47 1.0 0.006 100 r48 1.0 0.006 100 r49 1.0 0.006 100 r50 1.0 0.006 100 r51 1.0 0.006 100 r52 1.0 0.006 100 r53 1.5 0.009 150 r54 1.5 0.009 150 r55 1.5 0.009 150 r56 2.0 0.013 200 r57 2.0 0.013 200 r58 2.5 0.016 250 r59 2.5 0.016 250 r60 3.0 0.019 300 r61 5.0 0.032 500 r 62 8.0 0.050 800 Caution There is no connection between V4 and V5 terminal in the chip. Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1.

µµµµPD16732D Figure 5–3. Relationship between Input Data and Output Voltage (POL21,POL22 = L) (Output Voltage 1) VDD2 – 0.1 V ≥≥≥≥ V0 > V1 > V2 > V3 > V4 ≥≥≥≥ 0.5 VDD2 (Output Voltage 2) 0.5 VDD2 ≥≥≥≥ V5 > V6 > V7 > V8 > V9 ≥≥≥≥ VSS2 + 0.1 V Input Data 00H V0' V0 V0'' V9 02H V2' V1+(V0-V1)× 6500 / 8050 V2'' V9+(V8-V9)× 1550 / 8050 03H V3' V1+(V0-V1)× 5800 / 8050 V3'' V9+(V8-V9)× 2250 / 8050 04H V4' V1+(V0-V1)× 5150 / 8050 V4'' V9+(V8-V9)× 2900 / 8050 05H V5' V1+(V0-V1)× 4550 / 8050 V5'' V9+(V8-V9)× 3500 / 8050 06H V6' V1+(V0-V1)× 4000 / 8050 V6'' V9+(V8-V9)× 4050 / 8050 07H V7' V1+(V0-V1)× 3450 / 8050 V7'' V9+(V8-V9)× 4600 / 8050 08H V8' V1+(V0-V1)× 2950 / 8050 V8'' V9+(V8-V9)× 5100 / 8050 09H V9' V1+(V0-V1)× 2450 / 8050 V9'' V9+(V8-V9)× 5600 / 8050 0AH V10' V1+(V0-V1)× 2050 / 8050 V10'' V9+(V8-V9)× 6000 / 8050 0BH V11' V1+(V0-V1)× 1650 / 8050 V11'' V9+(V8-V9)× 6400 / 8050 0CH V12' V1+(V0-V1)× 1300 / 8050 V12'' V9+(V8-V9)× 6750 / 8050 0DH V13' V1+(V0-V1)× 950 / 8050 V13'' V9+(V8-V9)× 7100 / 8050 0EH V14' V1+(V0-V1)× 600 / 8050 V14'' V9+(V8-V9)× 7450 / 8050 0FH V15' V1+(V0-V1)× 300 / 8050 V15'' V9+(V8-V9)× 7750 / 8050 10H V16' V1 V16'' V8 11H V17' V2+(V1-V2)× 2450 / 2750 V17'' V8+(V7-V8)× 300 / 2750 12H V18' V2+(V1-V2)× 2200 / 2750 V18'' V8+(V7-V8)× 550 / 2750 13H V19' V2+(V1-V2)× 1950 / 2750 V19'' V8+(V7-V8)× 800 / 2750 14H V20' V2+(V1-V2)× 1700 / 2750 V20'' V8+(V7-V8)× 1050 / 2750 15H V21' V2+(V1-V2)× 1500 / 2750 V21'' V8+(V7-V8)× 1250 / 2750 16H V22' V2+(V1-V2)× 1300 / 2750 V22'' V8+(V7-V8)× 1450 / 2750 17H V23' V2+(V1-V2)× 1100 / 2750 V23'' V8+(V7-V8)× 1650 / 2750 18H V24' V2+(V1-V2)× 950 / 2750 V24'' V8+(V7-V8)× 1800 / 2750 19H V25' V2+(V1-V2)× 800 / 2750 V25'' V8+(V7-V8)× 1950 / 2750 1AH V26' V2+(V1-V2)× 650 / 2750 V26'' V8+(V7-V8)× 2100 / 2750 1BH V27' V2+(V1-V2)× 500 / 2750 V27'' V8+(V7-V8)× 2250 / 2750 1CH V28' V2+(V1-V2)× 400 / 2750 V28'' V8+(V7-V8)× 2350 / 2750 1DH V29' V2+(V1-V2)× 300 / 2750 V29'' V8+(V7-V8)× 2450 / 2750 1EH V30' V2+(V1-V2)× 200 / 2750 V30'' V8+(V7-V8)× 2550 / 2750 1FH V31' V2+(V1-V2)× 100 / 2750 V31'' V8+(V7-V8)× 2650 / 2750 20H V32' V2 V32'' V7 21H V33' V3+(V2-V3)× 1500 / 1600 V33'' V7+(V6-V7)× 100 / 1600 22H V34' V3+(V2-V3)× 1400 / 1600 V34'' V7+(V6-V7)× 200 / 1600 23H V35' V3+(V2-V3)× 1300 / 1600 V35'' V7+(V6-V7)× 300 / 1600 24H V36' V3+(V2-V3)× 1200 / 1600 V36'' V7+(V6-V7)× 400 / 1600 25H V37' V3+(V2-V3)× 1100 / 1600 V37'' V7+(V6-V7)× 500 / 1600 26H V38' V3+(V2-V3)× 1000 / 1600 V38'' V7+(V6-V7)× 600 / 1600 27H V39' V3+(V2-V3)× 900 / 1600 V39'' V7+(V6-V7)× 700 / 1600 28H V40' V3+(V2-V3)× 800 / 1600 V40'' V7+(V6-V7)× 800 / 1600 29H V41' V3+(V2-V3)× 700 / 1600 V41'' V7+(V6-V7)× 900 / 1600 2AH V42' V3+(V2-V3)× 600 / 1600 V42'' V7+(V6-V7)× 1000 / 1600 2BH V43' V3+(V2-V3)× 500 / 1600 V43'' V7+(V6-V7)× 1100 / 1600 2CH V44' V3+(V2-V3)× 400 / 1600 V44'' V7+(V6-V7)× 1200 / 1600 2DH V45' V3+(V2-V3)× 300 / 1600 V45'' V7+(V6-V7)× 1300 / 1600 2EH V46' V3+(V2-V3)× 200 / 1600 V46'' V7+(V6-V7)× 1400 / 1600 2FH V47' V3+(V2-V3)× 100 / 1600 V47'' V7+(V6-V7)× 1500 / 1600 30H V48' V3 V48'' V6 31H V49' V4+(V3-V4)× 3350 / 3450 V49'' V6+(V5-V6)× 100 / 3450 32H V50' V4+(V3-V4)× 3250 / 3450 V50'' V6+(V5-V6)× 200 / 3450 33H V51' V4+(V3-V4)× 3150 / 3450 V51'' V6+(V5-V6)× 300 / 3450 34H V52' V4+(V3-V4)× 3050 / 3450 V52'' V6+(V5-V6)× 400 / 3450 35H V53' V4+(V3-V4)× 2950 / 3450 V53'' V6+(V5-V6)× 500 / 3450 36H V54' V4+(V3-V4)× 2800 / 3450 V54'' V6+(V5-V6)× 650 / 3450 37H V55' V4+(V3-V4)× 2650 / 3450 V55'' V6+(V5-V6)× 800 / 3450 38H V56' V4+(V3-V4)× 2500 / 3450 V56'' V6+(V5-V6)× 950 / 3450 39H V57' V4+(V3-V4)× 2300 / 3450 V57'' V6+(V5-V6)× 1150 / 3450 3AH V58' V4+(V3-V4)× 2100 / 3450 V58'' V6+(V5-V6)× 1350 / 3450 3BH V59' V4+(V3-V4)× 1850 / 3450 V59'' V6+(V5-V6)× 1600 / 3450 3CH V60' V4+(V3-V4)× 1600 / 3450 V60'' V6+(V5-V6)× 1850 / 3450 3DH V61' V4+(V3-V4)× 1300 / 3450 V61'' V6+(V5-V6)× 2150 / 3450 3EH V62' V4+(V3-V4)× 800 / 3450 V62'' V6+(V5-V6)× 2650 / 3450 3FH V 63' V63'' Output Voltage1 Out put Voltage2 V4 V5 Caution There is no connection between V4 and V5 terminal in the chip.

Data Sheet S15022EJ1V0DS 9 µµµµPD16732D 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x 2 RGBs (6 dots) Input width : 36 bits (2-pixel data) (1) R,/L = H (Right shift) Output S 1 S2 S3 S4 ... S383 S384 Data D 00 to D05 D10 to D15 D20 to D25 D30 to D35 ... D 40 to D45 D50 to D55 (2) R,/L = L (Left shift) Output S 1 S2 S3 S4 ... S 383 S384 Data D 00 to D05 D10 to D15 D20 to D25 D30 to D35 ... D 40 to D45 D50 to D55 POL S 2n–1 Note S2n Note LV 0 to V4 V5 to V9 HV 5 to V9 V0 to V4 Note S2n–1 (Odd output), S2n (Even output) 7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. Selected voltage V0 to V4 Hi-Z STB POL S2n S2n-1 Hi-Z Hi-Z Selected voltage V5 to V9 Selected voltage V0 to V4 Selected voltage V0 to V4 Selected voltage V5 to V9 Selected voltage V5 to V9

Data Sheet S15022EJ1V0DS 11 µµµµPD16732D 9. CURRENT CONSUMPTION REDUCTION FUNCTION The µPD16732D has a low power control function (LPC) which can switch the bias current of the output amplifier between two levels and a bias control function (Bcont) which can be used to finely control the bias current. <Low power control function (LPC)> The bias current of the output amplifier can be switched between two levels using this pin. (Bcont: open) LPC = H or open: normal power mode LPC = L: low power mode The V DD2 of static current consumption can be reduced to two thirds of that in normal mode, input a stable DC current (VDD1/VSS1) to this pin. <Bias current control function (Bcont)> It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (V SS2) via an external resistor (REXT). When not using this function, leave this pin open. Figure 9–1. Bias Current Control Function (Bcont) PD16732Dµ Bcont LPC R EXT H/L VSS2 Refer to the table below for the percentage of current regulation when using the bias current control-function. Table 9–1. Current Consumption Regulation Percentage Compared to Normal Mode VDD1 = 3.3 V VDD2 = 8.7 V LPC = 3.3 V/ 0 V Current Consumption Regulation Percentage (%) REXT (kΩ) LPC = H LPC = L ∞ (Open) 100 65 50 110 70 20 115 80 10 120 85 Remark The above current consumption regulation percentages are not product-characteristic guaranteed as they are based on the results of simulation. Caution Because the low-power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality.

Data Sheet S15022EJ1V0DS12 µµµµPD16732D Figure9−−−−2. Output Wave Form (LPC = L) Bcont = Open Output Voltage(1 V/div) Time (4 µs / div) Bcont = 1.0 kΩ Bcont = 10 kΩ Bcont = 50 kΩ [1] [2] <Test Condition> C L R LR L R L R L = 1 kΩ C L = 15 pF R L C L R L C LC LC L VIN + [1] [2]

Data Sheet S15022EJ1V0DS 13 µµµµPD16732D Figure9−−−−3. Output Wave Form (LPC = H) Bcont = Open Time (4 Output Voltage(1 V/div) µs / div) Bcont = 1.0 kΩ Bcont = 10 kΩ Bcont = 50 kΩ

Data Sheet S15022EJ1V0DS14 µµµµPD16732D 10. ELECTRICAL SPECIFICATIONS Parameter Symbol Rating Unit Logic Part Supply Voltage V DD1 –0.5 to +4.0 V Driver Part Supply Voltage V DD2 –0.5 to +10.0 V Logic Part Input Voltage V I1 –0.5 to VDD1 + 0.5 V Driver Part Input Voltage V I2 –0.5 to VDD2 + 0.5 V Logic Part Output Voltage V O1 –0.5 to VDD1 + 0.5 V Driver Part Output Voltage V O2 –0.5 to VDD2 + 0.5 V Operating Ambient Temperature T A –10 to +75 °C Storage Temperature T stg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (T A = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Logic Part Supply Voltage V DD1 2.3 3.6 V Driver Part Supply Voltage V DD2 8.0 8.5 9.0 V High-Level Input Voltage V IH 0.7 VDD1 VDD1 V Low-Level Input Voltage V IL 0 0.3 V DD1 V V0 to V4 0.5 VDD2 VDD2 – 0.1 Vγ -Corrected Voltage V5 to V9 VSS2 + 0.1 0.5 V DD2 V Driver Part Output Voltage V O VSS2 + 0.1 V DD2 – 0.1 V 2.3 ≤ V VDD1 < 3.0 V 45 MHzClock Frequency f CLK 3.0 V ≤ VDD1 ≤ 3.6 V 65 MHz

Data Sheet S15022EJ1V0DS 15 µµµµPD16732D Unless otherwise specified, LPC = H or open, Bcont = open) Parameter Symbol Condition MIN. TYP. MAX. Unit Input Leak Current I IL ±1.0 µA High-Level Output Voltage V OH STHR (STHL), IOH = 0 mA V DD1 – 0.1 V Low-Level Output Voltage V OL STHR (STHL), IOL = 0 mA 0.1 V γ -Corrected Resistance R γ V0 to V4 = V5 to V9 = 4.0 V 8 16 32 k Ω IVOH VX = 7.0 V, VOUT = 6.5 V Note –30 µADriver Output Current IVOL VX = 1.0 V, VOUT = 1.5 V Note 30 µA Output Voltage Deviation ∆VO ±7 ±20 mV Output Swing Difference Deviation ∆VP–P VDD1 = 3.3 V, VDD2 = 8.5 V VOUT = 2.0 V, 4.25 V, 6.5 V ±2 ±15 mV Output Voltage Range V O All input data 0.1 V DD2 – 0.1 V Logic Part Dynamic Current Consumption IDD1 VDD1, with no load 1.0 6.0 mA IDD21 VDD2 = 8.0 to 9.0 V, with no load, LPC =H, Bcont = open 3.0 6.0 mADriver Part Dynamic Current Consumption IDD22 VDD2 = 8.0 to 9.0 V, with no load, LPC =L, Bcont = open 2.0 4.0 mA Note VX refers to the output voltage of analog output pins S 1 to S384. VOUT refers to the voltage applied to analog output pins S 1 to S384. Cautions 1. STB cycle is 20 µµµµs, fCLK = 40 MHz 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of XGA+ single-sided mounting (8 units).

Data Sheet S15022EJ1V0DS16 µµµµPD16732D Switching Characteristics (TA = –10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V, Unless otherwise specified, LPC = H or open, Bcont = open) Parameter Symbol Condition MIN. TYP. MAX. Unit CL = 10 pF, 2.3 ≤ V VDD1 < 3.0 V 10 17 nsStart Pulse Delay Time t PLH1 CL = 10 pF, 3.0 V ≤ VDD1 ≤ 3.6 V 7 10.5 ns tPLH2 2.5 5 µs tPLH3 58 µs tPHL2 2.5 5 µs Driver Output Delay Time tPHL3 CL = 75 pF, RL = 5 kΩ 58 µs CI1 Exclude STHR (STHL), TA = 25°C 5 10 pFInput Capacitance CI2 STHR (STHL),TA = 25°C 8 10 pF <Test Condition> Output R L2 R L3 R L4 R L5 R Ln = 1 kΩ C L1 C L2 C L3 C L4 C L5 C Ln = 15 pF R L1 Timing Requirements (TA = –10 to +75°°°°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 8.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit 2.3 ≤ V VDD1 < 3.0 V 22 nsClock Pulse Width PW CLK 3.0 V ≤ VDD1 ≤ 3.6 V 15 ns Clock Pulse High Period PW CLK(H) 4n s 2.3 ≤ V VDD1 < 3.0 V 6 nsClock Pulse Low Period PW CLK(L) 3.0 V ≤ VDD1 ≤ 3.6 V 4 ns Data Setup Time t SETUP1 4n s Data Hold Time t HOLD1 0n s Start Pulse Setup Time t SETUP2 4n s Start Pulse Hold Time t HOLD2 0n s POL21,POL22 Setup Time t SETUP3 4n s POL21,POL22 Hold Time t HOLD3 0n s STB Pulse Width PW STB 2C L K Last Data Timing t LDT 2C L K CLK-STB Time t CLK-STB CLK ↑ → STB ↑ 6n s STB ↑ → CLK ↑, VDD1 = 2.3 to 3.6 V 9n sSTB-CLK Time t STB-CLK STB ↑ → CLK ↑, VDD1 = 3.0 to 3.6 V 6n s Time Between STB and Start Pulse t STB-STH STB ↑ → STHR(STHL) ↑ 2C L K POL-STB Time t POL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time t STB-POL STB ↓ → POL ↓ or ↑ 6n s Remark Unless otherwise specified, the input level is defined to be V IH = 0.7 VDD1, VIL = 0.3 VDD1.

Data Sheet S15022EJ1V0DS 17 µµµµPD16732D Switching Characteristic Waveform(R,/L= H) Unless otherwise specified, the input level is defined to be V IH = 0.7 VDD1, VIL = 0.3 VDD1. PW CLK(L) CLK POL Sn (VX) STB D n0 to D n5 STHR STHL PW CLK(H) tr tSETUP2 INVALID D 1 to D6 tHOLD2 36 4 6 5 6 6 513 514 tf VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 PW CLK tCLK-STB tSTB-CLK tSTB-STHtSETUP1 90% 10% tHOLD1 tPLH1 tPOL-STB tSTB-POL tPLH3 tPLH2 tPHL2 tPHL3 Hi-Z Target Voltage +0.1 VDD2 6-bit accuracy tLDT PW STB D 7 to D 12 D 1 to D6 D 7 to D12D 373 to D 378 D 379 to D 384 D 385 to D 390 D 3067 to D 3072 INVALID INVALID VDD1 VSS1 tSETUP3 tHOLD3 POL21,POL22 (1st Dr.) (1st Dr.) INVALID

Data Sheet S15022EJ1V0DS18 µµµµPD16732D 11. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD16732D. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µPD16732DN-xxx : TCP (TAB Package) Mounting Condition Mounting Method Condition Soldering Heating tool 300 to 350 °C, heating for 2 to 3 seconds : pressure 100g (per solder) Thermocompression ACF (Adhesive Conductive Film) Temporary bonding 70 to 100°C : pressure 3 to 8 kg/cm 2: time 3 to 5 sec. Real bonding 165 to 180°C: pressure 25 to 45 kg/cm2: time 30 to 40 sec. (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.

Data Sheet S15022EJ1V0DS 19 µµµµPD16732D NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µµµµPD16732D Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) M8E 00. 4 The information in this document is current as of June, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard":Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).