PD16640C

PD16640C_15 RENESAS | Alldatasheet

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. © 1999 MOS INTEGRATED CIRCUIT µ µ µ µ PD16640C 300/309-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE) DATA SHEET Document No. S11269EJ1V1DS00 (1st edition) Date Published June 1999 NS CP (K) Printed in Japan

DESCRIPTION

The µ PD16640C is a source driver for TFT-LCD 64-gray scale displays. Its logic circuit operates at 3.3 V and the driver circuit operates at 3.3 or 5.0 V (selectable). The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed in 64-value outputs γ-corrected by the internal D/A converter and 11 external power supplies. The clock frequency is 55 MHz MIN. By switching over the number of outputs between 300 and 309, the µ PD16640C can be used in TFT-LCD panels conforming to the SVGA/XGA standards.

FEATURES

• CMOS level input
• Number of outputs selectable (Osel = H : 300 outputs, Osel = L : 309 outputs)
• 6 bits (gray scale data) x 3 dots input
• 64-value output by 11 external power supplies and internal D/A converter
• Output dynamic range : VSS2 + 0.1 V to VDD2 − 0.1 V
• High-speed data transfer: fMAX. =55 MHz MIN.(internal data transfer speed when VDD1 = 3.0 V)
• Precharge-less output buffer
• Level of γ-corrected power supply can be inverted.
• Input data inversion function (INV)
• Logic power supply (VDD1 ) : 3.3 V ± 0.3 V
• Driver power supply (VDD2 ) : 3.3 V ± 0.3 V (Vsel = H) 5.0 V ± 0.5 V (Vsel = L)

ORDERING INFORMATION

µ PD16640CN-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC salesperson.

Data Sheet S11269EJ1V1DS002 µ µ µ µ PD16640C 1. BLOCK DIAGRAM C 1 C 2 C 102 C 103 STHR R,/L CLK O sel D 00 - D 05 D 10 - D 15 D 20 - D 25 STB Vsel V0 - V10 S1 S2 S3 S309 VSS2 VDD2 (3.3/5.0 V) VSS1 VDD1 (3.3 V) STHL INV 103-bit bidirectional shift register Data register Latch D/A converter Output buffer Remark /xxx indicates active low signal.

Data Sheet S11269EJ1V1DS00 3 µ µ µ µ PD16640C 2. PIN CONFIGURATION (µ µ µ µ PD16640CN-xxx) Vsel VSS2 VDD2 V10 S309 S308 R,/L D 20 D 21 D 22 D 23 D 24 D 25 STB STHL V DD1 CLK V SS1 STHR D 10 D 11 D 12 D 13 D 14 D 15 D 00 D 01 D 02 D 03 D 04 D 05 VDD2 VSS2 O sel INV Copper Foil Surface S307 Remark O sel and Vsel pins are internally pulled up. Therefore, the number of input pins can be reduced by opening or short-circuiting these pins to VSS2 by means of TCP writing.

Data Sheet S11269EJ1V1DS004 µ µ µ µ PD16640C 3. PIN FUNCTIONS Pin Symbol Pin Name Description S1 to S309 Driver output Output 64 gray scale analog voltages converted from digital signals. O sel = H : 300 outputs (S1 - S150, S160 - S309) O sel = L : 309 outputs (S1 - S309) Output pins S151 to S159 are invalid in 300-output mode. D 00 to D05 Display data input Inputs 18-bit-wide display gray scale data (6 bits) x 3 dots (RGB). D 10 to D15 D X0 : LSB, DX5 : MSB D 20 to D25 R,/L Shift direction select input This pin inputs/outputs start pulses in cascade mode. Shift direction of shift register is as follows: R,/L = H : STHR input, S 1 → S309, STHL output R,/L = L : STHL input, S309 → S1, STHR output STHR Right shift start pulse I/O R,/L = H : Inputs start pulse R,/L = L : Outputs start pulse STHL Left shift start pulse I/O R,/L = H : Outputs start pulse R,/L = L : Inputs start pulse O sel Number of output selection Selects number of outputs. This pin is internally pulled up by VDD1 power supply. O sel = H : 300 outputs O sel = L : 309 outputs Vsel Driver voltage selection Selects driver voltage. This pin is internally pulled up by VDD2 power supply. Vsel = H : 300 outputs Vsel = L : 309 outputs CLK Shift clock input Inputs shift clock to shift register. Display data is loaded to data register at rising edge of this pin. When O sel = H, start pulse output goes high at rising edge of 100th clock after start pulse has been input, and serves as start pulse to driver in next stage. When O sel = L, start pulse output goes high at rising edge of 103rd clock after start pulse has been input, and serves as start pulse to driver in next stage. 103rd clock of driver in first stage serves as start pulse of driver in next stage. STB Latch input Contents of data register are latched at rising edge, transferred to D/A converter, and output as analog voltage corresponding to display data. Contents of internal shift register are cleared after STB has been input. One pulse of this signal is input when µPD16640C is started, and then device operates normally. For STB input timing, refer to 8. SWITCHING CHARACTERISTIC WAVEFORM. V0 to V10 γ-corrected power supply Inputs γ-corrected power from external source. VSS2 +0.1 V ≤ V10 ≤ V9 ≤ V8 ≤ V7 ≤ V6 ≤ V5 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤VDD2 −0.1 V or V SS2 +0.1 V ≤ V0 ≤ V1 ≤ V2 ≤ V3 ≤ V4 ≤ V5 ≤ V6 ≤ V7 ≤ V8 ≤ V9 ≤ V10 ≤VDD2 −0.1 V Maintain gray scale power supply during gray scale voltage output. INV Data inversion input Input data can be inverted when display data is loaded. INV = H : Inverts and loads input data. INV = L : Does not invert input data. VDD1 Logic circuit power supply 3.3 V ± 0.3 V VDD2 Driver circuit power supply Vsel = H : VDD2 = 3.3 V ± 0.3 V Vsel = L : VDD2 = 5.0 V ± 0.5 V VSS1 Logic ground Ground VSS2 Driver ground Ground Caution Be sure to turn on power in the order VDD1 , logic input, VDD2 , and gray scale power (V0 to V10), and turn off power in the reverse order, to prevent the µ µ µ µ PD16640C from being damaged by latchup. Be sure to observe this power sequence even during a transition period.

Data Sheet S11269EJ1V1DS00 5 µ µ µ µ PD16640C 4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The 11 major points on the γ-characteristic curve of the LCD panel are arbitrarily set by external power supplies V0 through V10. If the display data is 00H or 3FH, gray scale voltage V0 or V10 is output. If the display data is in the range 01H to 3EH, the high-order 3 bits select an external powers pair Vn+1, Vn. The low-order 3 bits evenly divide the range of Vn+1, Vn into eight segments by means of D/A conversion (however, the ranges from V9 to V8 and from V2 to V1 are divided into seven segments) to output a 64-grayscale voltage. D X5 (MSB) D X4 D X3 D X2 D X1 D X0 (LSB) D X5 D X4 D X3 Vn+1-Vn

000 V1-V2

001 V2-V3

010 V3-V4

011 V4-V5

100 V5-V6

101 V6-V7

110 V7-V8

111 V8-V9

High-order 3 bits : γ-corrected power selected (Vn+1-Vn) Low-order 3 bits : 3-bit D/A (range Vn-Vn+1 is divided into 7 or 8 segments) Figure 4-1. Relation between Input Data and γ γ γ γ -corrected Voltage 0.1 V 0.1 V 07F 1 7 1 F Input data (HEX) 27 2F 37 3F VDD2 VSS2 V10 gray scale supply specified by 00H 7 segments 8 segments 8 segments 8 segments 8 segments 8 segments 8 segments 7 segments gray scale supply specified by 3FH

Data Sheet S11269EJ1V1DS006 µ µ µ µ PD16640C Table 4-1. Relation between Input Data and Output Voltage Input Data D X5 D X4 D X3 D X2 D X1 D X0 Output Voltage 0 0 H 000000 V 0 0 1 H 000001 V2 + (V1 – V2) × 6/7 0 2 H 000010 V2 + (V1 – V2) × 5/7 0 3 H 000011 V2 + (V1 – V2) × 4/7 0 4 H 000100 V2 + (V1 – V2) × 3/7 0 5 H 000101 V2 + (V1 – V2) × 2/7 0 6 H 000110 V2 + (V1 – V2) × 1/7 0 7 H 000111 V 2 0 8 H 001000 V3 + (V2 – V3) × 7/8 0 9 H 001001 V3 + (V2 – V3) × 6/8

0 A H 001010 V3 + (V2 – V3) × 5/8

0 B H 001011 V3 + (V2 – V3) × 4/8

0 C H 001100 V3 + (V2 – V3) × 3/8

0 D H 001101 V3 + (V2 – V3) × 2/8

0 E H 001110 V3 + (V2 – V3) × 1/8

0 F H 001111 V 3

1 0 H 010000 V4 + (V3 – V4) × 7/8 1 1 H 010001 V4 + (V3 – V4) × 6/8 1 2 H 010010 V4 + (V3 – V4) × 5/8 1 3 H 010011 V4 + (V3 – V4) × 4/8 1 4 H 010100 V4 + (V3 – V4) × 3/8 1 5 H 010101 V4 + (V3 – V4) × 2/8 1 6 H 010110 V4 + (V3 – V4) × 1/8 1 7 H 010111 V 4 1 8 H 011000 V5 + (V4 – V5) × 7/8 1 9 H 011001 V5 + (V4 – V5) × 6/8

1 A H 011010 V5 + (V4 – V5) × 5/8

1 B H 011011 V5 + (V4 – V5) × 4/8

1 C H 011100 V5 + (V4 – V5) × 3/8

1 D H 011101 V5 + (V4 – V5) × 2/8

1 E H 011110 V5 + (V4 – V5) × 1/8

1 F H 011111 V 5

2 0 H 100000 V6 + (V5 – V6) × 7/8 2 1 H 100001 V6 + (V5 – V6) × 6/8 2 2 H 100010 V6 + (V5 – V6) × 5/8 2 3 H 100011 V6 + (V5 – V6) × 4/8 2 4 H 100100 V6 + (V5 – V6) × 3/8 2 5 H 100101 V6 + (V5 – V6) × 2/8 2 6 H 100110 V6 + (V5 – V6) × 1/8 2 7 H 100111 V 6 2 8 H 101000 V7 + (V6 – V7) × 7/8 2 9 H 101001 V7 + (V6 – V7) × 6/8

2 A H 101010 V7 + (V6 – V7) × 5/8

2 B H 101011 V7 + (V6 – V7) × 4/8

2 C H 101100 V7 + (V6 – V7) × 3/8

2 D H 101101 V7 + (V6 – V7) × 2/8

2 E H 101110 V7 + (V6 – V7) × 1/8

2 F H 101111 V 7

3 0 H 110000 V8 + (V7 – V8) × 7/8 3 1 H 110001 V8 + (V7 – V8) × 6/8 3 2 H 110010 V8 + (V7 – V8) × 5/8 3 3 H 110011 V8 + (V7 – V8) × 4/8 3 4 H 110100 V8 + (V7 – V8) × 3/8 3 5 H 110101 V8 + (V7 – V8) × 2/8 3 6 H 110110 V8 + (V7 – V8) × 1/8 3 7 H 110111 V 8 3 8 H 111000 V9 + (V8 – V9) × 6/7 3 9 H 111001 V9 + (V8 – V9) × 5/7

3 A H 111010 V9 + (V8 – V9) × 4/7

3 B H 111011 V9 + (V8 – V9) × 3/7

3 C H 111100 V9 + (V8 – V9) × 2/7

3 D H 111101 V9 + (V8 – V9) × 1/7

3 E H 111110 V 9

3 F H 111111 V 10

Data Sheet S11269EJ1V1DS00 7 µ µ µ µ PD16640C 4.1 γγγγ-corrected Power Circuit The reference power supply of the D/A converter consists of a ladder circuit with a total of 64 resistors, and resistance Σri between γ-corrected power pins differs depending on each pair of γ-corrected power pins. One pair of γ-corrected power pins consists of seven or eight series resistors, and resistance Σri in the figure below is indicated as the sum of the seven or eight resistors. The resistance ratio between the γ-corrected power pins (Σri ratio) is designed to be a value relatively close to the ratio of the γ-corrected voltages V1 to V9 (gray-scale voltages in 8 steps) used in an actual LCD panel. Under ideal conditions where there is no difference between the two, therefore, there is no voltage difference between the voltage of the γ-corrected power supplies and the gray-scale voltages in 8 steps of the resistor ladder circuits of the µPD16640C, and no current flows into the γ-corrected power pins V1 to V9. As a result, a voltage-follower circuit is not necessary. Figure 4-2. γ γ γ γ -corrected Power Circuit V10 R 0 = 2.39 kΩ PD16640C R 1 = Σ ri = 4.45 kΩ i10 i = 1 R 2 = Σ ri = 6.19 kΩ i = 1 R 3 = Σ ri = 3.58 kΩ i = 1 R 4 = Σ ri = 2.15 kΩ i = 1 R 5 = Σ ri = 2.03 kΩ i = 1 R 6 = Σ ri = 1.61 kΩ i = 1 R 7 = Σ ri = 2.03 kΩ i = 1 R 8 = Σ ri = 3.39 kΩ i = 1 R 9 = 2.55 kΩ µ γ-corrected power pin γ-corrected resistor Sum of eight γ-corrected resistors

Data Sheet S11269EJ1V1DS008 µ µ µ µ PD16640C 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format : 6 bits x RGB(3 dots) Input width : 18 bits (1) R,/L = H (right shift) Output S 1 S2 S3 … S308 S309 Data D 00 to D05 D 10 to D15 D 20 to D25 … D 10 to D15 D 20 to D25 (2) R,/L = L (left shift) Output S 1 S2 S3 … S299 S300 Data D 00 to D05 D 10 to D15 D 20 to D25 … D 10 to D15 D 20 to D25 6. OPERATION OF OUTPUT BUFFER The output buffer consists of an operational amplifier circuit that does not perform precharge operation. Therefore, driver output current IVOH1/2 is the charging current to the LCD, and IVOL1/2 is the discharging current. Figure 6-1. LCD Panel Driving Waveform (IVOL1/2/IVOH1/2 ) Write (IVOL1/2/IVOH1/2 ) VDD2 Sn VSS2 Write 1 horizontal period

Data Sheet S11269EJ1V1DS00 9 µ µ µ µ PD16640C 7. ELECTRICAL SPECIFICATIONS Parameter Symbol Ratings Unit Logic power supply V DD1 –0.3 to +4.5 V Driver power supply V DD2 –0.3 to +6.0 V Input voltage V I –0.3 to VDD1,2 + 0.3 V Output voltage V O –0.3 to VDD1,2 + 0.3 V Operating ambient temperature T A –10 to +75 °C Storage temperature T stg –55 to +125 °C Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings. Recommended Operating Range (T A = –10 to +75 °C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Logic supply voltage V DD1 3.0 3.3 3.6 V Driver supply voltage V DD2 Vsel = H 3.0 3.3 3.6 V Vsel = L 4.5 5.0 5.5 V High-level input voltage V IH R,/L, CLK, STB, Osel, Vsel, 0.7VDD1 VDD1 V Low-level input voltage V IL STHR(STHL), D 00-D05,D10-D15, D20-D25 00 . 3 V DD1 V γ-corrected supply voltage V 0-V10 VSS2 +0.1 V DD2 −0.1 V Maximum clock frequency f MAX. 55 MHz

Data Sheet S11269EJ1V1DS0010 µ µ µ µ PD16640C VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Input leakage current I IL D 00-D05, D10-D15, D20-D25, R,/L, STB ±1.0 µ A Pull-up resistor R PU VDD1 = 3.3 V, Osel, Vsel 40 100 250 k Ω High-level output voltage V OH STHR(STHL),IO =−1.0 mA V DD1 − 0.5 V Low-level output voltage V OL STHR(STHL),IO =+1.0 mA 0.5 V Static current consumption ofIvn1 VDD1 =3.3 V V 0-V1 105 210 420 µ A γ -corrected supply current V n−Vn+1=0.5 V V 1-V2 56 113 226 µ A (VDD2 = 3.3 V or 5.0 V) V2-V3 41 82 164 µ A V3-V4 70 140 280 µ A V4-V5 117 234 468 µ A V5-V6 124 248 496 µ A V6-V7 156 313 626 µ A V7-V8 124 248 496 µ A V8-V9 74 149 298 µ A V9-V10 99 198 396 µ A Driver output current (VDD2 = 3.3 V) IVOH1 VOUT =2.7 V, Vx=3.2 VNote1 VDD1 =V DD2 =3.3 V −0.16 −0.08 mA IVOL1 VOUT =0.6 V, Vx=0.1 VNote1 VDD1 =V DD2 =3.3 V 0.07 0.14 mA Driver output current (VDD2 = 5.0 V) IVOH2 VOUT =4.4 V, Vx=4.9 VNote1 VDD1 =3.3 V, VDD2 =5.0 V −0.24 −0.12 mA IVOL2 VOUT =0.6 V, Vx=0.1 VNote1 VDD1 =3.3 V, VDD2 =5.0 V 0.10 0.20 mA Output voltage deviation ΔVO VDD1 =3.3 V, VDD2 =3.3 V or 5.0 V, VOUT = 0.5 V,1.5 V, 2.5 VNote1 ±10 ±20 mV Output voltage deviation ΔVP-P Input data ±5m V Output voltage range V O Input data : 00H to 3FH V SS2 + 0.1 V DD2 − 0.1 V Dynamic logic current consumption IDD1 No loadNote2 0.5 2.5 mA Dynamic driver current consumption IDD21 No load, VDD2 =3.3 VNote2 3.0 10 mA IDD22 No load, VDD2 =5.0 VNote2 3.0 10 mA Notes 1. VX is output voltage of analog output pins S1 to S309. VOUT is the voltage applied to analog output pins S1 to S309. 2. The STB cycle is specified at 31 µ s and fCLK = 16 MHz.

Data Sheet S11269EJ1V1DS00 11 µ µ µ µ PD16640C VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Start pulse delay time t PLH1 C L = 15 pF 7 12 ns tPHL1 71 2 n s Driver output delay time t PLH21 VDD2 =3.3 V V O :0.1 V 2.6 µ s tPLH31 2 kΩ +75 pF x 2 → 3.2 V 3.0 10 µ s tPHL21 VO :3.2 V 2.4 µ s tPHL31 → 0.1 V 3.2 10 µ s Driver output delay time t PLH22 VDD2 =5.0 V V O :0.1 V 2.2 µ s tPLH32 2 kΩ +75 pF x 2 → 4.9 V 2.9 10 µ s tPHL22 VO :4.9 V 2.6 µ s tPHL32 → 0.1 V 3.6 10 µ s Input capacitance C I1 STHR(STHL), TA=25 °C1 0 2 0 p F C I2 V0-V10, TA = 25 °C 60 100 pF C I3 STHR(STHL), other than V0-V10, TA=25 °C 10 15 pF Timing Requirements (TA = −−−−10 to +75 °C, VDD1 = 3.3 V ±±±± 0.3 V, VSS1 = 0 V, tr = tf = 3.0 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock pulse width PW CLK 18 ns Clock pulse high period PW CLK (H) 4n s Clock pulse low period PW CLK (L) 4n s Data setup time t SETUP1 4n s Data hold time t HOLD1 0n s Start pulse setup time t SETUP2 4n s Start pulse hold time t HOLD2 0n s INV setup time t SETUP4 4n s INV hold time t HOLD4 0n s Start pulse low period t SPL 2C L K Start pulse rise time t SPR1 O sel=H 100 CLK tSPR2 O sel=L 103 CLK Final data timing t SETUP3 1C L K CLK-STB time t INV 1C L K STB-CLK time t LDT 1C L K Time between STB and start pulse tCLK-STB CLK ↑→ STB ↑ 7n s STB-POL time t STB-CLK STB ↑ → CLK ↑ 7n s

Data Sheet S11269EJ1V1DS0012 µ µ µ µ PD16640C 8. SWITCHING CHARACTERISTIC WAVEFORM(R,/L= H) Unless otherwise specified, the input level is defined to VIH = 0.7 VDD1 , VIL = 0.3 VDD1 . tSETUP2 D n0 - D n5 VOUT CLK STHR (1st Dr.) STHL (1st Dr.) STB tHOLD1tSETUP1 tPLH1 tSETUP3 tr 90% 10% tINV VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 VDD1 VSS1 tHOLD2 PW CLK(L) PW CLK tSPL tf D 1 - D 3 D 1 - D 3 D 4 - D 6D 304 - D 306 D 307 - D 309 D 310 - D 312 D 3067 - D 3069 D 3070 - D 3072D 4 - D 6 1024 10252 104 1053 103 INVALID INVALID tCLK-STB PW CLK(H) tSPR1/2 tLDT Hi-Z tPLH31/32 Target Voltage ±0.1 VDD2 6-bit accuracy tPLH21/22 tPHL31/32 tPHL21/22 1023 D 3064 - D 3066 tPHL1 INV tSETUP4 VDD1 VSS1 INVALID INVALID tHOLD4 tSTB-CLK

Data Sheet S11269EJ1V1DS00 13 µ µ µ µ PD16640C 9. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD16640C. For more details, refer to the Semiconductor Device Mounting Technology Manual(C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µ PD16640CN- xxx : TCP(TAB Package) Mounting Condition Mounting Method Condition Thermocompression Soldering Heating tool 300 to 350 °C, heating for 2 to 3 sec ; pressure 100g(per solder) ACF (Adhesive Conductive Film) Temporary bonding 70 to 100 °C ; pressure 3 to 8 kg/cm 2; time 3 to 5 sec. Real bonding 165 to 180 °C pressure 25 to 45 kg/cm2 time 30 to 40secs(When using the anisotropy conductive film SUMIZAC1003 of Sumitomo Bakelite,Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time.

Data Sheet S11269EJ1V1DS0014 µ µ µ µ PD16640C [MEMO]

Data Sheet S11269EJ1V1DS00 15 µ µ µ µ PD16640C NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µ µ µ µ PD16640C Reference Documents NEC Semiconductor Device Reliability/Quality Control System(C10983E) Quality Grades to NEC’s Semiconductor Devices(C11531E)• The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

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