PD161602AB

PD161602AB_15 RENESAS | Alldatasheet

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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. © 2001 MOS INTEGRATED CIRCUIT µµµµ PD161602A/B 360/396-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DATA SHEET Document No. S15381EJ1V0DS00 (1st edition) Date Published May 2002 NS CP (K) Printed in Japan The mark # shows major revised points.

DESCRIPTION

The µ PD161602A/B is a source driver for TFT-LCDs supporting 64 gray-scale display and can operate with a supply voltage of 2.5 V for the logic block and 5.0 V for the driver block. Data input as 6-bit x 3-dot digital data is output as 64 γ -corrected values using an internal D/A converter and 5 external power modules, thus achieving a 260,000-color (full-color) display. In addition, the difference with A articles and B articles is only a difference in γ compensation resistance.

FEATURES

• CMOS level input
• 360/396 outputs
• Input of 6 bits (gray-scale data) by 3 dots
• Capable of outputting 64 values by means of 5 external power modules and a D/A converter
• Output dynamic range: VSS2 to VDD2
• High-speed data transfer: fCLK = 15 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.5 V)
• Level inversion γ -correction power supply is possible
• Logic power supply voltage (VDD1): 2.2 to 3.6 V
• Driver power supply voltage (VDD2): 4.5 to 5.5 V

ORDERING INFORMATION

µ PD161602AP Chip µ PD161602BP Chip Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives.

µµµµPD161602A/B 1. BLOCK DIAGRAM STHL VDD1 VSS1 VDD2 VSS2 S2S1 V0 to V4 D00 to D05 C1 C2 C131 C132 STB CLK 132-bit bidirectional shift register Data register Latch Level shifter D/A converter Output buffer R,/L STHR D10 to D15 D20 to D25 S3 S396 POL BA Osel INBUF Mode control γ control BIAS control INV CM AP VCOM BUF VCsel VCOM GAM TESTO2 TESTO1 TESTIN VDD1 Remark /xxx indicates active low signal.

Data Sheet S15381EJ1V0DS 3 µµµµPD161602A/B 2. PIN CONFIGURATION (Pad Layout) Chip size: 16980 x 1620 µm2 Bump size (Input/VCOM/test/dummy): 86 x 80 µm2 Bump size (Output): 33 x 120 µm2 Alignment Mark (µm) X: –8284.4 Y: 600 X: 8284.4 Y: 600 510 509 500 499 397 398 407 408 X(+ Y(- 60 µm 60 µm 72 µm 72 µm 72 µm 72 µm 40 µm plover Driver output pad 33 µm 120 µm 35.5 µm Bump size 3960 µm2 Input/VCOM/test/dummy pad 86 µm Bump size 6880 µm2 80 µm

µµµµPD161602A/B Table 2–1. Pad Layout (1/3) No. Pad Name X [µm] Y [ µm] No. Pad Name X [µm] Y [ µm] No. Pad Name X [µm] Y [ µm]

Data Sheet S15381EJ1V0DS 5 µµµµPD161602A/B Table 2–1. Pad Layout (2/3) No. Pad Name X [µm] Y [ µm] No. Pad Name X [µm] Y [ µm] No. Pad Name X [µm] Y [ µm]

µµµµPD161602A/B Table 2–1. Pad Layout (3/3) No. Pad Name X [µm] Y [ µm] No. Pad Name X [µm] Y [ µm] No. Pad Name X [µm] Y [ µm] 395 S395 -7860.0 667.7 453 V2 25.1 -687.0 396 S396 -7900.0 512.2 454 V2 125.0 -687.0 397 Dummy1 -8031.4 687.0 455 V2 225.0 -687.0 398 Dummy2 -8367.0 347.0 456 Dummy21 400.0 -687.0 399 Dummy3 -8367.0 247.0 457 V1 575.1 -687.0 400 Dummy4 -8367.0 147.0 458 V1 675.0 -687.0 401 Dummy5 -8367.0 47.0 459 V1 775.0 -687.0 402 Dummy6 -8367.0 -53.1 460 Dummy22 950.0 -687.0 403 Dummy7 -8367.0 -153.1 461 V0 1125.1 -687.0 404 Dummy8 -8367.0 -253.1 462 V0 1225.1 -687.0 405 Dummy9 -8367.0 -353.1 463 V0 1325.0 -687.0 406 Dummy10 -8367.0 -453.2 464 Dummy23 1500.1 -687.0

Data Sheet S15381EJ1V0DS 7 µµµµPD161602A/B 3. PIN FUNCTIONS (1/2) Pin Symbol Pin Name Pad No. I/O Description S1 to S396 Driver output 1 to 396 Output The D/A converted 64-gray-scale analog voltage is output. Osel = L: S1 to S396 Osel = H: S19 to S378 D00 to D05 477 to 472 D10 to D15 471 to 466 D20 to D25 Display data input 442 to 437 Input The display data is input with a width of 18 bits, viz., the gray scale data (6 bits) by 3 dots (1 pixels). D X0: LSB, DX5: MSB R,/L Shift direction control input 429 Input These refer to the shift direction control input. The shift directions of the shift registers are as follows. <When in O sel = L> R,/L = L (left shift): STHL (input), S396 → S1 → STHR (output) R,/L = H (right shift) : STHR (input), S1 → S396 → STHL (output) <When in Osel = H> R,/L = L (left shift): STHL (input), S378 → S19 → STHR (output) R,/L = H (right shift) : STHR (input), S19 → S378 → STHL (output) STHR Right shift start pulse input/output

498 I/O

410 I/O

These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift): STHR input, STHL output R,/L = L (left shift): STHL input, STHR output CLK Shift clock input 443 Input This pin is the shift clock input of the shift register. Display data is captured into the data register at the rising edge. O sel = L: The start pulse output enters high level at the rising edge of the 132 th clock following the start pulse input, and becomes the start pulse of the next level driver. The 133th clock of the first driver becomes the start pulse input of the next driver O sel = H: The start pulse output enters high level at the rising edge of the 120th clock following the start pulse input, and becomes the start pulse of the next driver. The 121th clock of the first driver becomes the start pulse input of the next driver. STB Latch input 436 Input A timing signal that latches the contents of the data register. When an H level is read at the rising edge of CLK, the contents of the data register are latched and transferred to the D/A converter, and analog voltage corresponding to the display data is output. Also, because the internal operation via CLK continues even after the STB latch, do not stop CLK. The contents of the shift register are cleared at the rising edge of STB. Following a 1-pulse input at startup, this IC will operate normally. Note that the output switch is turned off at the rising edge of STB. For the STB input timing, refer to Switching Characteristics Waveform. POL Polarity inversion signal 434 Input This pin inverts the output polarity. The polarity inversion signal data is captured at the rising edge of STB. The γ -resistor is switched in accordance with the positive/negative polarity. POL = L: Negative polarity POL = H: Positive polarity INV Data inversion 465 Input This pin inverts the input data. Input data in synchronization with the shift clock. INV = L: Normal input INV = H: Data inversion input VCOM COM amplitude output

409 Output This pin inverts the signal input from the POL pin and outputs it following conversion to

the VDD2 potential at the rising edge of STB. When the VCOM output is not used, VCsel must be fixed to L.

µµµµPD161602A/B (2/2) Pin Symbol Pin Name Pad No. I/O Description VCsel COM amplitude output fixing signal 428 Input The VCOM output is fixed to L. When the VCOM output is not used, VC sel needs to be fixed to L. VC sel = L: VCOM output fixed to L VCsel = H: VCOM signal output in correspondence with POL signal CM 8-color display mode switching 433 Input The operating mode is switched to 8-color mode. In this mode, turn off the γ - resistor, amplifier, and BIAS circuit. However, when the γ -correction power supply is input externally, the γ -circuit current will flow continuously. CM = L: Normal display mode CM = H: 8-color display mode AP Output SW ON/OFF 435 Input This pin turns ON/OFF the BIAS circuit and turns on the output SW and amplifier. When AP is H, the amplifier is set and the LCD is driving. The amplifier output and output SW are turned on at the rising edge of AP, starting the LCD drive. Note that the output SW is turned off at the rising edge of STB and the output becomes Hi-Z. For the AP input timing, refer to Switching Characteristics Waveform. GAM External γ usage selection 432 Input When the γ -correction power supply is input externally, switch GAM to H. If two or more chips are used, be sure to input the γ -correction power supply externally. Figure 4–1 shows an input example of the γ -correction power supply. GAM = L: External γ -correction power supply not input (open) GAM = H: External γ -correction power supply input Osel Driver output count switching 430 Input The output count can be selected. When O sel = H, the unused pins S1 to S18 and S379 to S396 always become Hi-Z. Osel = L: 396 outputs Osel = H: 360 outputs V0 to V4 γ -corrected power supplies 461 to 463, 457 to 459, 453 to 455, 449 to 451, 445 to 447 − These pins input the γ -corrected power supplies from outside, the relationship below must be observed. Also, be sure to stabilize the gray-scale-level power supply during gray-scale voltage output. V SS2 ≤ V4 ≤ V3 ≤ V2 ≤ V1 ≤ V0 ≤ VDD2 BA BIAS current adjustment function 431 Input This pin adjusts the BIAS current. Select either the high power mode or low power mode. BA = L: Low power mode BA = H: high power mode TESTIN TEST input pin 480 Input Set to H or leave open TESTO1, TESTO2 TEST output pin 478, 479 Output Leave open. VDD1 Logic power supply 416 to 418, 482 to 484 − 2.2 to 3.6 V VDD2 Driver power supply 412 to 414, 494 to 496 − 4.5 to 5.5 V VSS1 Logic ground 420 to 422, 486 to 488 − Ground VSS2 Driver ground 424 to 426, 490 to 492 − Ground Dummy1 to dummy40 Dummy 397 to 408, 411, 415, 419, 423, 427, 444, 448, 452, 456, 460, 464, 481, 485, 489, 493, 487, 499 to 510 − This pin is dummy. Caution To avoid latchup failure, the sequence when turning on the power must be V DD1 →→→→ logic input →→→→ VDD2 →→→→gray-scale power supply (V0 to V4), and the reverse sequence when turning off the power. Follow this sequence during shift periods as well.

Data Sheet S15381EJ1V0DS 9 µµµµPD161602A/B 4. EXAMPLES OF EACH SINGAL INPUT OR OUTPUT Examples of the input/output timing of each signal during white and black display are shown below. Figure 4–1. Timing Chart STB AP POL DATA DATA = 000000 DATA = 111111 VCOM 260,000-color display mode (CM = L) UndefinedOUT Hi-Z Hi-Z Hi-Z Hi-Z Black level Black level White level White level 8-color display mode OUT White level White levelBlack level Black level LSB MSB MSB used in 8-color display mode

Data Sheet S15381EJ1V0DS10 µµµµPD161602A/B 4.1 γγγγ-Correction Power Supply Connection Example The µ PD161602A/B enables customization of the γ -correction power supply on both the positive and negative polarity sides (refer to 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE). Consequently, a γ -correction power supply does not have to be input externally when a single source-driver chip is being used in the panel. Multiple chips can also be used without having to input a γ -correction power supply externally because the error between the chips can be absorbed by shorting the γ -correction power supply pins, as shown in Figure 4–2. Figure 4–2. γγγγ -Correction Power-Supply Connection Example /K6D PD161602 VDD2 VSS2 V0 V1 V2 V3 V4 VSS2 VDD2 External power supply input Open <Example 1 (GAM = L)>

• Single chip /K6D PD161602 VDD2 VSS2 V0 V1 V2 V3 V4 VSS2 VDD2 <Example 2 (GAM = H)> /K6D PD161602 VDD2 VSS2 V0 V1 V2 V3 V4 VSS2 VDD2 <Example 1 (GAM = L)>
• Multiple chips /K6D PD161602 VDD2 VSS2 V0 V1 V2 V3 V4 VSS2 VDD2 Vn - Vn short /K6D PD161602 VDD2 VSS2 V0 V1 V2 V3 V4 VSS2 VDD2 <Example 2 (GAM = H)> /K6D PD161602 VDD2 VSS2 V0 V1 V2 V3 V4 VSS2 VDD2 External power supply input External power supply input External power supply input External power supply input External power supply input

Data Sheet S15381EJ1V0DS 11 µµµµPD161602A/B

4.2 AP Signal Timing

The driver power consumption is dependent on the high period of the AP signal because the operational amplifier in the IC is operation and current is constantly flowing in this period. A chart indication the recommended timing of inputting the AP signal vis-a-vis the STB signal is shown below. Hi-Z MIN. 10 µs Amp driving 10 to 15 µs SW driving STB AP Note that the ideal AP signal high period differs depending on the load of the liquid crystal. The AP period must therefore be able to be adjusted using a controller. The AP signal can also be used as shown below. However, in these cases, be sure to perform sufficient evaluation before use. <When SW drive in not used> Only the amp is driven (SW drive is not used) if one horizontal period is short (40 µs or less) or the liquid crystal load is large (50 pF or more). STB AP <When the AP signal high period is 10 µµµµs or less> The amp drive period is shortened and the SW drive period lengthened when one horizontal period is long (100 µs or more) and the liquid crystal load is small (20 pF). STB AP

Data Sheet S15381EJ1V0DS12 µµµµPD161602A/B

4.3 CLK Signal Input

Input at least 4 clocks of the CLK signal after the rising of the STB signal. STB CLK STH Internal latch signal1 Internal latch signal2 Internal latch signal3 /1 2 3 4 5 61 2 3 4 7 8 Note Invalid D0 to D3 D4 to D6 D7 to D9 D10 to D12 D13 to D15 D16 to D18 D19 to D21 Note Note Note Internal latch signal : It is the signal that do latch the display data put in data register in output latch circuit. 5. MODE EXPLANATION Normal Mode/ 8-clor Display Mode CM POL Data Driver Output Status Driver Output (in normally white) MSB = H White level displayH MSB = L Black level display MSB = H White level display H L MSB = L 8-color mode Black level display All bit = H White level displayH All bit = L Black level display All bit = H White level display L L All bit = L 260,000-color mode Black level display

Data Sheet S15381EJ1V0DS 13 µµµµPD161602A/B 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The relation between input data and output voltage are shown in Table 6 −2, 6−3. Any 3 major points V1 to V3 from the LCD panel γ-characteristics curve can be used as the external power supplies. The relationship V0 to V4 external power supplies and γ-correction resistance is shown in Table 6−1, Figure 6−1. Table 6–1. Relationship between External Power Supply Pins and γγγγ-correction Resistance Pin Name Voltage (V) Resistance ( Ω) V0 5.0 0 V1 3.5 7,500 V2 2.5 12,500 V3 1.5 17,500 V4 0 25,000 Figure 6–1. Relationship between External Power Supply Pins and γγγγ-correction Resistance VDD2 VSS2 7500 Ω 5000 Ω 5000 Ω 7500 Ω This external power supply pins (V0 to V4) can customize the γ-correction voltage by selecting the desired voltage from one of 250 divisions of the string resistor between V SS2 and VDD2, which generated γ-correction voltage. Note that the voltage can be selected individually for both positive and negative polarity.

Data Sheet S15381EJ1V0DS14 µµµµPD161602A/B Table 6−−−−2. Relation of Input Data and Output Voltage in µµµµPD161602A Input Data Gray Scale Positive Polarity Side (V) Negative Polarity Side (V) Positive Polarity Side (Ω) Negative Polarity Side (Ω) Input Data Gray Scale Positive Polarity Side (V) Negative Polarity Side (V) Positive Polarity Side (Ω) Negative Polarity Side (Ω) 00H 0 5.000 0.000 0 25000 20H 32 2.480 2.720 12600 11400 01H 1 4.920 0.080 400 24600 21H 33 2.460 2.760 12700 11200 02H 2 4.760 0.260 1200 23700 22H 34 2.420 2.800 12900 11000 03H 3 4.540 0.480 2300 22600 23H 35 2.400 2.820 13000 10900 04H 4 4.280 0.760 3600 21200 24H 36 2.360 2.860 13200 10700 05H 5 3.960 1.080 5200 19600 25H 37 2.340 2.900 13300 10500 06H 6 3.840 1.200 5800 19000 26H 38 2.300 2.940 13500 10300 07H 7 3.740 1.300 6300 18500 27H 39 2.280 2.960 13600 10200 08H 8 3.640 1.400 6800 18000 28H 40 2.240 3.000 13800 10000 09H 9 3.540 1.520 7300 17400 29H 41 2.220 3.040 13900 9800 0AH 10 3.480 1.580 7600 17100 2AH 42 2.180 3.080 14100 9600 0BH 11 3.400 1.660 8000 16700 2BH 43 2.160 3.100 14200 9500 0CH 12 3.320 1.740 8400 16300 2CH 44 2.140 3.140 14300 9300 0DH 13 3.240 1.840 8800 15800 2DH 45 2.120 3.180 14400 9100 0EH 14 3.160 1.920 9200 15400 2EH 46 2.080 3.200 14600 9000 0FH 15 3.100 2.000 9500 15000 2FH 47 2.060 3.240 14700 8800 10H 16 3.060 2.060 9700 14700 30H 48 2.040 3.260 14800 8700 11H 17 3.000 2.100 10000 14500 31H 49 2.020 3.300 14900 8500 12H 18 2.960 2.160 10200 14200 32H 50 1.980 3.340 15100 8300 13H 19 2.900 2.220 10500 13900 33H 51 1.960 3.360 15200 8200 14H 20 2.860 2.280 10700 13600 34H 52 1.920 3.400 15400 8000 15H 21 2.820 2.320 10900 13400 35H 53 1.900 3.440 15500 7800 16H 22 2.780 2.360 11100 13200 36H 54 1.860 3.480 15700 7600 17H 23 2.740 2.400 11300 13000 37H 55 1.840 3.520 15800 7400 18H 24 2.700 2.440 11500 12800 38H 56 1.780 3.580 16100 7100 19H 25 2.680 2.480 11600 12600 39H 57 1.740 3.620 16300 6900 1AH 26 2.640 2.520 11800 12400 3AH 58 1.680 3.680 16600 6600 1BH 27 2.620 2.560 11900 12200 3BH 59 1.620 3.760 16900 6200 1CH 28 2.600 2.580 12000 12100 3CH 60 1.520 3.860 17400 5700 1DH 29 2.560 2.620 12200 11900 3DH 61 1.360 4.040 18200 4800 1EH 30 2.540 2.660 12300 11700 3EH 62 1.180 4.220 19100 3900 1FH 31 2.500 2.700 12500 11500 3FH 63 0.400 5.000 23000 0 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 01 0 2 0 3 0 gray-scale 40 50 60 γ- curve

Data Sheet S15381EJ1V0DS 15 µµµµPD161602A/B Table 6−−−−3. Relation of Input Data and Output Voltage in µµµµPD161602B Input Data Gray Scale Positive Polarity Side (V) Negative Polarity Side (V) Positive Polarity Side (Ω) Negative Polarity Side (Ω) Input Data Gray Scale Positive Polarity Side (V) Negative Polarity Side (V) Positive Polarity Side (Ω) Negative Polarity Side (Ω) 00H 0 5.000 0.000 0 25000 20H 32 2.780 2.400 11100 13000 01H 1 4.980 0.020 100 24900 21H 33 2.760 2.440 11200 12800 02H 2 4.960 0.060 200 24700 22H 34 2.720 2.480 11400 12600 03H 3 4.920 0.100 400 24500 23H 35 2.680 2.520 11600 12400 04H 4 4.880 0.140 600 24300 24H 36 2.660 2.540 11700 12300 05H 5 4.800 0.220 1000 23900 25H 37 2.620 2.580 11900 12100 06H 6 4.720 0.300 1400 23500 26H 38 2.600 2.620 12000 11900 07H 7 4.600 0.440 2000 22800 27H 39 2.560 2.660 12200 11700 08H 8 4.460 0.580 2700 22100 28H 40 2.520 2.700 12400 11500 09H 9 4.320 0.740 3400 21300 29H 41 2.480 2.740 12600 11300 0AH 10 4.160 0.920 4200 20400 2AH 42 2.460 2.780 12700 11100 0BH 11 4.000 1.080 5000 19600 2BH 43 2.400 2.820 13000 10900 0CH 12 3.860 1.240 5700 18800 2CH 44 2.360 2.860 13200 10700 0DH 13 3.780 1.320 6100 18400 2DH 45 2.340 2.900 13300 10500 0EH 14 3.700 1.420 6500 17900 2EH 46 2.300 2.940 13500 10300 0FH 15 3.620 1.500 6900 17500 2FH 47 2.260 2.980 13700 10100 10H 16 3.540 1.600 7300 17000 30H 48 2.220 3.020 13900 9900 11H 17 3.460 1.680 7700 16600 31H 49 2.180 3.060 14100 9700 12H 18 3.380 1.760 8100 16200 32H 50 2.140 3.100 14300 9500 13H 19 3.320 1.820 8400 15900 33H 51 2.100 3.160 14500 9200 14H 20 3.280 1.880 8600 15600 34H 52 2.040 3.220 14800 8900 15H 21 3.220 1.940 8900 15300 35H 53 2.000 3.260 15000 8700 16H 22 3.160 2.000 9200 15000 36H 54 1.960 3.320 15200 8400 17H 23 3.120 2.040 9400 14800 37H 55 1.900 3.380 15500 8100 18H 24 3.060 2.100 9700 14500 38H 56 1.840 3.420 15800 7900 19H 25 3.040 2.140 9800 14300 39H 57 1.780 3.520 16100 7400 1AH 26 3.000 2.180 10000 14100 3AH 58 1.700 3.600 16500 7000 1BH 27 2.960 2.220 10200 13900 3BH 59 1.580 3.720 17100 6400 1CH 28 2.940 2.240 10300 13800 3CH 60 1.460 3.840 17700 5800 1DH 29 2.900 2.280 10500 13600 3DH 61 1.260 4.060 18700 4700 1EH 30 2.860 2.320 10700 13400 3EH 62 1.080 4.280 19600 3600 1FH 31 2.820 2.360 10900 13200 3FH 63 0.400 5.000 23000 0 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 01 0 2 0 3 0 gray-scale 40 50 60 γ- curve

Data Sheet S15381EJ1V0DS16 µµµµPD161602A/B

6.1 Connection between γγγγ-correction Resistance, Power Supply, and GND Pin

Connection of γ- compensation resistance power supply (V0-V4) and a power supply pin (VDD2 and VSS2) is indicated below to be γ- compensation resistance of µPD161602 A/B. By setup of a GAM pin, as for γ-compensation resistance, connection changes the highest minimum potential between VDD2-VSS2 or among V0-V4. Figure 6−−−−2. GAM Pin Function Positive polarity γ -selectionSW GAM GAMSW1 SW2 SW1 SW2 SW1 SW2 GAM = L GAM = H VDD2 VSS2 Negative polarity

Data Sheet S15381EJ1V0DS 17 µµµµPD161602A/B 7. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 6 bits x RGBs (3 dots) Input width: 18 bits (1-pixel data) R,/L = H (Right shift), Osel = L (396 outputs) Output S 1 S2 S3 S4 ... S395 S396 Data D 00 to D05 D10 to D15 D20 to D25 D00 to D05 ... D 10 to D15 D20 to D25 R,/L = L (Left shift), Osel = L (396 outputs) Output S 1 S2 S3 S4 ... S395 S396 Data D 00 to D05 D10 to D15 D20 to D25 D00 to D05 ... D 10 to D15 D20 to D25

Data Sheet S15381EJ1V0DS18 µµµµPD161602A/B 8. ELECTRICAL SPECIFICATIONS Parameter Symbol Rating Unit Logic Part Supply Voltage V DD1 –0.3 to +4.5 V Driver Part Supply Voltage V DD2 –0.3 to +6.0 V Input Voltage V I –0.3 to VDD1,2 + 0.3 V Output Voltage V O –0.3 to VDD1,2 + 0.3 V Operating Ambient Temperature T A –20 to +75 °C Storage Temperature T stg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (T A = –20 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Logic Part Supply Voltage V DD1 2.2 3.6 V Driver Part Supply Voltage V DD2 4.5 5.0 5.5 V High-Level Input Voltage V IH 0.7 VDD1 VDD1 V Low-Level Input Voltage V IL 00 . 3 V DD1 V γ -Corrected Voltage V 0 to V4 VSS2 VDD2 V Clock Frequency f CLK 15 MHz

Data Sheet S15381EJ1V0DS 19 µµµµPD161602A/B Parameter Symbol Condition MIN. TYP. MAX. Unit Input Leak Current I IL D00-D05, D10-D15, D20-D25, R,/L, STB, CLK, STHR(L), INV, CM, AP, Osel, BA, POL, GAM, VCsel ±1.0 µA Input Current I IL2 TESTIN 10 40 200 µA High-Level Output Voltage V OH STHR (STHL), IOH = –1.0 mA V DD1 – 0.5 V Low-Level Output Voltage V OL STHR (STHL), IOL = +1.0 mA 0.5 V VOH2 VDD2 = 5.0 V, IO = –1.0 mA V DD2 – 0.5 VVCOM Output Voltage VOL2 VDD2 = 5.0 V, IO = +1.0 mA 0.5 V γ -Correction Power-supply Static Current Consumption Iγ V0 = 5.0 V, V4 = 0 V (when in γ -correction power mode) 100 200 400 µA IVOH1 VDD2 = 5.0 V, VOUT = VX – 1.0 V Note1 Input data: 1FH –0.5 –0.15 mADriver Output Current (AMP drive) IVOL1 VDD2 = 5.0 V, VOUT = VX + 1.0 V Note1 Input data: 20H 0.15 0.50 mA IVOH2 VDD2 = 5.0 V, VOUT = VX – 1.0 V Note1 Input data: 1FH –50 –15 µADriver Output Current (Switch drive) IVOL2 VDD2 = 5.0 V, VOUT = VX + 1.0 V Note1 Input data: 20H 15 40 µA VOH3 VDD2 = 5.0 V, IO = –50 uA V DD2 – 0.5 VDriver Output Current (8-color display mode) VOL3 VDD2 = 5.0 V, IO = +50 uA 0.5 V Output Voltage Deviation ∆VO VDD1 = 2.5 V, VDD2 = 5.0 V, VOUT = 2.5 V Note1 ±10 ±20 mV Output Voltage Range V O Input data: 00H to 3FH V SS2 + 0.05 V DD2 – 0.05 V Logic Part Dynamic Current Consumption IDD1 With no load Note2 0.4 0.8 mA Driver Part Dynamic Current Consumption IDD2 VDD = 5.0 V, with no load Note2 0.9 1.5 mA Notes 1. VX refers to the output voltage of analog output pins S 1 to S396. VOUT refers to the voltage applied to analog output pins S 1 to S396. 2. fCLK = 15 MHz, STB cycle = 60 µs, AP pulse width = 15 µs, BA = L (low power mode)

Data Sheet S15381EJ1V0DS20 µµµµPD161602A/B Switching Characteristics (TA = –20 to +75°C, VDD1 = 2.2 to 3.6 V, VDD2 = 5.0 V ±±±± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit tPLH1 25 nsStart Pulse Delay Time tPHL1 CL = 15 pF 25 ns tPLH2H 12 µsDriver Output Delay Time (High power mode) tPHL2H CL = 30 pF AP↓ →VOUT – 100 mV or VOUT + 100 mV 12 µs tPLH2L 15 µsDriver Output Delay Time (Low power mode) tPHL2L CL = 30 pF AP↓ →VOUT – 100 mV or VOUT + 100 mV 15 µs CI1 V0 to V4, TA = 25°C 5 15 pFInput Capacitance CI2 Excluded V0 to V4, TA = 25°C 10 15 pF Timing Requirements (TA = –20 to +75°°°°C, VDD1 = 2.2 to 3.6 V, VSS1 = 0 V, tr = tf = 10 ns) Parameter Symbol Condition MIN. TYP. MAX. Unit Clock Pulse Width PW CLK 65 ns Clock Pulse High Period PW CLK(H) 20 ns Clock Pulse Low Period PW CLK(L) 20 ns Data Setup Time t SETUP1 20 ns Data Hold Time t HOLD1 20 ns Start Pulse Setup Time t SETUP2 20 ns Start Pulse Hold Time t HOLD2 20 ns Start Pulse Low Period t SPL 3C L K Last Data Timing t LDT 2C L K CLK-STB Time t CLK-STB CLK↑ →STB↑ 20 ns STB Pulse Width PW STB 40 ns Start Pulse Rising Time t STB-STH STB↑ →STH↑ 3C L K INV Set-up Time t SETUP3 20 ns INV Hold Time t HOLD3 20 ns STB Set-up Time t SETUP4 20 ns STB Hold Time t HOLD4 20 ns POL-STB Time t POL-STB 0n s STB-POL Time t STB-POL 40 ns CM-STB Time t CM-STB 0n s STB-CM Time t STB-CM 40 ns STB-AP Time t STB-AP STB↑ →AP↓ 20 µs AP Pulse Width (High power mode) PW APH 12 µs AP Pulse Width (Low power mode) PW APL STB cycle 40µs, CL = 30 pF 15 µs

Data Sheet S15381EJ1V0DS 21 µµµµPD161602A/B Switching Characteristic Waveform (R,/L= H, OSEL=L) Unless otherwise specified, the input level is defined to be V IH = 0.7 VDD1, VIL = 0.3 VDD1. PWCLK(L) CLK POL VOUT STB DATA STHR STHL PWCLK(H) tr tSETUP2 INVALID D1 to D3 tHOLD2 12 3 132 133 tfPWCLK tPLH1 tSTB-AP tSETUP1 90% 10% tHOLD1 tSTB-STH PWSTB tHOLD3 tHOLD4tSETUP4 tSPL PWAB D4 to D6 tPOL-STB tSTB-POL (1st Dr.) (1st Dr.) INV CM AP tPHL1 tSETUP3 tCM-STB tSTB-CM tCLK-STB tPLH2 tPHL2 Hi-Z Hi-Z tLDT Last Data INVALID

Data Sheet S15381EJ1V0DS22 µµµµPD161602A/B [MEMO]

Data Sheet S15381EJ1V0DS 23 µµµµPD161602A/B NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

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