PD10256H

PD10256H DATADELAY | Alldatasheet

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Technical content

8-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU10256H) FEATURES PACKAGES

• Digitally programmable in 128 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 10KH-ECL interfaced & buffered
• Fits 48-pin DIP socket PIN DESCRIPTIONS IN Signal Input OUT Signal Output A0-A7 Address Bits ENB Output Enable VEE -5 Volts GND Ground FUNCTIONAL DESCRIPTION The PDU10256H-series device is an 8-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A7-A0) according to the following formula: TDA = TD0 + TINC * A where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The enable pin (ENB) is held LOW during normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. The address is not latched and must remain asserted during normal operation. SERIES SPECIFICATIONS datadelaydevices, inc. N/C N/C OUT GND ENB N/C N/C N/C GND ENB N/C N/C N/C N/C N/C N/C N/C GND ENB IN N/C N/C VEE N/C VEE N/C N/C N/C N/C N/C N/C VEE GND IN VEE GND ENB VEE GND OUT GND VEE GND GND P P PDU10256H-xxC5 SMD PDU10256H-xxMC5 Mil SMD DU10256H-xx DIP DU10256H-xxM Mil DIP DASH NUMBER SPECIFICATIONS Part Number Incremental Delay Per Step (ns) Total Delay (ns) PDU10256H-1 1.0 ± 0.5 255 ± 12.8 PDU10256H-2 2.0 ± 0.5 510 ± 25.5 PDU10256H-3 3.0 ± 1.0 765 ± 38.2 PDU10256H-4 4.0 ± 1.0 1020 ± 51.0 PDU10256H-5 5.0 ± 1.5 1275 ± 63.8 PDU10256H-6 6.0 ± 1.5 1530 ± 76.5 PDU10256H-8 8.0 ± 2.0 2040 ± 102 PDU10256H-10 10.0 ± 2.0 2550 ± 128 NOTE: Any dash number between .5 and 10 not shown is also available.
• Total programmed delay tolerance: 5% or 2ns, whichever is greater Inherent delay (TD0): 12ns typical
• Setup time and propagation delay: Address to input setup (TAIS): 3.6ns Disable to output delay (TDISO): 1.7ns typical
• Operating temperature: 0° to 70° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 5%
• Power Dissipation: 925mw typical (no load)
• Minimum pulse width: 16% of total delay 2009 Data Delay Devices Doc #97047 DATA DELAY DEVICES, INC. 1 2/9/2009 3 Mt. Prospect Ave. Clifton, NJ 07013

The PDU10256H is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1. After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation: TOAX = max { (Ai - A i-1) * TINC , 0 } where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed. A similar situation occurs when using the ENB signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to “clear” itself. This is achieved by holding the ENB signal high and the IN signal low for a time given by: TDISH = Ai * TINC Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TDISH has elapsed. INPUT RESTRICTIONS There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input. When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements. Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses. TDISO TOAXTAENS TENIS PWIN TDA PWOUT TDISH A7-A0 ENB IN OUT Figure 1: Timing Diagram A i-1 Ai TAIS Doc #97047 DATA DELAY DEVICES, INC. 2 12/17/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

Doc #97047 DATA DELAY DEVICES, INC. 3 12/17/97 3 Mt. Prospect Ave. Clifton, NJ 07013 DEVICE SPECIFICATIONS TABLE 1: AC CHARACTERISTICS PARAMETER SYMBOL MIN TYP UNITS Total Programmable Delay TDT 127 TINC Inherent Delay TD0 12.0 ns Disable to Output Low Delay TDISO 1.7 ns Address to Enable Setup Time TAENS 1.0 ns Address to Input Setup Time TAIS 3.6 ns Enable to Input Setup Time TENIS 3.6 ns Output to Address Change TOAX See Text Disable Hold Time TDISH See Text Absolute PERIN 12 % of TDT Input Period Suggested PERIN 32 % of TDT Recommended PERIN 200 % of TDT Absolute PWIN 6 % of TDT Input Pulse Width Suggested PWIN 16 % of TDT Recommended PWIN 100 % of TDT TABLE 2: ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNITS NOTES DC Supply Voltage VEE -7.0 0.3 V Input Pin Voltage VIN VEE - 0.3 0.3 V Storage Temperature TSTRG -55 150 C Lead Temperature TLEAD 300 C 10 sec TABLE 3: DC ELECTRICAL CHARACTERISTICS (0C to 75C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES High Level Output Voltage VOH -1.020 -0.735 V VIH = MAX,50Ω to -2V Low Level Output Voltage VOL -1.950 -1.600 V VIL = MIN, 50Ω to -2V High Level Input Voltage VIH -1.070 V Low Level Input Voltage VIL -1.480 V High Level Input Current IIH 475 µA VIH = MAX Low Level Input Current IIL 0.5 µA VIL = MIN

Doc #97047 DATA DELAY DEVICES, INC. 4 12/17/97 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com PACKAGE DIMENSIONS PDU10256H-xx (Commercial DIP) PDU10256H-xxM (Military DIP) .150 ±.030 2.450 TYP. 2415 .320 MAX. .018 TYP. .400 TYP. .300 TYP. .012 TYP. .020 TYP. 40 3334 32 25 782 48 4142 9 1916 17 23 .600 .100 .700 .800 1.400 1.600 2.200 .075 1.500 1.800 2.300 PDU10256H-xxC5 (Commercial SMD) PDU10256H-xxMC5 (Military SMD) 2.080±.020 .882 ±.00 .020 TYP. .040 TYP. .100.090 1.100 .320 MAX. .590 MAX. .010±.002 .050 ±.01 .710 ±.00 .007 ±.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122232425262728 29 30 31 32 33 34 35 36 37 38 39 40

DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: OUTPUT: Ambient Temperature: 25 oC ± 3oC Load: 50 Ω to -2V Supply Voltage (Vcc): -5.0V ± 0.1V Cload: 5pf ± 10% Input Pulse: Standard 10KH ECL Threshold: (V OH + VOL) / 2 levels (Rising & Falling) Source Impedance: 50 Ω Max. Rise/Fall Time: 2.0 ns Max. (measured between 20% and 80%) Pulse Width: PW IN = 1.5 x Total Delay Period: PER IN = 10 x Total Delay NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. OUTOUT TRIG IN REF TRIG Test Setup DEVICE UNDER TEST (DUT) OSCILLOSCOPEPULSE GENERATOR IN ADDRESS SELECT Timing Diagram For Testing TRISE TFALL PERIN PWIN TRISE TFALL 20%20% 50%50% 80% 80% 50%50% VIH VIL VOH VOL INPUT SIGNAL OUTPUT SIGNAL Doc #97047 DATA DELAY DEVICES, INC. 5 12/17/97 3 Mt. Prospect Ave. Clifton, NJ 07013