PCZ33742EP

33742 FREESCALE | Alldatasheet

Document overview

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• PDF pages: 65

Technical content

Features

• 1 . 0 Mbps CAN Transceiver Bus Interface with Bus Diagnostic Capability
• SPI Control at Frequencies up to 4.0 Mhz
• 5.0 V Low Dropout Voltage Regulator with Current Limiting, Overtemperature Pre-Warning, and Output Monitoring and Reset
• A Second 5.0 V Regulator Capability using an External Series Pass Transistor
• Normal, Standby, Stop, and Sleep Modes of Operation with Low Sleep and Stop Mode Current
• A High-Side (HS) Switch Output Driver for Controlling External Circuitry.
• Pb-Free Packaging Designated by Suffix Code EG and EP

Figure 1. 33742 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC33742DW/R2 - 40°C to 125°C

28 SOICW

EG SUFFIX (PB-FREE) 98ASB42345B 28-PIN SOICW EP SUFFIX (PB-FREE) 98ARH99048A 48-PIN QFN 5.0 V MCU GND VSUP 33742 GND VDD RST V2CTRL HS WDOG VPWR VPWR Safe Circuitry SCLK MOSI MISO CS SPI SCLK MOSI MISO CS INT TXD RXD CANH CANL Twisted Pair ECU Local Supply CAN Bus

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Table 1. Device Differences During a Reset Condition watchdog register is not properly triggered. watchdog register is not properly triggered.

Figure 2. 33742 Simplified Internal Block Diagram

5.0 V / 200 mA

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Figure 3. 33742 28-Pin Connections Table 2. 33742 28-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 22. 1 RXD Receive Data CAN bus receive data output pin. 2 TXD Transmit Data CAN bus transmit data input pin. 3 VDD Voltage Digital Drain 5.0 V regulator output pin. Supply pin for the MCU.

4 RST Reset Output

an internal pullup current source to VDD.

5 INT Interrupt Output

a 33742-to-PCB thermal path. internal supply for the CAN transceiver. 11 V2CTRL Voltage Source 2 Control Output drive source for the V2 regulator connected to the external series pass transistor. 12 VSUP Voltage Supply Supply input pin for the 33742. 13 HS High-Side Output Output of the internal high-side switch. The output current is internally limited to 150 mA. 14 –17 L0- L3 Level 0 - 3 Inputs Inputs from external switches or from logic circuitry. 18 CANH CAN High Output CAN high output pin. 19 CANL CAN Low Output CAN low output pin. 24 SCLK Serial Data Clock Clock input pin for the Serial Peripheral Interface (SPI). 26 MOSI Master Out Slave In SPI data received by the 33742.

27 CS Chip Select

LOW, the 33742 is the selected device of the SPI bus.

28 WDOG Watchdog Output

Figure 4. 33742 48-Pin Connections Table 3. 33742 48-Pin Definitions A functional description of each pin can be found in the Functional Pin description section beginning on page 22. NC No Connect No connection. 2 SCLK Serial Data Clock Clock input pin for the Serial Peripheral Interface (SPI). 4 MOSI Master Out Slave In SPI data received by the 33742.

5 CS Chip Select

LOW, the 33742 is the selected device of the SPI bus.

6 WDOG Watchdog Output

7 RXD Receive Data CAN bus receive data output pin. 8 TXD Transmit Data CAN bus transmit data input pin. 9 VDD Voltage Digital Drain 5.0 V regulator output pin. Supply pin for the MCU.

10 RST Reset Output

an internal pullup current source to VDD.

11 INT Interrupt Output

a 33742-to-PCB thermal path.

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internal supply for the CAN transceiver. 28 VSUP Voltage Supply Supply input pin for the 33742. 29 HS High-Side Output Output of the internal high-side switch. The output current is internally limited to 150 mA. 30-33 L0- L3 Level 0 - 3 Inputs Inputs from external switches or from logic circuitry. 34 CANH CAN High Output CAN high output pin. 35 CANL CAN Low Output CAN low output pin. Table 3. 33742 48-Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin description section beginning on page 22.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 33742

ELECTRICAL CHARACTERISTICS

Table 4. Maximum Ratings permanent damage to the device.

1. Testing done in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
2. Testing done in accordance with ISO 7637-1. See Figure 5.
3. Load dump testing done in accordance with ISO 7637-1, Transient test done in accordance with ISO 7637-1. See Figure 6.

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Figure 5. Transient Test Setup for L0 : L3 Inputs Figure 6. Transient Test Setup for CANH / CANL

1. Maximum power dissipation is at 85°C am bient temperature in free aIr and with no heatsink, according to JEDEC JESD51-2 and
2. The package is not designed for imme rsion soldering. The maximum soldering time is 10 seconds at 240 °C on any pin. Exceeding the

maximum temperature and time limits may cause permanent damage to the device.

1. Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

1. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

MC33xxxD enter 33xxx), and review parametrics. Table 4. Maximum Ratings (continued) permanent damage to the device. Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b. Note Waveform per ISO 7637-1. Test Pulses 1, 2, 3a, and 3b.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 33742 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

1. All functions and modes available and operating: Watchdog, HS turn ON / turn OFF, CAN transceiver operating, L0 : L3 inputs operating,

normal SPI operation. The 33742 may experience an over temperature fault.

1. At VDD > 4.0 V, RST HIGH if reset 2 selected via SPI. The logic HIGH level will be degraded but the 33742 is functional.
2. Current measured at VSUP pin.
3. If CAN Module is Sleep-Enabled for wake-up, an additional current (ICAN-SLEEP) must be added to specified value.
4. Oscillator running means one of the follo wing function is active: Forced Wake-Up or Cyclic Sense or Software Watchdog in Stop mode.
5. Oscillator not running means none of the foll owing functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in

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STATIC ELECTRICAL CHARACTERISTICS INPUT PIN (VSUP) (CONTINUED) Supply Current in Stop Mode (14) ( IOUT at VDD < 2.0 mA, VDD ON, VSUP < 13.5 V, Oscillator Not Running, CAN in Sleep Mode with Wake-Up Enabled) (15) TA = - 40°C TA = 25°C TA = 125°C ISUP(STOP-WE) 100 µA BATFAIL Flag Internal Threshold VBF 1.5 3.0 4.0 V BATFAIL Flag Hysteresis (16) VBF(HYS) — 1.0 — V Battery Fall Early Warning Threshold In Normal and Standby Modes VBF(EW) 5.3 5.8 6.3 V Battery Fall Early Warning Hysteresis In Normal and Standby Modes (16) VBF(EW-HYST) 0.1 0.2 0.3 V OUTPUT PIN (VDD) (17) VDD Output Voltage (2.0 mA < IV1 < 200 mA)

5.5 V < VSUP < 27 V

4.5 V < VSUP < 5.5 V VDDOUT 4.9 4.0 5.0 5.1 V Dropout Voltage IDD = 200 mA VDDDRP1 — 0.2 0.5 V Dropout Voltage, Limited Output Current and Low VSUP IDD = 50 mA, 4.5 V < VSUP VDDDRP2 — 0.1 0.25 V Output Current Internally Limited IDD 200 285 350 mA Thermal Shutdown (Junction) Normal or Standby Mode TSD 160 — 200 Overtemperature Pre-Warning (Junction) VDDTEMP Bit Set TPW 125 — 160 Notes 14. Current measured at VSUP pin. 15. Oscillator not running means none of the foll owing functions are active: Forced Wake-Up and Cyclic Sense and Software Watchdog in Stop mode. 16. Guaranteed by design; it is not production tested. 17. I DD is the total regulator output current. V1 specification with external capacitor. Stability requirement: Capacitance > 47 µF, ESR < 1.3 Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes. Measures with capacitance = 47 µF tantalum. Table 5. Static Electrical Characteristics (continued) noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 33742 STATIC ELECTRICAL CHARACTERISTICS OUTPUT PIN (VDD) (CONTINUED) (18) Temperature Threshold Difference TSD - TPW 20 — 40 °C Reset Threshold Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0] Threshold 2, RSTTH Bit Set to Logic [1] VRSTTH 4.5 4.0 4.6 4.2 4.7 4.3 V VDD for Reset Active VDDR 1.0 — VRSTTH V Line Regulation (IDD = 10 mA, Capacitance = 47 µF Tantalum at VDD)

9.0 V < VSUP < 18 V

5.0 mV Load Regulation (Capacitance = 47 µF Tantalum at V1) 1.0 mA < IDD < 200 mA VLD — 25 75 mV Thermal Stability VSUP = 13.5 V, IDD = 100 mA (19) VTHERM-S — 30 50 mV OUTPUT PIN IN STOP MODE (VDD) (18) VDD Output Voltage IDD ≤ 2.0 mA IDD ≤ 10 mA VDDSTOP 4.75 4.75 5.0 5.0 5.25 5.25 V IDD Output Current to Wake-Up IDDS-WU 10 17 25 mA Reset Threshold (18) Threshold 1, Default Value after Reset, RSTTH Bit Set to Logic [0] Threshold 2, RSTTH Bit Set to Logic [1] VRST-STOP 4.5 4.1 4.6 4.2 4.7 4.3 V Line Regulation (Capacitance = 47 µF Tantalum at VDD) 5.5 V < VSUP < 27 V, IDD = 2.0 mA VLR-STOP — 5.0 25 mV Load Regulation (Capacitance = 47 µF Tantalum at V1) 1.0 mA < IDD < 10 mA VLD-STOP — 15 75 mV Notes 18. I DD is the total regulator output current. VDD specification with external capacitor. Stability requirement: capacitance > 47 µF, ESR < 1.3 Ω (tantalum capacitor). In Reset, Normal Request, Normal and Standby modes, measures with capacitance = 47 µF tantalum.Selectable by RSTTH bit in SPI Register Reset Control Register (RCR). 19. Guaranteed by characterization and des ign; it is not production tested. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS TRACKING VOLTAGE REGULATOR (V2) (20) V2 Output Voltage (Capacitance = 10 µF Tantalum at V2) 2.0 mA ≤ IV2 ≤ 200 mA, 5.5 V < VSUP < 27 V 0.99 1.0 1.01 VDD IV2 Output Current (for Information Only) Depending on External Ballast Transistor IV2 200 — — mA V2 Control Drive Current Capability (21) Worst Case at TJ = 125°C IV2CTRL 0.0 — 10 mA V2LOW Flag Threshold V2LTH 3.75 4.0 4.25 V LOGIC OUTPUT PIN (MISO) (22) Low-Level Output Voltage IOUT = 1.5 mA VOL 0.0 — 1.0 V High-Level Output Voltage IOUT = -250 µA VOH VDD - 0.9 — VDD V Tri-Stated MISO Leakage Current

0 V < VMISO < VDD

• 2.0 — 2.0 µA Notes 20. V2 specification with external capacit or. Stability requirement: capacitance > 42 µF and ESR < 1.3 Ω (tantalum capacitor), external resistor between base and emitter required. Measurement conditions: ballast transistor MJD32C, capacitance > 10 µF tantalum, 2.2 kΩ resistor between base and emitter of ballast transistor. 21. The guaranteed V2CTRL current capability is 10 mA. No active current limiting is used so the actual available current may be higher. 22. Push-pull structure with tri-state condition ( CS HIGH).

noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 33742 STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUT PINS (MOSI, SCLK, CS) High-Level Input Voltage VIH 0.7 VDD — VDD + 0.3 V Low-Level Input Voltage VIL - 0.3 — 0.3 VDD V High-Level Input Current on CS VIN = 4.0 V I IH -100 — - 20 µA Low-Level Input Current on CS VIN = 1.0 V I IL -100 — - 20 µA MOSI and SCLK Input Current

0 V < VIN < VDD

-10 — 10 µA OUTPUT PIN (RST) (23) High-Level Output Current 0 V < VOUT < 0.7 VDD IOH - 300 - 250 -150 µA Low-Level Output Voltage IO = 1.5 mA, 5.5 V < VSUP < 27 V IO = 0 mA, 1.0 V <VSUP < 5.5 V VOL 0.0 0.0 0.9 0.9 V RST Pulldown Current V > 0.9 V IPDW 2.3 — 5.0 mA OUTPUT PIN (WDOG) (24) Low-Level Output Voltage IO = 1.5 mA, 1.0 V < VSUP < 27 V VOL 0.0 — 0.9 V High-Level Output Voltage IO = -250 µA VOH VDD - 0.9 — VDD V OUTPUT PIN (INT) (24) Low-Level Output Voltage IO = 1.5 mA VOL 0.0 — 0.9 V High-Level Output Voltage IO = -250 µA VOH VDD - 0.9 — VDD V Notes 23. Output pin only. Supply from VDD. Structur e switch to ground with pullup current source. 24. Push-pull structure. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS OUTPUT PIN (HS) Driver Output ON Resistance TA = 25°C, IOUT - 150 mA, VSUP > 9.0 V TA = 125°C, IOUT - 150 mA, VSUP > 9.0 V TA = 125°C, IOUT - 120 mA, 5.5 V < VSUP < 9.0 V RDS(ON) 2.0 3.5 2.5 4.5 5.5 Ω Output Current Limitation VSUP - VHS > 1.0 V ILIM 160 — 500 mA HS Thermal Shutdown TSD 155 — 190 °C HS Leakage Current ILEAK — — 10 µA Output Clamp Voltage IOUT = -10 mA, No Inductive Load Drive Capability VCL -1.5 — - 0.3 V INPUT PINS (L0, L1, L2, AND L3) Low-Voltage Detection Threshold 5.5 V < VSUP < 6.0 V

6.0 V < VSUP < 18 V

18 V < VSUP < 27 V

2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.6 3.7 V High-Voltage Detection Threshold 5.5 V < VSUP < 6.0 V 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.6 4.7 V Hysteresis 0.6 — 1.3 V Input Current - 0.2 V < VIN < 40 V I IN -10 — 10 µA CAN TRANSCEIVER CURRENT Supply Current of CAN Module CAN in Normal Mode, Bus Recessive State CAN in Normal Mode, Bus Dominant State without Bus Load CAN in Sleep State, Wake-Up Enabled, V2 Regulator OFF CAN in Sleep State, Wake-Up Disabled, V2 Regulator OFF (25) IRES IDOM ICAN-SLEEP IDIS 1.3 1.5 3.0 3.5 1.0 mA mA µA µA Notes 25. Guaranteed by design; it is not production tested. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 33742 STATIC ELECTRICAL CHARACTERISTICS PINS (CANH AND CANL) Bus Pin Common Mode Voltage VCM - 27 — 40 V Differential Input Voltage (Common Mode Between - 3.0 V and 7.0 V) Recessive State at RXD Dominant State at RXD VCANH - VCANL 900 500 mV Differential Input Hysteresis (RXD) VHYS 100 — — mV Input Resistance RIN 5.0 — 100 kΩ Differential Input Resistance RIND 10 — 100 kΩ CANH Output Voltage TXD Dominant State TXD Recessive State VCANH 2.75 4.5 3.0 V CANL Output Voltage TXD Dominant State TXD Recessive State VCANL 0.5 2.0 2.25 V Differential Output Voltage TXD Dominant State TXD Recessive State VoH - VoL 1.5 3.0 100 V mV Output Current Capability (Dominant State) CANH CANL ICANH ICANL - 35 mA Overtemperature Shutdown TSD 160 180 — °C CANL Overcurrent Detection (26) CANL CANH ICANL /OC ICANH /OC - 200 200 - 60 mA CANH and CANL Input Current, Device Supplied (CAN Sleep Mode with CAN Wake-Up Enabled or Disabled) VCANH, VCANL from 0 V to 5.0 V VCANH, VCANL = - 2.0 V VCANH, VCANL = 7.0 V ICAN1 - 60 3.0 - 50 µA CANH and CANL Input Current, Device Unsupplied VCANH, VCANL = 2.5 V VCANH, VCANL = - 2.0 V VCANH, VCANL = 7.0 V ICAN2 - 60 - 50 190 100 240 µA Notes 26. Reported in CAN register. For a description of the contents of the CAN register, refer to CAN Register (CAN) on page 44 noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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STATIC ELECTRICAL CHARACTERISTICS DIAGNOSTIC INFORMATION (CANH AND CANL) CANL to GND Threshold VLG — 1.75 — V CANH to GND Threshold VHG — 1.75 — V CANL to VSUP Threshold VLVB — VSUP - 2.0 — V CANH to VSUP Threshold VHVB — VSUP - 2.0 — V CANL to VDD Threshold VL5 — VDD - 0.43 — V CANH to VDD Threshold VH5 — VDD - 0.43 — V RXD Weak Pull-down Current Source (27) RXD Permanent Dominant Failure Condition IRXDW — 100 — µA PINS (TXD AND RXD) TXD Input High Voltage VIH 0.7 VDD — VDD + 0.4 V TXD Input Low Voltage VIL - 0.4 — 0.3 VDD V TXD High-Level Input Current VTXD = V2 IIH -10 — 10 µA TXD Low-Level Input Current VTXD = 0 V IIL -150 - 100 - 50 µA RXD Output High Voltage IRXD = 250 µA VOH VDD - 1.0 — — V RXD Output Low Voltage IRXD = 1.0 mA VOL — — 0.5 V Notes 27. Guaranteed by design; it is not production tested. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 33742 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

1. See Figure 7, SPI Timing Diagram, page 21.
2. Not production tested. Guaranteed by design.
3. Not production tested. Guaranteed by design. Detected by V2 OFF.
4. f OSC is indirectly measured (1.0 ms reset) and trimmed.

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DYNAMIC ELECTRICAL CHARACTERISTICS STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Normal Request Mode Timeout Normal Request Mode t NRTOUT 308 350 392 ms Watchdog Period Stop Mode Period 1 Period 2 Period 3 Period 4 t WD-STOP 6.82 31.5 245 9.75 100 350 12.7 58.5 130 455 ms Watchdog Period Accuracy Normal and Standby Modes Stop Mode t ACC -12 - 30 Cyclic Sense / FWU Timing Sleep and Stop Modes Timing 1 Timing 2 Timing 3 Timing 4 Timing 5 Timing 6 Timing 7 Timing 8 t CSFWU 3.22 6.47 12.9 25.9 51.8 66.8 134 271 4.6 9.25 18.5 95.5 191 388 5.98 48.1 96.2 124 248 504 ms Cyclic Sense ON Time Sleep and Stop Modes. t ON 200 350 500 µs Cyclic Sense / FWU Timing Accuracy Sleep and Stop Modes t ACC - 30 — 30 Delay Between SPI Command and HS Turn ON (32) Normal or Standby Mode, VSUP > 9.0 V t S-HSON — — µs Delay Between SPI Command and HS Turn OFF (32) Normal or Standby Mode, VSUP > 9.0 V t S-HSOFF — — µs Delay Between SPI and V2 Turn ON (32) Standby Mode t S-V2ON 9.0 — 22 µs Delay Between SPI and V2 Turn OFF (32) Normal Mode t S-V2OFF 9.0 — 22 µs Delay Between Normal Request and Normal Mode After Watchdog Trigger Command (32) Normal Request Mode t S-NR2N 15 35 70 µs Notes 32. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2. Table 6. Dynamic Electrical Characteristics (continued) noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 33742 DYNAMIC ELECTRICAL CHARACTERISTICS STATE MACHINE TIMING (CS, SCLK, MOSI, MISO, WDOG, INT) (CONTINUED) Delay Between SPI and CAN Normal Mode (33) Normal Mode (34) t S-CAN_N — — 10 µs Delay Between SPI and CAN Sleep Mode (33) Normal Mode (34) t S-CAN_S — — 10 µs Delay Between CS Wake-Up (CS LOW to HIGH) and Device in Normal Request Mode (VDD ON and RST HIGH) Stop Mode t W-CS 15 40 90 µs Delay Between CS Wake-Up (CS LOW to HIGH) and First Accepted SPI Command Device in Stop Mode After Wake-Up t W-SPI 90 — N/A µs Delay Between INT Pulse and First SPI Command Accepted Device in Stop Mode After Wake-Up t S-1STSPI 20 — N/A µs Delay Between Two SPI Messages Addressing the Same Register t 2SPI 25 — — µs OUTPUT PIN (VDD) Reset Delay Time Measured at 50% of Reset Signal t D 4.0 — 30 µs IDD Overcurrent to Wake-Up Deglitcher Time (34) tIDD-DGLT 40 55 75 µs OUTPUT PIN (RST) Reset Duration After VDD HIGH 33742 33742S t RSTDUR t RSTDURS 3.0 3.5 4.0 ms INPUT PINS (L0, L1, L2, AND L3) Wake-Up Filter Time t WUF 8.0 20 38 µs Notes 33. Delay starts at falling edge of clock cycle #8 of the SPI command and start of “Turn ON” or “Turn OFF” of HS or V2. 34. Guaranteed by design; it is not production tested. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

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DYNAMIC ELECTRICAL CHARACTERISTICS CAN MODULE – SIGNAL EDGE RISE AND FALL TIMES (CANH, CANL) Dominant State Timeout t DOUT 200 360 520 µs Propagation Loop Delay TXD to RXD (Recessive to Dominant) (35) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t LRD 110 100 110 130 200 210 225 255 310 ns Propagation Delay TXD to CAN (Recessive to Dominant) (36) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t TRD 100 160 110 150 200 300 ns Propagation Delay CAN to RXD (Recessive to Dominant) (37) t RRD 10 50 140 ns Propagation Loop Delay TXD to RXD (Dominant to Recessive) (35) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t LDR 100 120 140 250 150 165 200 340 200 220 250 410 ns Propagation Delay TXD to CAN (Dominant to Recessive) (36) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t TDR 200 125 150 180 310 150 190 250 460 ns Propagation Delay CAN to RXD (Dominant to Recessive) (37) t RDR 20 30 60 ns Non-Differential Slew Rate (CANL or CANH) Slew Rate 3 Slew Rate 2 Slew Rate 1 Slew Rate 0 t SL3 t SL2 t SL1 t SL0 4.0 3.0 2.0 1.0 13.5 8.0 5.0 V/µs Bus Communication Rate tBUS 60k — 1.0M bps Νοτεσ 35. See Figure 8, page 21. 36. See Figure 9, page 21. 37. See Figure 10, page 21. noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 33742 Figure 7. SPI Timing Diagram Figure 8. Propagation Loop Delay TXD to RXD Figure 9. Propagation Delay TXD to CAN Figure 10. Propagation Delay CAN to RXD is set by the 33742 at SCLK rising edge (after tVALID delay time).

0.9 VVDIFF

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The 33742 and the 33742S are system basis chips (SBCs) dedicated to automotive applications. Their functions include the following:

• One fully protected 5.0 V voltage regulator with 200 mA total output current capability available at the VDD pin.
• VDD regulator undervol tage reset function, programmable window or time-out software watchdog function.
• Internal driver (V2) for an external series pass transistor to implement a second 5.0 V voltage regulator.
• Two running modes: Normal and Standby modes set by the system microcontroller.
• Sleep and Stop modes low power operating modes to reduce an application’s current consumption while providing a wake-up capability from the CAN interface, L3 : L0 wake-up inputs, or from a timer wake-up.
• Programmable wake-up input and cyclic sense wake- ups.
• CAN high-speed physical bus interface with TXD and RXD fault diagnostic capability and enhanced protection features.
• An SPI interface for use in communicating with a MCU and Interrupt outputs to report SBC status, perform diagnostics, and report wake-up events. FUNCTIONAL PIN DESCRIPTION RECEIVE AND TRANSMIT DATA (RXD AND TXD) The RXD and TXD pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol handler. TXD is an input and controls the CANH and CANL line state (dominant when TXD is LOW, recessive when TXD is HIGH). RXD is an output and reports the bus state (RXD LOW when CAN bus is dominant, HIGH when CAN bus is recessive). Voltage Digital Drain (VDD) The VDD pin is the output pin of the 5.0 V internal regulator. It can deliver up to 200 mA. This output is protected against overcurrent and overtemperature. It includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130°C typical. When the temperature exceeds the overtemperature shutdown (170°C typical), the regulator is turned off. VDD includes an undervoltage reset circuitry, which sets the RST pin LOW when VDD is below the undervoltage reset threshold. RESET OUTPUT (RST) The Reset pin RST is an output that is set LOW when the device is in reset mode. The RST pin is set HIGH when the device is not in reset mode. RST includes an internal pullup current source. When RST is LOW, the sink current capability is limited, allowing RST to be shorted to 5.0 V for software debug or software download purposes. INTERRUPT OUTPUT (INT) The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared. INT output also reports a wake-up event by a 10 µs typical pulse when the device is in Stop mode. VOLTAGE SOURCE 2 (V2) The V2 pin is the input sense for the V2 regulator. It is connected to the external series pass transistor. V2 is also the 5.0 V supply of the internal CAN interface. It is possible to connect V2 to an external 5.0 V regulator or to the VDD output when no external series pass transistor is used. In this case, the V2CTRL pin must be left open. Refer to Figure 31, SBC Typical Application Schematic, page 52. VOLTAGE SOURCE 2 CONTROL (V2CTRL) The V2CTRL pin is the output drive pin for the V2 regulator connected to the external series pass transistor. VOLTAGE SUPPLY (VSUP) The VSUP pin is the battery supply input of the device. HIGH-SIDE OUTPUT (HS) The HS pin is the internal high-side driver output. It is internally protected against overcurrent and overtemperature. LEVEL 0-3 INPUTS (L0: L3) The L0 : L3 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by SPI. These inputs can be used as wake-up events for the SBC when operating in the Sleep or Stop mode. CAN HIGH AND CAN LOW OUTPUTS (CANH AND CANL) The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TXD input level, and the state of CANH and CANL is reported through RXD output. A 60 Ω termination resistor is connected between CANH and CANL pins.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 33742 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION SERIAL DATA CLOCK (SCLK) SCLK is the Serial Data Clock input pin of the serial peripheral interface. MASTER IN SLAVE OUT (MISO) MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin. MASTER OUT SLAVE IN (MOSI) MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin. CHIP SELECT (CS) CS is the Chip Select pin of the serial peripheral interface. When this pin is LOW, the SPI port of the device is selected. WATCHDOG OUTPUT (WDOG) The Watchdog output pin is asserted LOW to flag that the software watchdog has not been properly triggered.

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION SUPPLY VOLTAGE AT VSUP The 33742 receives its operating voltage via the VSUP pin. An external diode is needed in series with the VSUP pin and the supply voltage to protect the SBC against negative transients or from a reverse battery situation that can occur in a vehicle application. The 33742 will operate from a supply voltage input as low as 4.5 VDC to as high as 27 VDC. The later voltage is often encountered during a vehicle jump-start. The VSUP pin can tolerate automotive transient conditions such as load dump to 40 V. The SBC is able to detect when VSUP falls below 3.0 V typical. This undervoltage state is detected and retained in the parts Mode Control Register (MCR) as the BATFAIL bit. This detection capability is available across all operating modes. Note For a detailed description of all the registers mentioned in this section, refer to the section titled SPI Interface And Register Description beginning on page 42. The SBC incorporates a VSUP level early warning function, which provides a maskable interrupt if the VSUP voltage level falls below 6.0 V typical. Hysteresis is used to reduce false detections. The early warning function works only in Normal and Standby operation modes. An undervoltage at the VSUP pin is reported in the Input / Output Register (IOR). VDD REGULATOR The VDD regulator provides a 5.0 V low dropout voltage capable of supplying up to 200 mA with monitoring circuitry for undervoltage detection and a reset function. The VDD regulator is protected against overcurrent and short circuit conditions. It has overtemperature detection and will set warning flags (bit VDDTEMP in the MCR and INTR registers) and has overtemperature shutdown with hysteresis. V2 REGULATOR The V2 regulator feature provides for a second 5.0 VDC voltage source The internal V2 circuitry will drive an external series pass transistor, substantially increasing the available supply current. Two pins, the V2 and the V2CTRL, are used to sense and drive the series pass transistor. The output voltage is 5.0 V and tracks the VDD regulator. The MJD32C transistor is recommended for use as the external pass device. Other PNP transistors can be used but depending on the device’s gain, an external resistor-capacitor network might be needed. V2 is also the supply voltage for the on- board CAN module. An undervoltage condition for the V2 voltage is reported in the IOR Register (bit V2LOW set to logic [1] if V2 falls below 4.0 V typical). HS VSUP SWITCH OUTPUT The HS output is a 2.0 Ω typical switch tied to the VSUP pin. It can power or bias external switches and their associated pullup or put-downs or other circuitry. An example is biasing a set of switches connected to the L0 : L3 wake-up input pins. The HS VSUP output current is limited to 200 mA and is protected against short circuits conditions and will report an overtemperature shutdown condition (bit HSOT in the IOR register and bit HSOT - V2LOW in the INTR register). The HS output “on” state is set by the HSON bit in the IOR register. A cyclic mode of operation can be implemented using an internal timer in the Sleep and Stop operating modes. It can also be turned on in Normal or Standby modes to drive loads or supply peripheral components. No internal protection circuitry is provided, however. Dedicated chip protection circuitry is required for inductive load applications. The HS output pin should not go below - 0.3 V. BATTERY FAIL EARLY WARNING Refer to the discussion under the heading, Supply Voltage at VSUP above. INTERNAL CLOCK The 33742 has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time, etc.). There are two on-board oscillators;: a higher accuracy (±12 percent) oscillator used in Normal Request, Normal, and Standby modes,; and a lower accuracy (±30 percent) oscillator used during Sleep and Stop modes. OPERATIONAL MODES INTRODUCTION The 33742 has four modes of operation, all controllable via the SPI. The modes are Standby, Normal, Stop, and Sleep. An additional temporary mode called Normal Request mode is automatically accessed by the device after reset or wake- up from Stop mode. A Reset mode is also implemented. Special modes and configurations are possible for debug and program microcontroller flash memory. Table 7, page 25, offers a summary of the functional modes. STANDBY MODE In Standby mode only the VDD regulator is ON. The V2 regulator is turned OFF by disabling the V2CTRL pin. Other functions available are the L0 : L3 inputs read through via the SPI and HS output activation. The CAN interface is not able to send messages. If a CAN message is received, the CANWU bit is set. The watchdog timer is running.

running and must be periodically cleared through SPI. VDD) or from the MCU side (key wake-up, etc.). In Sleep mode, the VDD and V2 regulators are OFF. the Reset mode before entering Normal Request mode. time-out, or watchdog trigger in a closed window). after the 33742 wakes up from the Stop mode. mode, the 33742 enters the Normal Request mode directly. to set the watchdog timer configuration. Table 7. Table of Operations

Analog Integrated Circuit Device Data

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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES APPLICATION WAKE-UP FROM THE 33742 When the application is in Stop mode, it can be awakened from the SBC side. When a wake-up condition is detected by the SBC (for example, CAN, wake-up input), the 33742 enters the Normal Request mode and generates an interrupt pulse at the INT pin. APPLICATION WAKE-UP FROM THE MCU When the device is in the Stop mode, a wake-up event may come from the system MCU. In this case the MCU selects the device the using a LOW-to-HIGH transition on the 33742 CS pin. Then the 33742S goes into Normal Request mode and generates an interrupt pulse at the INT pin. STOP MODE CURRENT MONITOR If the VDD output current exceeds an internal set threshold (IDDS-WU), the SBC automatically enters the Normal Request mode and generates an interrupt at the INT pin. The interrupt is a non-maskable and the INTR register will have no flag set. INTERRUPT GENERATION WHEN WAKE-UP FROM STOP MODE When the SBC wakes from Stop mode, it first enters the Normal Request mode before generating a 10 µs typical pulse on the INT pin. These are non-maskable interrupts with the wake-up event read through the SPI registers, the CANWU bit in the CAN Register (CANR), or the LCTRx bit in the Wake-Up Register (WUR). In case of wake-up from Stop mode overcurrent situation or from forced wake-up, no bits are set. After the INT pulse, the 33742 accepts SPI command after a time delay (t S-1STSPI). WATCHDOG SOFTWARE IN STOP MODE If the SBC watchdog is enabled, the application must provide a “system ok” response before the end of the 33742 watchdog time. Typically an MCU initiates the wake-up of the 33742 through the SPI wake-up ( CS activation). The SBC will awaken and jump into the Normal Request mode. The MCU has to configure the 33742 to go to either Normal or Standby mode. The MCU can then decide to return to the Stop mode. If no MCU wake-up occurs within the watchdog time period, the SBC activates the RST pin and jumps into the Normal Request mode. The MCU can then be re-initialized. STOP MODE ENTER COMMAND Stop mode is entered at the end of the SPI message at the rising edge of the CS. (Refer to the t CS-STOP data in the Dynamic Electrical Characteristics table on page 17.) Once Stop mode is entered, the SBC can wake up from a VDD regulator overcurrent detection state. In order to allow time for the MCU to complete the last CPU instruction and enter its low power mode, a deglitcher time of 40 µs typical is implemented. Figure 11, page 27, depicts the operation of entering the Stop mode. Stop VDD: ON (Limited Current Capability), V2: OFF, HS:OFF or Cyclic Sense CAN, SPI, L0 : L3, Cyclic Sense, Forced Wake-Up, IDD Overcurrent (39) Normally HIGH. Active LOW if WDOG (40) or VDD undervoltage occurs Signal 33742S wake-up and IDD > IDDS-WU (not maskable) Running if enabled. Not running if disabled Low power. Wake-up capability if enabled Sleep VDD: OFF, V2: OFF, HS: OFF or Cyclic CAN, SPI, L0 : L3, Cyclic Sense Forced Wake-Up LOW Not Active Not running Low power. Wake-up capability if enabled Normal Debug (38) Same as Normal – Normally HIGH. Active LOW if VDD undervoltage occurs Same as Normal Not running Same as Normal Standby Debug (38) Same as Standby – Normally HIGH. Active LOW if VDD undervoltage occurs Same as Standby Not running Same as Standby Stop Debug (38) Same as Stop Same as Stop Normally HIGH. Active LOW if VDD undervoltage occurs Same as Stop Not running Same as Stop Flash Programming Forced externally – Not operating Not operating Not operating Not operating Notes 38. Mode entered via special sequence described under the heading Debug Mode: Hardware and Software Debug with the 33742 beginning on page 30. 39. I DD overcurrent always enabled. 40. WDOG if enabled.

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Figure 12. RST and WDOG Output Operation wake-up occurs from Stop mode. (bits LX2HS and HSAUTO are set to 0). and L3 are configured together. cyclic sense) is valid for all four wake-up inputs. independent of the 33742 operational modes. details of the wake-up detection. event comes through the MCU.

33742 POWER-UP AND WAKE-UP FROM SLEEP

mode prior to moving into Normal Request mode. shows device operation after power-up.

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of the SBC internal software watchdog timer. will generate a reset every 350 ms until the part is configured.

• Step 1– Power down the SBC.
• Step 2 – Power up the SBC. This sets the BATFAIL bit, allowing the 33742 to enter Normal Request mode.
• Step 3 – Write to the TIM1 sub register to allow the SBC to enter Normal mode.
• Step 4 – Write to the MCR register with data 0000. This enables the debug mode. Complete SPI byte is 0001 0000.
• Step 5 – Write to the MCR register normal debug. SPI byte is 0001 x101. Important While in debug mode, the SBC can be used without having to clear the watchdog on a regular basis to facilitate software and hardware debug.
• Step 6 – To leave the debug mode, write 0000 to the MCR register. At Step 2, the SBC is in Normal Request. Steps 3, 4, and 5 should be completed consecutively and within the 350 ms time period of the Normal Request mode. If not, the 33742 will go into Reset mode and enter Normal Request again. Figure 15, page 30, illustrates debug mode selection.

Figure 15. Entering Debug Mode window of the Normal Request mode. of the SBC once the debug mode has been selected.

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Figure 18. Simplified Schematic for Microcontroller Flash Programming

33742 MCU with

Note External supply and sources applied to VDD, RST, and WDOG test points on application circuit board.

5.0 V Programming Tool

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Figure 20. CAN Interface Levels page 25, Table 9, below, and Table 10, page 35. RXD loop time is affected by the slew rate selection. Table 9. CAN Interface / 33742S Modes and Pin Status—Ope ration with Ballast on V2 (44)

5.0 V Internal Pullup

Sleep Sleep 0.0 V LOW LOW Floating to GND NO. Stop Sleep 0.0 V LOW LOW Floating to GND NO.

1. See also Figure 31, page 52.

• Sleep mode with CAN wake-up enable: detection of incoming CAN message and SBC wake-up.
• Sleep mode with CAN wake-up disable: no detection of incoming CAN message. The CAN Sleep modes are set via the CAN SPI register. In CAN Sleep mode (with wake-up enable or disable), the CAN interface is internally supplied from the VSUP pin. The voltage at V2 pin can be either 5.0 V or turned off. When the CAN is in Sleep mode, the current sourced from V2 is extremely low. In most cases the V2 voltage is off; however, the CAN can be placed into Sleep mode even with 5.0 V applied on V2. In CAN Sleep mode, the CANH and CANL drivers are disabled, and the receiver is also disabled. CANH and CANL are high-impedance mode to ground. CAN SIGNALS IN TXRX AND SLEEP MODES When the CAN interface is set back into TXRX mode by an SPI command, CAN H and CANL are set in recessive level. This is illustrated in Figure 21.

Table 10. CAN Interface / 33742 Modes and Pin Status — Operation without Ballast on V2 (45) Sleep Sleep 0.0 V LOW LOW Floating to GND NO. Stop Sleep 0.0 V LOW LOW Floating to GND NO.

1. See also Figure 36, page 55.

36 Freescale Semiconductor

Figure 21. CAN Signals in TXRX and Sleep Modes

• The CAN interface wake-up receiver must receive a series of three consecutive valid dominant pulses, each of which must be longer than 500 ns and shorter than 500 µs.
• The distance between 2 pulses must be lower than 500 µs.
• The three pulses must occur within a time frame of 1.0 ms. The pattern wake-up of the 33742 CAN interface allow wake-up by any CAN message content. Figure 22 below illustrates the CAN signals during a CAN bus Sleep state and wake-up sequence.

Figure 22. CAN Bus Signal During Can Sleep State and Wake-Up Sequence

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Figure 24. CAN Bus Simplified Structure Table 11. Short to GND, Short to VSUP , and Short to 5.0 V (VDD) Detection Truth Table

measured by the Hg comparator, is also close to zero. which bus line, CANL or CANH, is shorted to GND or VSUP. once the driver is turned on. indicate that a CAN bus failure has been detected. however, is it not possible to fully identify the specific error. [1} if the error is not identified). registers and bit D1 will be reset to logic [0]. Figure 25 and explained below, is necessary. Figure 25. RXD Path and RXD Permanent Recessive Detection Principle

2.0 V Sampling Sampling

Note RXD Flag is neither the RXPR bit in the LPC register nor the CAN-F bit in the INTR register.

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Figure 26. RXD Recovery Conditions possible. The SBC has a TXD permanent time-out detector. failure is reported in the TIM1 register. CANCLR bit in the CAN register). CAN message is received, the RXD will be at a LOW. mode and no further communication is possible. is done by an SPI command and controlled by the MCU. reported in the CAN register. nor the CAN-F bit in INTR register.

Table 12 describes the relationship between device fault or warning and the operation of the VDD, V2, CAN, and HS interface. Table 12. Fault / Warning Battery Fail Turn OFF Turn OFF Turn OFF due to V2. VDD Overtemperature Turn OFF Turn OFF Turn OFF due to V2. Turn OFF Turn OFF due to V2. Watchdog Reset ON Turn OFF Turn OFF due to V2.

1. Refer to descriptions of CANH and CANL shor t to GND, VDD, and VSUP elsewhere in table.
2. Peak current 150 mA during TXD dominant only. Due to loss of communication, CAN controller reaches bus OFF state. Average current
3. Overcurrent might be detected. THERM-CUR bit set in CAN register.

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the internal SBC register address. Bit 4 is a read/write bit. read back from the 33742 to the MCU. Figure 27. Data Format Description. Table 13. Possible Reset Conditions

33742 Reset POR Power-ON Reset

33742 Mode

33742 Mode RESET 33742S in Reset Mode

Table 14. List of Registers

• TIM1: Watchdog timing control, Watch - dog Window (WDW) or Watchdog Tim- eout (WTO) mode
• TIM2: Cyclic Sense and Forced Wake- Up timing selection CANL and TXD failure reporting LPC $110 Low Power Control Register (LPC) on page 49 Control HS periodic activation in Sleep and Stop modes, Forced Wake-Up mode activation, CAN-INT mode selection CANH and RXD failure reporting INTR $111 Interrupt Register (INTR) on page 51 Enable or Disable of Interrupts Interrupt source

Tables 15 through 17 describes the various Mode Control Registers. Table 15. Mode Control Register

1. BATFAIL bit cannot be set by SPI. BATFA IL is set when VSUP falls below 3.0 V.
2. See Table 13 page 42, for definitions of reset conditions

Table 16. Mode Control Register Control Bits Software Debug with the 33742, page 30. 1 0 1 Normal No Watchdog running. Debug Mode.

1. Watchdog ON or OFF depends on RCR bit D3.
2. Before entering Sleep mode, BATFAIL bit in MCR must be previ ously cleared (MCR read operation), and NOSTOP bit in RCR must be

previously set to logic [1]. Table 17. Mode Control Register Status Bits 0 No overtemperature pre-warning. 1 Temperature pre-warning on VDD regulator (bit latched). 1 CAN Failure or HS overtemperature or V2 low. 0 No watchdog reset occurred.

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Tables 18 and 19 contain various Reset Control Register information. mode, slew rate, and wake-up. Table 18. Reset Control Register

1. See Table 13 page 42, for definitions of reset conditions.

Table 19. Reset Control Register Control Bits 1 Watchdog runs in Stop Mode. 0 Device cannot enter Sleep Mode. 1 Sleep mode allowed. Device can enter Sleep Mode. 0 CAN Sleep Mode disable (despite D0 bit in CAN register). 1 CAN Sleep Mode enabled (in addition to D0 in CAN register). 0 Reset Threshold 1 selected (typ 4.6 V). 1 Reset Threshold 2 selected (typ 4.2 V). Table 20. CAN Register

1. See Table 13, page 42, for definitions of reset conditions.

Table 21. CANCLR Control Bits recovery conditions must occur to re-enable.

in Normal and Standby modes, while Table 26 provides status bit information. Table 22. CAN High-Speed Transceiver Modes Table 23. CAN Register Status Bits 0 Identified CAN failure (55). 1 Non-identified CAN failure. 0 No overtemperature or overcurrent on CANH or CANL drivers. 1 Overtemperature or overcurrent on CANH or CANL drivers.

1. Error bits are latched in the CAN register.

Table 24. Input / Output Register

1. See Table 13, page 42, for definitions of reset conditions.

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Standby modes as port expander, as well as for waking up the SBC from Sleep or Stop modes (Table 27). configured together (Table 28). Table 25. HSON Control Bits 0 HS OFF, in Normal and Standby modes. 1 HS ON, in Normal and Standby modes. (57).

1. When HS is turned OFF due to an overtemperature condition, it can be turned ON again by setting the appropriate control bit to 1. Error

bits are latched in the IOR register. Table 26. Input / Output Register Status Bits 1 SBC accepts command to go to Debug modes (no Watchdog). Table 27. Wake-Up Register

1. See Table 13, page 42, for definitions of reset conditions.

• T I M 1 — Controls the watchdog timing selection as well as either the watchdog window or the watchdog time-out option (Figure 28 and Figure 29, respectively). TIM1 is selected when bit D3 is 0 (Table 30). Watchdog timing characteristics are described in Table 31.
• T I M 2 — Selects an appropriate timing for sensing the wake-up circuitry or cyclically supplying devices by switching the HS on or off. TIM2 is selected when bit D3 is 1 (Table 32). Figure 30, page 49, describes HS operation when cyclic sense is selected Cyclic sense timing characteristics are described in Table 34, page 49. Both subregisters also report the CANL and TXD diagnostics.

Table 28. Wake-Up Register Control Bits Table 29. Wake-Up Register Status Bits (59)

1. WUR status bits have two functions. After SBC wake-up, they indicate the wake up source; for example, L2WU set at logic [1] if wake-

first reading of the WUR register, the LxWU bits are reset. This can occur only if the SBC was in Stop mode. Table 30. TIM1 Timing and CANL Failure Diagnostic Register

1. See Table 13, page 42, for definitions of reset conditions.

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Figure 28. Window Watchdog Figure 29. Timeout Watchdog Table 31. TIM1 Control Bits Table 32. Timing Register Status Bits Table 33. TIM2 Timing and CANL Failure Diagnostic Register

1. See Table 13, page 42, for definitions of reset conditions.

Figure 30. HS Operation When Cyclic Sense Is Selected

• The state of HS in Stop and Sleep mo des (HS permanently OFF or HS cyclic).
• Enable or disable of the forced wake-up function (SBC automatic wake-up after time spent in Sleep or Stop modes; time is defined by the TIM2 sub register).
• Enable or disable the sense of the wake-up inputs (Lx) at the sampling point of the Cyclic Sense period (LX2HS bit). (Refer to Reset Control Register (RCR) on page 44 for details of the LPC register setup required for proper cyclic sense or direct wake- up operation. The LPC register also reports the CANH and RXD diagnostic. Cyclic Sense Timing, OFF Time time HS Sample 10 µs HS OFF HS ON Lx Sampling Point Cyclic Sense Timing, ON Time

Table 34. TIM2 Control Bits Table 35. Low Power Control Register

1. See Table 13, page 42, for definitions of reset conditions.

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Table 36. LX2HS Control Bits 1 Yes. Lx inputs sensed at sampling point. Table 37. HSAUTO Control Bits 1 ON, HS Cyclic, period defined in TIM2 subregister. Table 38. CAN-INT Control Bits 0 Interrupt as soon as CAN bus failure detected. 1 Interrupt when CAN bus failure detected and fully identified.

1. If CAN-INT is at logic [0], any undetermined CAN failure will be latched in the CAN register (bit D1: CAN-UF) and can be accessed by

allow clearing the CAN-UF bit. Table 39. LPC Status Bits 0 No RXD permanent recessive.

in the CAN register and the IOR register. (not bit set into the INTR register). Table 40. Interrupt Register

1. If only HSOT - V2LOW interrupt is selected (only bit D2 set in INTR register), reading INTR register bit D2 leads to two possibilities:
2. Bit D2 = 1: Interrupt source is HSOT.
3. Bit D2 = 0: Interrupt source is V2LOW.

HSOT and V2LOW bits status are available in the IOR register.

1. See Table 13, page 42, for definitions of reset conditions.

Table 41. Interrupt Register Control Bits CANF Mask bit for CAN failures. HSOT - V2LOW Mask bit for HS overtemperature AND V2LTH < 4.0 V. VSUPLOW Mask bit for VBF(EW) < 5.8 V. Table 42. Interrupt Register Status Bits 0 No VDD medium temperature (pre-warning). 1 VDD medium temperature (pre-warning).

52 Freescale Semiconductor

and from reverse battery. This is illustrated in Figure 31. Figure 31. SBC Typical Application Schematic

1.0 Mbps CAN

5.0 V/200 mA

Rp, Rd: Example: 1.0 kΩ depending on switch type.

54 Freescale Semiconductor

Figure 33. Power up sequence, No W/D write at first When the VDD overload condition is removed, the 33742 restarts in Normal Request mode. Figure 34. Undervoltage on VDD

Analog Integrated Circuit Device Data

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PACKAGE AND THERMAL CONSIDERATIONS PACKAGING PACKAGE AND THERMAL CONSIDERATIONS The 33742 SBC is a standard surface mount 28-pin SOIC wide body. In order to improve the thermal performances of the SOIC package, eight of the 28 pins are internally connected to the package lead frame for heat transfer to the printed circuit board. PACKAGING DIMENSIONS Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on the 98A drawing number below. DW SUFFIX EG SUFFIX (PB-FREE) 28-LEAD SOICW PLASTIC PACKAGE 98ASB42345B ISSUE G

Analog Integrated Circuit Device Data Freescale Semiconductor 57 33742 PACKAGING PACKAGING DIMENSIONS DW SUFFIX EG SUFFIX (PB-FREE) 28-LEAD SOICW PLASTIC PACKAGE 98ASB42345B ISSUE G

Analog Integrated Circuit Device Data

58 Freescale Semiconductor

EP SUFFIX (PB-FREE) 48-LEAD QFN 98ARH99048A ISSUE F

Analog Integrated Circuit Device Data Freescale Semiconductor 59 33742 PACKAGING PACKAGING DIMENSIONS EP SUFFIX (PB-FREE) 48-LEAD QFN 98ARH99048A ISSUE F

Analog Integrated Circuit Device Data

60 Freescale Semiconductor

EP SUFFIX (PB-FREE) 48-LEAD QFN 98ARH99048A ISSUE F

J), and thermal resistance (RθJA). measurement and simulation according to the standards listed below. Figure 38. Surface Mount for SOIC Wide Body Table 43. Thermal Performance Comparison

1. Per JEDEC JESD51-2 at natural convection, still air
2. 2s2p thermal test board per JEDEC JESD51-7.
3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the center lead.

1. Single layer thermal test board per JEDEC JESD51-3.
2. Thermal resistance between the die junction and the

surface and remaining surfaces insulated.

28 Pin SOICW

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Figure 39. Thermal Test Board Table 44. Thermal Resistance Performance

33742 Pin Connections

Figure 40. Device on Thermal Test Board RθJA Figure 41. Transient Thermal Resistance RθJA,

1 W Step response, Device on Thermal Test Board Area A = 600 (mm2)

Analog Integrated Circuit Device Data

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REVISION HISTORY

REVISION DATE DESCRIPTION OF CHANGES 3.0 2/2006 • Converted to Freescale format

• Implemented Revision History page 4.0 6/2006 • Added Thermal Addendum (Rev. 1.0)
• Changed Data Sheet from “Advanced” to “Final” 5.0 8/2006 • Added MCZ33742EG/R2 and MCZ33742SEG/R2 to the Ordering Information block 6.0 8/2006 • Replaced label for Logic Inputs to Logic Signals (RXD, TXD, MOSI, MISO, CS, SCLK, RST, WDOG, and INT) on page 7 7.0 10/2006 • Removed all references to the 54 pin package.
• Removed Peak Package Reflow Temperature Duri ng Reflow (solder reflow) parameter from Maximum Ratings on page 7. Added note with instructions from www.freescale.com. 8.0 2/2007 • Restated notes in Maximum Ratings on page 7 9.0 3/2007 • Text corrections to the included thermal addendum 10.0 5/2007 • Added 48 pin QFN package, Part Number PCZ33742EP/R2, and Outline Package drawing Number 98ARH99048A.

Rev. 10.0 RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http:// www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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