PCS811 PULSECORE | Alldatasheet

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January 2007 PCS811/PCS812 rev 0.1 Notice: The information in this document is subject to change without notice. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com 5-Pin µP Voltage Supervisor with Manual Reset

FEATURES

  • Ultra Low Supply Current 1µA(typ.)
  • Guaranteed Reset Valid to VCC=0.9V
  • Available in two Output Types: Push-Pull Active Low (PCS811), Push-Pull Active High (PCS812)
  • 140ms Min. Power-On Reset Pulse Width
  • Internally Fixed Threshold 2.3V, 2.6V, 2.7V,
  • Tight Voltage Threshold Tolerance: 1.5%
  • Low profile Package: SOT-23-5

APPLICATIONS

  • Notebook Computers
  • Digital Still Cameras
  • PDAs
  • Critical Microprocessor Monitoring RESET THRESHOLD Suffix Voltage(V) L 4.6 M 4.4 J 4.0 T 3.1 S 2.9 Q 2.7 R 2.6 P 2.3

DESCRIPTION

PCS811/PCS812 are low-power microprocessor (µP) supervisory circuits used to monitor power supplies in µP and digital systems. They provide applications with benefits of circuit reliability and low cost by eliminating external components. PCS811/PCS812 also offer a manual reset input. These devices perform as valid singles in applications with VCC ranging from 6.0V down to 0.9V. The reset signal lasts for a minimum period of 140ms whenever VCC supply voltage falls below preset threshold. Both PCS811 and PCS812 were designed with a reset comparator to help identify invalid signals, which last less than 140ms. The only difference between them is that they have an active-low RESET output an d active-high RESET output, respectively. Low supply current (1µA) makes PCS811/PCS812 ideal for portable equipment. The devices are available in 5- SOT-23 package Typical Operating Circuit VCC GND GND VCC VCC RESET (RESET) RESET INPUT MR PCS811 (PCS812) Pushbutton Switch µP

January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 2 of 8 Notice: The information in this document is subject to change without notice. Pin Diagram Pin Description Block Diagram Pin# PCS811 PCS812 Pin Name Description 1 1 GND Ground. 2 2 NC No Connection 3 - RESET RESET is asserted LOW if VCC falls below VTH. RESET remains LOW for atleast 140ms (TRST) once VCC exceeds the Threshold. In addition, RESET is active LOW as long as the manual reset (MR) is low. - 3 RESET RESET is asserted HIGH if VCC falls below VTH. RESET remains HIGH for atleast 140ms (TRST) once VCC exceeds the threshold. In addition, RESET is active HIGH as long as the manual reset (MR) is low. 4 4 MR Manual Reset Input. A logic LOW on MR asserts reset. Reset remains active as long as MR is LOW and for at least 180ms (TMRST) once MR returns HIGH. The active low input has an internal 20kΩ pull-up resistor. The input should be left open if not used. It can be driven by TTL or CMOS logic or shorted to ground by a switch. 5 5 VCC Power supply input voltage (3.0V, 3.3V, 5.0V) GND VCC NC RESET (RESET) MR PCS811 (PCS812) RESET Generator Bandgap MR RPULL_UP 20K VCC GND RESET (RESET)

January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 3 of 8 Notice: The information in this document is subject to change without notice. DETAIL DESCRIPTION RESET OUTPUT µP will be activated at a valid reset state. These µP supervisory circuits assert reset to prevent code execution errors during power-up, power-down, or brownout conditions. RESET is guaranteed to be a logic low for V TH>VCC>0.9V. Once VCC exceeds the reset threshold, an internal timer keeps RESET low for the reset timeout period; after this interval, RESET goes high. If a brownout condition occurs (VCC drops below the reset threshold), RESET goes low. Any time VCC goes below the reset threshold, the inter nal timer resets to zero, and RESET goes low. The internal timer is activated after VCC returns above the reset thre shold, and RESET remains low for the reset timeout period. The manual reset input (MR) can also initiate a reset. PCS812 has an active-high RESET output that is the inverse of PCS811’s RESET output .PCS811’s RESET output. MANUAL RESET INPUT Many µP-based products require manual reset capability, allowing operators, test technicians, or external logic circuitry to initiate a reset. Logic low on MR asserts reset. Reset will remain asserted for the Reset Active Timeout Period (t RP) after MR returns high. This input has an internal 20KΩ pull-up resistor, so it can be floating if it is not used. MR can be driven with TTL or CMOS-logic levels, or with open-drain/collector outputs. Another alternative is to connect a normal switch from MR to GND to create a manual reset function. Connecting a 0.1µF capacitor from MR to ground can provide noise immunity to prevent noise caused by long cables of MR or noisy environment. BENEFITS OF HIGHLY ACCURATE RESET THRESHOLD PCS811/812 with specified voltage as 5V±10% or 3V±10% are ideal for systems using a 5V±5% or 3V±5% power supply. The reset is guaranteed to assert after the power supply falls out of re gulation, but before power drops below the minimum specified operating voltage range of the system ICs. The pre-trimmed thresholds are reducing the range over which an undesirable reset may occur.

APPLICATION INFORMATION

NEGATIVE-GOING VCC TRANSIENTS In addition to issuing a reset to the µP during power-up, power-down, and brownout conditions, PCS811 series are relatively resistant to short-duration negative-going VCC transient. ENSURING A VALID RESET OUTPUT DOWN TO VCC=0 When VCC falls below 0.9V, PCS811 RESET output no longer sinks current; it becomes an open circuit. In this case, high-impedance CMOS logic inputs connecting to RESET can drift to undetermined voltages. Therefore, PCS811/812 with CMOS is perfect for most applications of VCC below 0.9V. However in applications where RESET must be valid down to 0V, adding a pull-down resistor to RESET causes any leakage cu rrents to flow to ground, holding RESET low. INTERFACING TO µP WITH BIDIRECTIONAL RESET PINS µPs with bidirectional reset pins can contend with PCS811/812 reset outputs. If PCS811 RESET output is asserted high and the µP wants to pull it low, indeterminate logic levels ma y occur. To correct such cases, connect a resistor between PCS811 RESET (or PCS812 RESET) output and the µP reset I/O. Buffer the reset output to other system components.

January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 4 of 8 Notice: The information in this document is subject to change without notice. Absolute Maximum Rating Parameter Min Max Unit VCC 0.3 6.5 V RESET,RESET 0.3 Vcc+0.3 V Input Current (VCC,MR) 20 mA Output Current (RESET or RESET) 20 mA Continuous Power Dissipation (TA=+70°C) 320 mW Operating Junction Temperature Range -40 +85 °C Junction Temperature 125 °C Storage Temperature Range -65 150 °C Lead Temperature (Soldering) 10 sec 260 °C Test Circuit GND TEST CIRCUIT 0.1uF VCC VCC MR Pushbutton Switch RESET (RESET)

January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 5 of 8 Notice: The information in this document is subject to change without notice. Electrical Characteristics: (Typical valves are at TA=+25°C unless otherwise specified.) (Note1) Parameter Symbol Test Conditions Min Typ Max Unit Opreating Voltage VCC 0.9 6 V Supply Current I CC VCC= VTH +0.1V 1 3 μA TA=+25°C 2.265 2.335 P device TA-40°C to 85°C 2.254 2.3 2.346 TA=+25°C 2.561 2.639 R device TA-40°C to 85°C 2.548 2.6 2.652 TA=+25°C 2.660 2.741 Q device TA-40°C to 85°C 2.646 2.7 2.754 TA=+25°C 2.857 2.944 S device TA-40°C to 85°C 2.842 2.9 2.958 TA=+25°C 3.054 3.147 T device TA-40°C to 85°C 3.038 3.1 3.162 TA=+25°C 3.940 4.060 J device TA-40°C to 85°C 3.920 4.0 4.080 TA=+25°C 4.334 4.466 M device TA-40°C to 85°C 4.312 4.4 4.488 TA=+25°C 4.531 4.669 RESET threshold V TH L device TA-40°C to 85°C 4.508 4.6 4.692 V VCC to Reset Delay T RD VCC=V TH to (VTH-0.1V), VTH =3.1V 20 μS TA=+25°C 140 230 560 Reset Active Timeout Period T RP VCC=VTH (MAX) TA-40°C to 85°C 100 1030 mS MR to Reset Progation delay TMD VCC=6V 0.5 μS VIH 0.7VCC MR Input Threshold VIL 0.25VCC V MR Pull-up Resistance 10 20 30 k Ω VOH VCC = V TH +0.1V, ISOURECE =1mA 0.8VCC RESET output Voltage VOL VCC= V TH -0.1V, ISINK =1mA 0.2VCC VOH VCC = V TH +0.1V, ISOURECE =1mA 0.8VCC RESET output Voltage VOL VCC= V TH -0.1V, ISINK =1mA 0.2VCC V Note1: Specifications are production tested at T A =25°C. Specifications over the -40°C to 85°C operating temperature range are assured by design, characterization and correlation with Statistical Quality Controls (SQC). Note 2: RESET output is for PCS811: RESET output for PCS812

January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 6 of 8 Notice: The information in this document is subject to change without notice.

Ordering Information

Part # Threshold Voltage Temperature Range Package Top Marking PCS811LIUKF 4.6 -40°C to +85°C 5-SOT-23 BQ46P PCS811MIUKF 4.4 -40°C to +85°C 5-SOT-23 BQ44P PCS811JIUKF 4.0 -40°C to +85°C 5-SOT-23 BQ40P PCS811TIUKF 3.1 -40°C to +85°C 5-SOT-23 BQ31P PCS811SIUKF 2.9 -40°C to +85°C 5-SOT-23 BQ29P PCS811QIUKF 2.7 -40°C to +85°C 5-SOT-23 BQ27P PCS811RIUKF 2.6 -40°C to +85°C 5-SOT-23 BQ26P PCS811PIUKF 2.3 -40°C to +85°C 5-SOT-23 BQ23P PCS812 ACTIVE HIGH RESET, LEAD FREE DEVICE PCS812LIUKF 4.6 -40°C to +85°C 5-SOT-23 BR46P PCS812MIUKF 4.4 -40°C to +85°C 5-SOT-23 BR44P PCS812JIUKF 4.0 -40°C to +85°C 5-SOT-23 BR40P PCS812TIUKF 3.1 -40°C to +85°C 5-SOT-23 BR31P PCS812SIUKF 2.9 -40°C to +85°C 5-SOT-23 BR29P PCS812QIUKF 2.7 -40°C to +85°C 5-SOT-23 BR27P PCS812RIUKF 2.6 -40°C to +85°C 5-SOT-23 BR26P PCS812PIUKF 2.3 -40°C to +85°C 5-SOT-23 BR23P Note: For parts to be packed in tape and reel, add “T” at the end of the part number PulseCore Semiconductor parts are RoHS Compliant. All parts are lead free by default.

January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 7 of 8 Notice: The information in this document is subject to change without notice. Package Information: 5L SOT 23 Package Dimensions Inches Millimeters Symbol Min Max Min Max A 0.035 0.057 0.95 1.45 A1 0.00 0.006 0.05 0.15 A2 0.035 0.051 0.90 1.30 b 0.009 0.015 0.30 0.50 c 0.003 0.009 0.08 0.22 D 0.111 0.117 2.80 3.00 E 0.106 0.114 2.60 3.00 E1 0.060 0.066 1.50 1.70 L 0.014 0.022 0.30 0.60 L1 0.023 REF 0.60 REF e 0.0256 BSC 0.95 BSC e1 0.0768 BSC 1.90 BSC θ 0° 8° 0° 8°

January 2007 PCS811/PCS812 rev 0.1 5-Pin µP Voltage Supervisor with Manual Reset 8 of 8 Notice: The information in this document is subject to change without notice. © Copyright 2007 PulseCore Semiconductor Corporation. All righ ts reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intende d to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to t he sale and/or use of PulseCore products in cluding liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agree d to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask wor ks rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critic al components in life-supporting systems where a malfunction or failure may reasonably be expected to resu lt in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assu mes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Part Number: PCS811/812 Document Version: 0.1 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued PulseCore Semiconductor, dated 11-11-2003