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Technical content

Features

  • 1x, LVCMOS Peak EMI Reduction
  • Input Frequency: 10 MHz − 30 MHz @ 3.3 V

30 MHz − 100 MHz @ 5 V

  • Output Frequency: 10 MHz − 30 MHz @ 3.3 V
  • Four Different Frequency Deviation Selection
  • Selectable Spread Options: Down Spread and Center Spread
  • Frequency Range Selection
  • Supply V oltage: 5 V ± 0.5 V 3.3 V ± 0.3 V
  • 8 Pin TSSOP, SOIC Package
  • Commercial and Industrial Temperature Range
  • These are Pb−Free Devices This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com SOIC−8 S SUFFIX CASE 751BD PIN CONFIGURATION (Top View) See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

D_C CLKIN / XIN GND TSSOP−8 T SUFFIX CASE 948AL PCS3P2005A

Figure 1. Block Diagram Table 1. ABSOLUTE MAXIMUM RATINGS Table 2. PIN DESCRIPTION 1 CLKIN / XIN I External reference Clock input or Crystal connection. 2 XOUT O Crystal connection. If using an external reference, this pin must be left unconnected. 3 D_C I Deviation Selection. Has an internal pull−up resistor. Refer to Deviation Selection Table. 5 S0 I Deviation Selection. Has an internal pull−up resistor. Refer to Deviation Selection Table. 6 FRS I Frequency Range Selection. Has an internal pull−up resistor. 7 ModOUT O Buffered Modulated Clock Output. 8 VDD P Power supply for the entire chip (3.3 V/5 V). Table 3. FREQUENCY RANGE SELECTION TABLE Table 4. DEVIATION SELECTION TABLE

10 MHz 20 MHz 30 MHz 30 MHz 80 MHz 100 MHz

Table 5. OPERATING CONDITIONS Table 6. DC ELECTRICAL CHARACTERISTICS FOR VDD = 5 V /C0043 0.5 V Table 7. AC ELECTRICAL CHARACTERISTICS FOR VDD = 5 V /C0043 0.5 V

  1. All parameters are specified with 15 pF loaded output.
  2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Table 8. DC ELECTRICAL CHARACTERISTICS FOR VDD = 3.3 V /C0043 0.3 V Table 9. AC ELECTRICAL CHARACTERISTICS FOR VDD = 3.3 V /C0043 0.3 V

  1. All parameters are specified with 15 pF loaded output.
  2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

http://onsemi.com PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O E1 E e b D cA TOP VIEW SIDE VIEW END VIEW /C01131 L Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. SYMBOL θ MIN NOM MAX A b c D E e 0º 8º L 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30

0.65 BSC

1.00 REF

1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40

http://onsemi.com PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E A h θ L c e b D PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. SYMBOL MIN NOM MAX θ A b c D E e h 0º 8º 0.10 0.33 0.19 0.25 4.80 5.80 3.80

1.27 BSC

1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 L 0.40 1.27 1.35

Table 10. ORDERING INFORMATION arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.