PCS2P5T9050A PULSECORE | Alldatasheet

Document overview

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Technical content

Features

  • Optimized for 2.5V LVTTL
  • Guaranteed Low Skew < 25pS (max)
  • Very low duty cycle distortion< 300pS (max)
  • High speed propagation delay < 1.8nS. (max)
  • Up to 200MHz operation
  • Very low CMOS power levels
  • Hot Insert able and over-voltage tolerant inputs
  • 1:5 fan-out buffer
  • 2.5V Supply Voltage
  • Available in TSSOP Package Functional Description The PCS2P5T9050A 2.5V single data rate (SDR) clock buffer is a single-ended input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fan-out from a single input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise. Applications: PCS2P5T9050A is targeted towards Clock and signal distribution applications. Block Diagram OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL OUTPUT CONTROL A GL G Q1

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 2 of 10 Notice: The information in this document is subject to change without notice. Pin Configuration- Top View – TSSOP Package Pin Description Symbol I/O Type Description A I LVTTL Clock input G I LVTTL Gate control for Qn outputs. When G is LO W, these outputs are enabled. When G is HIGH, these outputs are asynchronously disabled to the level designated by GL1. GL I LVTTL Specifies output disable level. If HIGH, t he outputs disable HIGH. If LOW, the outputs disable LOW. Qn O LVTTL Clock outputs VDD PWR Power supply for the device core, inputs, and outputs GND PWR Power supply return for power NOTE: 1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 14 15 GND VDD GND GND VDD GND VDD GND GND V DD NC NC VDD VDD GND VDD A GND G VDD GND VDD GL PCS2P5T9050A

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 3 of 10 Notice: The information in this document is subject to change without notice. Absolute Maximum Ratings Symbol Description Max Unit VDD Power Supply Voltage -0.5 to +3.6 V VI Input Voltage -0.5 to +3.6 V VO Output Voltage -0.5 to V DD +0.5 V TSTG Storage Temperature -65 to +165 °C TJ Junction Temperature 150 °C Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Capacitance1 (TA = +25°C, F = 1.0MHz) Symbol Parameter Min Typ Max Unit CIN Input Capacitance 6 pF NOTE: 1. This parameter is measured at characterization but not tested. Recommended Operating Range Symbol Description Min Typ Max Unit TA Ambient Operating Temperature -40 +25 +85 ° C VDD Internal Power Supply Voltage 2.3 2.5 2.7 V

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 4 of 10 Notice: The information in this document is subject to change without notice. Symbol Parameter Test Conditions Min Typ4 Max Unit IIH Input HIGH Current V DD= 2.7V VI = VDD/GND ±5 µA IIL Input LOW Current V DD= 2.7V VI = GND/VDD ±5 VIK Clamp Diode Voltage V DD= 2.3V, IIN= -18mA -0.7 - 1.2 V VIN DC Input Voltage -0.3 +3.6 V VIH DC Input HIGH 2 1.7 V VIL DC Input LOW 3 0.7 V IOH= -12mA V DD- 0.4 V VOH Output HIGH Voltage IOH= -100µA V DD- 0.1 V IOL= 12mA 0.4 V VOL Output LOW Voltage IOL= 100µA 0.1 V NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Voltage required to maintain a logic HIGH. 3. Voltage required to maintain a logic LOW. 4. Typical values are at V DD = 2.5V, +25°C ambient. Power Supply Characteristics Symbol Parameter Test Conditions1 Typ Max Unit IDDQ Quiescent VDD Power Supply Current VDD= Max., Reference Clock = LOW Outputs enabled, All outputs unloaded 1 1.5 mA IDDD Dynamic VDD Power Supply Current per Output VDD= Max., CL= 0pF 100 150 µA/MHz VDD= 2.5V., FREFERENCE CLOCK = 100MHz, CL= 15pF 50 65 ITOT Total Power V DD Supply Current VDD= 2.5V., FREFERENCE CLOCK = 200MHz, CL= 15pF 75 100 mA NOTE: 1. The termination resistors are excluded from these measurements.

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 5 of 10 Notice: The information in this document is subject to change without notice. Input AC Test Conditions Symbol Parameter Value Units VIH Input HIGH Voltage V DD V VIL Input LOW Voltage 0 V VTH Input Timing Measurement Reference Level 1 V DD/2 V tR, tF Input Signal Edge Rate 2 2 V/nS NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform. Symbol Parameter Min Typ Max Unit Skew Parameters tSK(O) Same Device Out put Pin-to-Pin Skew1 25 pS tSK(P) Pulse Skew 2 300 pS tSK(PP) Part-to-Part Skew 3 300 pS Propagation Delay tPLH tPHL Propagation Delay A to Qn 1.8 nS tR Output Rise Time (20% to 80%) 350 850 pS tF Output Fall Time (20% to 80%) 350 850 pS fO Frequency Range 200 MHz Output Gate Enable/Disable Delay tPGE Output Gate Enable to Qn 3.5 nS tPGD Output Gate Enable to Qn Driven to GL Designated Level 3 nS NOTES: 1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device. 2. Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device. 3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical V DD levels and temperature. 4. Guaranteed by design.

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 6 of 10 Notice: The information in this document is subject to change without notice. AC Timing Waveforms Propagation and Skew Waveforms NOTE: Pulse Skew is calculated using the following expression: t SK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse. Gate Disable/Enable Showing Runt Pulse Generation NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their G signal to avoid this problem.

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 7 of 10 Notice: The information in this document is subject to change without notice. Test Circuit and Conditions Test Circuit for Input/Output Input/Output Test Conditions Symbol VDD= 2.5V ± 0.2V Unit VTH V DD/ 2 V R1 100 Ω R2 100 Ω CL 15 pF

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 8 of 10 Notice: The information in this document is subject to change without notice. Package Diagram 28L TSSOP (173 mil) Dimensions Inches Millimeters Symbol Min Max Min Max A …. 0.043 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.031 0.041 0.80 1.05 D 0.3779 0.3858 9.60 9.80 L 0.020 0.030 0.50 0.75 E 0.252 BSC 6.40 BSC E1 0.169 0.177 4.30 4.50 b 0.007 0.012 0.19 0.30 b1 0.007 0.010 0.19 0.25 c 0.004 0.008 0.09 0.20 c1 0.004 0.006 0.09 0.16 L1 0.039 REF 1.0 REF e 0.026 BSC 0.65 BSC θ1 0° 8° 0° 8° θ2 12° REF 12° REF θ3 12° REF 12° REF

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 9 of 10 Notice: The information in this document is subject to change without notice.

Ordering Information

Part Number Marking Package Type Operating Range PCS2P5T9050AF-28TT 2P5T9050AF 28 Pin TSSOP, Tube, Pb Free Commercial PCS2P5T9050AF-28TR 2P5T9050AF 28 Pin TSSOP, Tape and Reel, Pb Free Commercial PCS2I5T9050AF-28TT 2I5T9050AF 28 Pin T SSOP, TUBE, Pb Free Industrial PCS2I5T9050AF-28TR 2I5T9050AF 28 Pin TSSOP, Tape and Reel, Pb Free Industrial PCS2P5T9050AG-28TT 2P5T9050AG 28 Pin TSSOP, Tube, Green Commercial PCS2P5T9050AG-28TR 2P5T9050AG 28 Pin TSSOP, Tape and Reel, Green Commercial PCS2I5T9050AG-28TT 2I5T9050AG 28 Pi n TSSOP, TUBE, Green Industrial PCS2I5T9050AG-28TR 2I5T9050AG 28 Pin T SSOP, Tape and Reel, Green Industrial Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. OR – TSOT23 -6,T/R SR – SOIC, T/R TT – TSSOP, TUBE QR – QFN, T/R TR – TSSOP, T/R QT – QFN, TRAY VT – TVSOP, TUBE BT – BGA, TRAY VR – TVSOP, T/R BR – BGA, T/R ST – SOIC, TUBE UR – SOT-23, T/R AR – SSOP, T/R DR – QSOP, T/R AT – SSOP, TUBE DT – QSOP, TUBE PIN COUNT X = Automotive I = Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 – reserved 6 – power management 2 – Non PLL based 7 – power management 3 – EMI Reduction 8 – power management 4 – DDR support products 9 – Hi performance 5 – STD Zero Delay Buffer 0 - reserved PulseCore Semiconductor Mixed Signal Product F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS LEAD FREE PART

November 2006 PCS2P5T9050A rev 0.2 2.5V Single Data Rate1:5 Clock Buffer Terabuffer 10 of 10 Notice: The information in this document is subject to change without notice. © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All ot her brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors t hat may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product descri bed herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not in tended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the app lication or use of any product described herein, and disclaims any express or implied warrant ies related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, mercha ntability, or infringement of any intellec tual property rights, except as express agreed to in PulseCore’ s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusiv ely according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellect ual property rights of PulseCore or third partie s. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseC ore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P5T9050 Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003