PCS2I2310ANZ PULSECORE | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- One input to 10 output buffer/driver
- Supports up to four SDRAM SO-DIMMs
- Two additional outputs for feedback
- Serial interface for output control
- Low skew outputs
- Up to 133MHz operation
- Multiple V DD and VSS pins for noise reduction
- Dedicated OE pin for testing
- Space-saving 28 Pin SSOP package
- 3.3V operation Functional Description The PCS2I2310ANZ is a 3.3V buffer designed to distribute high-speed clocks in mobile PC applications. The part has 10 outputs, 8 of which can be used to drive up to four SDRAM SO-DIMMs, and the remaining can be used for external feedback to a PLL. The device operates at 3.3V and outputs can run up to 133MHz, thus making it compatible with Pentium II®i processors. The PCS2I2310ANZ also includes a serial interface (IIC), which can enable or disable each output clock. The IIC is Slave Receiver only and is Standard mode compliant. IIC Master can write into the IIC registers but cannot read back. The first two bytes after address should be ignored by IIC Block and data is valid after these two bytes as given in IIC Byte Flow Table. On power-up, all output clocks are enabled. A separate Output Enable pin facilitates testing on ATE. i Pentium II is a registered trademark of Intel Corporation Block Diagram
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 2 of 12 Notice: The information in this document is subject to change without notice. Pin Configuration
28 Pin SSOP Package-- Top View
Description
Pins Name Type Description 1, 5, 10, 19, 24, 28 V DD P 3.3V Digital voltage supply 4, 8, 12, 17, 21, 25 V SS P Ground 13 V DDIIC P 3.3V Serial interface voltage supply
16 V SSIIC P Ground for serial interface
9 BUF_IN I Input clock, 5V tolerant
20 OE I Output Enable, three-states outputs when LOW. Internal pull-up to VDD 14 SDATA I/O Bi-directional Serial data pin. Internal pull-up to VDD. 5V tolerant 15 SCLK I Serial clock input. Internal pull-up to V DD. 5V tolerant 2, 3, 6, 7 SDRAM [0–3] O SDRAM byte 0 Clock Outputs 22, 23, 26, 27 SDRAM [4–7] O SDRAM byte 1 Clock Outputs 11, 18 SDRAM [8–9] O SDRAM byte 2 Clock Outputs 16pi TSSOP PCS2P2310ANZ VDD SDRAM7 VSS VDD SDRAM5 SDRAM4 VSS SDRAM6 VSS SDRAM3 SDRAM2 VDD VSS VDD SDRAM0 SDRAM1 SDATA VDDIIC VSS SDRAM8 VDD BUF_IN VDD SDRAM9 VSS VSSIIC SCLOCK OE 28 pin SSOP
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 3 of 12 Notice: The information in this document is subject to change without notice. Device Functionality OE SDRAM [0–17]
0 High-Z
1 1 x BUF_IN Serial Configuration Map
- The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
- Reserved and unused bits can be programmed to either “0” or “1”.
- Serial interface address for the PCS2I2310ANZ is: A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 ---- Byte 0: SDRAM Active/Inactive Register1 (1 = Enable, 0 = Disable), Default = Enable Bit Pin # Description Bit 7 -- Unused Bit 6 -- Unused Bit 5 -- Unused Bit 4 -- Unused Bit 3 7 SDRAM3 (Active/Inactive) Bit 2 6 SDRAM2 (Active/Inactive) Bit 1 3 SDRAM1 (Active/Inactive) Bit 0 2 SDRAM0 (Active/Inactive) Byte 1: SDRAM Active/Inactive Register1 (1 = Enable, 0 = Disable), Default = Enable Bit Pin # Description Bit 7 27 SDRAM7 (Active/Inactive) Bit 6 26 SDRAM6 (Active/Inactive) Bit 5 23 SDRAM5 (Active/Inactive) Bit 4 22 SDRAM4 (Active/Inactive) Bit 3 -- Unused Bit 2 -- Unused Bit 1 -- Unused Bit 0 -- Unused Byte 2: SDRAM Active/Inactive Register1 (1 = Enable, 0 = Disable), Default = Enable Bit Pin # Description Bit 7 18 SDRAM9 (Active/Inactive) Bit 6 11 SDRAM8 (Active/Inactive) Bit 5 -- Reserved Bit 4 -- Reserved Bit 3 -- Reserved Bit 2 -- Reserved Bit 1 -- Reserved Bit 0 -- Reserved Note 1 : When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default value of all the bits is high after chip is powered up. IIC Byte Flow Byte Description
1 IIC Address
2 Command (dummy value, ignored)
3 Byte Count (dummy value, ignored)
4 IIC Data Byte 0
5 IIC Data Byte 1
6 IIC Data Byte 2
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 4 of 12 Notice: The information in this document is subject to change without notice. Absolute Maximum Ratings Operating Conditions Parameter Description Min Max Unit VDD Supply Voltage 3.135 3.465 V TA Operating Temperature (Amb ient Temperature) 0 70 °C CL Load Capacitance 20 30 pF CIN Input Capacitance 7 pF tPU Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms
Electrical Characteristics
Parameter Description Test Conditions Min Typ Max Unit VIL Input LOW Voltage Except seri al interface pins 0.8 V VILIIC Input LOW Voltage For serial in terface pins only 0.7 V VIH Input HIGH Voltage 2.0 V VOL Output LOW Voltage 1 I OL= 25 mA 0.4 V VOH Output HIGH Voltage 1 I OH = –36 mA 2.4 V ICC Quiescent Supply Current VDD= 3.465V, Vi = VDD or GND IO =0 50 100 µA IOZ High Impedance Output Current VDD= 3.465V, Vi = VDD or GND ±10 µA IOFF OffState Current (for SCL ,SDATA) VDD= 0V, Vi = 0V or 5.5V 50 µA ∆ICC Change in Supply Current VDD= 3.135V to 3.465V One Input at VDD-0.6, All other Inputs at VDD or GND 500 µA Ii Input Leakage VDD= 3.465V or GND (Applicable to all Input Pins) -5 +5 µA IDD Supply Current 1 Unloaded outputs, 133MHz 266 mA IDD Supply Current 1 Loaded outputs, 30pF, 133MHz 360 mA IDD Supply Current 1 Unloaded outputs, 100MHz 200 mA IDD Supply Current 1 Loaded outputs, 30pF,100MHz 290 mA IDD Supply Current 1 Unloaded outputs, 66.67MHz 150 mA IDD Supply Current 1 Loaded outputs, 30pF ,66.67MHz 185 mA IDDS Supply Current BUF_IN=VDD or VSS, all other inputs at VDD 500 µA Note: 1. Parameter is guaranteed by design and characterization. Not 100% tested in production. Symbol Parameter Rating Unit VDD Supply Voltage to Ground Potential -0.5V to +7.0 V VIN DC Input Voltage (Except BUF_IN) -0.5V to V DD + 0.5 V VINB DC Input Voltage (BUF_IN) -0.5V to +7.0 V TSTG Storage Temperature -65°C to +150 °C TJ Junction Temperature 150 °C TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) 2000 V
Notice: The information in this document is subject to change without notice. Note: 1 .All parameters specified with loaded outputs.
- Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/nS
- Parameter is guaranteed by design and characterization. Not 100% tested in production.
Figure 1. Load circuit for Switching times
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 7 of 12 Notice: The information in this document is subject to change without notice. Switching Waveforms Duty Cycle Timing All Outputs Rise/Fall Time Output - Output Skew SDRAM Buffer LH and HL Propagation Delay Test Circuits 1.5 V 1.5 V 1.5 V 1.5 V 1.5 V OUTPUT OUTPUT 0.4 V 2.4 V 0.4 V 2.4 V 3.3 V 0 V t3 t4 OUTPUT OUTPUT INPUT VDD VDD GND GND CLKOUT CLOAD OUTPUT TEST CIRCUIT 0.1uF 0.1uF +3.3V +3.3V
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 8 of 12 Notice: The information in this document is subject to change without notice.
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done. Summary
- Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1µF. In some cases, smaller value capacitors may be required.
- The value of the series terminating resistor satisfies the fo llowing equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout
- Footprints must be laid out for optional EMI-reducing capac itors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7pF to 22pF.
- A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50Ω impedance at the clock frequency, under loaded DC conditions.
- If a Ferrite Bead is used, a 10 µF–22µF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. Rs BUF_IN SDATA SCLK VDD VSS Rs SDRAMX Ct VDD Cd = 0.1µ F PCS2I2310ANZ SSOP 28 Cd = Decoupling Capacitor Ct = Optional EMI-Reducing Capacitor Rs = Series Terminating Resistors X = 0 to 10 CPUCLK SDATA SCLK
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 9 of 12 Notice: The information in this document is subject to change without notice. IIC Serial Interface Information The information in this section assumes familiarity with IIC programming. How to program PCS2I2310ANZ through IIC:
- Master (host) sends a start bit.
- Master (host) sends the write address D3 (H).
- PCS2I2310ANZ device will acknowledge.
- Master (host) sends the Command Byte.
- PCS2I2310ANZ device will acknowledge the Command Byte.
- Master (host) sends a Byte count
- PCS2I2310ANZ device will acknowledge the Byte count.
- Master (host) sends the Byte 0
- PCS2I2310ANZ device will acknowledge Byte 0
- Master (host) sends the Byte 1
- PCS2I2310ANZ device will acknowledge Byte 1
- Master (host) sends the Byte 2
- PCS2I2310ANZ device will acknowledge Byte 2
- Master (host) sends a Stop bit. Controller (Host) PCS2I2310ANZ (slave/receiver) Start Bit Slave Address D3(H) ACK Command Byte ACK Byte count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Stop Bit
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 10 of 12 Notice: The information in this document is subject to change without notice.
Package Information
28L SSOP (209 mil) Dimensions Inches Millimeters Symbol Min Max Min Max A …. 0.079 … 2.0 A1 0.002 … 0.05 … A2 0.065 0.073 1.65 1.85 D 0.394 0.409 10.00 10.40 L 0.021 0.037 0.55 0.95 E 0.295 0.319 7.50 8.10 E1 0.197 0.220 5.00 5.60 b 0.009 0.015 0.22 0.38 b1 0.009 0.013 0.22 0.33 c 0.004 0.010 0.09 0.25 c1 0.004 0.008 0.09 0.21 L1 0.050REF 1.25 REF e 0.026 BSC 0.65 BSC θ 0° 8° 0° 8°
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 11 of 12 Notice: The information in this document is subject to change without notice.
Ordering Information
Part Number Marking Package Type Operating Range PCS2P2310ANZG-28-AT 2P2310ANZG 28-pin SSOP –Tube, Green Commercial PCS2P2310ANZG-28-AR 2P2310ANZG 28-pin SSOP –Tape and Reel, Green Commercial PCS2I2310ANZG-28-AT 2I2310ANZG 28-pin SSOP –Tube, Green Industrial PCS2I2310ANZG-28-AR 2I2310ANZG 28-pin SSOP –Tape and Reel, Green Industrial Device Ordering Information PCS2I2310ANZG-28-AR Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. O = SOT U = MSOP S = SOIC E = TQFP T = TSSOP L = LQFP A = SSOP U = MSOP V = TVSOP P = PDIP B = BGA D = QSOP Q = QFN X = SC-70 DEVICE PIN COUNT X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 6 = Power Management 2 = Non PLL based 7 = Power Management 3 = EMI Reduction 8 = Power Management 4 = DDR support products 9 = Hi Performance 5 = STD Zero Delay Buffer 0 = Reserved PulseCore Semiconductor Mixed Signal Product PART NUMBER G = GREEN PACKAGE, LEAD FREE, and RoHS R = Tape & Reel, T = Tube or Tray
September 2006 PCS2I2310ANZ rev 0.5 3.3V SDRAM Buffer for Mobile PCs with 4 SO-DIMMs 12 of 12 Notice: The information in this document is subject to change without notice. © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All ot her brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors t hat may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product descri bed herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not in tended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the app lication or use of any product described herein, and disclaims any express or implied warrant ies related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, mercha ntability, or infringement of any intellec tual property rights, except as express agreed to in PulseCore’ s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusiv ely according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellect ual property rights of PulseCore or third partie s. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseC ore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I2310ANZ Document Version: 0.5 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003