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Technical content

Features

  • One Input to 10 Output Buffer/Driver
  • Supports up to Four SDRAM SO−DIMMs
  • Two Additional Outputs for Feedback
  • Serial Interface for Output Control
  • Low Skew Outputs
  • Up to 133 MHz Operation
  • Multiple VDD and VSS Pins for Noise Reduction
  • Dedicated OE Pin for Testing
  • Space−saving 28 Pin SSOP Package
  • 3.3 V Operation
  • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com SSOP−28 A SUFFIX CASE 565AH PIN CONFIGURATION (Top View) See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.

ORDERING INFORMATION

BUF_IN VDD SDRAM8 VSS VDDIIC SDATA

Figure 1. Block Diagram Table 1. PIN DESCRIPTION

16 VSSIIC P Ground for serial interface

9 BUF_IN I Input clock, 5 V tolerant

Table 2. DEVICE FUNCTIONALITY

0 High−Z

  • The Serial bits will be read by the clock driver in the following order: 1. Byte 0 − Bits 7, 6, 5, 4, 3, 2, 1, 0 2. Byte 1 − Bits 7, 6, 5, 4, 3, 2, 1, 0 3. Byte N − Bits 7, 6, 5, 4, 3, 2, 1, 0
  • Reserved and unused bits can be programmed to either “0” or “1”.
  • Serial interface address for the PCS2I2310ANZ is: A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 −−−

Table 3. BYTE 0: SDRAM Active/Inactive Register Table 4. BYTE 1: SDRAM Active/Inactive Register Table 5. BYTE 2: SDRAM Active/Inactive Register Table 6. IIC BYTE FLOW

1 IIC Address

2 Command (dummy value, ignored)

3 Byte Count (dummy value, ignored)

4 IIC Data Byte 0

5 IIC Data Byte 1

6 IIC Data Byte 2

  1. When the value of bit in these bytes is high, the output is enabled. When the value of the bit is low, the output is forced to low state. The default

value of all the bits is high after chip is powered up.

Table 7. ABSOLUTE MAXIMUM RATINGS Table 8. OPERATING CONDITIONS Table 9. ELECTRICAL CHARACTERISTICS

  1. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Table 10. SWITCHING CHARACTERISTICS (Note 3)

  1. All parameters specified with loaded outputs.
  2. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1 V/nS.
  3. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Figure 2. Load Circuit for Switching Times

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Application Information

Clock traces must be terminated with either series or parallel termination, as is normally done. Figure 10. Cd = Decoupling Capacitor Ct = Optional EMI−Reducing Capacitor Rs = Series Terminating Resistors X = 0 to 10 SDRAMX RS Ct RS CPUCLK SDATA SDATA VDD SCLK SCLK BUF_IN VDD VSS Cd = 0.1 /C0109F PCS2I2310ANZ SSOP 28 Summary

  • Surface mount, low−ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 /C0109F. In some cases, smaller value capacitors may be required.
  • The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the buffer (typically 25 /C0087), and Rseries is the series terminating resistor. Rseries > Rtrace – Rout
  • Footprints must be laid out for optional EMI−reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
  • A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 /C0087 impedance at the clock frequency, under loaded DC conditions.
  • If a Ferrite Bead is used, a 10 /C0109F–22 /C0109F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.

http://onsemi.com IIC Serial Interface Information The information in this section assumes familiarity with IIC programming. How to Program PCS2I2310ANZ through IIC:

  • Master (host) sends a start bit.
  • Master (host) sends the write address D3 (H).
  • PCS2I2310ANZ device will acknowledge.
  • Master (host) sends the Command Byte.
  • PCS2I2310ANZ device will acknowledge the Command Byte.
  • Master (host) sends a Byte count.
  • PCS2I2310ANZ device will acknowledge the Byte count.
  • Master (host) sends the Byte 0.
  • PCS2I2310ANZ device will acknowledge Byte 0.
  • Master (host) sends the Byte 1.
  • PCS2I2310ANZ device will acknowledge Byte 1.
  • Master (host) sends the Byte 2.
  • PCS2I2310ANZ device will acknowledge Byte 2.
  • Master (host) sends a Stop bit. Controller (Host) PCS2I2310ANZ (slave/receiver) Start Bit Slave Address D3(H) ACK Command Byte ACK Byte count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Stop Bit

http://onsemi.com PACKAGE DIMENSIONS SSOP 28 CASE 565AH−01 ISSUE O

Table 11. ORDERING INFORMATION arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Pentium II is a registered trademark of Intel Corporation.