PCS2P20805A PULSECORE | Alldatasheet

Document overview

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Technical content

Features

  • Advanced CMOS Technology
  • Guaranteed low skew < 200pS (max.)
  • Very low propagation delay < 2.5nS (max)
  • Very low duty cycle distortion < 270pS (max)
  • Very low CMOS power levels
  • Operating frequency up to 166MHz
  • TTL compatible inputs and outputs
  • Two independent output banks with 3-state control
  • 1:5 fanout per bank
  • "Heartbeat" monitor output
  • V CC = 2.5V ± 0.2V
  • Available in SSOP and QSOP packages Block Diagram Functional Description The PCS2P20805A is a 2.5V Clock driver built using advanced CMOS technology. The device consists of two banks of drivers, each with a 1: 5 fanout and its own output enable control. The device has a "heartbeat" monitor for diagnostics and PLL driving. The MON output is identical to all other outputs and complies with the output specifications in this document. The PCS2P20805A offers low capacitance inputs. The PCS2P20805A is designed for high speed clock distribution where signal quality and skew are critical. The PCS2P20805A also allows single point-to- point transmission line driving in applications such as address distribution, where one signal must be distributed to multiple receivers with low skew and high signal quality. Pin Diagram OB1 – OB5 INA INB OEB OEA OA1 – OA5 MON SSOP/ QSOP PACKAGE TOP VIEW VCCA OA1 OA2 OA3 GNDA OA4 OA5 GNDQ OEA INA INB OEB MON OB5 OB4 GNDB OB3 OB2 OB1 VCCB PCS2P20805A 10 11

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 2 of 11 Notice: The information in this document is subject to change without notice. Pin Description Pin # Pin Names Description 9,12 OE ¯¯ A, OE¯¯ B 3-State Output Enable Inputs (Active LOW) 10,11 IN A, INB Clock Inputs 2,3,4,6,7 OA 1-OA5 Clock Outputs 19,18,17,15,14 OB 1-OB5 Clock Outputs

1 V CCA Power supply for Bank A

20 V CCB Power supply for Bank B

5 GND A Ground for Bank A

16 GND B Ground for Bank B

8 GND Q Ground

13 MON Monitor Output

OE¯¯ A, OE¯¯ B IN A, INB OA n, OBn MON L L L L L H H H H L Z L H H Z H Note: H = HIGH; L = LOW; Z = High-Impedance Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter* Conditions Typ Max Unit CIN Input Capacitance V IN= 0V 3 4 pF COUT Output Capacitance V OUT = 0V 6 pF *This parameter is measured at characterization but not tested.

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 3 of 11 Notice: The information in this document is subject to change without notice. Absolute Maximum Ratings Symbol Description Max Unit VCC Input Power Supply Voltage -0.5 to +4.6 V VI Input Voltage -0.5 to +5.5 V VO Output Voltage -0.5 to V CC+0.5 V TJ Junction Temperature 150 °C Ts Max. Soldering Temperature (10 sec) 260 °C TSTG Storage Temperature -65 to +165 ° C TDV Static Discharge Voltage (As per JEDEC STD22- A114-B) 2 KV Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. Following Conditions Apply Unless Otherwise Specified Industrial: TA = -40°C to +85°C, VCC = 2.5V ± 0.2V Symbol Parameter Test Conditions1 Min Typ2 Max Unit VIH Input HIGH Level 1.7 5.5 V VIL Input LOW Level -0.5 0.7 V IIH Input HIGH Current V CC= Max. V I = 5.5V ±1 IIL Input LOW Current V CC= Max. V I = GND ±1 IOZH V O = VCC ±1 IOZL High Impedance Output Current (3-State Outputs Pins) VCC= Max. VO = GND ±1 µA VIK Clamp Diode Voltage V CC= Min., IIN = -18mA -0.7 -1.2 V IODH Output HIGH Current VCC= 2.5V, VIN = VIH or VIL, VO = 1.25V3,4 -15 -35 -90 mA IODL Output LOW Current VCC= 2.5V, VIN = VIH or VIL, VO = 1.25V3,4 25 55 100 mA IOS Short Circuit Current VCC= Max., VO = GND3,4 -30 -50 -120 mA IOH= -8mA 1.75 VOH Output HIGH Voltage VCC= Min. VIN = VIH or VIL IOH= -100µA V CC - 0.2 V IOL= 8mA 0.2 0.4 VOL Output LOW Voltage VCC= Min. VIN = VIH or VIL IOL= 100µA 0.2 V Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 2.5V, 25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC -0.6V at rated current.

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 4 of 11 Notice: The information in this document is subject to change without notice. Power Supply Characteristics Symbol Parameter Test Conditions1 Min Typ2 Max Unit ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max. VIN = GND or VCC 0.1 20 µA ∆ICC Power Supply Current per Input HIGH VCC = Max. VIN = VCC –0.6V 35 250 µA ICCD Dynamic Power Supply Current per Output3 VCC= Max. CL= 15pF All Outputs Toggling VIN = VCC VIN = GND 65 100 µA/MHz VIN = VCC VIN = GND 140 160 VCC= Max. CL= 15pF All Outputs Toggling fi = 133MHz VIN = VCC –0.6V VIN = GND 140 160 VIN = VCC VIN = GND 170 200 IC Total Power Supply Current4 VCC= Max. CL= 15pF All Outputs Toggling fi = 166MHz VIN = VCC –0.6V VIN= GND 170 200 mA Notes: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 2.5V, +25°C ambient. 3. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 4. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = VCC -0.6V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 5 of 11 Notice: The information in this document is subject to change without notice. Switching Characteristics Over Operating Range3,4 Symbol Parameter Conditions1 Min2 Max Unit tPLH tPHL Propagation Delay INA to OAn, INB to OBn 1 3 nS tR Output Rise Time (Measured from 0.8V to 2V) 1.5 nS tF Output Fall Time (Measured from 2V to 0.8V) 1.5 nS tSK(O) Same device output pin to pin skew5 270 pS tSK(P) Pulse skew6,9 270 pS tSK(PP) Part to part skew7 550 pS tPZL tPZH Output Enable Time OE¯¯ A to OAn, OE¯¯ B to OBn 5.2 nS tPLZ tPHZ Output Disable Time OE¯¯ A to OAn, OE¯¯ B to OBn 5.2 nS fMAX Input Frequency CL= 15pF f ≤133MHz

133 MHz

INA to OAn, INB to OBn 0.5 2.5 nS tR Output Rise Time (Measured from 0.7V to 1.7V) 1.25 nS tF Output Fall Time (Measured from 1.7V to 0.7V) 1.25 nS tSK(O) Same device output pin to pin skew5 200 pS tSK(P) Pulse skew6,9 270 pS tSK(PP) Part to part skew7 550 pS tPZL tPZH Output Enable Time OE¯¯ A to OAn, OE¯¯ B to OBn 5.2 nS tPLZ tPHZ Output Disable Time OE¯¯ A to OAn, OE¯¯ B to OBn 5.2 nS fMAX Input Frequency CL= 15pF 133MHz ≤ f ≤166MHz

166 MHz

Notes: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. t PLH and tPHL are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 5. Skew measured between all outputs under identical transitions and load conditions. 6. Skew measured is difference between propagation delay times tPHL and tPLH of same outputs under identical load conditions. 7. Part to part skew for all outputs given identical transitions and load conditions at identical VCC levels and temperature. 8. Airflow of 1m/s is recommended for frequencies above 133MHz. 9. This parameter is measured using f = 1MHz.

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 6 of 11 Notice: The information in this document is subject to change without notice. Test Circuits and Waveforms Switch Position Test Conditions Symbol VCC = 2.5V ±0.2V Unit CL 15 pF RT Z OUT of pulse generator Ω RL 33 Ω tR / tF 1 (0V to 2.5V or 2.5V to 0V) nS Definitions: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator. Test Switch Disable Low Enable Low 4.6V Disable High Enable High GND RL VCC RT Pulse Generator VIN D.U.T CL CL = 15pF Test Circuit VOUT INPUT tPLH1 tPHL1 1.25V VOH 1.25V VOL OUTPUT 1 tSK(O) = | tPLH2 - tPLH1 | or | tPHL2 -t PHL1 | tSK(O) tSK(O) tPLH2 tPHL2 VOH 1.25V VOL OUTPUT 2 Output Skew – tSK(o) VCC RT Pulse Generator VIN D.U.T CL GND 4.6V 500Ω 500Ω VOUT Enable and Disable Time Circuit Open RL

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 7 of 11 Notice: The information in this document is subject to change without notice. Test Circuits and Waveforms INPUT OUTPUT tPLH tPHL 1.25V 2.5V VOH 1.7V 1.25V 0.7V VOL tF tR Propagation Delay 2.5V INPUT tPLH tPHL 1.25V VOH 1.25V VOL OUTPUT Pulse Skew tSK(P) = | tPLH - tPLH | INPUT tPLH1 tPHL1 1.25V 2.5V VOH 1.25V VOL Package 1 OUTPUT tSK(PP) = | tPLH2 - tPLH1 | or | tPHL2 -t PHL1 | tSK(PP) tSK(PP) tPLH2 tPHL2 VOH 1.25V VOL Package 2 OUTPUT Part-to- Part Skew Note: Part-to- Part Skew is for package and speed grade. ENABLE tPLZ 2.5V 1.25V DISABLE VOH VOL VOL 0.3V VOH 0.3V tPZL VOL 1.25V VOH 1.25V SWITCH CLOSED tPZH tPHZ SWITCH OPEN CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH Enable and Disable Times Note: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 8 of 11 Notice: The information in this document is subject to change without notice.

Package Information

20-lead SSOP ( 209 mil ) Dimensions Inches Millimeters Symbol Min Max Min Max A 0.053 0.069 1.346 1.753 A1 0.004 0.010 0.102 0.254 D 0.337 0.344 8.560 8.738 c 0.007 0.011 0.178 0.274 E 0.228 0.244 5.791 6.198 E1 0.150 0.157 3.810 3.988 L 0.016 0.035 0.406 0.890 L1 0.010 BASIC 0.254 BASIC b 0.008 0.014 0.203 0.356 a 0° 8° 0° 8° e 0.025 BASIC 0.635 BASIC

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 9 of 11 Notice: The information in this document is subject to change without notice. 20-lead QSOP Dimensions Inches Millimeters Symbol Min Max Min Max A 0.060 0.068 1.52 1.73 A1 0.004 0.008 0.10 0.20 b 0.009 0.012 0.23 0.30 c 0.007 0.010 0.18 0.25 D 0.337 0.344 8.56 8.74 E 0.150 0.157 3.81 3.99 e 0.025 BSC 0.64 BSC H 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 S 0.056 0.060 1.42 1.52 a 0° 8° 0° 8°

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 10 of 11 Notice: The information in this document is subject to change without notice.

Ordering Information

Part Number Marking Package Type Temperature PCS2P20805AG-20-AR 2P20805AG 20-Pin SSOP, TAPE & REEL , Green Commercial PCS2P20805AG-20-AT 2P20805AG 20-Pin SSOP, TUBE, Green Commercial PCS2P20805AG-20-DR 2P20805AG 20-Pin QSOP, TAPE & REEL, Green Commercial PCS2P20805AG-20-DT 2P20805AG 20-Pin QSOP, TUBE, Green Commercial PCS2I20805AG-20-AR 2I20805AG 20-Pin SSOP, TAPE & REEL, Green Industrial PCS2I20805AG-20-AT 2I20805AG 20- Pin SSOP, TUBE, Green Industrial PCS2I20805AG-20-DR 2I20805AG 20-Pin QSOP, TAPE & REEL, Green Industrial PCS2I20805AG-20-DT 2I20805AG 20-Pin QSOP, TUBE, Green Industrial Device Ordering Information PCS2P20805AG-20-AR Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. O = SOT U = MSOP S = SOIC E = TQFP T = TSSOP L = LQFP A = SSOP U = MSOP V = TVSOP P = PDIP B = BGA D = QSOP Q = QFN X = SC-70 DEVICE PIN COUNT X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 6 = Power Management 2 = Non PLL based 7 = Power Management 3 = EMI Reduction 8 = Power Management 4 = DDR support products 9 = Hi Performance 5 = STD Zero Delay Buffer 0 = Reserved PART NUMBER G = GREEN PACKAGE, LEAD FREE, and RoHS R = Tape & Reel, T = Tube or Tray PulseCore Semiconductor Mixed Signal Product

September 2006 PCS2P20805A rev 0.3 2.5V CMOS Dual 1-To-5 Clock Driver 11 of 11 Notice: The information in this document is subject to change without notice. © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All ot her brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors t hat may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product descri bed herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not in tended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the app lication or use of any product described herein, and disclaims any express or implied warrant ies related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, mercha ntability, or infringement of any intellec tual property rights, except as express agreed to in PulseCore’ s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusiv ely according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellect ual property rights of PulseCore or third partie s. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseC ore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2P20805A Document Version: 0.3 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003