PCM78

PCM78P BURR-BROWN | Alldatasheet

Document overview

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Technical content

FEATURES

l LOW COST/HIGH PERFORMANCE 16-BIT AUDIO A/D CONVERTER l FAST 5µs MAX CONVERSION TIME (4µs typ) l VERY LOW THD+N ( typ –88dB at FS; max –82dB) l ±3V INPUT RANGE l TWO SERIAL OUTPUT MODES PROVIDE VERSATILE INTERFACING l COMPLETE WITH INTERNAL REFERENCE AND CLOCK IN 28-PIN PLASTIC DIP l ±5V TO ±15V SUPPLY RANGE (600mW Power Dissipation) 16-bit SAR + Timing Control Comp Audio Input Internal Clock Circuit 16-bit D/A Converter Convert Command External Clock Status Serial Output 1 Serial Output 2 Clock Output International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 PCM78P 16-Bit Audio ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

l SAMPLING KEYBOARD SYNTHESIZERS l DIGITAL AUDIO TAPE l BROADCAST AUDIO PROCESSING l TELECOMMUNICATIONS

DESCRIPTION

The PCM78P is a low-cost 16-bit analog-to-digital converter which is specifically designed and tested for dynamic applications. It features very fast, low distortion performance (4µs/–88dB THD+N typical) and is complete with internal clock and reference circuitry. The PCM78P is packaged in a reliable, low- cost 28-pin plastic DIP and data output is available in user-selectable serial output formats. The PCM78P is ideal for digital audio tape (DAT) recorders. Many similar applications such as digital signal processing and telecom applications are equally well served by the PCM78P. The PCM78P uses a SAR technique. Analog and digital portions are efficiently partitioned into a high- speed, bipolar section and a low-power CMOS section. The PCM78P has been optimized for excel- lent dynamic performance and low cost. © 1989 Burr-Brown Corporation PDS-989A Printed in U.S.A. October, 1993

At TC = +25°C, +VDD = +5V, and ±VCC = ±12V, and one minute warm-up in convection environment, unless otherwise noted. PCM78P PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 16 Bits INPUT/OUTPUT ANALOG INPUT Input Range –3 +3 V Input Impedance 1.5 k Ω DIGITAL INPUT/OUTPUT Logic Family TTL Compatible CMOS Logic Level: VIH IIH = +40µA +2 +5.5 V VIL IIL = –100µA 0 +0.8 V VOH IOH = 2TTL Loads +2.4 V VOL IOL = 2TTL Loads +0.4 V Data Format Serial BOB or BTC Convert Command Negative Edge (1) Pulse Width 25 50 ns CONVERSION TIME 45 µs DYNAMIC CHARACTERISTICS SIGNAL-TO-NOISE RATIO (SNR) (2) fS = 200kHz/TCONV = 4µs(3) f = 1kHz (0dB) BW = 20kHz 90 dB (4) f = 10kHz (0dB) BW = 100kHz 80 dB TOTAL HARMONIC DISTORTION (5) fS = 200kHz/TCONV = 4µs f = 1kHz (0dB) BW = 20kHz –91 dB f = 19kHz (0dB) BW = 20kHz –90 dB f = 10kHz (0dB) BW = 100kHz –90 dB f = 90kHz (0dB) BW = 100kHz –89 dB TOTAL HARMONIC DISTORTION + NOISE (6) fS = 200kHz/TCONV = 4µs f = 1kHz (0dB) BW = 20kHz –88 –82 dB f = 1kHz (–20dB) BW = 20kHz –74 –68 dB f = 1kHz (–60dB) BW = 20kHz –34 dB f = 19kHz (0dB) BW = 20kHz –87 dB f = 10kHz (0dB) BW = 100kHz –82 dB f = 90kHz (0dB) BW = 100kHz –81 dB TRANSFER CHARACTERISTICS ACCURACY Gain Error ±2% Bipolar Zero Error ±20 mV Differential Linearity Error ±0.002 % of FSR (7) Integral Linearity Error ±0.003 % of FSR Missing Codes None 14 Bits (8) DRIFT Gain 0 °C to +70°C ±25 ppm/ °C Bipolar Zero 0 °C to +70°C ±4 ppm of FSR/ °C POWER SUPPLY SENSITIVITY +V CC ±0.008 %FSR/%V CC –VCC ±0.003 %FSR/%V CC +V DD ±0.003 %FSR/%V DD POWER SUPPLY REQUIREMENTS Voltage Range: +VCC +4.75 +15.6 V –VCC –4.75 –15.6 V +VDD +4.75 +5.25 V Current: +V CC +V CC = +12V +15 mA –VCC –VCC = –12V –21 mA +VDD +V DD = +5V +7 mA Power Dissipation ±VCC = ±12V 575 mW TEMPERATURE RANGE Specification 0 +70 °C Storage –50 +100 °C Operating –25 +85 °C NOTES: (1) When convert command is high, converter is in a halt/reset mode. Actual conversion begins on negative edge. See detailed text on timing for convert command description when using external clock. (2) Ratio of Noise rms/Signal rms. (3) f = input frequency; fS = sample frequency (PCM78P and SHC702 in combination); BW = bandwidth of output (based on FFT or actual analog reconstruction using a 20kHz low-pass filter). (4) Referred to input signal level. (5) Ratio of Distortion rms/Signal rms. (6) Ratio of Distortion rms + Noise rms/Signal rms. (7) FSR: Full-Scale Range = 6Vp-p. (8) Typically no missing Codes at 14-bit resolution.

1 Analog In I Analog Signal Input (1.5k Ω impedance). 2– V CC I Analog power supply (–5V to –15V). 3 MSB Adjust I Internal adjustment point to allow adjustment of MSB major carry. 4+ V DD I Power connection for comparator (+5V). 5 No Connection — No internal connection. 6 Comparator Common I Comparator common connection. Connect to ground. 7 MSB O Parallel output of bit 1 (MSB) inverted. 8 BTC/BOB Select I Two’s complement (open) or straight binary (grounded) data output format selection. 9 Status O Output signal held high until conversion is complete. 10 Clock Out O Internal clock output generated from RC network on pins 11 and 12 (also present when external clock is used lagging external clock by ~24ns and same duty cycle). 11 R 1C 1 I RC connection point used to generate internal clock. Sets clock high time. See text for details. 12 R 2C 2 I RC connection point used to generate internal clock. Sets clock low time. See text for details. 13 S OUT2 O Internal shift register containing the previous conversion result. (Alternate latched data output mode). 14 +V DD I Power connection for +5V logic supply. 15 S OUT1 O Primary real-time data output synchronized to clock out. 16 External Clock I External clock input point (internal clock must be disabled). 17 Int/Ext Clock Select I Selects either internal or external clock mode (low = internal; open = external). 18 Short Cycle I Terminates conversion at less than 16 bits (open for 16-bit mode). See text for details. 19 Convert Command I Starts conversion process (can optionally be generated internally). 20 S OUT2 Latch I Latches previous conversion result for readout (must be issued with the SOUT2 clock to initiate latch and an internal convert command). 21 S OUT2 Clock I Used to read out internally latched data from previous conversion. 22 Digital Common I Digital grounding pin. 23 +V CC I Analog supply connection (+5V to +15V). 24 V POT O Voltage output (~2.5V) for optional adjustment of MSB transition. 25 Reference Decouple I Reference decoupling point. 26 Analog Common I Analog grounding pin. 27 Reference Out O 2V reference out. Should not be used except as shown in connection diagram. 28 Speed Up I Connection point for a capacitor to speed reference settling. See text for details. NOTE: Analog and digital commons are connected internally. PIN ASSIGNMENTS ABSOLUTE MAXIMUM RATINGS Stresses above these ratings may permanently damage the device. DIGITAL OUTPUT ANALOG INPUT CONDITION BTC BOB +2.999908V + Full Scale 7FFF Hex FFFF Hex –3.000000V –Full Scale 8000 Hex 0000 Hex 0.000000V Bipolar Zero 0000 Hex 8000 Hex –0.000092V Zero-1 LSB FFFF Hex 7FFF Hex INPUT/OUTPUT RELATIONSHIPS

PACKAGE INFORMATION

MODEL PACKAGE NUMBER (1) PCM78P 28-Pin Plastic DIP 215 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

20Current (mA) SS –VCC Supply Voltage (V) 6 8 12 14 +V CC V vs TEMP 2.002 1.998 1.996 1.994 1.992 1.988 –25 0 25 70 125 Temperature (°C) 2.000 REF V (V)REF 1.99 PSRR at –FS INPUT 0.012 0.008 0.006 0.004 0.002 –25 0 25 70 125 Temperature (°C) % / % 0.01 –VCC +VCC VDD PSRR at +FS INPUT 0.012 0.010 0.008 0.006 0.004 0.002 –0.002 –0.004 –0.006 –0.008 –25 0 25 70 125 Temperature (°C) % / % –0.010 –VCC +VCC VDD BIPOLAR GAIN ERROR as % FSR 25°C; N = 33 UNITS –0.35 –0.45 –0.60 % FSR Number of Units –0.40 –0.55 –0.50 BPZ ERROR vs TEMPERATURE 10mV 9mV 8mV 7mV 6mV 5mV 4mV 3mV 2mV 1mV –25 0 25 70 125 Temperature (°C) BPZ Error (mV) TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = ±15V, unless otherwise noted.

at 25°C 1.40 0.80 0.60 0.00 1.20 LSB 0.20 Major Carry Bit Number 1.00 0.40 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 INTEGRAL NONLINEARITY at 25°C 5.00 2.00 1.00 –2.00 4.00 LSB –1.00 Major Carry Bit Number 3.00 0.00 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 DIFFERENTIAL NONLINEARITY at 0°C 1.40 0.80 0.60 0.00 1.20 LSB 0.20 Major Carry Bit Number 1.00 0.40 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 INTEGRAL NONLINEARITY at 0°C 5.00 2.00 1.00 –2.00 4.00 LSB –1.00 Major Carry Bit Number 3.00 0.00 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 DIFFERENTIAL NONLINEARITY at –25°C 1.40 1.00 0.00 LSB Major Carry Bit Number 1.20 0.80 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 0.60 0.40 0.20 INTEGRAL NONLINEARITY at –25°C 7.00 4.00 3.00 –1.00 6.00 LSB 1.00 Major Carry Bit Number 5.00 2.00 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 0.00 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = ±15V, unless otherwise noted.

DIFFERENTIAL NONLINEARITY ERROR (to 14-Bit LSB) 2.00 1.00 0.50 –1.00 –8192 0.000 8192 BIN 1.50 LSB 0.00 –0.50 –4096 4096 DIFFERENTIAL NONLINEARITY at 125°C 2.50 1.50 0.00 LSB Major Carry Bit Number 2.00 1.00 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 0.50 INTEGRAL NONLINEARITY at 125°C 3.00 0.00 –1.00 –7.00 2.00 LSB –3.00 Major Carry Bit Number 1.00 –2.00 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 –4.00 –5.00 –6.00 DIFFERENTIAL NONLINEARITY at 70°C 1.80 1.20 1.00 0.00 1.60 LSB 0.60 Major Carry Bit Number 1.40 0.80 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 0.40 0.20 INTEGRAL NONLINEARITY at 70°C 7.00 4.00 3.00 0.00 6.00 LSB 1.00 Major Carry Bit Number 5.00 2.00 23456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 INTEGRAL NONLINEARITY ERROR (to 14-Bit LSB) 1.50 0.50 –2.00 –8192 0.000 8192 BIN 1.00 Differential 0.00 –0.50 –4096 4096 –1.00 –1.50 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = ±15V, unless otherwise noted. Histograms done with conversion time = 8µs.

–20 –40 –60 –80 –100 –120 –140 0 50 100 Frequency (kHz) Magnitude (dB) 25 75 –20 –40 –60 –80 –100 –120 –140 0 50 100 Frequency (kHz) Magnitude (dB) 25 75 Input Frequency 976.6Hz Fund: –60.06dB 6th: –106.00dB 2nd: –109.18dB THD: –42.15dB 3rd: –108.31dB SNR: 21.73dB 4th: –134.66dB SINAD: 21.69dB 5th: –114.73dB –20 –40 –60 –80 –100 –120 –140 0 50 100 Frequency (kHz) Magnitude (dB) 25 75 –20 –40 –60 –80 –100 –120 –140 0 50 100 Frequency (kHz) Magnitude (dB) 25 75 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VCC = ±15V, unless otherwise noted. Histograms done with Conversion Time = 8µs. Input Frequency 976.6Hz Fund: –20.07dB 6th: –110.06dB 2nd: –108.36dB THD: –76.75dB 3rd: –100.44dB SNR: 61.79dB 4th: –111.52dB SINAD: 61.65dB 5th: –102.06dB SPECTRAL RESPONSE, f IN ≈ 1kHz Input Frequency 976.6Hz Fund: –0.07dB 6th: –135.02dB 2nd: –87.80dB THD: –87.10dB 3rd: –97.43dB SNR: 81.05dB 4th: –102.35dB SINAD: 80.09dB 5th: –107.86dB –20 –40 –60 –80 –100 –120 –140 0 50 100 Frequency (kHz) Magnitude (dB) 25 75 –20 –40 –60 –80 –100 –120 –140 0 50 100 Frequency (kHz) Magnitude (dB) 25 75 SPECTRAL RESPONSE, f IN ≈ 20kHz Input Frequency 19970.7Hz Fund: –19.94dB 6th: –107.32dB 2nd: –105.69dB THD: –72.81dB 3rd: –95.90dB SNR: 61.60dB 4th: –106.71dB SINAD: 61.28dB 5th: –97.57dB SPECTRAL RESPONSE, f IN ≈ 20kHz Input Frequency 19970.7Hz Fund: –59.96dB 6th: –110.11dB 2nd: –109.09dB THD: –41.60dB 3rd: –124.49dB SNR: 21.93dB 4th: –116.40dB SINAD: 21.88dB 5th: –112.18dB SPECTRAL RESPONSE, f IN ≈ 20kHz Input Frequency 19970.7Hz Fund: –0.08dB 6th: –101.44dB 2nd: –92.21dB THD: –88.12dB 3rd: –91.59dB SNR: 79.25dB 4th: –101.23dB SINAD: 78.72dB 5th: –109.32dB SPECTRAL RESPONSE, f IN ≈ 1kHz SPECTRAL RESPONSE, f IN ≈ 1kHz

FIGURE 9. Timing when using SOUT2 Latch. TA = +25°C, VCC = +5V, guaranteed by sample testing; these parameters are not 100% tested in production. FIGURE 10. Application Example of SOUT 2 Operation.

15 X X X X 0

11 X X 0 0 X

80 X X 0 X

FIGURE 11 . Short Cycle Circuit. FIGURE 12. Short Cycle Operation Timing.

2.2µF2 2.2µF 4 14 23 2.2µF 2.2µF ANALOG In Clock Out V MSB Adj Serial Out 1 Status JP7 JP8 R 3.3kΩ R 200kΩ + 27 REF Out MSB 7 TP1 EXT CLK 16 TP2 S Latch

20 TP6

S Clock 21OUT 2 Speed Up REF DCPL

6 Comparator

8 BOB/BTC SEL

13 TP4S OUT 2

RV 1kΩ Ω 100pF C 26221917 Convert Command J RC1 RC2 INT External Clock IN4148IN4148 CR +15 2.2µF2.2µF 2.2µF 911 SHC5320 U1+ R 20k Ω J1Analog Input R R 3kΩ Status 4U43 6U451 2 U413 10U411 8U49 HCT14 HCT14 HCT14 HCT14 HCT14 10 9 87 65 4 3 1 GND 18 17 16 15 14 13 12 11 B10 B11 B12 B13 B14 B15 B16 2 DV 1 2 3 4 5 6 GND +15 GND –15 –5+5+15 74HC594 2.2µF 101316

12 RCK

2.2µF PCM56 2.2µF 83 1 6 2.2µF 2.2µF OUTV RF SJ IOUT Trim MSB ADJ CLK DATA LE J Reconstructed Output 2.2µF +5 122 HCT14 111412 74HCT74 Q Q CLK SOUT 1 100pF 7 1 POT R 1.5kΩ R Ω R 100kΩ 4 R 3.3kΩ 10 R 3.3kΩ 91 0 JP12 JP13

2 CR 1

2.2µF 4U83 100pF HCT05HCT05HCT05 4 –15 7 2 –15 2.2µF 101316 SER SRCK C 1 5 123 4567 A BC D E F GH 100pF C R Ω 3.3k R Ω 3.3k R Ω 3.3k RCK 2.2µF FIGURE 20.Schematic for Demonstration Board (DEM1122).