PCM6XX0-Q1

Texas Instruments

PCM6xx0-Q1 Automotive, 4-Channel and 6-Channel, 768-kHz, Audio ADC With Integrated Microphone Bias and Input Fault Diagnostics

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ADVANCE□INFORMATION Audio Serial Interface (TDM, I2S, LJ) PLL and Clock Generation I2C or SPI Control Interface Input Diagnostics, Regulators and Voltage Reference Programmable Digital Filters and Biquads Multi-Channel ADC with Front-End PGA and Input Attenuator IN1P IN1M IN2P IN2M IN3P IN3M IN4P IN4M MICBIAS VREF FSYNC BCLK SDOUT GPIO1 SHDNZ SDA_SSZ SCL_MOSI ADDR0_SCLK ADDR1_MISO AREG DREG AVSSVSS AVDD IOVDD Boost Converter and Programmable MICBIAS IN5P IN5M IN6P IN6M BSTOUT BSTSW BSTVDD VBAT_IN Noise Cancellation Microphones Hands-free Calling Microphones Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 SBAS884 –MARCH 2020 PCM6xx0-Q1Automotive,4-Channeland6-Channel,768-kHz,AudioADC WithIntegratedMicrophoneBiasandInputFaultDiagnostics

1 Features

1• AEC-Q100 qualified for automotive applications – Temperature grade 1: –40°C ≤ TA ≤ +125°C

ADC performance: – Line differential input dynamic range: 110 dB – Microphone differential input dynamic range: 110 dB – THD+N: –94 dB – Channel summing mode supports high SNR
ADC input voltage: – Differential, 10-VRMS full-scale inputs – Single-ended, 5-VRMS full-scale inputs
ADC sample rate (fS) = 8 kHz to 768 kHz
Programmable channel settings: – Channel gain: 0 dB to 42 dB, 1-dB steps – Digital volume control: –100 dB to 27 dB – Gain calibration with 0.1-dB resolution – Phase calibration with 163-ns resolution
Programmable microphone bias (5 V to 9 V): – With integrated efficient boost converter, or – With external high voltage HVDD supply
Programmable microphone input fault diagnostics: – Open inputs or shorted inputs – Short to ground, MICBIAS or VBAT – Microphone bias over current protection
Low-latency signal processing filter selection
Programmable HPF and biquad digital filters
I2C or SPI controls
Audio serial data interface: – Format: TDM, I2S, or left-justified (LJ) – Word length: 16 bits, 20 bits, 24 bits, or 32 bits – Master or slave interface
Single-supply, 3.3-V operation
I/O supply operation: 3.3 V or 1.8 V
Power consumption: < 21.5 mW/channel at 48- kHz

2 Applications

Automotive active noise cancellation
Automotive head units
Automotive external amplifiers

3 Description

The 4-channel PCM6x40-Q1 (PCM6240-Q1, PCM6340-Q1) and 6-channel PCM6x60-Q1 (PCM6260-Q1, PCM6360-Q1) are high-performance, audio analog-to-digital converters (ADCs) that support analog input signals up to 10 VRMS. The PCM6x40-Q1 and PCM6x60-Q1 (PCM6xx0-Q1) support line and microphone inputs, and allows for both single-ended and differential input configurations. These devices offer an integrated high-voltage, programmable microphone bias, and input diagnostic circuitry that allow direct connection to microphone-based automotive systems with full fault diagnostic capability for direct-coupled inputs. The PCM62x0-Q1 integrate an efficient boost converter to generate a high voltage microphone bias using an external, low-voltage, 3.3-V supply, whereas the PCM63x0-Q1 directly uses an external high- voltage supply (HVDD), which is a readily available supply in the system to generate the high-voltage, programmable microphone bias. The PCM6xx0-Q1 integrate the programable channel gain, digital volume control, a low-jitter phase-locked loop (PLL), a programmable high-pass filter (HPF), biquad filters, low-latency filter modes, and allows for sample rates up to 768 kHz. The PCM6xx0-Q1 support time- division multiplexing (TDM), I2S, or left-justified (LJ) audio formats, and can be controlled with either the I2C or SPI interface. These integrated high- performance features, along with a single, 3.3-V supply operation, make the PCM6xx0-Q1 family an excellent choice for space-constrained automotive systems. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) PCM6xx0-Q1 WQFN (32) 5.00 mm x 5.00 mm with 0.5-mm pitch (1) For all available packages, see the package option addendum at the end of the data sheet. Simplified Application Diagram (PCM6260-Q1)

7.11 Switching Characteristics: TDM, I2S or LJ

12.4 Receiving Notification of Documentation

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES March 2020 * Initial release.

5 Device Comparison Table

FEATURE PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Control interface I2C or SPI Digital audio serial interface TDM or I2S or left-justified (LJ) Audio analog channel 4 6 4 6 General-purpose input or output pins 5 1 5 1 Microphone bias voltage Programmable 5 V to 9 V in steps of 0.5 V Microphone bias LDO supply Generated using integrated efficient boost converter with external low-voltage BSTVDD = 3.3-V supply Powered directly using external high-voltage HVDD (as high as 12 V) supply Input fault diagnostics Comprehensive input fault diagnostics for DC-coupled microphone inputs with programmable thresholds Package WQFN (RTV), 32-pin, 5.00 mm x 5.00 mm (0.5-mm pitch)

6 Pin Configuration and Functions

32-Pin WQFN With Exposed Thermal Pad Top View Pin Functions: PCM6240-Q1 PIN TYPE DESCRIPTION NO. NAME 1 AVDD Analog supply Analog power (3.3 V, nominal) 2 AREG Analog supply Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) 3 BSTVDD Analog supply Boost converter supply voltage (3.3 V, nominal)

4 BSTSW Analog supply Boost converter switch input

5 BSTOUT Analog supply Boost converter output voltage

6 MICBIAS Analog MICBIAS output (programmable output up to 9 V)

7 VREF Analog Analog reference voltage filter output

8 AVSS Analog supply Analog ground. Short this pin directly to the board ground plane.

9 IN1P Analog input Analog input 1P pin

10 IN1M Analog input Analog input 1M pin

11 IN2P Analog input Analog input 2P pin

12 IN2M Analog input Analog input 2M pin

13 IN3P Analog input Analog input 3P pin

14 IN3M Analog input Analog input 3M pin

15 IN4P Analog input Analog input 4P pin

16 IN4M Analog input Analog input 4M pin

17 GPI2 Digital input General-purpose digital input 2 (multipurpose functions such as daisy-chain input, PLL input clock source, and so forth) 18 GPIO3 Digital I/O General-purpose digital input/output 3 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth) 19 GPI1 Digital input General-purpose digital input 1 (multipurpose functions such as daisy-chain input, PLL input clock source, and so forth) 20 GPIO2 Digital I/O General-purpose digital input/output 2 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth)

21 VBAT_IN Analog Analog VBAT input monitoring pin (used for input diagnostics)

22 SHDNZ Digital input Device hardware shutdown and reset (active low)

23 ADDR1_MISO Digital I/O For I2C operation: I2C slave address A1 pin

For SPI operation: SPI slave output pin

24 ADDR0_SCLK Digital input For I2C operation: I2C slave address A0 pin

For SPI operation : SPI serial bit clock

25 SCL_MOSI Digital input For I2C operation: clock pin for I2C control bus

For SPI operation: SPI slave input pin

26 SDA_SSZ Digital I/O For I2C operation: data pin for I2C control bus

For SPI operation: SPI slave-select pin 27 IOVDD Digital supply Digital I/O power supply (1.8 V or 3.3 V, nominal) 28 GPIO1 Digital I/O General-purpose digital input/output 1 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth)

29 SDOUT Digital output Audio serial data interface bus output

30 BCLK Digital I/O Audio serial data interface bus bit clock

31 FSYNC Digital I/O Audio serial data interface bus frame synchronization signal

32 DREG Digital supply Digital regulator output voltage for digital core supply (1.5 V, nominal) Thermal Pad (VSS) Ground supply Thermal pad shorted to internal device ground. Short the thermal pad directly to the board ground plane.

ADVANCE□INFORMATION

32 DREG9IN1P

1AVDD 24 ADDR0_SCLK

31 FSYNC10IN1M

2AREG 23 ADDR1_MISO

30 BCLK11IN2P

29 SDOUT12IN2M

4BSTSW 21 VBAT_IN

28 GPIO113IN3P

27 IOVDD14IN3M

26 SDA_SSZ15IN4P

25 SCL_MOSI16IN4M

Thermal Pad (VSS) PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 SBAS884 –MARCH 2020 www.ti.com Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 32-Pin WQFN With Exposed Thermal Pad Top View Pin Functions: PCM6260-Q1 PIN TYPE DESCRIPTION NO. NAME 1 AVDD Analog supply Analog power (3.3 V, nominal) 2 AREG Analog supply Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) 3 BSTVDD Analog supply Boost converter supply voltage (3.3 V, nominal) 8 AVSS Analog supply Analog ground. Short this pin directly to the board ground plane.

17 IN5P Analog input Analog input 5P pin

18 IN5M Analog input Analog input 5M pin

19 IN6P Analog input Analog input 6P pin

20 IN6M Analog input Analog input 6M pin

For SPI operation: SPI slave output pin For SPI operation : SPI serial bit clock For SPI operation: SPI slave input pin For SPI operation: SPI slave-select pin 27 IOVDD Digital supply Digital I/O power supply (1.8 V or 3.3 V, nominal)

ADVANCE□INFORMATION PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 SBAS884 –MARCH 2020 www.ti.com Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 32-Pin WQFN With Exposed Thermal Pad Top View Pin Functions: PCM6340-Q1 PIN TYPE DESCRIPTION NO. NAME 1 AVDD Analog supply Analog power (3.3 V, nominal) 2 AREG Analog supply Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) 3 AVDD Analog supply Analog power (3.3 V, nominal)

4 AVSS Analog supply Analog ground

5 HVDD Analog supply Analog power (11 V, nominal)

8 AVSS Analog supply Analog ground. Short this pin directly to the board ground plane. 17 GPI2 Digital input General-purpose digital input 2 (multipurpose functions such as daisy-chain input, PLL input clock source, and so forth) 18 GPIO3 Digital I/O General-purpose digital input/output 3 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth) 19 GPI1 Digital input General-purpose digital input 1 (multipurpose functions such as daisy-chain input, PLL input clock source, and so forth) 20 GPIO2 Digital I/O General-purpose digital input/output 2 (multipurpose functions such as daisy-chain input, audio data output, PLL input clock source, interrupt, and so forth)

ADVANCE□INFORMATION PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 SBAS884 –MARCH 2020 www.ti.com Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 32-Pin WQFN With Exposed Thermal Pad Top View Pin Functions: PCM6360-Q1 PIN TYPE DESCRIPTION NO. NAME 1 AVDD Analog supply Analog power (3.3 V, nominal) 2 AREG Analog supply Analog on-chip regulator output voltage for analog supply (1.8 V, nominal) 3 AVDD Analog supply Analog power (3.3 V, nominal) 8 AVSS Analog supply Analog ground. Short this pin directly to the board ground plane. For SPI operation: SPI slave output pin For SPI operation: SPI serial bit clock

7 Specifications

7.1 Absolute Maximum Ratings

over the operating ambient temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage AVDD to AVSS –0.3 3.9 V BSTVDD(2) to VSS (thermal pad) –0.3 3.9 IOVDD to VSS (thermal pad) –0.3 3.9 HVDD(3) to VSS (thermal pad) –0.3 14 Ground voltage differences AVSS to VSS (thermal pad) –0.3 0.3 V Battery voltage VBAT_IN to AVSS –0.3 18 V Analog input voltage Analog input pins voltage to AVSS –0.3 18 V Digital input voltage Digital input pins voltage to VSS (thermal pad) –0.3 IOVDD + 0.3 V Temperature Operating ambient, TA –40 125 °CJunction, TJ –40 150 Storage, Tstg –65 150 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 VCharged-device model (CDM), per AEC Q100-011 Corner package pins ±750 All other non-corner package pins ±500 (1) AVSS and VSS (thermal pad); all ground pins must be tied together and must not differ in voltage by more than 0.2 V. (2) BSTVDD is required only for the PCM62x0-Q1. (3) HVDD is required only for the PCM63x0-Q1 and the minimum voltage must be 0.6 V higher than the programmed MICBIAS value.

7.3 Recommended Operating Conditions

AVDD(1) Analog supply voltage to AVSS 3.0 3.3 3.6 V BSTVDD(2) Boost converter supply voltage to VSS (thermal pad) 3.0 3.3 3.6 V IOVDD IO supply voltage to VSS (thermal pad) - IOVDD 3.3-V operation 3.0 3.3 3.6 V IO supply voltage to VSS (thermal pad) - IOVDD 1.8-V operation 1.65 1.8 1.95 HVDD(3) MICBIAS LDO supply voltage to VSS (thermal pad) 5.6 11 12 V INPUTS VBAT_IN VBAT_IN input pin voltage to AVSS 0 12.6 18 V INxx Analog input pins voltage to AVSS for line-in recording 0 14.2 V Analog input pins voltage to AVSS for microphone recording 0.1 MICBIAS – 0.1 V Analog input pins voltage to AVSS during short to VBAT_IN VBAT_IN V Digital input pins voltage to VSS (thermal pad) 0 IOVDD V TEMPERATURE TA Operating ambient temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) PCM6xx0-Q1 UNITRTV (WQFN)

32 PINS

RθJA Junction-to-ambient thermal resistance 30.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 17.0 °C/W RθJB Junction-to-board thermal resistance 11.0 °C/W ψJT Junction-to-top characterization parameter 0.2 °C/W ψJB Junction-to-board characterization parameter 10.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.8 °C/W (1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the AC signal input shorted to ground, measured A- weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer. (2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter can result in higher THD and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, can affect dynamic specification values.

7.5 Electrical Characteristics

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT ADC PERFORMANCE FOR LINE INPUT RECORDING Differential input full-scale AC signal voltage AC-coupled input, input fault diagnostic not supported

10 VRMSDC-coupled input, DC common-mode voltage INxP =

INxM = 7.1 V, input fault diagnostic not supported Single-ended input full- scale AC signal voltage AC-coupled input, input fault diagnostic not supported

5 VRMSDC-coupled input, DC common-mode voltage INxP =

INxM = 7.1 V, input fault diagnostic not supported SNR Signal-to-noise ratio, A- weighted(1)(2) IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain TBD 109 dBIN1 differential DC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 109 IN1 differential DC-coupled input selected and AC signal shorted to ground, 12-dB channel gain 101 DR Dynamic range, A- weighted(2) IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 110 dBIN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 109 IN1 differential DC-coupled input selected and –72-dB full-scale AC signal input, 12-dB channel gain 101 THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –94 TBD dBIN1 differential DC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –94 IN1 differential DC-coupled input selected and –13-dB full-scale AC signal input, 12-dB channel gain –92

ADVANCE□INFORMATION PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 SBAS884 –MARCH 2020 www.ti.com Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT (3) Microphone inputs support a 2 VRMS differential input full-scale AC signal voltage, if the CHx_MIC_RANGE register bit is set to low (default value). However, if the input DC common-mode differential voltage is higher than 4 V, then TI recommends setting the CHx_MIC_RANGE register bit high to avoid any saturation resulting from the high input DC common-mode differential voltage. (4) If the CHx_MIC_RANGE register bit is set to high (default value is low) in DC-coupled input configuration mode, then the input differential DC common-mode along with input differential AC signal must be less than 10 VRMS for differential input configuration mode. Similarly, for single-ended input configuration mode, the input DC common-mode voltage along with the input AC signal must be less than 5 VRMS . Channel gain control range Programmable 1-dB steps 0 42 dB ADC PERFORMANCE FOR MICROPHONE INPUT RECORDING Differential input full-scale AC signal voltage(3) AC-coupled input, input fault diagnostic not supported. CHx_MIC_RANGE register bit is set to high.

10 VRMS

DC-coupled input, DC differential common-mode voltage INxP – INxM > 3.4 V, DC common-mode voltage INxP < (MICBIAS – 1.7 V) and DC common-mode voltage INxM > 1.7 V. CHx_MIC_RANGE register bit is set to high to support AC differential signal max swing > 2 Vrms(4). SNR Signal-to-noise ratio, A- weighted(1)(2) IN1 differential AC-coupled input selected and AC signal shorted to ground, 0-dB channel gain 109 dBIN1 differential DC-coupled input selected and AC-signal shorted to ground, DC differential common-mode voltage IN1P – IN1M < 5.0 V, 0-dB channel gain TBD 109 DR Dynamic range, A- weighted(2) IN1 differential AC-coupled input selected and –60-dB full-scale AC signal input, 0-dB channel gain 110 dBIN1 differential DC-coupled input selected and –60-dB full-scale AC signal input, DC differential common-mode voltage IN1P – IN1M < 5.0 V, 0-dB channel gain 109 THD+N Total harmonic distortion(2) IN1 differential AC-coupled input selected and –1-dB full-scale AC signal input, 0-dB channel gain –94 dB IN1 differential DC-coupled input selected and –15-dB full-scale AC signal input, 0-dB channel gain –90 TBD Channel gain control range Programmable 1-dB steps 0 42 dB ADC OTHER PARAMETERS Input impedance Differential input, between INxP and INxM 50 kΩ Single-ended input, between INxP and INxM 25 Digital volume control range Programmable 0.5-dB steps –100 27 dB Output data sample rate Programmable 7.35 768 kHz Output data sample word length Programmable 16 32 Bits Digital high-pass filter cutoff frequency First-order IIR filter with programmable coefficients, –3-dB point (default setting) 12 Hz Interchannel isolation –1-dB full-scale AC signal line-in input to non measurement channel –132 dB Interchannel gain mismatch –6-dB full-scale AC signal line-in input, 0-dB channel gain 0.1 dB Interchannel phase mismatch 1-kHz sinusoidal signal 0.02 Degrees PSRR Power-supply rejection ratio 100-mVPP, 1-kHz sinusoidal signal on AVDD, differential input selected, 0-dB channel gain 89 dB CMRR Common-mode rejection ratio Differential microphone input selected, 0-dB channel gain, 1-VRMS AC input, 1-kHz signal on both pins and measure level at output 80 dB MICROPHONE BIAS MICBIAS noise BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor between MICBIAS and AVSS 8 µVRMS MICBIAS voltage Programmable 0.5-V steps 5 9 V MICBIAS current drive MICBIAS voltage 9 V 80 mA MICBIAS load regulation MICBIAS voltage 9 V, measured up to maximum load 0 1 %

ADVANCE□INFORMATION PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 www.ti.com SBAS884 –MARCH 2020 Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT MICBIAS over current protection threshold 85 mA INPUT DIAGNOSTICS Fault monitoring repetition rate Programmable, DC-coupled input 1 4 8 ms Fault response time Fault monitoring repetition rate 4-ms, DC-coupled input 16 ms Threshold voltage for (INxx – AVSS) input shorted to ground Programmable 60-mV steps, DC-coupled input 0 900 mV Threshold voltage for (INxP – INxM) input shorted together Programmable 30-mV steps, DC-coupled input 0 450 mV Threshold voltage for (MICBIAS – INxx) input shorted to MICBIAS Programmable 30-mV steps, DC-coupled input 0 450 mV Threshold voltage for (VBAT – INxx) input shorted to VBAT_IN Programmable 30-mV steps, DC-coupled input 0 450 mV DIGITAL I/O VIL Low-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation –0.3 0.35 × IOVDD V All digital pins except SDA and SCL, IOVDD 3.3-V operation –0.3 0.8 VIH High-level digital input logic voltage threshold All digital pins except SDA and SCL, IOVDD 1.8-V operation 0.65 × IOVDD IOVDD + 0.3 V All digital pins except SDA and SCL, IOVDD 3.3-V operation 2 IOVDD + 0.3 VOL Low-level digital output voltage All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 1.8-V operation 0.45 V All digital pins except SDA and SCL, IOL = –2 mA, IOVDD 3.3-V operation 0.4 VOH High-level digital output voltage All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 1.8-V operation IOVDD – 0.45 V All digital pins except SDA and SCL, IOH = 2 mA, IOVDD 3.3-V operation 2.4 VIL(I2C) Low-level digital input logic voltage threshold SDA and SCL –0.5 0.3 × IOVDD V VIH(I2C) High-level digital input logic voltage threshold SDA and SCL 0.7 × IOVDD IOVDD + 0.5 V VOL1(I2C) Low-level digital output voltage SDA, IOL(I2C) = –3 mA, IOVDD > 2 V 0.4 V VOL2(I2C) Low-level digital output voltage SDA, IOL(I2C) = –2 mA, IOVDD ≤ 2 V 0.2 x IOVDD V IOL(I2C) Low-level digital output current SDA, VOL(I2C) = 0.4 V, standard-mode or fast-mode 3 mA SDA, VOL(I2C) = 0.4 V, fast-mode plus 20 IIL Input logic-low leakage for digital inputs All digital pins, input = 0 V –5 0.1 5 µA IIH Input logic-high leakage for digital inputs All digital pins, input = IOVDD –5 0.1 5 µA CIN Input capacitance for digital inputs All digital pins 5 pF RPD Pulldown resistance for digital I/O pins when asserted on 20 kΩ TYPICAL SUPPLY CURRENT CONSUMPTION IAVDD Current consumption in hardware shutdown mode SHDNZ = 0, all device external clocks stopped µAIBSTVDD, or IHVDD 0.1 IIOVDD 0.1

ADVANCE□INFORMATION PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 SBAS884 –MARCH 2020 www.ti.com Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Electrical Characteristics (continued) at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, BSTVDD = 3.3 V, HVDD = 11 V (for the PCM63x0-Q1), fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS, TDM slave mode and PLL on (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT IAVDD Current consumption in sleep mode (software shutdown mode) All device external clocks stopped µAIBSTVDD, or IHVDD 0.1 IIOVDD 0.1 IAVDD Current consumption when MICBIAS ON, MICBIAS voltage 9 V, 40 mA load, ADC off fS = 48 kHz, BCLK = 256 × fS 1.4 mA IBSTVDD 164.3 IHVDD 41.1 IIOVDD 0.01 IAVDD Current consumption with ADC 2-channel operation at fS 16-kHz, MICBIAS off, PLL on, BCLK = 512 × fS 13.5 mAIBSTVDD, or IHVDD IIOVDD 0.2 IAVDD Current consumption with ADC 2-channel operation at fS 48-kHz, MICBIAS off, PLL off, BCLK = 512 × fS 13.5 mAIBSTVDD, or IHVDD IIOVDD 0.4 IAVDD Current consumption with ADC 4-channel operation at fS 48-kHz, MICBIAS off, PLL on, BCLK = 256 × fS mAIBSTVDD, or IHVDD IIOVDD 0.6 IAVDD Current consumption with ADC 6-channel operation at fS 48 kHz, MICBIAS off, PLL on, BCLK = 256 × fS, (PCM6x60-Q1) mAIBSTVDD, or IHVDD IIOVDD 0.8

7.6 Timing Requirements: I2C Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 1 for timing diagram MIN NOM MAX UNIT STANDARD-MODE fSCL SCL clock frequency 0 100 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 4 μs tLOW Low period of the SCL clock 4.7 μs tHIGH High period of the SCL clock 4 μs tSU;STA Setup time for a repeated START condition 4.7 μs tHD;DAT Data hold time 0 3.45 μs tSU;DAT Data setup time 250 ns tr SDA and SCL rise time 1000 ns tf SDA and SCL fall time 300 ns tSU;STO Setup time for STOP condition 4 μs tBUF Bus free time between a STOP and START condition 4.7 μs FAST-MODE fSCL SCL clock frequency 0 400 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.6 μs tLOW Low period of the SCL clock 1.3 μs tHIGH High period of the SCL clock 0.6 μs tSU;STA Setup time for a repeated START condition 0.6 μs tHD;DAT Data hold time 0 0.9 μs tSU;DAT Data setup time 100 ns tr SDA and SCL rise time 20 300 ns tf SDA and SCL fall time 20 × (IOVDD / 5.5 V) 300 ns tSU;STO Setup time for STOP condition 0.6 μs tBUF Bus free time between a STOP and START condition 1.3 μs FAST-MODE PLUS fSCL SCL clock frequency 0 1000 kHz tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. 0.26 μs tLOW Low period of the SCL clock 0.5 μs tHIGH High period of the SCL clock 0.26 μs tSU;STA Setup time for a repeated START condition 0.26 μs tHD;DAT Data hold time 0 μs tSU;DAT Data setup time 50 ns tr SDA and SCL Rise Time 120 ns tf SDA and SCL Fall Time 20 × (IOVDD / 5.5 V) 120 ns tSU;STO Setup time for STOP condition 0.26 μs tBUF Bus free time between a STOP and START condition 0.5 μs

7.7 Switching Characteristics: I2C Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V (unless otherwise noted); see Figure 1 for timing diagram PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(SDA) SCL to SDA delay Standard-mode 300 1250 ns Fast-mode 300 850 ns Fast-mode plus 400 ns

7.8 Timing Requirements: SPI Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 2 for timing diagram MIN NOM MAX UNIT t(SCLK) SCLK period 40 ns tH(SCLK) SCLK high pulse duration 18 ns tL(SCLK) SCLK low pulse duration 18 ns tLEAD Enable lead time 16 ns tTRAIL Enable trail time 16 ns tDSEQ Sequential transfer delay 20 ns tSU(MOSI) MOSI data setup time 8 ns tHLD(MOSI) MOSI data hold time 8 ns tr(SCLK) SCLK rise time 10% - 90% rise time 6 ns tf(SCLK) SCLK fall time 90% - 10% fall time 6 ns

7.9 Switching Characteristics: SPI Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 2 for timing diagram PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ta(MISO) MISO access time 21 ns td(MISO) SCLK to MISO delay 50% of SCLK to 50% of MISO 21 ns tdis(MISO) MISO disable time 21 ns (1) The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

7.10 Timing Requirements: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram MIN NOM MAX UNIT t(BCLK) BCLK period 40 ns tH(BCLK) BCLK high pulse duration (1) 18 ns tL(BCLK) BCLK low pulse duration (1) 18 ns tSU(FSYNC) FSYNC setup time 8 ns tHLD(FSYNC) FSYNC hold time 8 ns tr(BCLK) BCLK rise time 10% - 90% rise time 10 ns tf(BCLK) BCLK fall time 90% - 10% fall time 10 ns (1) The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

7.11 Switching Characteristics: TDM, I2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(SDOUT-BCLK) BCLK to SDOUT delay 50% of BCLK to 50% of SDOUT 21 ns td(SDOUT-FSYNC) FSYNC to SDOUT delay in TDM or LJ mode (for MSB data with TX_OFFSET = 0) 50% of FSYNC to 50% of SDOUT 21 ns f(BCLK) BCLK output clock frequency; master mode (1) 24.576 MHz tH(BCLK) BCLK high pulse duration; master mode 14 ns tL(BCLK) BCLK low pulse duration; master mode 14 ns td(FSYNC) BCLK to FSYNC delay; master mode 50% of BCLK to 50% of FSYNC 21 ns tr(BCLK) BCLK rise time; master mode 10% - 90% rise time 8 ns tf(BCLK) BCLK fall time; master mode 90% - 10% fall time 8 ns

7.12 Typical Characteristics

Figure 4. THD+N vs Input Amplitude Figure 5. THD+N vs Input Amplitude Figure 6. THD+N vs Input Frequency With a –1-dBr Input Figure 7. THD+N vs Input Frequency With a –1-dBr Input Figure 8. FFT With Idle Input Figure 9. FFT With a –60-dBr Input

8 Detailed Description

8.1 Overview

Multichannel, multibit, high-performance delta-sigma (ΔΣ) ADCs
Configurable single-ended or differential audio inputs with high voltage signal swing
High-voltage, low-noise programmable microphone bias output
Highly flexible, comprehensive input fault diagnostic
Automatic gain controller (AGC)
Programmable decimation filters with linear-phase or low-latency filter
Programmable channel gain, volume control, and biquad filters for each channel
Programmable phase and gain calibration with fine resolution for each channel
Programmable high-pass filter (HPF) and digital channel mixer
Integrated low-jitter, phase-locked loop (PLL) supporting a wide range of system clocks
Integrated digital and analog voltage regulators to support single-supply operation Communication to the PCM6xx0-Q1 for configuring the control registers is supported using an I2C or SPI interface. The device supports a highly flexible audio serial interface [time-division multiplexing (TDM), I2S, or left-justified (LJ)] to transmit audio data seamlessly in the system across devices. The device can support multiple devices by sharing the common I2C and TDM buses across devices. Moreover, the device includes a daisy-chain feature and a secondary audio serial output data pin. These features relax the shared TDM bus timing requirements and board design complexities when operating multiple devices for applications requiring high audio data bandwidth. Table 1 lists the reference abbreviations used throughout this document to registers that control the device.

Table 1. Abbreviations for Register References

8.2 Functional Block Diagrams

Figure 20. Simplified Device Functional Block Diagram for the PCM6240-Q1

Figure 21. Simplified Device Functional Block Diagram for the PCM6340-Q1

Figure 22. Simplified Device Functional Block Diagram for the PCM6260-Q1

Figure 23. Simplified Device Functional Block Diagram for the PCM6360-Q1

8.3 Feature Description

8.3.1 Serial Interfaces

configuration. The audio data serial interface is used for transmitting audio data to the host device.

8.3.1.1 Control Serial Interfaces

communication to the device. For more information, see the Programming section.

8.3.1.2 Audio Serial Interfaces

bus clock lines, and the ability to communicate with multiple devices within a system directly. 20, 24, or 32 bits by configuring the ASI_WLEN[1:0], P0_R7_D[5:4] register bits. Table 2. Audio Serial Interface Format

01 Inter IC sound (I2S) mode

10 Left-justified (LJ) mode

11 Reserved (do not use this setting)

Table 3. Audio Output Channel Data Word-Length

00 Output channel data word-length set to 16 bits

01 Output channel data word-length set to 20 bits

10 Output channel data word-length set to 24 bits

output channels with the programmed data word length.

and Left-Justified (LJ) Interface sections. Table 4. Output Channel Slot Assignment Settings 00 0000 = 0d (default) Slot 0 for TDM or left slot 0 for I2S, LJ. 00 0001 = 1d Slot 1 for TDM or left slot 1 for I2S, LJ. 01 1111 = 31d Slot 31 for TDM or left slot 31 for I2S, LJ. 10 0000 = 32d Slot 32 for TDM or right slot 0 for I2S, LJ. 11 1110 = 62d Slot 62 for TDM or right slot 30 for I2S, LJ. 11 1111 = 63d Slot 63 for TDM or right slot 31 for I2S, LJ. (P0_R12) to CH6_SLOT (P0_R16) registers, respectively. up to 31 cycles of the bit clock. Table 5 lists the programmable offset configuration settings. Table 5. Programmable Offset Settings for the ASI Slot Start 0 0000 = 0d (default) The device follows the standard protocol timing without any offset. Slot start is offset by one BCLK cycle, as compared to standard protocol timing. Slot start is offset by 30 BCLK cycles, as compared to standard protocol timing. Slot start is offset by 31 BCLK cycles, as compared to standard protocol timing. which can be set using the BCLK_POL, P0_R7_D2 register bit.

8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface

each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK. Figure 24 to Figure 27 illustrate the protocol timing for TDM operation with various configurations.

8.3.1.2.2 Inter IC Sound (I2S) Interface

of BCLK. Figure 28 to Figure 31 show the protocol timing for I2S operation with various configurations. Figure 28. I2S Mode Standard Protocol Timing (TX_OFFSET = 0) Figure 29. I2S Protocol Timing (TX_OFFSET = 1) Figure 30. I2S Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0) Figure 31. I2S Protocol Timing (TX_OFFSET = 0 and BCLK_POL = 1)

times the data word length configured.

8.3.1.2.3 Left-Justified (LJ) Interface

after the rising edge of FSYNC. Each subsequent data bit is transmitted on the falling edge of BCLK. illustrate the protocol timing for LJ operation with various configurations. Figure 32. LJ Mode Standard Protocol Timing (TX_OFFSET = 0) Figure 33. LJ Protocol Timing (TX_OFFSET = 2) Figure 34. LJ Protocol Timing (No Idle BCLK Cycles, TX_OFFSET = 0)

Figure 35. LJ Protocol Timing (TX_OFFSET = 1 and BCLK_POL = 1) value higher than 0 is recommended.

8.3.1.3 Using Multiple Devices With Shared Buses

beam-forming operation, hands-free in-vehicle communication, car cabin active noise cancellation, and so forth. Figure 36. Multiple PCM6xx0-Q1 Devices With Shared Control and Audio Data Buses

Supports up to four pin-programmable I2C slave addresses
I2C broadcast simultaneously writes to (or triggers) all PCM6xx0-Q1 devices
Supports up to 64 configuration output channel slots for the audio serial interface
Tri-state feature (with enable and disable) for the unused audio data slots of the device
Supports a bus-holder feature (with enable and disable) to keep the last driven value on the audio bus
The GPIOx pin can be configured as a secondary output data lane for the audio serial interface
The GPIOx or GPIx pin can be used in a daisy-chain configuration of multiple PCM6xx0-Q1 devices
Supports one BCLK cycle data latching timing to relax the timing requirement for the high-speed interface
Programmable master and slave options for the audio serial interface

Ability to synchronize the multiple devices for the simultaneous sampling requirement across devices See the Multiple PCM6xx0-Q1 Devices With Shared TDM and I2C Bus application report for further details.

8.3.2 Phase-Locked Loop (PLL) and Clock Generation

frequency of the FSYNC and BCLK signal on the audio bus. FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming. Table 6 and Table 7 list the supported FSYNC and BCLK frequencies. Table 6. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies Table 7. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies

FSYNC ratios, the device generates an ASI clock-error interrupt and mutes the record channels accordingly. some processing features may not be supported if the external audio clock source frequency is not high enough. Power Consumption Matrix Across Various Usage Scenario application report. Operating the PCM6xx0-Q1 as an Audio Bus Master application report. graphical development suite.

8.3.3 Input Channel Configuration

Table 8. Input Source Selection for the Record Channel

01 Analog single-ended input for channel 1

CH2_INSRC[1:0] (P0_R65_D[6:5]) to CH6_INSRC[1:0] (P0_R85_D[6:5]) registers bits, respectively. CH1_DC (P0_R60_D4) to CH6_DC (P0_R85_D4) register bits. high as 8.4 V (for the MICBIAS 9-V setting), including the AC signal and DC differential common-mode voltage. full-scale corresponds to the 10-VRMS AC signal in this case.

External Resistor Calculator to calculate the R0 value for the desired system configuration. Figure 39. AC-Coupled Microphone or Line Differential Input Connection Figure 40. AC-Coupled Microphone or Line Single-Ended Input Connection

8.3.4 Reference Voltage

externally using a minimum 1-µF capacitor connected from the VREF pin to the analog ground (AVSS). P0_R2_D[4:3] register bits, which support options of 3.5 ms (default), 10 ms, 50 ms, or 100 ms.

8.3.5 Microphone Bias

programmed microphone bias voltage and must be lower than 12 V. available microphone bias programmable options. Table 9. MICBIAS Programmable Settings

8.3.6 Input DC Fault Diagnostics

detect fault conditions in the DC-coupled input configuration and trigger an interrupt request to a host processor. supported in the AC-coupled input configuration. by any short-duration transient events.

8.3.6.1 Fault Conditions

8.3.6.1.1 Input Pin Short to Ground

respect to ground (AVSS). The threshold can be set by configuring DIAG_SHT_GND, P0_R102_D7-4.

8.3.6.1.2 Input Pin Short to MICBIAS

A short to MICBIAS fault occurs when the difference between the voltage measured for the MICBIAS pin and the input pin (MICBIAS – INxx) is less than the threshold. The threshold can be set by configuring DIAG_SHT_MICBIAS, P0_R102_D3-0.

8.3.6.1.3 Open Inputs

In the event that a microphone becomes disconnected from the inputs, the microphone bias resistors pull INxP to MICBIAS and INxM to ground. The combination of INxP shorted to MICBIAS and INxM shorted to ground for the same channel in a diagnostic sweep results in an open input fault condition.

8.3.6.1.4 Short Between INxP and INxM

An input terminal shorted fault occurs when the difference between the voltage measured for the input pin INxP and the input pin INxM of the same channel is less than the threshold. The threshold can be set by configuring DIAG_SHT_TERM, P0_R101_D7-4.

8.3.6.1.5 Input Pin Overvoltage

An input terminal overvoltage fault occurs when the voltage measured for the input pin is above the voltage measured for the MICBIAS pin.

8.3.6.1.6 Input Pin Short to VBAT_IN

A short to VBAT_IN fault occurs when the difference between the voltage measured for the VBAT_IN pin and the input pin, ABS(VBAT_IN – INxx), is less than the threshold or both the VBAT_IN and INxx pin measured voltages are above 11.7 V. The threshold can be set by configuring DIAG_SHT_VBAT_IN, P0_R101_D3-0. When VBAT_IN is less than MICBIAS, false fault detections can exist based on the signal level of the INxx pin. To minimize false detections there is also a separate debounce count for this condition set by configuring VSHORT_DBNCE, P0_R106_D1.

8.3.6.2 Fault Reporting

Faults are reported in live and latched status registers. The live registers, P1_R45 to P1_R55, are updated continuously with each new scan and report the most recent measurements reported by the diagnostics processor. The latched status of each diagnostic fault is reported by the channel in P0_R46 to P0_R55, and a latched summary by the channel is reported in CHx_LTCH, P0_R45. The latched registers clear upon reading, and are latched if the associated bit in the live fault registers transitions from a ‘0’to a ‘1’. A transition of any bit in the latched register from a ‘0’to ‘1’triggers an interrupt request. For detecting a persistent fault, an additional mode is available for the latched registers. In this mode, the latched registers are only cleared upon reading if the status bit in the associated live status register is ‘0’at the time of reading. This mode is enabled by configuring LTCH_CLR_ON_READ, P0_R40_D0 to a ‘1’.

8.3.6.2.1 Overcurrent and Overtemperature Protection

The device has an overcurrent protection circuit that limits the current drawn out of the MICBIAS output to the maximum supported level when an external undesired short event occurs on the MICBIAS pin. The device sets the status flag, P0_R44_D4 bit, on an overcurrent detection. Additionally, the device has an overtemperature detection circuit that is enabled by default and sets the status flag, P0_R44_D5 bit, whenever the die junction temperature goes higher than the supported level. Additionally, register P0_R58 and P0_R40_D4:3 can be configured to shutdown MICBIAS along with the on-chip boost on an overtemperature detection. TI recommends configuring PD_ON_FLT_CFG, P0_R40_D4-3 to "10" so that on an overtemperature detection, the device powers-down MICBIAS, the on-chip boost, and all ADC channels. More details and information on fault diagnostics are discussed in the PCM6xx0-Q1 Fault Diagnostics, Interrupts, and Protection Features application report.

8.3.7 Signal-Chain Processing

building blocks used in the signal chain, and how the blocks interact in the signal chain. Figure 41. Signal-Chain Processing Flowchart sharply cuts off any out-of-band frequency noise with high stop-band attenuation. Filter application report for further details. details on these processing blocks are discussed further in this section. 1 in this mode of operation. be recorded by using a 176.4-kHz (or higher) sample rate.

8.3.7.1 Programmable Channel Gain and Digital Volume Control

(see the Reference Voltage section), which determines the ADC full-scale signal level. Table 10 shows the programmable options available for the channel gain. Table 10. Channel Gain Programmable Settings (P0_R66) to CH6_GAIN (P0_R86) register bits, respectively. disabled using the DISABLE_SOFT_STEP (P0_R108_D4) register bit. or powered down. This gang-up can be enabled using the DVOL_GANG (P0_R108_D7) register bit. Table 11 shows the programmable options available for the digital volume control. Table 11. Digital Volume Control (DVC) Programmable Settings

CH2_DVOL (P0_R67) to CH6_DVOL (P0_R87) register bits, respectively. using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.

8.3.7.2 Programmable Channel Gain Calibration

0.1 dB. Table 12 shows the programmable options available for the channel gain calibration. Table 12. Channel Gain Calibration Programmable Settings CH2_GCAL (P0_R68) to CH6_GCAL (P0_R88) register bits, respectively.

8.3.7.3 Programmable Channel Phase Calibration

programmable options for channel phase calibration. Table 13. Channel Phase Calibration Programmable Settings CH2_PCAL (P0_R69) to CH6_PCAL (P0_R89) register bits, respectively.

231 F &1VF1

8.3.7.4 Programmable Digital High-Pass Filter

2'b00. Figure 42 shows a frequency response plot for the HPF filter. Table 14. HPF Programmable Settings

00 Programmable 1st-order IIR filter Programmable 1st-order IIR filter Programmable 1st-order IIR filter

Figure 42. HPF Filter Frequency Response Plot complement numbers. Table 15 shows the filter coefficients for the first-order IIR filter. Table 15. 1st-Order IIR Filter Coefficients

231 F 2&1VF1 F &2VF2

8.3.7.5 Programmable Digital Biquad Filters

Programmable Biquad Filter Configuration and Applications application report for further details. Table 16. Biquad Filter Allocation to the Record Output Channel Table 17 shows the biquad filter coefficients mapping to the register space. Table 17. Biquad Filter Coefficients Register Mapping

8.3.7.6 Programmable Channel Summer and Digital Mixer

settings available for channel summing mode. Table 18. Channel Summing Mode Programmable Settings

11 Reserved (do not use this setting) Not applicable

channel 4. Figure 43 shows a block diagram that describes the mixer 1 operation to generate output channel 1. Page = 0x04 section. All mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format. are 32-bit, two’s complement numbers. Figure 43. Programmable Digital Mixer Block Diagram and channel 4, respectively.

8.3.7.7 Configurable Digital Decimation Filters

decimation filter mode selection for the record channel. Table 19. Decimation Filter Mode Selection for the Record Channel

01 Low-latency filters are used for the decimation

10 Ultra-low latency filters are used for the decimation

8.3.7.7.1 Linear Phase Filters

8-kHz or 7.35-kHz sampling rate. Figure 44. Linear Phase Decimation Filter Magnitude Figure 45. Linear Phase Decimation Filter Pass-Band Table 20. Linear Phase Decimation Filter Specifications

8.3.7.7.2 Low-Latency Filters

filter with a 16-kHz or 14.7-kHz sampling rate. Figure 62. Low-Latency Decimation Filter Magnitude Figure 63. Low-Latency Decimation Filter Pass-Band Table 29. Low-Latency Decimation Filter Specifications

Table 34. Low-Latency Decimation Filter Specifications

8.3.7.7.3 Ultra-Low-Latency Filters

filter with a 16-kHz or 14.7-kHz sampling rate. Figure 74. Ultra-Low-Latency Decimation Filter Magnitude Figure 75. Ultra-Low-Latency Decimation Filter Pass-Band Table 35. Ultra-Low-Latency Decimation Filter Specifications

8.3.8 Automatic Gain Controller (AGC)

time constants, and noise thresholds that allow the algorithm to be fine-tuned for any particular application. Figure 88. AGC Characteristics the AGC target level configuration settings. Table 42. AGC Target Level Programmable Settings

0000 The AGC target level is the –6-dB output signal level

0001 The AGC target level is the –8-dB output signal level

0010 The AGC target level is the –10-dB output signal level

1111 The AGC target level is the –36-dB output signal level

dB and the default value is set to 24 dB. Table 43 lists the AGC_MAXGAIN configuration settings. Table 43. AGC Maximum Gain Programmable Settings

0000 The AGC maximum gain allowed is 3 dB

0001 The AGC maximum gain allowed is 6 dB

0010 The AGC maximum gain allowed is 9 dB

1110 The AGC maximum gain allowed is 39 dB

1111 The AGC maximum gain allowed is 42 dB

Gain Controller (AGC) in PCM6xx0-Q1 application report.

8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing

Invalid FSYNC frequency
Invalid SBCLK to FSYNC ratio
Long pauses of the SBCLK or FSYNC clocks When an ASI bus clock error is detected, the device shuts down the record channel as quickly as possible. After all ASI bus clock errors are resolved, the device volume ramps back to its previous state to recover the record channel. During an ASI bus clock error, the internal interrupt request (IRQ) interrupt signal asserts low if the clock error interrupt mask register bit INT_MASK0[7], P0_R51_D7 is set low. The clock fault is also available for readback in the live fault status register bit INT_LIVE0, P1_R44 as well as latched to the fault status register bit INT_LTCH0, P0_R44, which is a read-only register. Reading the latched fault status register, INT_LTCH0, clears all latched fault statuses. The device can be additionally configured to route the internal IRQ interrupt signal on the GPIOx pins and also can be configured as an open-drain output so that these pins can be wire-ANDed to the open-drain interrupt outputs of other devices. When an input DC fault event is detected, the internal IRQ signal is asserted if the interrupt mask registers INT_MASK1, P0_R42 and INT_MASK2, P0_R43 are configured appropriately to unmask all the desired fault diagnostics interrupts. Each input channel can be independently set for an interrupt mask. Table 44 and Table 45 list the mask settings available for the input DC diagnostics fault interrupts.

Table 44. Interrupt Mask Register-1 for DC Faults Diagnostic

Table 45. Interrupt Mask Register-2 for DC Faults Diagnostic CH1_LTCH to CH6_LTCH, clears all the latched fault status including the summary status register, CHx_LTCH. Table 46 shows various input DC fault diagnostics status bits that are supported by the device. Table 46. Input DC Faults Diagnostic Latched Status CH2_LTCH (P0_R47) to CH6_LTCH (P0_R51) registers, respectively. interrupt outputs of other devices.

(1) S means the feature mentioned in this row is supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column. (2) NS means the feature mentioned in this row is not supported for the respective GPIO1, GPOx, or GPIx pin mentioned in this column. other features. Table 47 shows all possible allocation of these multifunction pins for all the various features. Table 47. Multifunction Pin Assignments register bits. Table 48 lists the drive configuration settings. Table 48. GPIOx Pins Drive Configuration Settings

000 The GPIO1 pin is set to high impedance (floated)

001 The GPIO1 pin is set to be driven active low or active high

011 The GPIO1 pin is set to be driven active low or Hi-Z (floated)

100 The GPIO1 pin is set to be driven weak low (on-chip pulldown) or active high

101 The GPIO1 pin is set to be driven Hi-Z (floated) or active high

GPIO3_DRV(P0_R35) register bits, respectively. GPIOx and GPIx pins when configured as a general-purpose input (GPI).

8.4 Device Functional Modes

8.4.1 Hardware Shutdown

The device enters hardware shutdown mode when the SHDNZ pin is asserted low or the AVDD supply voltage is not applied to the device. In hardware shutdown mode, the device consumes the minimum quiescent current from the AVDD supply. All configuration registers and programmable coefficients lose their value in this mode, and I2C or SPI communication to the device is not supported. If the SHDNZ pin is asserted low when the device is in active mode, the device ramps down volume on the record data, powers down the analog and digital blocks, and puts the device into hardware shutdown mode in 25 ms (typical). The device can also be immediately put into hardware shutdown mode from active mode if the SHDNZ_CFG[1:0], P0_R5_D[3:2], register bits are set to 2'b00. After the SHDNZ pin is asserted low, and after the device enters hardware shutdown mode, keep the SHDNZ pin low for at least 1 ms before releasing SHDNZ for further device operation. Assert the SHDNZ pin high only when the IOVDD supply settles to a steady voltage level. When the SHDNZ pin goes high, the device sets all configuration registers and programmable coefficients to their default values, and then enters sleep mode.

8.4.2 Sleep Mode or Software Shutdown

In sleep mode or software shutdown mode, the device consumes very low quiescent current from the AVDD supply and, at the same time, allows the I2C or SPI communication to wake the device for active operation. The device can also enter sleep mode when the host device sets the SLEEP_ENZ, P0_R2_D0 bit to 1'b0. If the SLEEP_ENZ bit is asserted low when the device is in active mode, the device ramps down the volume on the record data, powers down the analog and digital blocks, and enters sleep mode. However, the device still continues to retain the last programmed value of the device configuration registers and programmable coefficients. In sleep mode, do not perform any I2C or SPI transactions, except for exiting sleep mode in order to enter active mode. After entering sleep mode, wait at least 10 ms before starting I2C or SPI transactions to exit sleep mode.

8.4.3 Active Mode

If the host device exits sleep mode by setting the SLEEP_ENZ bit to 1'b1, the device enters active mode. In active mode, I2C or SPI transactions can be done to configure and power-up the device for active operation. After entering active mode, wait at least 1 ms before starting any I2C or SPI transactions in order to allow the device to complete the internal wake-up sequence. After configuring all other registers for the target application and system settings, configure the input and output channel enable registers, P0_R115 (IN_CH_EN) and P0_R116 (ASI_OUT_CH_EN), respectively. Lastly, configure the device power-up register, P0_R117 (PWR_CFG). All the programmable coefficient values must be written before powering up the respective channel. In active mode, the power-up and power-down status of various blocks is monitored by reading the read-only device status bits located in the P0_R117 (DEV_STS0) and P0_R118 (DEV_STS1) registers.

8.4.4 Software Reset

A software reset can be done any time by asserting the SW_RESET bit, P0_R1_D0, which is a self-clearing bit. This software reset immediately shuts down the device, and restores all device configuration registers and programmable coefficients to their default values.

8.5 Programming

bits in width, mapped using a page scheme. can be switched to a new desired page by using the PAGE[7:0] bits located in register 0 of every page.

8.5.1 Control Serial Interfaces

The device control registers can be accessed using either I2C or SPI communication to the device. either the I2C or SPI interface, but not both, to configure the device.

8.5.1.1 I2C Control Interface

Q1 devices in the system. Table 49 lists the four possible device addresses resulting from this configuration. Table 49. I2C Slave Address Settings

8.5.1.1.1 General I2C Operation

generic data transfer sequence. Figure 89. Typical I2C Sequence In the system, use external pullup resistors for the SDA and SCL signals to set the logic high level for the bus. The SDA and SCL voltages must not exceed the device supply voltage, IOVDD.

8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers

as long as the master device continues to respond with acknowledges. Figure 90. I2C Single-Byte Write Transfer

the last data-byte write transfer. Figure 91. I2C Multiple-Byte Write Transfer to be read. As a result, the read/write bit is set to 0. acknowledge (NACK) followed by a STOP condition to complete the single-byte data read transfer. Figure 92. I2C Single-Byte Read Transfer Figure 93. I2C Multiple-Byte Read Transfer

8.5.1.2 SPI Control Interface

shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. Table 50. SPI Command Word Figure 94. SPI Single-Byte Write Transfer Figure 95. SPI Single-Byte Read Transfer

8.6 Register Maps

This section describes the control registers for the device in detail. All registers are eight bits in width and are allocated to the device configuration and programmable coefficients settings. These registers are mapped internally using a page scheme that can be controlled using either I2C or SPI communication to the device. Each page contains 128 bytes of registers. All device configuration registers are stored in page 0, which is the default page setting at power up (and after a software reset). Page 1 consists of the live status registers and input diagnostic SAR data for advanced diagnostic purposes. All programmable coefficient registers are located in page 2, page 3, and page 4. The device current page can be switched to a new desired page by using the PAGE[7:0] bits located in register 0 of every page. Do not read from or write to reserved pages or reserved registers. Write only default values for the reserved bits in the valid registers. The procedure for register access across pages is:

Select page N (write data N to register 0 regardless of the current page number)
Read or write data from or to valid registers in page N
Select the new page M (write data M to register 0 regardless of the current page number)
Read or write data from or to valid registers in page M
Repeat as needed

8.6.1 Device Configuration Registers

This section describes the device configuration registers for page 0 and page 1.

8.6.1.1 Register Summary Table Page=0x00

ADDRESS REGISTER DESCRIPTION SECTION 0x00 PAGE_CFG Device page register PAGE_CFG Register (P0_R0) 0x01 SW_RESET Software reset register SW_RESET Register (P0_R1) 0x02 SLEEP_CFG Sleep mode register SLEEP_CFG Register (P0_R2) 0x05 SHDN_CFG Shutdown configuration register SHDN_CFG Register (P0_R5) 0x07 ASI_CFG0 ASI configuration register 0 ASI_CFG0 Register (P0_R7) 0x08 ASI_CFG1 ASI configuration register 1 ASI_CFG1 Register (P0_R8) 0x09 ASI_CFG2 ASI configuration register 2 ASI_CFG2 Register (P0_R9) 0x0B ASI_CH1 Channel 1 ASI slot configuration register ASI_CH1 Register (P0_R11) 0x0C ASI_CH2 Channel 2 ASI slot configuration register ASI_CH2 Register (P0_R12) 0x0D ASI_CH3 Channel 3 ASI slot configuration register ASI_CH3 Register (P0_R13) 0x0E ASI_CH4 Channel 4 ASI slot configuration register ASI_CH4 Register (P0_R14) 0x0F ASI_CH5 Channel 5 ASI slot configuration register ASI_CH5 Register (P0_R15) 0x10 ASI_CH6 Channel 6 ASI slot configuration register ASI_CH6 Register (P0_R16) 0x13 MST_CFG0 ASI master mode configuration register 0 MST_CFG0 Register (P0_R19) 0x14 MST_CFG1 ASI master mode configuration register 1 MST_CFG1 Register (P0_R20) 0x15 ASI_STS ASI bus clock monitor status register ASI_STS Register (P0_R21) 0x16 CLK_SRC Clock source configuration register CLK_SRC Register (P0_R22) 0x21 GPIO_CFG0 GPIO configuration register 0 GPIO_CFG0 Register (P0_R33) 0x22 GPIO_CFG1 GPIO configuration register 1 GPIO_CFG1 Register (P0_R34) 0x23 GPIO_CFG2 GPIO configuration register 2 GPIO_CFG2 Register (P0_R35) 0x24 GPI_CFG0 GPI configuration register 0 GPI_CFG0 Register (P0_R36) 0x25 GPI_CFG1 GPI configuration register 1 GPI_CFG1 Register (P0_R37) 0x26 GPIO_VAL GPIO output value register GPIO_VAL Register (P0_R38) 0x27 GPIO_MON GPIO monitor value register GPIO_MON Register (P0_R39) 0x28 INT_CFG Interrupt configuration register INT_CFG Register (P0_R40) 0x29 INT_MASK0 Interrupt mask register 0 INT_MASK0 Register (P0_R41) 0x2A INT_MASK1 Interrupt mask register 1 INT_MASK1 Register (P0_R42) 0x2B INT_MASK2 Interrupt mask register 2 INT_MASK2 Register (P0_R43) 0x2C INT_LTCH0 Latched interrupt readback register 0 INT_LTCH0 Register (P0_R44)

ADVANCE□INFORMATION PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 SBAS884 –MARCH 2020 www.ti.com Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Register Maps (continued) 0x2D CHx_LTCH Channel diagnostic summary latched status register CHx_LTCH Register (P0_R45) 0x2E CH1_LTCH Channel 1 diagnostic latched status register CH1_LTCH Register (P0_R46) 0x2F CH2_LTCH Channel 2 diagnostic latched status register CH2_LTCH Register (P0_R47) 0x30 CH3_LTCH Channel 3 diagnostic latched status register CH3_LTCH Register (P0_R48) 0x31 CH4_LTCH Channel 4 diagnostic latched status register CH4_LTCH Register (P0_R49) 0x32 CH5_LTCH Channel 5 diagnostic latched status register CH5_LTCH Register (P0_R50) 0x33 CH6_LTCH Channel 6 diagnostic latched status register CH6_LTCH Register (P0_R51) 0x34 INT_MASK3 Interrupt mask register 3 INT_MASK3 Register (P0_R52) 0x35 INT_LTCH1 Latched interrupt readback register 1 INT_LTCH1 Register (P0_R53) 0x36 INT_LTCH2 Latched interrupt readback register 2 INT_LTCH2 Register (P0_R54) 0x37 INT_LTCH3 Latched interrupt readback register 3 INT_LTCH3 Register (P0_R55) 0x38 MBDIAG_CFG0 MICBIAS diagnostic register 0 MBDIAG_CFG0 Register (P0_R56) 0x39 MBDIAG_CFG1 MICBIAS diagnostic register 1 MBDIAG_CFG1 Register (P0_R57) 0x3A MBDIAG_CFG2 MICBIAS diagnostic register 2 MBDIAG_CFG2 Register (P0_R58) 0x3B BIAS_CFG Bias configuration register BIAS_CFG Register (P0_R59) 0x3C CH1_CFG0 Channel 1 configuration register 0 CH1_CFG0 Register (P0_R60) 0x3D CH1_CFG1 Channel 1 configuration register 1 CH1_CFG1 Register (P0_R61) 0x3E CH1_CFG2 Channel 1 configuration register 2 CH1_CFG2 Register (P0_R62) 0x3F CH1_CFG3 Channel 1 configuration register 3 CH1_CFG3 Register (P0_R63) 0x40 CH1_CFG4 Channel 1 configuration register 4 CH1_CFG4 Register (P0_R64) 0x41 CH2_CFG0 Channel 2 configuration register 0 CH2_CFG0 Register (P0_R65) 0x42 CH2_CFG1 Channel 2 configuration register 1 CH2_CFG1 Register (P0_R66) 0x43 CH2_CFG2 Channel 2 configuration register 2 CH2_CFG2 Register (P0_R67) 0x44 CH2_CFG3 Channel 2 configuration register 3 CH2_CFG3 Register (P0_R68) 0x45 CH2_CFG4 Channel 2 configuration register 4 CH2_CFG4 Register (P0_R69) 0x46 CH3_CFG0 Channel 3 configuration register 0 CH3_CFG0 Register (P0_R70) 0x47 CH3_CFG1 Channel 3 configuration register 1 CH3_CFG1 Register (P0_R71) 0x48 CH3_CFG2 Channel 3 configuration register 2 CH3_CFG2 Register (P0_R72) 0x49 CH3_CFG3 Channel 3 configuration register 3 CH3_CFG3 Register (P0_R73) 0x4A CH3_CFG4 Channel 3 configuration register 4 CH3_CFG4 Register (P0_R74) 0x4B CH4_CFG0 Channel 4 configuration register 0 CH4_CFG0 Register (P0_R75) 0x4C CH4_CFG1 Channel 4 configuration register 1 CH4_CFG1 Register (P0_R76) 0x4D CH4_CFG2 Channel 4 configuration register 2 CH4_CFG2 Register (P0_R77) 0x4E CH4_CFG3 Channel 4 configuration register 3 CH4_CFG3 Register (P0_R78) 0x4F CH4_CFG4 Channel 4 configuration register 4 CH4_CFG4 Register (P0_R79) 0x50 CH5_CFG0 Channel 5 configuration register 0 CH5_CFG0 Register (P0_R80) 0x51 CH5_CFG1 Channel 5 configuration register 1 CH5_CFG1 Register (P0_R81) 0x52 CH5_CFG2 Channel 5 configuration register 2 CH5_CFG2 Register (P0_R82) 0x53 CH5_CFG3 Channel 5 configuration register 3 CH5_CFG3 Register (P0_R83) 0x54 CH5_CFG4 Channel 5 configuration register 4 CH5_CFG4 Register (P0_R84) 0x55 CH6_CFG0 Channel 6 configuration register 0 CH6_CFG0 Register (P0_R85) 0x56 CH6_CFG1 Channel 6 configuration register 1 CH6_CFG1 Register (P0_R86) 0x57 CH6_CFG2 Channel 6 configuration register 2 CH6_CFG2 Register (P0_R87) 0x58 CH6_CFG3 Channel 6 configuration register 3 CH6_CFG3 Register (P0_R88) 0x59 CH6_CFG4 Channel 6 configuration register 4 CH6_CFG4 Register (P0_R89) 0x64 DIAG_CFG0 Input diagnostic configuration register 0 DIAG_CFG0 Register (P0_R100) 0x65 DIAG_CFG1 Input diagnostic configuration register 1 DIAG_CFG1 Register (P0_R101) 0x66 DIAG_CFG2 Input diagnostic configuration register 2 DIAG_CFG2 Register (P0_R102) 0x67 DIAG_CFG3 Input diagnostic configuration register 3 DIAG_CFG3 Register (P0_R103) 0x68 DIAG_CFG4 Input diagnostic configuration register 4 DIAG_CFG4 Register (P0_R104) 0x6B DSP_CFG0 DSP configuration register 0 DSP_CFG0 Register (P0_R107) 0x6C DSP_CFG1 DSP configuration register 1 DSP_CFG1 Register (P0_R108)

ADVANCE□INFORMATION PCM6240-Q1, PCM6260-Q1, PCM6340-Q1, PCM6360-Q1 www.ti.com SBAS884 –MARCH 2020 Product Folder Links: PCM6240-Q1 PCM6260-Q1 PCM6340-Q1 PCM6360-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Register Maps (continued) 0x70 AGC_CFG0 AGC configuration register 0 AGC_CFG0 Register (P0_R112) 0x73 IN_CH_EN Input channel enable configuration register IN_CH_EN Register (P0_R115) 0x74 ASI_OUT_CH_EN ASI output channel enable configuration register ASI_OUT_CH_EN Register (P0_R116) 0x75 PWR_CFG Power up configuration register PWR_CFG Register (P0_R117) 0x76 DEV_STS0 Device status value register 0 DEV_STS0 Register (P0_R118) 0x77 DEV_STS1 Device status value register 1 DEV_STS1 Register (P0_R119)

8.6.1.2 Register Summary Table Page=0x01

ADDRESS REGISTER DESCRIPTION SECTION 0x00 PAGE_CFG Device page register PAGE_CFG Register (P1_R0) 0x16 MBIAS_LOAD MICBIAS internal load sink configuration register MBIAS_LOAD Register (P1_R22) 0x2C INT_LIVE0 Live interrupt readback register 0 INT_LIVE0 Register (P1_R44) 0x2D CHx_LIVE Channel diagnostic summary live status register CHx_LIVE Register (P1_R45) 0x2E CH1_LIVE Channel 1 diagnostic live status register CH1_LIVE Register (P1_R46) 0x2F CH2_LIVE Channel 2 diagnostic live status register CH2_LIVE Register (P1_R47) 0x30 CH3_LIVE Channel 3 diagnostic live status register CH3_LIVE Register (P1_R48) 0x31 CH4_LIVE Channel 4 diagnostic live status register CH4_LIVE Register (P1_R49) 0x32 CH5_LIVE Channel 5 diagnostic live status register CH5_LIVE Register (P1_R50) 0x33 CH6_LIVE Channel 6 diagnostic live status register CH6_LIVE Register (P1_R51) 0x35 INT_LIVE1 Live interrupt readback register 1 INT_LIVE1 Register (P1_R53) 0x37 INT_LIVE3 Live interrupt readback register 3 INT_LIVE3 Register (P1_R55) 0x59 DIAGDATA_CFG Diagnostic data configuration register DIAGDATA_CFG Register (P1_R89) 0x5A DIAG_MON_MSB_VBAT Diagnostic VBAT_IN data MSB byte register DIAG_MON_MSB_VBAT Register (P1_R90) 0x5B DIAG_MON_LSB_VBAT Diagnostic VBAT_IN data LSB nibble register DIAG_MON_LSB_VBAT Register (P1_R91) 0x5C DIAG_MON_MSB_MBIAS Diagnostic MICBIAS data MSB byte register DIAG_MON_MSB_MBIAS Register (P1_R92) 0x5D DIAG_MON_LSB_MBIAS Diagnostic MICBIAS data LSB nibble register DIAG_MON_LSB_MBIAS Register (P1_R93) 0x5E DIAG_MON_MSB_IN1P Diagnostic IN1P data MSB byte register DIAG_MON_MSB_IN1P Register (P1_R94) 0x5F DIAG_MON_LSB_IN1P Diagnostic IN1P data LSB nibble register DIAG_MON_LSB_IN1P Register (P1_R95) 0x60 DIAG_MON_MSB_IN1M Diagnostic IN1M data MSB byte register DIAG_MON_MSB_IN1M Register (P1_R96) 0x61 DIAG_MON_LSB_IN1M Diagnostic IN1M data LSB nibble register DIAG_MON_LSB_IN1M Register (P1_R97) 0x62 DIAG_MON_MSB_IN2P Diagnostic IN2P data MSB byte register DIAG_MON_MSB_IN2P Register (P1_R98) 0x63 DIAG_MON_LSB_IN2P Diagnostic IN2P data LSB nibble register DIAG_MON_LSB_IN2P Register (P1_R99) 0x64 DIAG_MON_MSB_IN2M Diagnostic IN2M data MSB byte register DIAG_MON_MSB_IN2M Register (P1_R100) 0x65 DIAG_MON_LSB_IN2M Diagnostic IN2M data LSB nibble register DIAG_MON_LSB_IN2M Register (P1_R101) 0x66 DIAG_MON_MSB_IN3P Diagnostic IN3P data MSB byte register DIAG_MON_MSB_IN3P Register (P1_R102) 0x67 DIAG_MON_LSB_IN3P Diagnostic IN3P data LSB nibble register DIAG_MON_LSB_IN3P Register (P1_R103) 0x68 DIAG_MON_MSB_IN3M Diagnostic IN3M data MSB byte register DIAG_MON_MSB_IN3M Register (P1_R104) 0x69 DIAG_MON_LSB_IN3M Diagnostic IN3M data LSB nibble register DIAG_MON_LSB_IN3M Register (P1_R105) 0x6A DIAG_MON_MSB_IN4P Diagnostic IN4P data MSB byte register DIAG_MON_MSB_IN4P Register (P1_R106) 0x6B DIAG_MON_LSB_IN4P Diagnostic IN4P data LSB nibble register DIAG_MON_LSB_IN4P Register (P1_R107) 0x6C DIAG_MON_MSB_IN4M Diagnostic IN4M data MSB byte register DIAG_MON_MSB_IN4M Register (P1_R108) 0x6D DIAG_MON_LSB_IN4M Diagnostic IN4M data LSB nibble register DIAG_MON_LSB_IN4M Register (P1_R109) 0x6E DIAG_MON_MSB_IN5P Diagnostic IN5P data MSB byte register DIAG_MON_MSB_IN5P Register (P1_R110) 0x6F DIAG_MON_LSB_IN5P Diagnostic IN5P data LSB nibble register DIAG_MON_LSB_IN5P Register (P1_R111) 0x70 DIAG_MON_MSB_IN5M Diagnostic IN5M data MSB byte register DIAG_MON_MSB_IN5M Register (P1_R112) 0x71 DIAG_MON_LSB_IN5M Diagnostic IN5M data LSB nibble register DIAG_MON_LSB_IN5M Register (P1_R113) 0x72 DIAG_MON_MSB_IN6P Diagnostic IN6P data MSB byte register DIAG_MON_MSB_IN6P Register (P1_R114) 0x73 DIAG_MON_LSB_IN6P Diagnostic IN6P data LSB nibble register DIAG_MON_LSB_IN6P Register (P1_R115) 0x74 DIAG_MON_MSB_IN6M Diagnostic IN6M data MSB byte register DIAG_MON_MSB_IN6M Register (P1_R116) 0x75 DIAG_MON_LSB_IN6M Diagnostic IN6M data LSB nibble register DIAG_MON_LSB_IN6M Register (P1_R117) 0x76 DIAG_MON_MSB_TEMP Diagnostic temperature data MSB byte register DIAG_MON_MSB_TEMP Register (P1_R118)

Table 51 lists the access codes used for the PCM6xx0-Q1 registers. Table 51. PCM6xx0-Q1 Access Type Codes

8.6.1.3 Register Description: Page = 0x00

8.6.1.3.1 PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]

The device memory map is divided into pages. This register sets the page. Figure 96. PAGE_CFG Register Table 52. PAGE_CFG Register Field Descriptions 7-0 PAGE[7:0] R/W 0h These bits set the device page.

8.6.1.3.2 SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]

Figure 97. SW_RESET Register Table 53. SW_RESET Register Field Descriptions 0 SW_RESET R/W 0h Software reset. This bit is self-clearing.

8.6.1.3.3 SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]

This register configures the regulator, VREF quick charge, I2C broadcast and sleep mode.

Figure 98. SLEEP_CFG Register Table 54. SLEEP_CFG Register Field Descriptions

7 Reserved RW 0h Reserved

an internal series impedance of 200 ohm. 2 I2C_BRDCAST_EN RW 0h I2C broadcast addressing setting.

1 Reserved R 0h Reserved

0 SLEEP_ENZ RW 0h Sleep mode setting.

8.6.1.3.4 SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]

Figure 99. SHDN_CFG Register Table 55. SHDN_CFG Register Field Descriptions 3-2 SHDNZ_CFG[1:0] RW 1h Shutdown configuration. 1-0 DREG_KA_TIME[1:0] RW 1h These bits set how long DREG remains active after SHDNZ asserts.

8.6.1.3.5 ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]

This register is the ASI configuration register 0. Figure 100. ASI_CFG0 Register

Table 56. ASI_CFG0 Register Field Descriptions 7-6 ASI_FORMAT[1:0] RW 0h ASI protocol format. 5-4 ASI_WLEN[1:0] RW 3h ASI word or slot length. 3 FSYNC_POL RW 0h ASI FSYNC polarity. 2 BCLK_POL RW 0h ASI BCLK polarity. 1 TX_EDGE RW 0h ASI data output (on the primary and secondary data pin) transmit edge.

0 TX_FILL RW 0h ASI data output (on the primary and secondary data pin) for any unused

8.6.1.3.6 ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]

This register is the ASI configuration register 1. Figure 101. ASI_CFG1 Register Table 57. ASI_CFG1 Register Field Descriptions

7 TX_LSB RW 0h ASI data output (on the primary and secondary data pin) for LSB

6-5 TX_KEEPER[1:0] RW 0h ASI data output (on the primary and secondary data pin) bus keeper. 4-0 TX_OFFSET[4:0] RW 0h ASI data MSB slot 0 offset (on the primary and secondary data pin).

8.6.1.3.7 ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]

This register is the ASI configuration register 2. Figure 102. ASI_CFG2 Register Table 58. ASI_CFG2 Register Field Descriptions 7 ASI_DAISY RW 0h ASI daisy chain connection.

6 Reserved R 0h Reserved

5 ASI_ERR RW 0h ASI bus error detection. 4 ASI_ERR_RCOV RW 0h ASI bus error auto resume.

8.6.1.3.8 ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]

This register is the ASI slot configuration register for channel 1. Figure 103. ASI_CH1 Register Table 59. ASI_CH1 Register Field Descriptions

7 Reserved R 0h Reserved

6 CH1_OUTPUT RW 0h Channel 1 output line. 5-0 CH1_SLOT[5:0] RW 0h Channel 1 slot assignment.

8.6.1.3.9 ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]

This register is the ASI slot configuration register for channel 2. Figure 104. ASI_CH2 Register

Table 60. ASI_CH2 Register Field Descriptions 6 CH2_OUTPUT RW 0h Channel 2 output line. 5-0 CH2_SLOT[5:0] RW 1h Channel 2 slot assignment.

8.6.1.3.10 ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]

This register is the ASI slot configuration register for channel 3. Figure 105. ASI_CH3 Register Table 61. ASI_CH3 Register Field Descriptions 6 CH3_OUTPUT RW 0h Channel 3 output line. 5-0 CH3_SLOT[5:0] RW 2h Channel 3 slot assignment.

8.6.1.3.11 ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]

This register is the ASI slot configuration register for channel 4. Figure 106. ASI_CH4 Register Table 62. ASI_CH4 Register Field Descriptions 6 CH4_OUTPUT RW 0h Channel 4 output line.

Table 62. ASI_CH4 Register Field Descriptions (continued) 5-0 CH4_SLOT[5:0] RW 3h Channel 4 slot assignment.

8.6.1.3.12 ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]

This register is the ASI slot configuration register for channel 5. Applicable only for PCM6x60-Q1. Figure 107. ASI_CH5 Register Table 63. ASI_CH5 Register Field Descriptions 6 CH5_OUTPUT RW 0h Channel 5 output line. 5-0 CH5_SLOT[5:0] RW 4h Channel 5 slot assignment.

8.6.1.3.13 ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]

This register is the ASI slot configuration register for channel 6. Applicable only for PCM6x60-Q1. Figure 108. ASI_CH6 Register Table 64. ASI_CH6 Register Field Descriptions 6 CH6_OUTPUT RW 0h Channel 6 output line.

Table 64. ASI_CH6 Register Field Descriptions (continued) 5-0 CH6_SLOT[5:0] RW 5h Channel 6 slot assignment.

8.6.1.3.14 MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]

This register is the ASI master mode configuration register 0. Figure 109. MST_CFG0 Register Table 65. MST_CFG0 Register Field Descriptions 7 MST_SLV_CFG RW 0h ASI master or slave configuration register setting. 6 AUTO_CLK_CFG RW 0h Automatic clock configuration setting. 5 AUTO_MODE_PLL_DIS RW 0h Automatic mode PLL setting. 4 BCLK_FSYNC_GATE RW 0h BCLK and FSYNC clock gate (valid when the device is in master mode). 3 FS_MODE RW 0h Sample rate setting (valid when the device is in master mode).

8.6.1.3.15 MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]

This register is the ASI master mode configuration register 1.

Figure 110. MST_CFG1 Register Table 66. MST_CFG1 Register Field Descriptions configured in slave mode auto clock configuration). when the device is configured in slave mode auto clock configuration).

8.6.1.3.16 ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]

Figure 111. ASI_STS Register Table 67. ASI_STS Register Field Descriptions 7-4 FS_RATE_STS[3:0] R Fh Detected sample rate of the ASI bus.

Table 67. ASI_STS Register Field Descriptions (continued) 3-0 FS_RATIO_STS[3:0] R Fh Detected BCLK to FSYNC frequency ratio of the ASI bus.

8.6.1.3.17 CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]

This register is the clock source configuration register. Figure 112. CLK_SRC Register Table 68. CLK_SRC Register Field Descriptions

7 DIS_PLL_SLV_CLK_SRC RW 0h Audio root clock source setting when the device is configured with the PLL

6 MCLK_FREQ_SEL_MODE RW 0h Master mode MCLK (GPIOx or GPIx) frequency selection mode (valid when

the device is in auto clock configuration). mode or when MCLK is used as the audio root clock source in slave mode.

8.6.1.3.18 GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]

This register is the GPIO configuration register 0.

Figure 113. GPIO_CFG0 Register Table 69. GPIO_CFG0 Register Field Descriptions 7-4 GPIO1_CFG[3:0] RW 2h GPIO1 configuration.

3 Reserved R 0h Reserved

8.6.1.3.19 GPIO_CFG1 Register (page = 0x00, address = 0x22) [reset = 0h]

This register is the GPIO configuration register 1. Not applicable for PCM6x60-Q1. Figure 114. GPIO_CFG1 Register Table 70. GPIO_CFG1 Register Field Descriptions 7-4 GPIO2_CFG[3:0] RW 0h GPIO2 configuration.

Table 70. GPIO_CFG1 Register Field Descriptions (continued)

8.6.1.3.20 GPIO_CFG2 Register (page = 0x00, address = 0x23) [reset = 0h]

This register is the GPIO configuration register 2. Not applicable for PCM6x60-Q1. Figure 115. GPIO_CFG2 Register Table 71. GPIO_CFG2 Register Field Descriptions 7-4 GPIO3_CFG[3:0] RW 0h GPIO3 configuration.

8.6.1.3.21 GPI_CFG0 Register (page = 0x00, address = 0x24) [reset = 0h]

This register is the GPI configuration register 0. Not applicable for PCM6x60-Q1. Figure 116. GPI_CFG0 Register

Table 72. GPI_CFG0 Register Field Descriptions 7-4 GPI1_CFG[3:0] RW 0h GPI1 configuration.

8.6.1.3.22 GPI_CFG1 Register (page = 0x00, address = 0x25) [reset = 0h]

This register is the GPI configuration register 1. Not applicable for PCM6x60-Q1. Figure 117. GPI_CFG1 Register Table 73. GPI_CFG1 Register Field Descriptions 7-4 GPI2_CFG[3:0] RW 0h GPI2 configuration.

8.6.1.3.23 GPIO_VAL Register (page = 0x00, address = 0x26) [reset = 0h]

This register is the GPIO output value register. Figure 118. GPIO_VAL Register Table 74. GPIO_VAL Register Field Descriptions 7 GPIO1_VAL RW 0h GPIO1 output value when configured as a GPO.

Table 74. GPIO_VAL Register Field Descriptions (continued)

8.6.1.3.24 GPIO_MON Register (page = 0x00, address = 0x27) [reset = 0h]

This register is the GPIO monitor value register. Figure 119. GPIO_MON Register Table 75. GPIO_MON Register Field Descriptions 7 GPIO1_MON R 0h GPIO1 monitor value when configured as a GPI.

8.6.1.3.25 INT_CFG Register (page = 0x00, address = 0x28) [reset = 0h]

This regiser is the interrupt configuration register. Figure 120. INT_CFG Register Table 76. INT_CFG Register Field Descriptions 7 INT_POL RW 0h Interrupt polarity.

Table 76. INT_CFG Register Field Descriptions (continued) 6-5 INT_EVENT[1:0] RW 0h Interrupt event configuration. all ADC channels gets powered-down based on P0_R58 settings. 2 LTCH_READ_CFG RW 0h Interrupt latch registers readback configuration. 1 PD_ON_FLT_RCV_CFG RW 0h Recovery configuration for ADC channels when fault goes away. 0 LTCH_CLR_ON_READ RW 0h Configuration for clearing LTCH register bits.

8.6.1.3.26 INT_MASK0 Register (page = 0x00, address = 0x29) [reset = FFh]

This register is the interrupt masks register 0. Figure 121. INT_MASK0 Register Table 77. INT_MASK0 Register Field Descriptions 7 INT_MASK0[7] RW 1h ASI clock error mask. 6 INT_MASK0[6] RW 1h PLL lock interrupt mask. 5 INT_MASK0[5] RW 1h Boost or MICBIAS over temperature interrupt mask. 4 INT_MASK0[4] RW 1h Boost or MICBIAS over current interrupt mask.

3 Reserved RW 1h Reserved

2 Reserved RW 1h Reserved

1 Reserved RW 1h Reserved

0 Reserved RW 1h Reserved

8.6.1.3.27 INT_MASK1 Register (page = 0x00, address = 0x2A) [reset = 3h]

This register is the interrupt masks register 1. Figure 122. INT_MASK1 Register Table 78. INT_MASK1 Register Field Descriptions 7 INT_MASK1[7] RW 0h Channel 1 input DC faults diagnostici interrupt mask. 6 INT_MASK1[6] RW 0h Channel 2 input DC faults diagnostici interrupt mask. 5 INT_MASK1[5] RW 0h Channel 3 input DC faults diagnostici interrupt mask. 4 INT_MASK1[4] RW 0h Channel 4 input DC faults diagnostici interrupt mask.

1 INT_MASK1[1] RW 1h Input faults diagnostic interrupt mask for "short to VBAT_IN" detect when

VBAT_IN voltage is less than MICBIAS voltage.

8.6.1.3.28 INT_MASK2 Register (page = 0x00, address = 0x2B) [reset = 0h]

This register is the interrupt masks register 2. Figure 123. INT_MASK2 Register Table 79. INT_MASK2 Register Field Descriptions 7 INT_MASK2[7] RW 0h Input diagnostics; Open inputs fault interrupt mask. 6 INT_MASK2[6] RW 0h Input diagnostics; Inputs shorted fault interrupt mask. 5 INT_MASK2[5] RW 0h Input diagnostics; INxP shorted to ground fault interrupt mask. 4 INT_MASK2[4] RW 0h Input diagnostics; INxM shorted to ground fault interrupt mask.

Table 79. INT_MASK2 Register Field Descriptions (continued) 3 INT_MASK2[3] RW 0h Input diagnostics; INxP shorted to MICBIAS fault interrupt mask. 2 INT_MASK2[2] RW 0h Input diagnostics; INxM shorted to MICBIAS fault interrupt mask. 1 INT_MASK2[1] RW 0h Input diagnostics; INxP shorted to VBAT_IN fault interrupt mask. 0 INT_MASK2[0] RW 0h Input diagnostics; INxM shorted to VBAT_IN fault interrupt mask.

8.6.1.3.29 INT_LTCH0 Register (page = 0x00, address = 0x2C) [reset = 0h]

This register is the latched Interrupt readback register 0. Figure 124. INT_LTCH0 Register Table 80. INT_LTCH0 Register Field Descriptions 7 INT_LTCH0[7] R 0h Fault status for an ASI bus clock error (self-clearing bit). 6 INT_LTCH0[6] R 0h Status of PLL lock (self-clearing bit). 5 INT_LTCH0[5] R 0h Fault status for boost or MICBIAS over temperature (self-clearing bit). 4 INT_LTCH0[4] R 0h Fault status for boost or MICBIAS over current (self-clearing bit).

2 Reserved R 0h Reserved

0 Reserved R 0h Reserved

8.6.1.3.30 CHx_LTCH Register (page = 0x00, address = 0x2D) [reset = 0h]

This register is the latched Interrupt status register for channel level diagnostic summary. Figure 125. CHx_LTCH Register Table 81. CHx_LTCH Register Field Descriptions 7 STS_CHx_LTCH[7] R 0h Status of CH1_LTCH (self-clearing bit).

Table 81. CHx_LTCH Register Field Descriptions (continued) 6 STS_CHx_LTCH[6] R 0h Status of CH2_LTCH (self-clearing bit). 5 STS_CHx_LTCH[5] R 0h Status of CH3_LTCH (self-clearing bit). 4 STS_CHx_LTCH[4] R 0h Status of CH4_LTCH (self-clearing bit). 3 STS_CHx_LTCH[3] R 0h Status of CH5_LTCH (self-clearing bit). Applicable only for PCM6x60-Q1. 2 STS_CHx_LTCH[2] R 0h Status of CH6_LTCH (self-clearing bit). Applicable only for PCM6x60-Q1.

1 STS_CHx_LTCH[1] R 0h Status of short to VBAT_IN fault detected when VBAT_IN is less than

MICBIAS (self-clearing bit).

8.6.1.3.31 CH1_LTCH Register (page = 0x00, address = 0x2E) [reset = 0h]

Figure 126. CH1_LTCH Register Table 82. CH1_LTCH Register Field Descriptions 7 CH1_LTCH[7] R 0h Channel 1 open input fault status (self-clearing bit). 6 CH1_LTCH[6] R 0h Channel 1 input pair short fault status (self-clearing bit). 5 CH1_LTCH[5] R 0h Channel 1 IN1P short to ground fault status (self-clearing bit). 4 CH1_LTCH[4] R 0h Channel 1 IN1M short to ground fault status (self-clearing bit). 3 CH1_LTCH[3] R 0h Channel 1 IN1P short to MICBIAS fault status (self-clearing bit). 2 CH1_LTCH[2] R 0h Channel 1 IN1M short to MICBIAS fault status (self-clearing bit). 1 CH1_LTCH[1] R 0h Channel 1 IN1P short to VBAT_IN fault status (self-clearing bit).